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Merge pull request #2472 from ytsuboi/master
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[TY51822r3] Added exporting support
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0xc0170 authored Aug 17, 2016
2 parents 8568c9e + f8a6af1 commit bdb4ab9
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Showing 3 changed files with 20 additions and 0 deletions.
1 change: 1 addition & 0 deletions hal/targets.json
Original file line number Diff line number Diff line change
Expand Up @@ -1536,6 +1536,7 @@
"TY51822R3": {
"inherits": ["MCU_NRF51_32K_UNIFIED"],
"macros_add": ["TARGET_NRF_32MHZ_XTAL"],
"progen": {"target": "ty51822r3"},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"detect_code": ["1019"],
"release_versions": ["2", "5"]
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18 changes: 18 additions & 0 deletions tools/export/gcc_arm_ty51822r3.tmpl
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@@ -0,0 +1,18 @@
{% extends "gcc_arm_common.tmpl" %}

{% block target_all %}
all: $(PROJECT).bin $(PROJECT)-combined.hex size
{% endblock %}

{% block additional_variables %}
SOFTDEVICE = {% for f in hex_files %}{{f}} {% endfor %}
{% endblock %}

{% block additional_executables %}
SREC_CAT = srec_cat
{% endblock %}

{% block additional_targets %}
$(PROJECT)-combined.hex: $(PROJECT).hex
$(SREC_CAT) $(SOFTDEVICE) -intel $(PROJECT).hex -intel -o $(PROJECT)-combined.hex -intel --line-length=44
{% endblock %}
1 change: 1 addition & 0 deletions tools/export/gccarm.py
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Expand Up @@ -58,6 +58,7 @@ class GccArm(Exporter):
'ARCH_PRO',
'NRF51822',
'HRM1017',
'TY51822R3',
'RBLAB_NRF51822',
'RBLAB_BLENANO',
'LPC2368',
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