targets:evkbimxrt1050: Adjust the SEMC re-order rules

Update the BMCR0, BMCR1 registers to adjust the SEMC re-order rules. This can improve the SDRAM stability under multiple AXI masters system. Signed-off-by: Gavin Liu <[email protected]>
ARMmbed · Feb 23, 2021 · 55a1465 · 55a1465
1 parent 376b7e3
commit 55a1465
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/...NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c b/...NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c
@@ -239,9 +239,9 @@ const uint8_t dcd_data[] = {
     /* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
     0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
     /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */
-    0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24,
+    0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
     /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */
-    0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24,
+    0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
     /* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
     0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
     /* #1.99, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */