Tarmac-browser syntax error

[adedespirlet]

Hello,
I keep getting this error when trying to run tarmac-browser on multiple different tarmac traces:

Reading trace file (0%)/projectdata/despir01/bigL3/corinth/logical/testbench/execution_tb/logs/aarch64_maxpwr_l3.exec_pe_0.mti/tarmac.cluster_execution_tb_u_cluster_g_core_0__g_big_u_ares_core_u_vcpu_u_cpu_u_ares_tarmac_capture_uinstracer.log:199: expected register contents
R V0<63:0> 00000000
^
I saw that it has been "fixed" a few years ago but despite the fixes i still get this error. Do you know what the issue is?

Thank you in advance.

[statham-arm]

The line you quote specifies a bit range <63:0>, meaning it's 64 bits wide. But the data field 00000000 only describes 32 bits of zeroes. Normally the TTU parser expects that the number of digits in the data matches the number of bits it's expected to occupy.

Can you tell me what Tarmac producer generated this file? And can you share a snippet of it in full, instead of just the error message?

[adedespirlet]

Hello, Thank you for the response. I have put in attachment a screenshot of the error appearing on my terminal. I installed the library from this github page: ARM-software/tarmac-trace-utilities: Tools for analyzing and browsing Tarmac instruction traces. (github.com) <https://github.com/ARM-software/tarmac-trace-utilities> Tarmac gives the same error for the different test files I compile to be executed on the cluster. It seems that when compiling my code they include some bootcode to initialize the caches,MMU, bank registers and FPU registers. Tarmac doesnt somehow like Initializing the FPU registers. Thank you for the help. I am available if you have any other questions. Best regards, Aurore [image: image.png] Le mar. 26 mars 2024 à 13:55, Simon Tatham ***@***.***> a écrit :

…

The line you quote specifies a bit range <63:0>, meaning it's 64 bits wide. But the data field 00000000 only describes 32 bits of zeroes. Normally the TTU parser expects that the number of digits in the data matches the number of bits it's expected to occupy. Can you tell me what Tarmac producer generated this file? And can you share a snippet of it in full, instead of just the error message? — Reply to this email directly, view it on GitHub <#17 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AORN3QIP42TMZIE56WY3NRDY2FO3BAVCNFSM6AAAAABFIRIN7OVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDAMRQGM2TGOBWGU> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[statham-arm]

Sorry, but your image attachment is nowhere to be seen. I guess you made that comment by replying to the Github email? Apparently, when you do that, the email attachments aren't transferred on to the bug ticket.

However, a screenshot wouldn't have been much use anyway. Could you provide a snippet of the actual Tarmac file, please? Not a picture, but some text.

Also, what tool or product generated the Tarmac file? You've told me what you used to read the file (Tarmac Trace Utilities, the project this bug tracker is all about). But what wrote it?

[adedespirlet]

Yes indeed I replied to the Github email, this is probably why.
The tarmac file is generated when I execute the testbench through Modelsim. The generation of the tarmac file is specified in a Makefile that is used to execute the simulation on modelsim. I don't know if this is an answer to your question but it is hard to understand exactly how it is generated since I did not install it , it was already included in the whole setup directory received by ARM for the DSU and Neoverse N1 core IPs. I have attached in this mail the tarmac generation flow described in a txt file that we received. I also attached the generated tarmac file. Both via github this time.
tarmac.cluster_execution_tb_u_cluster_g_core_0__g_big_u_ares_core_u_vcpu_u_cpu_u_ares_tarmac_capture_uinstracer.log
cm-tarmac-usage.txt