From 801f345131fca9c39b80c4f4ee59d7d114432461 Mon Sep 17 00:00:00 2001 From: aiamadeus <2789289348@qq.com> Date: Tue, 17 Sep 2024 23:15:26 +0800 Subject: [PATCH 1/4] kernel: refresh 6.1 patches Fixes: 718ac37 ("kernel: bump 6.1 to 6.1.111") Closed: #12487 --- ...i-gen-LRU-rename-lru_gen_struct-to-l.patch | 8 ++-- ...i-gen-LRU-remove-eviction-fairness-s.patch | 10 ++--- ...i-gen-LRU-remove-aging-fairness-safe.patch | 8 ++-- ...lti-gen-LRU-shuffle-should_run_aging.patch | 2 +- ...i-gen-LRU-per-node-lru_gen_folio-lis.patch | 30 +++++++------- ...i-gen-LRU-clarify-scan_control-flags.patch | 12 +++--- ...m-multi-gen-LRU-avoid-futile-retries.patch | 6 +-- ...3-10-UPSTREAM-mm-add-vma_has_recency.patch | 2 +- ...-multi-gen-LRU-section-for-memcg-LRU.patch | 4 +- ...i-gen-LRU-improve-lru_gen_exit_memcg.patch | 2 +- ...i-gen-LRU-remove-wait_event_killable.patch | 4 +- ...ilicon-Labs-SI3210-device-compatible.patch | 8 ++-- ...-03-v6.2-net-dpaa-Convert-to-phylink.patch | 12 +++--- ...cit-phylink_generic_validate-referen.patch | 2 +- ...-neg_mode-into-phylink_mii_c22_pcs_c.patch | 6 +-- ...ix-risk-of-NULL-pointer-deallocation.patch | 2 +- ...ansmit-URBs-without-trailing-padding.patch | 2 +- ...03-usbnet-ipheth-add-CDC-NCM-support.patch | 10 ++--- ...6xxx-fix-marvell-6350-switch-probing.patch | 8 ++-- ...dev-expose-netdev-trigger-modes-in-l.patch | 2 +- ...dev-add-additional-specific-link-spe.patch | 2 +- ...dev-add-additional-specific-link-dup.patch | 2 +- ...x-fix-88E6393X-family-internal-phys-.patch | 6 +-- ...xx-enable-support-for-88E6361-switch.patch | 2 +- ...ount-to-list.h-as-list_count_nodes-f.patch | 4 +- ...-of_parse_phandle_with_optional_args.patch | 2 +- ...v6.4-0003-of-Rename-of_modalias_node.patch | 2 +- ...0004-of-Move-of_modalias-to-module.c.patch | 4 +- ...uest-module-helper-logic-to-module.c.patch | 4 +- ...com-nvmem-use-SoC-ID-s-from-bindings.patch | 2 +- ...-nvmem-use-helper-to-get-SMEM-SoC-ID.patch | 2 +- ...igger-netdev-Extend-speeds-up-to-10G.patch | 2 +- ...ci_generic-Add-HP-variant-of-T99W175.patch | 2 +- ..._generic-Add-definition-for-some-VID.patch | 4 +- ..._generic-Drop-redundant-pci_enable_p.patch | 6 +-- ...-mhi-pci_generic-Add-Foxconn-T99W510.patch | 2 +- ..._generic-Add-support-for-Quectel-EM1.patch | 2 +- ..._generic-Add-support-for-Quectel-RM5.patch | 2 +- ..._generic-Add-support-for-Dell-DW5932.patch | 2 +- ..._generic-Add-support-for-Quectel-RM5.patch | 2 +- ...8-net-ethtool-implement-ethtool_puts.patch | 2 +- .../hack-6.1/230-openwrt_lzma_options.patch | 2 +- .../generic/hack-6.1/253-ksmbd-config.patch | 2 +- .../780-usb-net-MeigLink_modem_support.patch | 6 +-- .../generic/hack-6.1/902-debloat_proc.patch | 8 ++-- .../hack-6.1/904-debloat_dma_buf.patch | 2 +- .../911-kobject_add_broadcast_uevent.patch | 2 +- ...vert-driver-core-Set-fw_devlink-on-b.patch | 2 +- ...k-events-support-multiple-registrant.patch | 4 +- ...e_mem_map-with-ARCH_PFN_OFFSET-calcu.patch | 2 +- .../pending-6.1/630-packet_socket_type.patch | 16 ++++---- ...Add-support-for-MAP-E-FMRs-mesh-mode.patch | 18 ++++----- ...ng-with-source-address-failed-policy.patch | 2 +- ...les-ignore-EOPNOTSUPP-on-flowtable-d.patch | 2 +- ...equest-assisted-learning-on-CPU-port.patch | 2 +- ...dsa-b53-mmap-allow-passing-a-chip-ID.patch | 2 +- ...sa-b53-mdio-add-support-for-BCM53134.patch | 4 +- .../pending-6.1/834-ledtrig-libata.patch | 4 +- .../901-usb-add-more-modem-support.patch | 28 +++++++++++++ ...-overlays-to-built-from-.dtso-named-.patch | 2 +- ...d-Inline-Crypto-Engine-clock-control.patch | 2 +- ...fix-two-spelling-mistakes-in-comment.patch | 4 +- ...d-open-coding-by-using-mmc_op_tuning.patch | 39 ------------------- ...nctrl-add-mt7988-pd-pulltype-support.patch | 16 ++++---- .../901-arm-add-cmdline-override.patch | 2 +- 65 files changed, 180 insertions(+), 191 deletions(-) create mode 100644 target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch delete mode 100644 target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch diff --git a/target/linux/generic/backport-6.1/020-v6.3-01-UPSTREAM-mm-multi-gen-LRU-rename-lru_gen_struct-to-l.patch b/target/linux/generic/backport-6.1/020-v6.3-01-UPSTREAM-mm-multi-gen-LRU-rename-lru_gen_struct-to-l.patch index fe32acc9851223..2428bdcb72c0ce 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-01-UPSTREAM-mm-multi-gen-LRU-rename-lru_gen_struct-to-l.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-01-UPSTREAM-mm-multi-gen-LRU-rename-lru_gen_struct-to-l.patch @@ -294,7 +294,7 @@ Signed-off-by: T.J. Mercier struct mem_cgroup *memcg = lruvec_memcg(lruvec); VM_WARN_ON_ONCE(!list_empty(list)); -@@ -5249,7 +5249,7 @@ done: +@@ -5248,7 +5248,7 @@ done: static bool __maybe_unused state_is_valid(struct lruvec *lruvec) { @@ -303,7 +303,7 @@ Signed-off-by: T.J. Mercier if (lrugen->enabled) { enum lru_list lru; -@@ -5531,7 +5531,7 @@ static void lru_gen_seq_show_full(struct +@@ -5530,7 +5530,7 @@ static void lru_gen_seq_show_full(struct int i; int type, tier; int hist = lru_hist_from_seq(seq); @@ -312,7 +312,7 @@ Signed-off-by: T.J. Mercier for (tier = 0; tier < MAX_NR_TIERS; tier++) { seq_printf(m, " %10d", tier); -@@ -5581,7 +5581,7 @@ static int lru_gen_seq_show(struct seq_f +@@ -5580,7 +5580,7 @@ static int lru_gen_seq_show(struct seq_f unsigned long seq; bool full = !debugfs_real_fops(m->file)->write; struct lruvec *lruvec = v; @@ -321,7 +321,7 @@ Signed-off-by: T.J. Mercier int nid = lruvec_pgdat(lruvec)->node_id; struct mem_cgroup *memcg = lruvec_memcg(lruvec); DEFINE_MAX_SEQ(lruvec); -@@ -5835,7 +5835,7 @@ void lru_gen_init_lruvec(struct lruvec * +@@ -5834,7 +5834,7 @@ void lru_gen_init_lruvec(struct lruvec * { int i; int gen, type, zone; diff --git a/target/linux/generic/backport-6.1/020-v6.3-03-UPSTREAM-mm-multi-gen-LRU-remove-eviction-fairness-s.patch b/target/linux/generic/backport-6.1/020-v6.3-03-UPSTREAM-mm-multi-gen-LRU-remove-eviction-fairness-s.patch index e5ad78b61d3563..3a27bbcae03205 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-03-UPSTREAM-mm-multi-gen-LRU-remove-eviction-fairness-s.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-03-UPSTREAM-mm-multi-gen-LRU-remove-eviction-fairness-s.patch @@ -76,7 +76,7 @@ Signed-off-by: T.J. Mercier { int type; int scanned; -@@ -5095,9 +5104,6 @@ retry: +@@ -5094,9 +5103,6 @@ retry: goto retry; } @@ -86,7 +86,7 @@ Signed-off-by: T.J. Mercier return scanned; } -@@ -5136,67 +5142,26 @@ done: +@@ -5135,67 +5141,26 @@ done: return min_seq[!can_swap] + MIN_NR_GENS <= max_seq ? nr_to_scan : 0; } @@ -163,7 +163,7 @@ Signed-off-by: T.J. Mercier lru_add_drain(); -@@ -5220,7 +5185,7 @@ static void lru_gen_shrink_lruvec(struct +@@ -5219,7 +5184,7 @@ static void lru_gen_shrink_lruvec(struct if (!nr_to_scan) goto done; @@ -172,7 +172,7 @@ Signed-off-by: T.J. Mercier if (!delta) goto done; -@@ -5228,7 +5193,7 @@ static void lru_gen_shrink_lruvec(struct +@@ -5227,7 +5192,7 @@ static void lru_gen_shrink_lruvec(struct if (scanned >= nr_to_scan) break; @@ -181,7 +181,7 @@ Signed-off-by: T.J. Mercier break; cond_resched(); -@@ -5678,7 +5643,7 @@ static int run_eviction(struct lruvec *l +@@ -5677,7 +5642,7 @@ static int run_eviction(struct lruvec *l if (sc->nr_reclaimed >= nr_to_reclaim) return 0; diff --git a/target/linux/generic/backport-6.1/020-v6.3-04-BACKPORT-mm-multi-gen-LRU-remove-aging-fairness-safe.patch b/target/linux/generic/backport-6.1/020-v6.3-04-BACKPORT-mm-multi-gen-LRU-remove-aging-fairness-safe.patch index cb349abcdb6c6c..82958895541039 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-04-BACKPORT-mm-multi-gen-LRU-remove-aging-fairness-safe.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-04-BACKPORT-mm-multi-gen-LRU-remove-aging-fairness-safe.patch @@ -214,7 +214,7 @@ Signed-off-by: T.J. Mercier */ if (mutex_trylock(&oom_lock)) { struct oom_control oc = { -@@ -5113,33 +5117,27 @@ retry: +@@ -5112,33 +5116,27 @@ retry: * reclaim. */ static unsigned long get_nr_to_scan(struct lruvec *lruvec, struct scan_control *sc, @@ -254,7 +254,7 @@ Signed-off-by: T.J. Mercier } static unsigned long get_nr_to_reclaim(struct scan_control *sc) -@@ -5158,9 +5156,7 @@ static unsigned long get_nr_to_reclaim(s +@@ -5157,9 +5155,7 @@ static unsigned long get_nr_to_reclaim(s static void lru_gen_shrink_lruvec(struct lruvec *lruvec, struct scan_control *sc) { struct blk_plug plug; @@ -264,7 +264,7 @@ Signed-off-by: T.J. Mercier unsigned long nr_to_reclaim = get_nr_to_reclaim(sc); lru_add_drain(); -@@ -5181,13 +5177,13 @@ static void lru_gen_shrink_lruvec(struct +@@ -5180,13 +5176,13 @@ static void lru_gen_shrink_lruvec(struct else swappiness = 0; @@ -281,7 +281,7 @@ Signed-off-by: T.J. Mercier scanned += delta; if (scanned >= nr_to_scan) -@@ -5199,10 +5195,6 @@ static void lru_gen_shrink_lruvec(struct +@@ -5198,10 +5194,6 @@ static void lru_gen_shrink_lruvec(struct cond_resched(); } diff --git a/target/linux/generic/backport-6.1/020-v6.3-05-UPSTREAM-mm-multi-gen-LRU-shuffle-should_run_aging.patch b/target/linux/generic/backport-6.1/020-v6.3-05-UPSTREAM-mm-multi-gen-LRU-shuffle-should_run_aging.patch index 42caab7c3785e2..6374b425cd5495 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-05-UPSTREAM-mm-multi-gen-LRU-shuffle-should_run_aging.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-05-UPSTREAM-mm-multi-gen-LRU-shuffle-should_run_aging.patch @@ -95,7 +95,7 @@ Signed-off-by: T.J. Mercier static bool lruvec_is_sizable(struct lruvec *lruvec, struct scan_control *sc) { int gen, type, zone; -@@ -5111,6 +5049,68 @@ retry: +@@ -5110,6 +5048,68 @@ retry: return scanned; } diff --git a/target/linux/generic/backport-6.1/020-v6.3-06-BACKPORT-mm-multi-gen-LRU-per-node-lru_gen_folio-lis.patch b/target/linux/generic/backport-6.1/020-v6.3-06-BACKPORT-mm-multi-gen-LRU-per-node-lru_gen_folio-lis.patch index 7756d19d9bd970..259b5d697f65dd 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-06-BACKPORT-mm-multi-gen-LRU-per-node-lru_gen_folio-lis.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-06-BACKPORT-mm-multi-gen-LRU-per-node-lru_gen_folio-lis.patch @@ -335,7 +335,7 @@ Signed-off-by: T.J. Mercier if (order > 0) return 0; -@@ -5387,6 +5400,7 @@ static int mem_cgroup_css_online(struct +@@ -5408,6 +5421,7 @@ static int mem_cgroup_css_online(struct if (unlikely(mem_cgroup_is_root(memcg))) queue_delayed_work(system_unbound_wq, &stats_flush_dwork, 2UL*HZ); @@ -343,7 +343,7 @@ Signed-off-by: T.J. Mercier return 0; offline_kmem: memcg_offline_kmem(memcg); -@@ -5418,6 +5432,7 @@ static void mem_cgroup_css_offline(struc +@@ -5439,6 +5453,7 @@ static void mem_cgroup_css_offline(struc memcg_offline_kmem(memcg); reparent_shrinker_deferred(memcg); wb_memcg_offline(memcg); @@ -351,7 +351,7 @@ Signed-off-by: T.J. Mercier drain_all_stock(memcg); -@@ -5429,6 +5444,7 @@ static void mem_cgroup_css_released(stru +@@ -5450,6 +5465,7 @@ static void mem_cgroup_css_released(stru struct mem_cgroup *memcg = mem_cgroup_from_css(css); invalidate_reclaim_iterators(memcg); @@ -361,7 +361,7 @@ Signed-off-by: T.J. Mercier static void mem_cgroup_css_free(struct cgroup_subsys_state *css) --- a/mm/page_alloc.c +++ b/mm/page_alloc.c -@@ -7949,6 +7949,7 @@ static void __init free_area_init_node(i +@@ -7956,6 +7956,7 @@ static void __init free_area_init_node(i pgdat_set_deferred_range(pgdat); free_area_init_core(pgdat); @@ -421,7 +421,7 @@ Signed-off-by: T.J. Mercier /* check the order to exclude compaction-induced reclaim */ if (!min_ttl || sc->order || sc->priority == DEF_PRIORITY) return; -@@ -5116,8 +5113,7 @@ static bool should_run_aging(struct lruv +@@ -5115,8 +5112,7 @@ static bool should_run_aging(struct lruv * 1. Defer try_to_inc_max_seq() to workqueues to reduce latency for memcg * reclaim. */ @@ -431,7 +431,7 @@ Signed-off-by: T.J. Mercier { unsigned long nr_to_scan; struct mem_cgroup *memcg = lruvec_memcg(lruvec); -@@ -5134,10 +5130,8 @@ static unsigned long get_nr_to_scan(stru +@@ -5133,10 +5129,8 @@ static unsigned long get_nr_to_scan(stru if (sc->priority == DEF_PRIORITY) return nr_to_scan; @@ -443,7 +443,7 @@ Signed-off-by: T.J. Mercier } static unsigned long get_nr_to_reclaim(struct scan_control *sc) -@@ -5146,29 +5140,18 @@ static unsigned long get_nr_to_reclaim(s +@@ -5145,29 +5139,18 @@ static unsigned long get_nr_to_reclaim(s if (!global_reclaim(sc)) return -1; @@ -475,7 +475,7 @@ Signed-off-by: T.J. Mercier if (sc->may_swap) swappiness = get_swappiness(lruvec, sc); -@@ -5178,7 +5161,7 @@ static void lru_gen_shrink_lruvec(struct +@@ -5177,7 +5160,7 @@ static void lru_gen_shrink_lruvec(struct swappiness = 0; nr_to_scan = get_nr_to_scan(lruvec, sc, swappiness); @@ -484,7 +484,7 @@ Signed-off-by: T.J. Mercier break; delta = evict_folios(lruvec, sc, swappiness); -@@ -5195,10 +5178,251 @@ static void lru_gen_shrink_lruvec(struct +@@ -5194,10 +5177,251 @@ static void lru_gen_shrink_lruvec(struct cond_resched(); } @@ -736,7 +736,7 @@ Signed-off-by: T.J. Mercier /****************************************************************************** * state change -@@ -5656,11 +5880,11 @@ static int run_cmd(char cmd, int memcg_i +@@ -5655,11 +5879,11 @@ static int run_cmd(char cmd, int memcg_i if (!mem_cgroup_disabled()) { rcu_read_lock(); @@ -751,7 +751,7 @@ Signed-off-by: T.J. Mercier rcu_read_unlock(); if (!memcg) -@@ -5808,6 +6032,19 @@ void lru_gen_init_lruvec(struct lruvec * +@@ -5807,6 +6031,19 @@ void lru_gen_init_lruvec(struct lruvec * } #ifdef CONFIG_MEMCG @@ -771,7 +771,7 @@ Signed-off-by: T.J. Mercier void lru_gen_init_memcg(struct mem_cgroup *memcg) { INIT_LIST_HEAD(&memcg->mm_list.fifo); -@@ -5831,7 +6068,69 @@ void lru_gen_exit_memcg(struct mem_cgrou +@@ -5830,7 +6067,69 @@ void lru_gen_exit_memcg(struct mem_cgrou } } } @@ -842,7 +842,7 @@ Signed-off-by: T.J. Mercier static int __init init_lru_gen(void) { -@@ -5858,6 +6157,10 @@ static void lru_gen_shrink_lruvec(struct +@@ -5857,6 +6156,10 @@ static void lru_gen_shrink_lruvec(struct { } @@ -853,7 +853,7 @@ Signed-off-by: T.J. Mercier #endif /* CONFIG_LRU_GEN */ static void shrink_lruvec(struct lruvec *lruvec, struct scan_control *sc) -@@ -5871,7 +6174,7 @@ static void shrink_lruvec(struct lruvec +@@ -5870,7 +6173,7 @@ static void shrink_lruvec(struct lruvec bool proportional_reclaim; struct blk_plug plug; @@ -862,7 +862,7 @@ Signed-off-by: T.J. Mercier lru_gen_shrink_lruvec(lruvec, sc); return; } -@@ -6114,6 +6417,11 @@ static void shrink_node(pg_data_t *pgdat +@@ -6113,6 +6416,11 @@ static void shrink_node(pg_data_t *pgdat struct lruvec *target_lruvec; bool reclaimable = false; diff --git a/target/linux/generic/backport-6.1/020-v6.3-07-BACKPORT-mm-multi-gen-LRU-clarify-scan_control-flags.patch b/target/linux/generic/backport-6.1/020-v6.3-07-BACKPORT-mm-multi-gen-LRU-clarify-scan_control-flags.patch index d60ddb9dccafed..079f4fd20289ca 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-07-BACKPORT-mm-multi-gen-LRU-clarify-scan_control-flags.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-07-BACKPORT-mm-multi-gen-LRU-clarify-scan_control-flags.patch @@ -113,7 +113,7 @@ Signed-off-by: T.J. Mercier */ return isolated || !remaining ? scanned : 0; } -@@ -5119,8 +5115,7 @@ static long get_nr_to_scan(struct lruvec +@@ -5118,8 +5114,7 @@ static long get_nr_to_scan(struct lruvec struct mem_cgroup *memcg = lruvec_memcg(lruvec); DEFINE_MAX_SEQ(lruvec); @@ -123,7 +123,7 @@ Signed-off-by: T.J. Mercier return 0; if (!should_run_aging(lruvec, max_seq, sc, can_swap, &nr_to_scan)) -@@ -5148,17 +5143,14 @@ static bool try_to_shrink_lruvec(struct +@@ -5147,17 +5142,14 @@ static bool try_to_shrink_lruvec(struct long nr_to_scan; unsigned long scanned = 0; unsigned long nr_to_reclaim = get_nr_to_reclaim(sc); @@ -146,7 +146,7 @@ Signed-off-by: T.J. Mercier nr_to_scan = get_nr_to_scan(lruvec, sc, swappiness); if (nr_to_scan <= 0) -@@ -5289,12 +5281,13 @@ static void lru_gen_shrink_lruvec(struct +@@ -5288,12 +5280,13 @@ static void lru_gen_shrink_lruvec(struct struct blk_plug plug; VM_WARN_ON_ONCE(global_reclaim(sc)); @@ -161,7 +161,7 @@ Signed-off-by: T.J. Mercier if (try_to_shrink_lruvec(lruvec, sc)) lru_gen_rotate_memcg(lruvec, MEMCG_LRU_YOUNG); -@@ -5350,11 +5343,19 @@ static void lru_gen_shrink_node(struct p +@@ -5349,11 +5342,19 @@ static void lru_gen_shrink_node(struct p VM_WARN_ON_ONCE(!global_reclaim(sc)); @@ -182,7 +182,7 @@ Signed-off-by: T.J. Mercier set_initial_priority(pgdat, sc); -@@ -5372,7 +5373,7 @@ static void lru_gen_shrink_node(struct p +@@ -5371,7 +5372,7 @@ static void lru_gen_shrink_node(struct p clear_mm_walk(); blk_finish_plug(&plug); @@ -191,7 +191,7 @@ Signed-off-by: T.J. Mercier /* kswapd should never fail */ pgdat->kswapd_failures = 0; } -@@ -5944,7 +5945,7 @@ static ssize_t lru_gen_seq_write(struct +@@ -5943,7 +5944,7 @@ static ssize_t lru_gen_seq_write(struct set_task_reclaim_state(current, &sc.reclaim_state); flags = memalloc_noreclaim_save(); blk_start_plug(&plug); diff --git a/target/linux/generic/backport-6.1/020-v6.3-09-UPSTREAM-mm-multi-gen-LRU-avoid-futile-retries.patch b/target/linux/generic/backport-6.1/020-v6.3-09-UPSTREAM-mm-multi-gen-LRU-avoid-futile-retries.patch index c1ad1c538eabcc..2ed3f07bbf6c39 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-09-UPSTREAM-mm-multi-gen-LRU-avoid-futile-retries.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-09-UPSTREAM-mm-multi-gen-LRU-avoid-futile-retries.patch @@ -29,7 +29,7 @@ Signed-off-by: T.J. Mercier --- a/mm/vmscan.c +++ b/mm/vmscan.c -@@ -5218,18 +5218,20 @@ static int shrink_one(struct lruvec *lru +@@ -5217,18 +5217,20 @@ static int shrink_one(struct lruvec *lru static void shrink_many(struct pglist_data *pgdat, struct scan_control *sc) { @@ -52,7 +52,7 @@ Signed-off-by: T.J. Mercier gen = get_memcg_gen(READ_ONCE(pgdat->memcg_lru.seq)); rcu_read_lock(); -@@ -5253,14 +5255,22 @@ restart: +@@ -5252,14 +5254,22 @@ restart: op = shrink_one(lruvec, sc); @@ -78,7 +78,7 @@ Signed-off-by: T.J. Mercier /* restart if raced with lru_gen_rotate_memcg() */ if (gen != get_nulls_value(pos)) goto restart; -@@ -5269,11 +5279,6 @@ restart: +@@ -5268,11 +5278,6 @@ restart: bin = get_memcg_bin(bin + 1); if (bin != first_bin) goto restart; diff --git a/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch b/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch index 67fe4f96ec7825..4f01dc7d7e1588 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch @@ -87,7 +87,7 @@ Signed-off-by: T.J. Mercier mark_page_accessed(page); } rss[mm_counter(page)]--; -@@ -5219,8 +5218,8 @@ static inline void mm_account_fault(stru +@@ -5235,8 +5234,8 @@ static inline void mm_account_fault(stru #ifdef CONFIG_LRU_GEN static void lru_gen_enter_fault(struct vm_area_struct *vma) { diff --git a/target/linux/generic/backport-6.1/020-v6.3-15-UPSTREAM-mm-multi-gen-LRU-section-for-memcg-LRU.patch b/target/linux/generic/backport-6.1/020-v6.3-15-UPSTREAM-mm-multi-gen-LRU-section-for-memcg-LRU.patch index 101a0a37572e28..11c1b43db96903 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-15-UPSTREAM-mm-multi-gen-LRU-section-for-memcg-LRU.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-15-UPSTREAM-mm-multi-gen-LRU-section-for-memcg-LRU.patch @@ -303,7 +303,7 @@ Signed-off-by: T.J. Mercier * the eviction ******************************************************************************/ -@@ -5398,53 +5540,6 @@ done: +@@ -5397,53 +5539,6 @@ done: pgdat->kswapd_failures = 0; } @@ -357,7 +357,7 @@ Signed-off-by: T.J. Mercier /****************************************************************************** * state change ******************************************************************************/ -@@ -6090,67 +6185,6 @@ void lru_gen_exit_memcg(struct mem_cgrou +@@ -6089,67 +6184,6 @@ void lru_gen_exit_memcg(struct mem_cgrou } } diff --git a/target/linux/generic/backport-6.1/020-v6.3-16-UPSTREAM-mm-multi-gen-LRU-improve-lru_gen_exit_memcg.patch b/target/linux/generic/backport-6.1/020-v6.3-16-UPSTREAM-mm-multi-gen-LRU-improve-lru_gen_exit_memcg.patch index 1ee766f8613faf..fcb9708d8aaeec 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-16-UPSTREAM-mm-multi-gen-LRU-improve-lru_gen_exit_memcg.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-16-UPSTREAM-mm-multi-gen-LRU-improve-lru_gen_exit_memcg.patch @@ -20,7 +20,7 @@ Signed-off-by: T.J. Mercier --- a/mm/vmscan.c +++ b/mm/vmscan.c -@@ -6172,12 +6172,17 @@ void lru_gen_exit_memcg(struct mem_cgrou +@@ -6171,12 +6171,17 @@ void lru_gen_exit_memcg(struct mem_cgrou int i; int nid; diff --git a/target/linux/generic/backport-6.1/020-v6.4-19-mm-Multi-gen-LRU-remove-wait_event_killable.patch b/target/linux/generic/backport-6.1/020-v6.4-19-mm-Multi-gen-LRU-remove-wait_event_killable.patch index 1b0459cdb9cc97..958d4596865718 100644 --- a/target/linux/generic/backport-6.1/020-v6.4-19-mm-Multi-gen-LRU-remove-wait_event_killable.patch +++ b/target/linux/generic/backport-6.1/020-v6.4-19-mm-Multi-gen-LRU-remove-wait_event_killable.patch @@ -255,7 +255,7 @@ Signed-off-by: Andrew Morton } /****************************************************************************** -@@ -6117,7 +6087,6 @@ void lru_gen_init_lruvec(struct lruvec * +@@ -6116,7 +6086,6 @@ void lru_gen_init_lruvec(struct lruvec * INIT_LIST_HEAD(&lrugen->folios[gen][type][zone]); lruvec->mm_state.seq = MIN_NR_GENS; @@ -263,7 +263,7 @@ Signed-off-by: Andrew Morton } #ifdef CONFIG_MEMCG -@@ -6150,7 +6119,6 @@ void lru_gen_exit_memcg(struct mem_cgrou +@@ -6149,7 +6118,6 @@ void lru_gen_exit_memcg(struct mem_cgrou for_each_node(nid) { struct lruvec *lruvec = get_lruvec(memcg, nid); diff --git a/target/linux/generic/backport-6.1/412-v6.3-02-spidev-Add-Silicon-Labs-SI3210-device-compatible.patch b/target/linux/generic/backport-6.1/412-v6.3-02-spidev-Add-Silicon-Labs-SI3210-device-compatible.patch index 59d025e087b131..1f8501dc1c26f1 100644 --- a/target/linux/generic/backport-6.1/412-v6.3-02-spidev-Add-Silicon-Labs-SI3210-device-compatible.patch +++ b/target/linux/generic/backport-6.1/412-v6.3-02-spidev-Add-Silicon-Labs-SI3210-device-compatible.patch @@ -14,7 +14,7 @@ Signed-off-by: Mark Brown --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c -@@ -701,6 +701,7 @@ static const struct spi_device_id spidev +@@ -702,6 +702,7 @@ static const struct spi_device_id spidev { .name = "spi-petra" }, { .name = "spi-authenta" }, { .name = "em3581" }, @@ -22,9 +22,9 @@ Signed-off-by: Mark Brown {}, }; MODULE_DEVICE_TABLE(spi, spidev_spi_ids); -@@ -728,6 +729,7 @@ static const struct of_device_id spidev_ - { .compatible = "cisco,spi-petra", .data = &spidev_of_check }, - { .compatible = "micron,spi-authenta", .data = &spidev_of_check }, +@@ -730,6 +731,7 @@ static const struct of_device_id spidev_ + { .compatible = "rohm,dh2228fv", .data = &spidev_of_check }, + { .compatible = "semtech,sx1301", .data = &spidev_of_check }, { .compatible = "silabs,em3581", .data = &spidev_of_check }, + { .compatible = "silabs,si3210", .data = &spidev_of_check }, {}, diff --git a/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch b/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch index 63b651bb2dd309..bdcdf172ecd204 100644 --- a/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch +++ b/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch @@ -130,7 +130,7 @@ Signed-off-by: David S. Miller struct dpaa_priv *priv = netdev_priv(net_dev); struct qm_mcc_initcgr opts = { }; u32 cs_th; -@@ -2905,58 +2915,6 @@ static void dpaa_eth_napi_disable(struct +@@ -2920,58 +2930,6 @@ static void dpaa_eth_napi_disable(struct } } @@ -189,7 +189,7 @@ Signed-off-by: David S. Miller static int dpaa_open(struct net_device *net_dev) { struct mac_device *mac_dev; -@@ -2967,7 +2925,8 @@ static int dpaa_open(struct net_device * +@@ -2982,7 +2940,8 @@ static int dpaa_open(struct net_device * mac_dev = priv->mac_dev; dpaa_eth_napi_enable(priv); @@ -199,7 +199,7 @@ Signed-off-by: David S. Miller if (err) goto phy_init_failed; -@@ -2982,7 +2941,7 @@ static int dpaa_open(struct net_device * +@@ -2997,7 +2956,7 @@ static int dpaa_open(struct net_device * netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err); goto mac_start_failed; } @@ -208,7 +208,7 @@ Signed-off-by: David S. Miller netif_tx_start_all_queues(net_dev); -@@ -2991,6 +2950,7 @@ static int dpaa_open(struct net_device * +@@ -3006,6 +2965,7 @@ static int dpaa_open(struct net_device * mac_start_failed: for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) fman_port_disable(mac_dev->port[i]); @@ -216,7 +216,7 @@ Signed-off-by: David S. Miller phy_init_failed: dpaa_eth_napi_disable(priv); -@@ -3146,10 +3106,12 @@ static int dpaa_ts_ioctl(struct net_devi +@@ -3161,10 +3121,12 @@ static int dpaa_ts_ioctl(struct net_devi static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd) { int ret = -EINVAL; @@ -230,7 +230,7 @@ Signed-off-by: David S. Miller } if (cmd == SIOCSHWTSTAMP) -@@ -3552,6 +3514,7 @@ static int dpaa_remove(struct platform_d +@@ -3569,6 +3531,7 @@ static int dpaa_remove(struct platform_d dev_set_drvdata(dev, NULL); unregister_netdev(net_dev); diff --git a/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch b/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch index 31fde5f18ed92e..6bd0151323d29a 100644 --- a/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch +++ b/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch @@ -202,7 +202,7 @@ Signed-off-by: Jakub Kicinski .mac_link_up = am65_cpsw_nuss_mac_link_up, --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c -@@ -1736,7 +1736,6 @@ static void axienet_mac_link_up(struct p +@@ -1741,7 +1741,6 @@ static void axienet_mac_link_up(struct p } static const struct phylink_mac_ops axienet_phylink_ops = { diff --git a/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch b/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch index 5572850e95a8fe..f94a514f319eda 100644 --- a/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch +++ b/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch @@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski supported = mac_dev->phylink_config.supported_interfaces; --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c -@@ -1631,7 +1631,7 @@ static void axienet_pcs_an_restart(struc +@@ -1636,7 +1636,7 @@ static void axienet_pcs_an_restart(struc phylink_mii_c22_pcs_an_restart(pcs_phy); } @@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski phy_interface_t interface, const unsigned long *advertising, bool permit_pause_to_mac) -@@ -1653,7 +1653,8 @@ static int axienet_pcs_config(struct phy +@@ -1658,7 +1658,8 @@ static int axienet_pcs_config(struct phy } } @@ -72,7 +72,7 @@ Signed-off-by: Jakub Kicinski if (ret < 0) netdev_warn(ndev, "Failed to configure PCS: %d\n", ret); -@@ -2129,6 +2130,7 @@ static int axienet_probe(struct platform +@@ -2138,6 +2139,7 @@ static int axienet_probe(struct platform } of_node_put(np); lp->pcs.ops = &axienet_pcs_ops; diff --git a/target/linux/generic/backport-6.1/796-v6.5-01-usbnet-ipheth-fix-risk-of-NULL-pointer-deallocation.patch b/target/linux/generic/backport-6.1/796-v6.5-01-usbnet-ipheth-fix-risk-of-NULL-pointer-deallocation.patch index d9d6f36fcef385..da97cdad56b74e 100644 --- a/target/linux/generic/backport-6.1/796-v6.5-01-usbnet-ipheth-fix-risk-of-NULL-pointer-deallocation.patch +++ b/target/linux/generic/backport-6.1/796-v6.5-01-usbnet-ipheth-fix-risk-of-NULL-pointer-deallocation.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/usb/ipheth.c +++ b/drivers/net/usb/ipheth.c -@@ -510,8 +510,8 @@ err_register_netdev: +@@ -511,8 +511,8 @@ err_register_netdev: ipheth_free_urbs(dev); err_alloc_urbs: err_get_macaddr: diff --git a/target/linux/generic/backport-6.1/796-v6.5-02-usbnet-ipheth-transmit-URBs-without-trailing-padding.patch b/target/linux/generic/backport-6.1/796-v6.5-02-usbnet-ipheth-transmit-URBs-without-trailing-padding.patch index adfec356d9faee..383fd056668350 100644 --- a/target/linux/generic/backport-6.1/796-v6.5-02-usbnet-ipheth-transmit-URBs-without-trailing-padding.patch +++ b/target/linux/generic/backport-6.1/796-v6.5-02-usbnet-ipheth-transmit-URBs-without-trailing-padding.patch @@ -19,7 +19,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/usb/ipheth.c +++ b/drivers/net/usb/ipheth.c -@@ -373,12 +373,10 @@ static netdev_tx_t ipheth_tx(struct sk_b +@@ -374,12 +374,10 @@ static netdev_tx_t ipheth_tx(struct sk_b } memcpy(dev->tx_buf, skb->data, skb->len); diff --git a/target/linux/generic/backport-6.1/796-v6.5-03-usbnet-ipheth-add-CDC-NCM-support.patch b/target/linux/generic/backport-6.1/796-v6.5-03-usbnet-ipheth-add-CDC-NCM-support.patch index e3f2b9c3311e2f..9fb507ffba67ba 100644 --- a/target/linux/generic/backport-6.1/796-v6.5-03-usbnet-ipheth-add-CDC-NCM-support.patch +++ b/target/linux/generic/backport-6.1/796-v6.5-03-usbnet-ipheth-add-CDC-NCM-support.patch @@ -256,7 +256,7 @@ Signed-off-by: David S. Miller ipheth_rx_submit(dev, GFP_ATOMIC); } -@@ -310,6 +411,27 @@ static int ipheth_get_macaddr(struct iph +@@ -311,6 +412,27 @@ static int ipheth_get_macaddr(struct iph return retval; } @@ -284,7 +284,7 @@ Signed-off-by: David S. Miller static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags) { struct usb_device *udev = dev->udev; -@@ -317,7 +439,7 @@ static int ipheth_rx_submit(struct iphet +@@ -318,7 +440,7 @@ static int ipheth_rx_submit(struct iphet usb_fill_bulk_urb(dev->rx_urb, udev, usb_rcvbulkpipe(udev, dev->bulk_in), @@ -293,7 +293,7 @@ Signed-off-by: David S. Miller ipheth_rcvbulk_callback, dev); dev->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; -@@ -365,7 +487,7 @@ static netdev_tx_t ipheth_tx(struct sk_b +@@ -366,7 +488,7 @@ static netdev_tx_t ipheth_tx(struct sk_b int retval; /* Paranoid */ @@ -302,7 +302,7 @@ Signed-off-by: David S. Miller WARN(1, "%s: skb too large: %d bytes\n", __func__, skb->len); dev->net->stats.tx_dropped++; dev_kfree_skb_any(skb); -@@ -448,6 +570,8 @@ static int ipheth_probe(struct usb_inter +@@ -449,6 +571,8 @@ static int ipheth_probe(struct usb_inter dev->net = netdev; dev->intf = intf; dev->confirmed_pairing = false; @@ -311,7 +311,7 @@ Signed-off-by: David S. Miller /* Set up endpoints */ hintf = usb_altnum_to_altsetting(intf, IPHETH_ALT_INTFNUM); if (hintf == NULL) { -@@ -479,6 +603,12 @@ static int ipheth_probe(struct usb_inter +@@ -480,6 +604,12 @@ static int ipheth_probe(struct usb_inter if (retval) goto err_get_macaddr; diff --git a/target/linux/generic/backport-6.1/797-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch b/target/linux/generic/backport-6.1/797-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch index 36083bbaf53f0e..0afc69fa44cf5c 100644 --- a/target/linux/generic/backport-6.1/797-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch +++ b/target/linux/generic/backport-6.1/797-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch @@ -51,7 +51,7 @@ Signed-off-by: David S. Miller static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) { u16 reg, val; -@@ -4501,7 +4513,7 @@ static const struct mv88e6xxx_ops mv88e6 +@@ -4502,7 +4514,7 @@ static const struct mv88e6xxx_ops mv88e6 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, .stu_getnext = mv88e6352_g1_stu_getnext, .stu_loadpurge = mv88e6352_g1_stu_loadpurge, @@ -60,7 +60,7 @@ Signed-off-by: David S. Miller }; static const struct mv88e6xxx_ops mv88e6172_ops = { -@@ -4604,7 +4616,7 @@ static const struct mv88e6xxx_ops mv88e6 +@@ -4605,7 +4617,7 @@ static const struct mv88e6xxx_ops mv88e6 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, .stu_getnext = mv88e6352_g1_stu_getnext, .stu_loadpurge = mv88e6352_g1_stu_loadpurge, @@ -69,7 +69,7 @@ Signed-off-by: David S. Miller }; static const struct mv88e6xxx_ops mv88e6176_ops = { -@@ -5281,7 +5293,7 @@ static const struct mv88e6xxx_ops mv88e6 +@@ -5282,7 +5294,7 @@ static const struct mv88e6xxx_ops mv88e6 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, .stu_getnext = mv88e6352_g1_stu_getnext, .stu_loadpurge = mv88e6352_g1_stu_loadpurge, @@ -78,7 +78,7 @@ Signed-off-by: David S. Miller }; static const struct mv88e6xxx_ops mv88e6351_ops = { -@@ -5327,7 +5339,7 @@ static const struct mv88e6xxx_ops mv88e6 +@@ -5328,7 +5340,7 @@ static const struct mv88e6xxx_ops mv88e6 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, .avb_ops = &mv88e6352_avb_ops, .ptp_ops = &mv88e6352_ptp_ops, diff --git a/target/linux/generic/backport-6.1/804-v6.5-11-leds-trigger-netdev-expose-netdev-trigger-modes-in-l.patch b/target/linux/generic/backport-6.1/804-v6.5-11-leds-trigger-netdev-expose-netdev-trigger-modes-in-l.patch index 70aed850d13b4c..f23504b1d03256 100644 --- a/target/linux/generic/backport-6.1/804-v6.5-11-leds-trigger-netdev-expose-netdev-trigger-modes-in-l.patch +++ b/target/linux/generic/backport-6.1/804-v6.5-11-leds-trigger-netdev-expose-netdev-trigger-modes-in-l.patch @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller int current_brightness; --- a/include/linux/leds.h +++ b/include/linux/leds.h -@@ -527,6 +527,16 @@ static inline void *led_get_trigger_data +@@ -525,6 +525,16 @@ led_trigger_get_brightness(const struct #endif /* CONFIG_LEDS_TRIGGERS */ diff --git a/target/linux/generic/backport-6.1/805-v6.5-01-leds-trigger-netdev-add-additional-specific-link-spe.patch b/target/linux/generic/backport-6.1/805-v6.5-01-leds-trigger-netdev-add-additional-specific-link-spe.patch index 1c564b38970b84..38989a2a631696 100644 --- a/target/linux/generic/backport-6.1/805-v6.5-01-leds-trigger-netdev-add-additional-specific-link-spe.patch +++ b/target/linux/generic/backport-6.1/805-v6.5-01-leds-trigger-netdev-add-additional-specific-link-spe.patch @@ -230,7 +230,7 @@ Signed-off-by: Jakub Kicinski /* base state is ON (link present) */ --- a/include/linux/leds.h +++ b/include/linux/leds.h -@@ -530,6 +530,9 @@ static inline void *led_get_trigger_data +@@ -528,6 +528,9 @@ led_trigger_get_brightness(const struct /* Trigger specific enum */ enum led_trigger_netdev_modes { TRIGGER_NETDEV_LINK = 0, diff --git a/target/linux/generic/backport-6.1/805-v6.5-02-leds-trigger-netdev-add-additional-specific-link-dup.patch b/target/linux/generic/backport-6.1/805-v6.5-02-leds-trigger-netdev-add-additional-specific-link-dup.patch index a5ab4618281861..90213269914247 100644 --- a/target/linux/generic/backport-6.1/805-v6.5-02-leds-trigger-netdev-add-additional-specific-link-dup.patch +++ b/target/linux/generic/backport-6.1/805-v6.5-02-leds-trigger-netdev-add-additional-specific-link-dup.patch @@ -127,7 +127,7 @@ Signed-off-by: Jakub Kicinski /* base state is ON (link present) */ --- a/include/linux/leds.h +++ b/include/linux/leds.h -@@ -533,6 +533,8 @@ enum led_trigger_netdev_modes { +@@ -531,6 +531,8 @@ enum led_trigger_netdev_modes { TRIGGER_NETDEV_LINK_10, TRIGGER_NETDEV_LINK_100, TRIGGER_NETDEV_LINK_1000, diff --git a/target/linux/generic/backport-6.1/807-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch b/target/linux/generic/backport-6.1/807-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch index cadc70fd73b2e9..428b7c9b799002 100644 --- a/target/linux/generic/backport-6.1/807-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch +++ b/target/linux/generic/backport-6.1/807-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch @@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -5998,7 +5998,8 @@ static const struct mv88e6xxx_info mv88e +@@ -5999,7 +5999,8 @@ static const struct mv88e6xxx_info mv88e .name = "Marvell 88E6191X", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ @@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski .max_vid = 8191, .max_sid = 63, .port_base_addr = 0x0, -@@ -6021,7 +6022,8 @@ static const struct mv88e6xxx_info mv88e +@@ -6022,7 +6023,8 @@ static const struct mv88e6xxx_info mv88e .name = "Marvell 88E6193X", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski .max_vid = 8191, .max_sid = 63, .port_base_addr = 0x0, -@@ -6340,7 +6342,8 @@ static const struct mv88e6xxx_info mv88e +@@ -6341,7 +6343,8 @@ static const struct mv88e6xxx_info mv88e .name = "Marvell 88E6393X", .num_databases = 4096, .num_ports = 11, /* 10 + Z80 */ diff --git a/target/linux/generic/backport-6.1/807-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch b/target/linux/generic/backport-6.1/807-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch index 471e6a3903d49a..9a294b59fcbfd3 100644 --- a/target/linux/generic/backport-6.1/807-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch +++ b/target/linux/generic/backport-6.1/807-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch @@ -58,7 +58,7 @@ Signed-off-by: Jakub Kicinski } } -@@ -6285,6 +6291,32 @@ static const struct mv88e6xxx_info mv88e +@@ -6286,6 +6292,32 @@ static const struct mv88e6xxx_info mv88e .ptp_support = true, .ops = &mv88e6352_ops, }, diff --git a/target/linux/generic/backport-6.1/810-v6.3-i915-Move-list_count-to-list.h-as-list_count_nodes-f.patch b/target/linux/generic/backport-6.1/810-v6.3-i915-Move-list_count-to-list.h-as-list_count_nodes-f.patch index 5c4206da145761..998e4534436781 100644 --- a/target/linux/generic/backport-6.1/810-v6.3-i915-Move-list_count-to-list.h-as-list_count_nodes-f.patch +++ b/target/linux/generic/backport-6.1/810-v6.3-i915-Move-list_count-to-list.h-as-list_count_nodes-f.patch @@ -20,7 +20,7 @@ Signed-off-by: Greg Kroah-Hartman --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c -@@ -4157,17 +4157,6 @@ void intel_execlists_show_requests(struc +@@ -4153,17 +4153,6 @@ void intel_execlists_show_requests(struc spin_unlock_irqrestore(&sched_engine->lock, flags); } @@ -38,7 +38,7 @@ Signed-off-by: Greg Kroah-Hartman void intel_execlists_dump_active_requests(struct intel_engine_cs *engine, struct i915_request *hung_rq, struct drm_printer *m) -@@ -4178,8 +4167,8 @@ void intel_execlists_dump_active_request +@@ -4174,8 +4163,8 @@ void intel_execlists_dump_active_request intel_engine_dump_active_requests(&engine->sched_engine->requests, hung_rq, m); diff --git a/target/linux/generic/backport-6.1/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch b/target/linux/generic/backport-6.1/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch index f568c3f6ce5886..b4cb96d24832ef 100644 --- a/target/linux/generic/backport-6.1/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch +++ b/target/linux/generic/backport-6.1/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch @@ -24,7 +24,7 @@ Signed-off-by: Greg Kroah-Hartman --- a/include/linux/of.h +++ b/include/linux/of.h -@@ -1009,6 +1009,31 @@ static inline int of_parse_phandle_with_ +@@ -1011,6 +1011,31 @@ static inline int of_parse_phandle_with_ } /** diff --git a/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch b/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch index c11ccc6c3e0280..69d316b8fa3ce7 100644 --- a/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch +++ b/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch @@ -161,7 +161,7 @@ Signed-off-by: Greg Kroah-Hartman goto err_out; --- a/include/linux/of.h +++ b/include/linux/of.h -@@ -362,7 +362,8 @@ extern int of_n_addr_cells(struct device +@@ -364,7 +364,8 @@ extern int of_n_addr_cells(struct device extern int of_n_size_cells(struct device_node *np); extern const struct of_device_id *of_match_node( const struct of_device_id *matches, const struct device_node *node); diff --git a/target/linux/generic/backport-6.1/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch b/target/linux/generic/backport-6.1/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch index 39a84161a27c75..16baed118750e7 100644 --- a/target/linux/generic/backport-6.1/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch +++ b/target/linux/generic/backport-6.1/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch @@ -135,7 +135,7 @@ Signed-off-by: Greg Kroah-Hartman +} --- a/include/linux/of.h +++ b/include/linux/of.h -@@ -374,6 +374,9 @@ extern int of_parse_phandle_with_args_ma +@@ -376,6 +376,9 @@ extern int of_parse_phandle_with_args_ma extern int of_count_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name); @@ -145,7 +145,7 @@ Signed-off-by: Greg Kroah-Hartman /* phandle iterator functions */ extern int of_phandle_iterator_init(struct of_phandle_iterator *it, const struct device_node *np, -@@ -731,6 +734,12 @@ static inline int of_count_phandle_with_ +@@ -733,6 +736,12 @@ static inline int of_count_phandle_with_ return -ENOSYS; } diff --git a/target/linux/generic/backport-6.1/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch b/target/linux/generic/backport-6.1/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch index 046c1df5615f62..67dcea0d19d0fc 100644 --- a/target/linux/generic/backport-6.1/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch +++ b/target/linux/generic/backport-6.1/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch @@ -109,7 +109,7 @@ Signed-off-by: Greg Kroah-Hartman +EXPORT_SYMBOL_GPL(of_request_module); --- a/include/linux/of.h +++ b/include/linux/of.h -@@ -376,6 +376,7 @@ extern int of_count_phandle_with_args(co +@@ -378,6 +378,7 @@ extern int of_count_phandle_with_args(co /* module functions */ extern ssize_t of_modalias(const struct device_node *np, char *str, ssize_t len); @@ -117,7 +117,7 @@ Signed-off-by: Greg Kroah-Hartman /* phandle iterator functions */ extern int of_phandle_iterator_init(struct of_phandle_iterator *it, -@@ -739,6 +740,11 @@ static inline ssize_t of_modalias(const +@@ -741,6 +742,11 @@ static inline ssize_t of_modalias(const { return -ENODEV; } diff --git a/target/linux/generic/backport-6.1/830-04-v6.5-cpufreq-qcom-nvmem-use-SoC-ID-s-from-bindings.patch b/target/linux/generic/backport-6.1/830-04-v6.5-cpufreq-qcom-nvmem-use-SoC-ID-s-from-bindings.patch index e0f10f7642fb30..25a718bd7eb4f2 100644 --- a/target/linux/generic/backport-6.1/830-04-v6.5-cpufreq-qcom-nvmem-use-SoC-ID-s-from-bindings.patch +++ b/target/linux/generic/backport-6.1/830-04-v6.5-cpufreq-qcom-nvmem-use-SoC-ID-s-from-bindings.patch @@ -32,7 +32,7 @@ Link: https://lore.kernel.org/r/20230526204802.3081168-4-robimarko@gmail.com enum _msm8996_version { MSM8996_V3, -@@ -153,12 +148,12 @@ static enum _msm8996_version qcom_cpufre +@@ -157,12 +152,12 @@ static enum _msm8996_version qcom_cpufre msm_id++; switch ((enum _msm_id)*msm_id) { diff --git a/target/linux/generic/backport-6.1/830-05-v6.5-cpufreq-qcom-nvmem-use-helper-to-get-SMEM-SoC-ID.patch b/target/linux/generic/backport-6.1/830-05-v6.5-cpufreq-qcom-nvmem-use-helper-to-get-SMEM-SoC-ID.patch index 93e776f62cecb2..49d222662c9a81 100644 --- a/target/linux/generic/backport-6.1/830-05-v6.5-cpufreq-qcom-nvmem-use-helper-to-get-SMEM-SoC-ID.patch +++ b/target/linux/generic/backport-6.1/830-05-v6.5-cpufreq-qcom-nvmem-use-helper-to-get-SMEM-SoC-ID.patch @@ -36,7 +36,7 @@ Link: https://lore.kernel.org/r/20230526204802.3081168-5-robimarko@gmail.com struct qcom_cpufreq_drv; struct qcom_cpufreq_match_data { -@@ -134,60 +126,32 @@ static void get_krait_bin_format_b(struc +@@ -138,60 +130,32 @@ static void get_krait_bin_format_b(struc dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); } diff --git a/target/linux/generic/backport-6.1/834-v6.8-leds-trigger-netdev-Extend-speeds-up-to-10G.patch b/target/linux/generic/backport-6.1/834-v6.8-leds-trigger-netdev-Extend-speeds-up-to-10G.patch index 1c8e014a1aebf7..9d5a928f5f7cb2 100644 --- a/target/linux/generic/backport-6.1/834-v6.8-leds-trigger-netdev-Extend-speeds-up-to-10G.patch +++ b/target/linux/generic/backport-6.1/834-v6.8-leds-trigger-netdev-Extend-speeds-up-to-10G.patch @@ -99,7 +99,7 @@ Signed-off-by: Lee Jones interval = jiffies_to_msecs( --- a/include/linux/leds.h +++ b/include/linux/leds.h -@@ -533,6 +533,9 @@ enum led_trigger_netdev_modes { +@@ -531,6 +531,9 @@ enum led_trigger_netdev_modes { TRIGGER_NETDEV_LINK_10, TRIGGER_NETDEV_LINK_100, TRIGGER_NETDEV_LINK_1000, diff --git a/target/linux/generic/backport-6.1/851-v6.2-bus-mhi-host-pci_generic-Add-HP-variant-of-T99W175.patch b/target/linux/generic/backport-6.1/851-v6.2-bus-mhi-host-pci_generic-Add-HP-variant-of-T99W175.patch index 0dabc48bfad84b..6f9fc71a710956 100644 --- a/target/linux/generic/backport-6.1/851-v6.2-bus-mhi-host-pci_generic-Add-HP-variant-of-T99W175.patch +++ b/target/linux/generic/backport-6.1/851-v6.2-bus-mhi-host-pci_generic-Add-HP-variant-of-T99W175.patch @@ -22,7 +22,7 @@ Signed-off-by: Manivannan Sadhasivam --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c -@@ -596,6 +596,9 @@ static const struct pci_device_id mhi_pc +@@ -599,6 +599,9 @@ static const struct pci_device_id mhi_pc /* MV32-WB (Cinterion) */ { PCI_DEVICE(0x1269, 0x00bb), .driver_data = (kernel_ulong_t) &mhi_mv32_info }, diff --git a/target/linux/generic/backport-6.1/852-v6.2-bus-mhi-host-pci_generic-Add-definition-for-some-VID.patch b/target/linux/generic/backport-6.1/852-v6.2-bus-mhi-host-pci_generic-Add-definition-for-some-VID.patch index fbf6c8a5015713..12419fbe397ec7 100644 --- a/target/linux/generic/backport-6.1/852-v6.2-bus-mhi-host-pci_generic-Add-definition-for-some-VID.patch +++ b/target/linux/generic/backport-6.1/852-v6.2-bus-mhi-host-pci_generic-Add-definition-for-some-VID.patch @@ -28,7 +28,7 @@ Signed-off-by: Manivannan Sadhasivam /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration -@@ -557,11 +561,11 @@ static const struct pci_device_id mhi_pc +@@ -560,11 +564,11 @@ static const struct pci_device_id mhi_pc .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, @@ -43,7 +43,7 @@ Signed-off-by: Manivannan Sadhasivam .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), -@@ -585,16 +589,16 @@ static const struct pci_device_id mhi_pc +@@ -588,16 +592,16 @@ static const struct pci_device_id mhi_pc { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info }, /* MV31-W (Cinterion) */ diff --git a/target/linux/generic/backport-6.1/853-v6.2-bus-mhi-host-pci_generic-Drop-redundant-pci_enable_p.patch b/target/linux/generic/backport-6.1/853-v6.2-bus-mhi-host-pci_generic-Drop-redundant-pci_enable_p.patch index 2f5a0ac11dadf9..943227d2a809f6 100644 --- a/target/linux/generic/backport-6.1/853-v6.2-bus-mhi-host-pci_generic-Drop-redundant-pci_enable_p.patch +++ b/target/linux/generic/backport-6.1/853-v6.2-bus-mhi-host-pci_generic-Drop-redundant-pci_enable_p.patch @@ -36,7 +36,7 @@ Signed-off-by: Manivannan Sadhasivam #include #include #include -@@ -901,11 +900,9 @@ static int mhi_pci_probe(struct pci_dev +@@ -904,11 +903,9 @@ static int mhi_pci_probe(struct pci_dev mhi_pdev->pci_state = pci_store_saved_state(pdev); pci_load_saved_state(pdev, NULL); @@ -49,7 +49,7 @@ Signed-off-by: Manivannan Sadhasivam /* MHI bus does not power up the controller by default */ err = mhi_prepare_for_power_up(mhi_cntrl); -@@ -939,8 +936,6 @@ err_unprepare: +@@ -942,8 +939,6 @@ err_unprepare: mhi_unprepare_after_power_down(mhi_cntrl); err_unregister: mhi_unregister_controller(mhi_cntrl); @@ -58,7 +58,7 @@ Signed-off-by: Manivannan Sadhasivam return err; } -@@ -963,7 +958,6 @@ static void mhi_pci_remove(struct pci_de +@@ -966,7 +961,6 @@ static void mhi_pci_remove(struct pci_de pm_runtime_get_noresume(&pdev->dev); mhi_unregister_controller(mhi_cntrl); diff --git a/target/linux/generic/backport-6.1/854-v6.4-bus-mhi-pci_generic-Add-Foxconn-T99W510.patch b/target/linux/generic/backport-6.1/854-v6.4-bus-mhi-pci_generic-Add-Foxconn-T99W510.patch index f757ca28e5e533..8ec6f3e76fe3e2 100644 --- a/target/linux/generic/backport-6.1/854-v6.4-bus-mhi-pci_generic-Add-Foxconn-T99W510.patch +++ b/target/linux/generic/backport-6.1/854-v6.4-bus-mhi-pci_generic-Add-Foxconn-T99W510.patch @@ -31,7 +31,7 @@ Signed-off-by: Manivannan Sadhasivam static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { .name = "foxconn-sdx55", .fw = "qcom/sdx55m/sbl1.mbn", -@@ -587,6 +596,15 @@ static const struct pci_device_id mhi_pc +@@ -590,6 +599,15 @@ static const struct pci_device_id mhi_pc /* T99W373 (sdx62) */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info }, diff --git a/target/linux/generic/backport-6.1/856-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-EM1.patch b/target/linux/generic/backport-6.1/856-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-EM1.patch index 5c15eec712c2d6..2e01d4fd650250 100644 --- a/target/linux/generic/backport-6.1/856-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-EM1.patch +++ b/target/linux/generic/backport-6.1/856-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-EM1.patch @@ -23,7 +23,7 @@ Signed-off-by: Manivannan Sadhasivam --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c -@@ -591,6 +591,8 @@ static const struct pci_device_id mhi_pc +@@ -594,6 +594,8 @@ static const struct pci_device_id mhi_pc .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, diff --git a/target/linux/generic/backport-6.1/857-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-RM5.patch b/target/linux/generic/backport-6.1/857-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-RM5.patch index 5922207e294199..f547eb972ffadf 100644 --- a/target/linux/generic/backport-6.1/857-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-RM5.patch +++ b/target/linux/generic/backport-6.1/857-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-RM5.patch @@ -37,7 +37,7 @@ Signed-off-by: Manivannan Sadhasivam static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), -@@ -591,6 +601,9 @@ static const struct pci_device_id mhi_pc +@@ -594,6 +604,9 @@ static const struct pci_device_id mhi_pc .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, diff --git a/target/linux/generic/backport-6.1/858-v6.6-bus-mhi-host-pci_generic-Add-support-for-Dell-DW5932.patch b/target/linux/generic/backport-6.1/858-v6.6-bus-mhi-host-pci_generic-Add-support-for-Dell-DW5932.patch index bb7b3c3ffc7ac3..ba0e156a8cdbea 100644 --- a/target/linux/generic/backport-6.1/858-v6.6-bus-mhi-host-pci_generic-Add-support-for-Dell-DW5932.patch +++ b/target/linux/generic/backport-6.1/858-v6.6-bus-mhi-host-pci_generic-Add-support-for-Dell-DW5932.patch @@ -19,7 +19,7 @@ Signed-off-by: Manivannan Sadhasivam --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c -@@ -638,6 +638,12 @@ static const struct pci_device_id mhi_pc +@@ -641,6 +641,12 @@ static const struct pci_device_id mhi_pc /* T99W510 (sdx24), variant 3 */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info }, diff --git a/target/linux/generic/backport-6.1/859-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-RM5.patch b/target/linux/generic/backport-6.1/859-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-RM5.patch index c0dfe01e327d38..a09ae6fa478a46 100644 --- a/target/linux/generic/backport-6.1/859-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-RM5.patch +++ b/target/linux/generic/backport-6.1/859-v6.6-bus-mhi-host-pci_generic-Add-support-for-Quectel-RM5.patch @@ -24,7 +24,7 @@ Signed-off-by: Manivannan Sadhasivam --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c -@@ -604,6 +604,9 @@ static const struct pci_device_id mhi_pc +@@ -607,6 +607,9 @@ static const struct pci_device_id mhi_pc /* RM520N-GL (sdx6x), eSIM */ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, diff --git a/target/linux/generic/backport-6.1/894-v6.8-net-ethtool-implement-ethtool_puts.patch b/target/linux/generic/backport-6.1/894-v6.8-net-ethtool-implement-ethtool_puts.patch index 5094a6d7747a78..379a4fc7c074ae 100644 --- a/target/linux/generic/backport-6.1/894-v6.8-net-ethtool-implement-ethtool_puts.patch +++ b/target/linux/generic/backport-6.1/894-v6.8-net-ethtool-implement-ethtool_puts.patch @@ -123,7 +123,7 @@ Signed-off-by: Justin Stitt #endif /* _LINUX_ETHTOOL_H */ --- a/net/ethtool/ioctl.c +++ b/net/ethtool/ioctl.c -@@ -1974,6 +1974,13 @@ __printf(2, 3) void ethtool_sprintf(u8 * +@@ -1977,6 +1977,13 @@ __printf(2, 3) void ethtool_sprintf(u8 * } EXPORT_SYMBOL(ethtool_sprintf); diff --git a/target/linux/generic/hack-6.1/230-openwrt_lzma_options.patch b/target/linux/generic/hack-6.1/230-openwrt_lzma_options.patch index 55530c5c7e4e05..ddf7f5e0c0c297 100644 --- a/target/linux/generic/hack-6.1/230-openwrt_lzma_options.patch +++ b/target/linux/generic/hack-6.1/230-openwrt_lzma_options.patch @@ -23,7 +23,7 @@ Signed-off-by: Imre Kaloz { {0x02, 0x21}, "lz4", unlz4 }, --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib -@@ -443,10 +443,10 @@ quiet_cmd_bzip2_with_size = BZIP2 $@ +@@ -447,10 +447,10 @@ quiet_cmd_bzip2_with_size = BZIP2 $@ # --------------------------------------------------------------------------- quiet_cmd_lzma = LZMA $@ diff --git a/target/linux/generic/hack-6.1/253-ksmbd-config.patch b/target/linux/generic/hack-6.1/253-ksmbd-config.patch index a57c914180b84e..c968daf081c762 100644 --- a/target/linux/generic/hack-6.1/253-ksmbd-config.patch +++ b/target/linux/generic/hack-6.1/253-ksmbd-config.patch @@ -10,7 +10,7 @@ Subject: [PATCH] Kconfig: add tristate for OID and ASNI string --- a/init/Kconfig +++ b/init/Kconfig -@@ -2013,7 +2013,7 @@ config PADATA +@@ -2017,7 +2017,7 @@ config PADATA bool config ASN1 diff --git a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch index 2729a0ec38ec01..6e318a6e9a9da0 100644 --- a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch @@ -10,7 +10,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c -@@ -1082,12 +1082,18 @@ static const struct usb_device_id produc +@@ -1083,12 +1083,18 @@ static const struct usb_device_id produc USB_DEVICE_AND_INTERFACE_INFO(0x03f0, 0x581d, USB_CLASS_VENDOR_SPEC, 1, 7), .driver_info = (unsigned long)&qmi_wwan_info, }, @@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1156,6 +1161,11 @@ static const struct usb_device_id option +@@ -1158,6 +1163,11 @@ static const struct usb_device_id option { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */ .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) }, @@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support /* Quectel products using Qualcomm vendor ID */ { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)}, { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20), -@@ -1197,6 +1207,11 @@ static const struct usb_device_id option +@@ -1199,6 +1209,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, diff --git a/target/linux/generic/hack-6.1/902-debloat_proc.patch b/target/linux/generic/hack-6.1/902-debloat_proc.patch index ee3caa9f473bbc..2bc86fa1e27f8d 100644 --- a/target/linux/generic/hack-6.1/902-debloat_proc.patch +++ b/target/linux/generic/hack-6.1/902-debloat_proc.patch @@ -29,7 +29,7 @@ Signed-off-by: Felix Fietkau --- a/fs/locks.c +++ b/fs/locks.c -@@ -2909,6 +2909,8 @@ static const struct seq_operations locks +@@ -2907,6 +2907,8 @@ static const struct seq_operations locks static int __init proc_locks_init(void) { @@ -235,7 +235,7 @@ Signed-off-by: Felix Fietkau if (!pe) --- a/mm/vmalloc.c +++ b/mm/vmalloc.c -@@ -4222,6 +4222,8 @@ static const struct seq_operations vmall +@@ -4215,6 +4215,8 @@ static const struct seq_operations vmall static int __init proc_vmalloc_init(void) { @@ -341,7 +341,7 @@ Signed-off-by: Felix Fietkau --- a/net/ipv4/fib_trie.c +++ b/net/ipv4/fib_trie.c -@@ -3036,11 +3036,13 @@ static const struct seq_operations fib_r +@@ -3037,11 +3037,13 @@ static const struct seq_operations fib_r int __net_init fib_proc_init(struct net *net) { @@ -357,7 +357,7 @@ Signed-off-by: Felix Fietkau fib_triestat_seq_show, NULL)) goto out2; -@@ -3051,17 +3053,21 @@ int __net_init fib_proc_init(struct net +@@ -3052,17 +3054,21 @@ int __net_init fib_proc_init(struct net return 0; out3: diff --git a/target/linux/generic/hack-6.1/904-debloat_dma_buf.patch b/target/linux/generic/hack-6.1/904-debloat_dma_buf.patch index 0a73146d022354..8b6bd6a7862af4 100644 --- a/target/linux/generic/hack-6.1/904-debloat_dma_buf.patch +++ b/target/linux/generic/hack-6.1/904-debloat_dma_buf.patch @@ -73,7 +73,7 @@ Signed-off-by: Felix Fietkau +MODULE_LICENSE("GPL"); --- a/kernel/sched/core.c +++ b/kernel/sched/core.c -@@ -4366,6 +4366,7 @@ int wake_up_state(struct task_struct *p, +@@ -4363,6 +4363,7 @@ int wake_up_state(struct task_struct *p, { return try_to_wake_up(p, state, 0); } diff --git a/target/linux/generic/hack-6.1/911-kobject_add_broadcast_uevent.patch b/target/linux/generic/hack-6.1/911-kobject_add_broadcast_uevent.patch index 9854585d25913d..c828ecd450c8b9 100644 --- a/target/linux/generic/hack-6.1/911-kobject_add_broadcast_uevent.patch +++ b/target/linux/generic/hack-6.1/911-kobject_add_broadcast_uevent.patch @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau #endif /* _KOBJECT_H_ */ --- a/lib/kobject_uevent.c +++ b/lib/kobject_uevent.c -@@ -691,6 +691,43 @@ int add_uevent_var(struct kobj_uevent_en +@@ -706,6 +706,43 @@ int add_uevent_var(struct kobj_uevent_en EXPORT_SYMBOL_GPL(add_uevent_var); #if defined(CONFIG_NET) diff --git a/target/linux/generic/hack-6.1/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch b/target/linux/generic/hack-6.1/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch index f2ae028aa1f0b0..3476aa6edb09a9 100644 --- a/target/linux/generic/hack-6.1/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch +++ b/target/linux/generic/hack-6.1/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch @@ -19,7 +19,7 @@ Signed-off-by: Rafał Miłecki --- a/drivers/base/core.c +++ b/drivers/base/core.c -@@ -1717,7 +1717,7 @@ static void device_links_purge(struct de +@@ -1718,7 +1718,7 @@ static void device_links_purge(struct de #define FW_DEVLINK_FLAGS_RPM (FW_DEVLINK_FLAGS_ON | \ DL_FLAG_PM_RUNTIME) diff --git a/target/linux/generic/hack-6.1/952-add-net-conntrack-events-support-multiple-registrant.patch b/target/linux/generic/hack-6.1/952-add-net-conntrack-events-support-multiple-registrant.patch index b58aed506e716d..45797cb8e1113a 100644 --- a/target/linux/generic/hack-6.1/952-add-net-conntrack-events-support-multiple-registrant.patch +++ b/target/linux/generic/hack-6.1/952-add-net-conntrack-events-support-multiple-registrant.patch @@ -319,7 +319,7 @@ Signed-off-by: Zhi Chen struct nf_conn *ct = item->ct; struct sk_buff *skb; unsigned int type; -@@ -3754,11 +3761,17 @@ static int ctnetlink_stat_exp_cpu(struct +@@ -3755,11 +3762,17 @@ static int ctnetlink_stat_exp_cpu(struct } #ifdef CONFIG_NF_CONNTRACK_EVENTS @@ -337,7 +337,7 @@ Signed-off-by: Zhi Chen static const struct nfnl_callback ctnl_cb[IPCTNL_MSG_MAX] = { [IPCTNL_MSG_CT_NEW] = { -@@ -3857,8 +3870,12 @@ static int __net_init ctnetlink_net_init +@@ -3858,8 +3871,12 @@ static int __net_init ctnetlink_net_init static void ctnetlink_net_pre_exit(struct net *net) { #ifdef CONFIG_NF_CONNTRACK_EVENTS diff --git a/target/linux/generic/pending-6.1/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch b/target/linux/generic/pending-6.1/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch index edee0e46a56897..8fea984a330434 100644 --- a/target/linux/generic/pending-6.1/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch +++ b/target/linux/generic/pending-6.1/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch @@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf --- a/mm/page_alloc.c +++ b/mm/page_alloc.c -@@ -7903,7 +7903,7 @@ static void __init alloc_node_mem_map(st +@@ -7910,7 +7910,7 @@ static void __init alloc_node_mem_map(st if (pgdat == NODE_DATA(0)) { mem_map = NODE_DATA(0)->node_mem_map; if (page_to_pfn(mem_map) != pgdat->node_start_pfn) diff --git a/target/linux/generic/pending-6.1/630-packet_socket_type.patch b/target/linux/generic/pending-6.1/630-packet_socket_type.patch index 359d002b0ef1e8..5553fba94b4075 100644 --- a/target/linux/generic/pending-6.1/630-packet_socket_type.patch +++ b/target/linux/generic/pending-6.1/630-packet_socket_type.patch @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau #define PACKET_FANOUT_LB 1 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c -@@ -1866,6 +1866,7 @@ static int packet_rcv_spkt(struct sk_buf +@@ -1927,6 +1927,7 @@ static int packet_rcv_spkt(struct sk_buf { struct sock *sk; struct sockaddr_pkt *spkt; @@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau /* * When we registered the protocol we saved the socket in the data -@@ -1873,6 +1874,7 @@ static int packet_rcv_spkt(struct sk_buf +@@ -1934,6 +1935,7 @@ static int packet_rcv_spkt(struct sk_buf */ sk = pt->af_packet_priv; @@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau /* * Yank back the headers [hope the device set this -@@ -1885,7 +1887,7 @@ static int packet_rcv_spkt(struct sk_buf +@@ -1946,7 +1948,7 @@ static int packet_rcv_spkt(struct sk_buf * so that this procedure is noop. */ @@ -55,7 +55,7 @@ Signed-off-by: Felix Fietkau goto out; if (!net_eq(dev_net(dev), sock_net(sk))) -@@ -2131,12 +2133,12 @@ static int packet_rcv(struct sk_buff *sk +@@ -2192,12 +2194,12 @@ static int packet_rcv(struct sk_buff *sk unsigned int snaplen, res; bool is_drop_n_account = false; @@ -71,7 +71,7 @@ Signed-off-by: Felix Fietkau if (!net_eq(dev_net(dev), sock_net(sk))) goto drop; -@@ -2263,12 +2265,12 @@ static int tpacket_rcv(struct sk_buff *s +@@ -2324,12 +2326,12 @@ static int tpacket_rcv(struct sk_buff *s BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32); BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48); @@ -87,7 +87,7 @@ Signed-off-by: Felix Fietkau if (!net_eq(dev_net(dev), sock_net(sk))) goto drop; -@@ -3377,6 +3379,7 @@ static int packet_create(struct net *net +@@ -3443,6 +3445,7 @@ static int packet_create(struct net *net mutex_init(&po->pg_vec_lock); po->rollover = NULL; po->prot_hook.func = packet_rcv; @@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau if (sock->type == SOCK_PACKET) po->prot_hook.func = packet_rcv_spkt; -@@ -4014,6 +4017,16 @@ packet_setsockopt(struct socket *sock, i +@@ -4096,6 +4099,16 @@ packet_setsockopt(struct socket *sock, i WRITE_ONCE(po->xmit, val ? packet_direct_xmit : dev_queue_xmit); return 0; } @@ -112,7 +112,7 @@ Signed-off-by: Felix Fietkau default: return -ENOPROTOOPT; } -@@ -4070,6 +4083,13 @@ static int packet_getsockopt(struct sock +@@ -4152,6 +4165,13 @@ static int packet_getsockopt(struct sock case PACKET_VNET_HDR: val = po->has_vnet_hdr; break; diff --git a/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch index b799c6fc9cb6a6..a2f88d79e633ff 100644 --- a/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch +++ b/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch @@ -338,7 +338,7 @@ Signed-off-by: Steven Barth if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6)) return -1; -@@ -1545,6 +1706,14 @@ ip6_tnl_change(struct ip6_tnl *t, const +@@ -1546,6 +1707,14 @@ ip6_tnl_change(struct ip6_tnl *t, const t->parms.link = p->link; t->parms.proto = p->proto; t->parms.fwmark = p->fwmark; @@ -353,7 +353,7 @@ Signed-off-by: Steven Barth dst_cache_reset(&t->dst_cache); ip6_tnl_link_config(t); } -@@ -1579,6 +1748,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_ +@@ -1580,6 +1749,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_ p->flowinfo = u->flowinfo; p->link = u->link; p->proto = u->proto; @@ -361,7 +361,7 @@ Signed-off-by: Steven Barth memcpy(p->name, u->name, sizeof(u->name)); } -@@ -1965,6 +2135,15 @@ static int ip6_tnl_validate(struct nlatt +@@ -1967,6 +2137,15 @@ static int ip6_tnl_validate(struct nlatt return 0; } @@ -377,7 +377,7 @@ Signed-off-by: Steven Barth static void ip6_tnl_netlink_parms(struct nlattr *data[], struct __ip6_tnl_parm *parms) { -@@ -2002,6 +2181,46 @@ static void ip6_tnl_netlink_parms(struct +@@ -2004,6 +2183,46 @@ static void ip6_tnl_netlink_parms(struct if (data[IFLA_IPTUN_FWMARK]) parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]); @@ -424,7 +424,7 @@ Signed-off-by: Steven Barth } static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev, -@@ -2085,6 +2304,12 @@ static void ip6_tnl_dellink(struct net_d +@@ -2087,6 +2306,12 @@ static void ip6_tnl_dellink(struct net_d static size_t ip6_tnl_get_size(const struct net_device *dev) { @@ -437,7 +437,7 @@ Signed-off-by: Steven Barth return /* IFLA_IPTUN_LINK */ nla_total_size(4) + -@@ -2114,6 +2339,24 @@ static size_t ip6_tnl_get_size(const str +@@ -2116,6 +2341,24 @@ static size_t ip6_tnl_get_size(const str nla_total_size(0) + /* IFLA_IPTUN_FWMARK */ nla_total_size(4) + @@ -462,7 +462,7 @@ Signed-off-by: Steven Barth 0; } -@@ -2121,6 +2364,9 @@ static int ip6_tnl_fill_info(struct sk_b +@@ -2123,6 +2366,9 @@ static int ip6_tnl_fill_info(struct sk_b { struct ip6_tnl *tunnel = netdev_priv(dev); struct __ip6_tnl_parm *parm = &tunnel->parms; @@ -472,7 +472,7 @@ Signed-off-by: Steven Barth if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || -@@ -2130,9 +2376,27 @@ static int ip6_tnl_fill_info(struct sk_b +@@ -2132,9 +2378,27 @@ static int ip6_tnl_fill_info(struct sk_b nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || @@ -501,7 +501,7 @@ Signed-off-by: Steven Barth if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) || -@@ -2172,6 +2436,7 @@ static const struct nla_policy ip6_tnl_p +@@ -2174,6 +2438,7 @@ static const struct nla_policy ip6_tnl_p [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, diff --git a/target/linux/generic/pending-6.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-6.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch index 43d49f07d19b57..1d16b81543b7e3 100644 --- a/target/linux/generic/pending-6.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch +++ b/target/linux/generic/pending-6.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski static void rt_fibinfo_free(struct rtable __rcu **rtp) --- a/net/ipv4/fib_trie.c +++ b/net/ipv4/fib_trie.c -@@ -2783,6 +2783,7 @@ static const char *const rtn_type_names[ +@@ -2784,6 +2784,7 @@ static const char *const rtn_type_names[ [RTN_THROW] = "THROW", [RTN_NAT] = "NAT", [RTN_XRESOLVE] = "XRESOLVE", diff --git a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch index 916b6bc6a06ca6..99ea09ae8f38ab 100644 --- a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch +++ b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch @@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c -@@ -7958,7 +7958,7 @@ static int nft_register_flowtable_net_ho +@@ -8012,7 +8012,7 @@ static int nft_register_flowtable_net_ho err = flowtable->data.type->setup(&flowtable->data, hook->ops.dev, FLOW_BLOCK_BIND); diff --git a/target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch index 13a4d190ee7cab..6fa33ee1a81d60 100644 --- a/target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch +++ b/target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch @@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -7079,6 +7079,7 @@ static int mv88e6xxx_register_switch(str +@@ -7080,6 +7080,7 @@ static int mv88e6xxx_register_switch(str ds->ops = &mv88e6xxx_switch_ops; ds->ageing_time_min = chip->info->age_time_coeff; ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; diff --git a/target/linux/generic/pending-6.1/774-net-dsa-b53-mmap-allow-passing-a-chip-ID.patch b/target/linux/generic/pending-6.1/774-net-dsa-b53-mmap-allow-passing-a-chip-ID.patch index de237374af96b3..bb632b5eff4d99 100644 --- a/target/linux/generic/pending-6.1/774-net-dsa-b53-mmap-allow-passing-a-chip-ID.patch +++ b/target/linux/generic/pending-6.1/774-net-dsa-b53-mmap-allow-passing-a-chip-ID.patch @@ -100,7 +100,7 @@ Signed-off-by: Álvaro Fernández Rojas --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c -@@ -2466,6 +2466,19 @@ static const struct b53_chip_data b53_sw +@@ -2469,6 +2469,19 @@ static const struct b53_chip_data b53_sw .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, }, { diff --git a/target/linux/generic/pending-6.1/777-net-dsa-b53-mdio-add-support-for-BCM53134.patch b/target/linux/generic/pending-6.1/777-net-dsa-b53-mdio-add-support-for-BCM53134.patch index f0ae2defcecda0..7bed8c22a4a8c8 100644 --- a/target/linux/generic/pending-6.1/777-net-dsa-b53-mdio-add-support-for-BCM53134.patch +++ b/target/linux/generic/pending-6.1/777-net-dsa-b53-mdio-add-support-for-BCM53134.patch @@ -100,7 +100,7 @@ Signed-off-by: Álvaro Fernández Rojas --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c -@@ -2613,6 +2613,20 @@ static const struct b53_chip_data b53_sw +@@ -2616,6 +2616,20 @@ static const struct b53_chip_data b53_sw .jumbo_pm_reg = B53_JUMBO_PORT_MASK, .jumbo_size_reg = B53_JUMBO_MAX_SIZE, }, @@ -121,7 +121,7 @@ Signed-off-by: Álvaro Fernández Rojas }; static int b53_switch_init(struct b53_device *dev) -@@ -2790,6 +2804,7 @@ int b53_switch_detect(struct b53_device +@@ -2793,6 +2807,7 @@ int b53_switch_detect(struct b53_device case BCM53012_DEVICE_ID: case BCM53018_DEVICE_ID: case BCM53019_DEVICE_ID: diff --git a/target/linux/generic/pending-6.1/834-ledtrig-libata.patch b/target/linux/generic/pending-6.1/834-ledtrig-libata.patch index 39960bc0900443..4663a43c338a67 100644 --- a/target/linux/generic/pending-6.1/834-ledtrig-libata.patch +++ b/target/linux/generic/pending-6.1/834-ledtrig-libata.patch @@ -85,7 +85,7 @@ Signed-off-by: Daniel Golle ata_sff_port_init(ap); return ap; -@@ -5473,6 +5492,12 @@ static void ata_host_release(struct kref +@@ -5476,6 +5495,12 @@ static void ata_host_release(struct kref kfree(ap->pmp_link); kfree(ap->slave_link); @@ -98,7 +98,7 @@ Signed-off-by: Daniel Golle kfree(ap); host->ports[i] = NULL; } -@@ -5875,7 +5900,23 @@ int ata_host_register(struct ata_host *h +@@ -5880,7 +5905,23 @@ int ata_host_register(struct ata_host *h host->ports[i]->print_id = atomic_inc_return(&ata_print_id); host->ports[i]->local_port_no = i + 1; } diff --git a/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch b/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch new file mode 100644 index 00000000000000..da842d353f2c31 --- /dev/null +++ b/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch @@ -0,0 +1,28 @@ +--- a/drivers/net/usb/qmi_wwan.c ++++ b/drivers/net/usb/qmi_wwan.c +@@ -1437,6 +1437,9 @@ static const struct usb_device_id produc + {QMI_QUIRK_SET_DTR(0x1546, 0x1342, 4)}, /* u-blox LARA-L6 */ + {QMI_QUIRK_SET_DTR(0x33f8, 0x0104, 4)}, /* Rolling RW101 RMNET */ + {QMI_FIXED_INTF(0x2dee, 0x4d22, 5)}, /* MeiG Smart SRM825L */ ++ {QMI_FIXED_INTF(0x2077, 0x2002, 4)}, /* T&W TW04C */ ++ {QMI_FIXED_INTF(0x2077, 0x2003, 4)}, /* T&W TW12G */ ++ {QMI_FIXED_INTF(0x2077, 0x2004, 4)}, /* T&W TW510M */ + + /* 4. Gobi 1000 devices */ + {QMI_GOBI1K_DEVICE(0x05c6, 0x9212)}, /* Acer Gobi Modem Device */ +--- a/drivers/usb/serial/option.c ++++ b/drivers/usb/serial/option.c +@@ -2324,9 +2324,13 @@ static const struct usb_device_id option + { USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x0a06, 0xff) }, /* Fibocom FM650-CN (RNDIS mode) */ + { USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x0a07, 0xff) }, /* Fibocom FM650-CN (MBIM mode) */ + { USB_DEVICE_INTERFACE_CLASS(0x2df3, 0x9d03, 0xff) }, /* LongSung M5710 */ ++ { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1402, 0xff) }, /* GosunCn GM800 (Download mode) */ ++ { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1403, 0xff) }, /* GosunCn GM800 (rmnet, old) */ + { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1404, 0xff) }, /* GosunCn GM500 RNDIS */ + { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1405, 0xff) }, /* GosunCn GM500 MBIM */ + { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1406, 0xff) }, /* GosunCn GM500 ECM/NCM */ ++ { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1421, 0xff) }, /* GosunCn GM800 (rmnet) */ ++ { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1422, 0xff) }, /* GosunCn GM800 (EAP) */ + { USB_DEVICE(0x33f8, 0x0104), /* Rolling RW101-GL (laptop RMNET) */ + .driver_info = RSVD(4) | RSVD(5) }, + { USB_DEVICE_INTERFACE_CLASS(0x33f8, 0x01a2, 0xff) }, /* Rolling RW101-GL (laptop MBIM) */ diff --git a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch b/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch index 17c5c6098aa67d..8bc6e5d66d40d6 100644 --- a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch +++ b/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch @@ -32,7 +32,7 @@ Signed-off-by: Rob Herring --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib -@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T +@@ -412,6 +412,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE $(call if_changed_dep,dtc) diff --git a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch b/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch index db2802bd0f4511..1dd8d3a81b454c 100644 --- a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch +++ b/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch @@ -39,7 +39,7 @@ Signed-off-by: Ulf Hansson ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); if (ret) { dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); -@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor +@@ -2666,6 +2669,15 @@ static int msdc_drv_probe(struct platfor goto host_free; } diff --git a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch b/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch index 921d249f8cc5d8..f4e5c12c26cd8d 100644 --- a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch +++ b/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch @@ -25,8 +25,8 @@ Signed-off-by: Ulf Hansson bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; } -@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho - !host->hs400_tuning)) +@@ -1227,7 +1227,7 @@ static bool msdc_cmd_done(struct msdc_ho + (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) /* * should not clear fifo/interrupt as the tune data - * may have alreay come when cmd19/cmd21 gets response diff --git a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch b/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch deleted file mode 100644 index 8e2151e16bd468..00000000000000 --- a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001 -From: ChanWoo Lee -Date: Thu, 24 Nov 2022 17:00:31 +0900 -Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning() - -Replace code with the already defined function. No functional changes. - -Signed-off-by: ChanWoo Lee -Reviewed-by: Adrian Hunter -Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 8 ++------ - 1 file changed, 2 insertions(+), 6 deletions(-) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho - - if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { - if (events & MSDC_INT_CMDTMO || -- (cmd->opcode != MMC_SEND_TUNING_BLOCK && -- cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && -- !host->hs400_tuning)) -+ (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) - /* - * should not clear fifo/interrupt as the tune data - * may have already come when cmd19/cmd21 gets response -@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho - { - if ((cmd->error && - !(cmd->error == -EILSEQ && -- (cmd->opcode == MMC_SEND_TUNING_BLOCK || -- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || -- host->hs400_tuning))) || -+ (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || - (mrq->sbc && mrq->sbc->error)) - msdc_request_done(host, mrq); - else if (cmd == mrq->sbc) diff --git a/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch b/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch index 1fcb1e64c7dd80..fb65adb0115d5f 100644 --- a/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch +++ b/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch @@ -31,8 +31,8 @@ static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 pullup, u32 arg) -@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt - return err; +@@ -758,6 +782,12 @@ int mtk_pinconf_bias_set_combo(struct mt + return 0; } + if (try_all_type & MTK_PULL_PD_TYPE) { @@ -44,7 +44,7 @@ if (try_all_type & MTK_PULL_PU_PD_TYPE) { err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); if (!err) -@@ -875,6 +905,29 @@ out: +@@ -878,6 +908,29 @@ out: return err; } @@ -74,19 +74,19 @@ static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *pullup, u32 *enable) -@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt - if (!err) - return err; +@@ -947,6 +1000,12 @@ int mtk_pinconf_bias_get_combo(struct mt + return 0; } -+ + + if (try_all_type & MTK_PULL_PD_TYPE) { + err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); + if (!err) + return err; + } - ++ if (try_all_type & MTK_PULL_PU_PD_TYPE) { err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); + if (!err) --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -24,6 +24,7 @@ diff --git a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch index f8857bdf72ac72..9f54ece781a4fa 100644 --- a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch +++ b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch @@ -37,7 +37,7 @@ * CONFIG_CMDLINE is meant to be a default in case nothing else --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig -@@ -2239,6 +2239,14 @@ config CMDLINE_FORCE +@@ -2277,6 +2277,14 @@ config CMDLINE_FORCE endchoice From 5ea6cb7c3721298152784348c63090f56d43cfec Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Sat, 21 Sep 2024 17:22:54 +0800 Subject: [PATCH 2/4] rockchip: backport driver updates for rk3588 --- target/linux/rockchip/armv8/config-6.6 | 17 + ...ockchip-rk3588-fix-CLK_NR_CLKS-usage.patch | 78 + ...ndings-clock-rk3588-drop-CLK_NR_CLKS.patch | 27 + ...clock-rk3588-add-missing-PCLK_VO1GRF.patch | 26 + ...3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch | 59 + ...-v6.9-clk-rockchip-rk3588-fix-indent.patch | 26 + ...88-use-linked-clock-ID-for-GATE_LINK.patch | 78 + ...fine-reset-id-used-for-HDMI-Receiver.patch | 24 + ...588-Add-reset-line-for-HDMI-Receiver.patch | 25 + ...-for-standard-system-power-controlle.patch | 28 + ...k8xx-Add-support-for-RK806-power-off.patch | 29 + ...-rockchip-add-usbdp-combo-phy-driver.patch | 1670 ++ ...hip-usbdp-fix-uninitialized-variable.patch | 35 + ...rockchip-fix-CONFIG_TYPEC-dependency.patch | 43 + ...-rockchip-Fix-typo-in-function-names.patch | 79 + ...-rockchip-snps-pcie3-add-support-for.patch | 106 + ...c3-add-optional-PHY-interface-clocks.patch | 91 + ...dts-rockchip-Add-sfc-node-to-rk3588s.patch | 35 + ...d-I2S2-M0-pin-definitions-to-rk3588s.patch | 58 + ...d-UART9-M0-pin-definitions-to-rk3588.patch | 32 + ...chip-Add-AV1-decoder-node-to-rk3588s.patch | 37 + ...rm64-dts-rockchip-Add-DFI-to-rk3588s.patch | 50 + ...hip-rk3588s-Add-USB3-host-controller.patch | 48 + ...p-drop-interrupt-names-property-from.patch | 27 + ...ve-rk3588-serial-aliases-to-soc-dtsi.patch | 139 + ...p-add-rk3588-i2c-aliases-to-soc-dtsi.patch | 38 + ...-add-rk3588-gpio-aliases-to-soc-dtsi.patch | 34 + ...p-add-rk3588-spi-aliases-to-soc-dtsi.patch | 34 + ...arm64-dts-rockchip-Add-vop-on-rk3588.patch | 120 + ...dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch | 51 + ...dd-clock-to-vo1-grf-syscon-on-rk3588.patch | 25 + ...m64-dts-rockchip-Add-rk3588-GPU-node.patch | 81 + ...hip-Fix-ordering-of-nodes-on-rk3588s.patch | 384 + ...chip-fix-usb2phy-nodename-for-rk3588.patch | 35 + ...eorder-usb2phy-properties-for-rk3588.patch | 53 + ...ts-rockchip-add-USBDP-phys-on-rk3588.patch | 175 + ...p-add-USB3-DRD-controllers-on-rk3588.patch | 75 + ...kchip-add-rk3588-pcie-and-php-IOMMUs.patch | 74 + ...ip-Prepare-RK3588-SoC-dtsi-files-for.patch | 14208 ++++++++++++++++ ...d-thermal-zones-information-on-RK358.patch | 193 + ...ip-add-passive-GPU-cooling-on-RK3588.patch | 50 + ...Add-OPP-data-for-CPU-cores-on-RK3588.patch | 205 + ...dd-OPP-data-for-CPU-cores-on-RK3588j.patch | 140 + ...Split-GPU-OPPs-of-RK3588-and-RK3588j.patch | 177 + 44 files changed, 19019 insertions(+) create mode 100644 target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch create mode 100644 target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch create mode 100644 target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch create mode 100644 target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch create mode 100644 target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch create mode 100644 target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch create mode 100644 target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch create mode 100644 target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch create mode 100644 target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch create mode 100644 target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch create mode 100644 target/linux/rockchip/patches-6.6/032-01-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch create mode 100644 target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch create mode 100644 target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch create mode 100644 target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-Fix-typo-in-function-names.patch create mode 100644 target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch create mode 100644 target/linux/rockchip/patches-6.6/034-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch create mode 100644 target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch create mode 100644 target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk3588s.patch create mode 100644 target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-rk3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-Add-AV1-decoder-node-to-rk3588s.patch create mode 100644 target/linux/rockchip/patches-6.6/050-05-v6.8-arm64-dts-rockchip-Add-DFI-to-rk3588s.patch create mode 100644 target/linux/rockchip/patches-6.6/050-06-v6.8-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch create mode 100644 target/linux/rockchip/patches-6.6/050-07-v6.7-arm64-dts-rockchip-drop-interrupt-names-property-from.patch create mode 100644 target/linux/rockchip/patches-6.6/050-08-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch create mode 100644 target/linux/rockchip/patches-6.6/050-09-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch create mode 100644 target/linux/rockchip/patches-6.6/050-10-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch create mode 100644 target/linux/rockchip/patches-6.6/050-11-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch create mode 100644 target/linux/rockchip/patches-6.6/050-12-v6.8-arm64-dts-rockchip-Add-vop-on-rk3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-13-v6.9-arm64-dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-14-v6.9-arm64-dts-rockchip-add-clock-to-vo1-grf-syscon-on-rk3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-15-v6.10-arm64-dts-rockchip-Add-rk3588-GPU-node.patch create mode 100644 target/linux/rockchip/patches-6.6/050-16-v6.10-arm64-dts-rockchip-Fix-ordering-of-nodes-on-rk3588s.patch create mode 100644 target/linux/rockchip/patches-6.6/050-17-v6.10-arm64-dts-rockchip-fix-usb2phy-nodename-for-rk3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-18-v6.10-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-19-v6.10-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-20-v6.10-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-21-v6.10-arm64-dts-rockchip-add-rk3588-pcie-and-php-IOMMUs.patch create mode 100644 target/linux/rockchip/patches-6.6/050-22-v6.11-arm64-dts-rockchip-Prepare-RK3588-SoC-dtsi-files-for.patch create mode 100644 target/linux/rockchip/patches-6.6/050-23-v6.11-arm64-dts-rockchip-add-thermal-zones-information-on-RK358.patch create mode 100644 target/linux/rockchip/patches-6.6/050-24-v6.11-arm64-dts-rockchip-add-passive-GPU-cooling-on-RK3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-25-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588.patch create mode 100644 target/linux/rockchip/patches-6.6/050-26-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588j.patch create mode 100644 target/linux/rockchip/patches-6.6/050-27-v6.11-arm64-dts-rockchip-Split-GPU-OPPs-of-RK3588-and-RK3588j.patch diff --git a/target/linux/rockchip/armv8/config-6.6 b/target/linux/rockchip/armv8/config-6.6 index d38b2d8ac774ec..d385a0b7863b92 100644 --- a/target/linux/rockchip/armv8/config-6.6 +++ b/target/linux/rockchip/armv8/config-6.6 @@ -25,7 +25,21 @@ CONFIG_ARM64=y CONFIG_ARM64_4K_PAGES=y CONFIG_ARM64_CNP=y CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1530923=y CONFIG_ARM64_ERRATUM_1742098=y +CONFIG_ARM64_ERRATUM_2051678=y +CONFIG_ARM64_ERRATUM_2054223=y +CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2077057=y +CONFIG_ARM64_ERRATUM_2441007=y +CONFIG_ARM64_ERRATUM_2441009=y +CONFIG_ARM64_ERRATUM_2658417=y +CONFIG_ARM64_ERRATUM_3117295=y CONFIG_ARM64_ERRATUM_819472=y CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_826319=y @@ -50,6 +64,9 @@ CONFIG_ARM64_VA_BITS=48 # CONFIG_ARM64_VA_BITS_39 is not set CONFIG_ARM64_VA_BITS_48=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y # CONFIG_ARMV8_DEPRECATED is not set CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER=y diff --git a/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch b/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch new file mode 100644 index 00000000000000..6becaf6e86a844 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch @@ -0,0 +1,78 @@ +From 2dc66a5ab2c6fb532fbb16107ee7efcb0effbfa5 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 26 Jan 2024 19:18:22 +0100 +Subject: [PATCH] clk: rockchip: rk3588: fix CLK_NR_CLKS usage + +CLK_NR_CLKS is not part of the DT bindings and needs to be removed +from it, just like it recently happened for other platforms. This +takes care of it by introducing a new function identifying the +maximum used clock ID at runtime. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3588.c | 5 ++++- + drivers/clk/rockchip/clk.c | 17 +++++++++++++++++ + drivers/clk/rockchip/clk.h | 2 ++ + 3 files changed, 23 insertions(+), 1 deletion(-) + +--- a/drivers/clk/rockchip/clk-rk3588.c ++++ b/drivers/clk/rockchip/clk-rk3588.c +@@ -2458,15 +2458,18 @@ static struct rockchip_clk_branch rk3588 + static void __init rk3588_clk_init(struct device_node *np) + { + struct rockchip_clk_provider *ctx; ++ unsigned long clk_nr_clks; + void __iomem *reg_base; + ++ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches, ++ ARRAY_SIZE(rk3588_clk_branches)) + 1; + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + +- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); ++ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); +--- a/drivers/clk/rockchip/clk.c ++++ b/drivers/clk/rockchip/clk.c +@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct r + } + EXPORT_SYMBOL_GPL(rockchip_clk_register_plls); + ++unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, ++ unsigned int nr_clk) ++{ ++ unsigned long max = 0; ++ unsigned int idx; ++ ++ for (idx = 0; idx < nr_clk; idx++, list++) { ++ if (list->id > max) ++ max = list->id; ++ if (list->child && list->child->id > max) ++ max = list->id; ++ } ++ ++ return max; ++} ++EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id); ++ + void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + unsigned int nr_clk) +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -973,6 +973,8 @@ struct rockchip_clk_provider *rockchip_c + void __iomem *base, unsigned long nr_clks); + void rockchip_clk_of_add_provider(struct device_node *np, + struct rockchip_clk_provider *ctx); ++unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, ++ unsigned int nr_clk); + void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + unsigned int nr_clk); diff --git a/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch b/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch new file mode 100644 index 00000000000000..c8117f08c5ef8d --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch @@ -0,0 +1,27 @@ +From 11a29dc2e41ead2be78cfa9d532edf924b461acc Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 26 Jan 2024 19:18:23 +0100 +Subject: [PATCH] dt-bindings: clock: rk3588: drop CLK_NR_CLKS + +CLK_NR_CLKS should not be part of the binding. Let's drop it, since +the kernel code no longer uses it either. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240126182919.48402-3-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 -- + 1 file changed, 2 deletions(-) + +--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h ++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h +@@ -734,8 +734,6 @@ + #define PCLK_AV1_PRE 719 + #define HCLK_SDIO_PRE 720 + +-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) +- + /* scmi-clocks indices */ + + #define SCMI_CLK_CPUL 0 diff --git a/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch b/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch new file mode 100644 index 00000000000000..b960bc61978198 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch @@ -0,0 +1,26 @@ +From c81798cf9dd2f324934585b2b52a0398caefb88e Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 26 Jan 2024 19:18:24 +0100 +Subject: [PATCH] dt-bindings: clock: rk3588: add missing PCLK_VO1GRF + +Add PCLK_VO1GRF to complement PCLK_VO0GRF. This will be needed +for HDMI support. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240126182919.48402-4-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + include/dt-bindings/clock/rockchip,rk3588-cru.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h ++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h +@@ -733,6 +733,7 @@ + #define ACLK_AV1_PRE 718 + #define PCLK_AV1_PRE 719 + #define HCLK_SDIO_PRE 720 ++#define PCLK_VO1GRF 721 + + /* scmi-clocks indices */ + diff --git a/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch b/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch new file mode 100644 index 00000000000000..e12b73fb305708 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch @@ -0,0 +1,59 @@ +From 326be62eaf2e89767b7b9223f88eaf3c041b98d2 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 26 Jan 2024 19:18:25 +0100 +Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf + +Currently pclk_vo1grf is not exposed, but it should be referenced +from the vo1_grf syscon, which needs it enabled. That syscon is +required for HDMI RX and TX functionality among other things. + +Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates +and need the VO's hclk enabled in addition to their parent clock. + +No Fixes tag has been added, since the logic requiring these clocks +is not yet upstream anyways. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3588.c | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +--- a/drivers/clk/rockchip/clk-rk3588.c ++++ b/drivers/clk/rockchip/clk-rk3588.c +@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588 + RK3588_CLKGATE_CON(56), 0, GFLAGS), + GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 1, GFLAGS), +- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, +- RK3588_CLKGATE_CON(55), 10, GFLAGS), + COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 11, GFLAGS), +@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588 + RK3588_CLKGATE_CON(60), 9, GFLAGS), + GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 10, GFLAGS), +- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, +- RK3588_CLKGATE_CON(59), 12, GFLAGS), + GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 14, GFLAGS), + GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, +@@ -2447,12 +2443,14 @@ static struct rockchip_clk_branch rk3588 + GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), + GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), + GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), +- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), ++ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), +- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), ++ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), + GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), + GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), ++ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), ++ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), + }; + + static void __init rk3588_clk_init(struct device_node *np) diff --git a/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch b/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch new file mode 100644 index 00000000000000..27aa28edd57b75 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch @@ -0,0 +1,26 @@ +From 2a6e4710672242281347103b64e01693aa823a29 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 26 Jan 2024 19:18:26 +0100 +Subject: [PATCH] clk: rockchip: rk3588: fix indent + +pclk_mailbox2 is the only RK3588 clock indented with one tab instead of +two tabs. Let's fix this. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3588.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/rockchip/clk-rk3588.c ++++ b/drivers/clk/rockchip/clk-rk3588.c +@@ -1004,7 +1004,7 @@ static struct rockchip_clk_branch rk3588 + GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 12, GFLAGS), + GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, +- RK3588_CLKGATE_CON(16), 13, GFLAGS), ++ RK3588_CLKGATE_CON(16), 13, GFLAGS), + GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 3, GFLAGS), + GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, diff --git a/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch b/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch new file mode 100644 index 00000000000000..949041fb9f5856 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch @@ -0,0 +1,78 @@ +From dae3e57000fb2d6f491e3ee2956f5918326d6b72 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 26 Jan 2024 19:18:27 +0100 +Subject: [PATCH] clk: rockchip: rk3588: use linked clock ID for GATE_LINK + +In preparation for properly supporting GATE_LINK switch the unused +linked clock argument from the clock's name to its ID. This allows +easy and fast lookup of the 'struct clk'. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3588.c | 46 +++++++++++++++---------------- + 1 file changed, 23 insertions(+), 23 deletions(-) + +--- a/drivers/clk/rockchip/clk-rk3588.c ++++ b/drivers/clk/rockchip/clk-rk3588.c +@@ -29,7 +29,7 @@ + * power, but avoids leaking implementation details into DT or hanging the + * system. + */ +-#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ ++#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ + GATE(_id, cname, pname, f, o, b, gf) + #define RK3588_LINKED_CLK CLK_IS_CRITICAL + +@@ -2429,28 +2429,28 @@ static struct rockchip_clk_branch rk3588 + GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 2, GFLAGS), + +- GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), +- GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), +- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), +- GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), +- GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), +- GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), +- GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), +- GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), +- GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), +- GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), +- GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), +- GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), +- GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), +- GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), +- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), +- GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), +- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), +- GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), +- GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), +- GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), +- GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), +- GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), ++ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), ++ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), ++ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), ++ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), ++ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), ++ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), ++ GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), ++ GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), ++ GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), ++ GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), ++ GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), ++ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), ++ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), ++ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), ++ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), ++ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), ++ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), ++ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), ++ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), ++ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), ++ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), ++ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), + }; + + static void __init rk3588_clk_init(struct device_node *np) diff --git a/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch b/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch new file mode 100644 index 00000000000000..0b9082f9b65ed8 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch @@ -0,0 +1,24 @@ +From ca151fd56b5736a7adbdba5675b9d87d70f20b23 Mon Sep 17 00:00:00 2001 +From: Shreeya Patel +Date: Thu, 28 Mar 2024 04:20:52 +0530 +Subject: [PATCH] dt-bindings: reset: Define reset id used for HDMI Receiver + +Add reset id used for HDMI Receiver in RK3588 SoCs + +Acked-by: Rob Herring +Signed-off-by: Shreeya Patel +Link: https://lore.kernel.org/r/20240327225057.672304-2-shreeya.patel@collabora.com +Signed-off-by: Heiko Stuebner +--- + include/dt-bindings/reset/rockchip,rk3588-cru.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h ++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h +@@ -751,4 +751,6 @@ + #define SRST_P_TRNG_CHK 658 + #define SRST_TRNG_S 659 + ++#define SRST_A_HDMIRX_BIU 660 ++ + #endif diff --git a/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch b/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch new file mode 100644 index 00000000000000..6aa9c058a34cef --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch @@ -0,0 +1,25 @@ +From 7af67019cd78d028ef377df689ac103d51905518 Mon Sep 17 00:00:00 2001 +From: Shreeya Patel +Date: Thu, 28 Mar 2024 04:20:53 +0530 +Subject: [PATCH] clk: rockchip: rk3588: Add reset line for HDMI Receiver + +Export hdmirx_biu reset line required by the Synopsys +DesignWare HDMIRX Controller. + +Signed-off-by: Shreeya Patel +Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/rst-rk3588.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/rockchip/rst-rk3588.c ++++ b/drivers/clk/rockchip/rst-rk3588.c +@@ -577,6 +577,7 @@ static const int rk3588_register_offset[ + + /* SOFTRST_CON59 */ + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10), diff --git a/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch b/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch new file mode 100644 index 00000000000000..94d998fe93409b --- /dev/null +++ b/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch @@ -0,0 +1,28 @@ +From 2a46cd97f401a669d71b3d36b78bd6653f8424ee Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Thu, 19 Oct 2023 18:57:25 +0200 +Subject: [PATCH] mfd: rk8xx: Add support for standard system-power-controller + property + +DT property rockchip,system-power-controller is now deprecated. + +Signed-off-by: Ondrej Jirman +Reviewed-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20231019165732.3818789-4-megi@xff.cz +Signed-off-by: Lee Jones +--- + drivers/mfd/rk8xx-core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/mfd/rk8xx-core.c ++++ b/drivers/mfd/rk8xx-core.c +@@ -677,7 +677,8 @@ int rk8xx_probe(struct device *dev, int + if (ret) + return dev_err_probe(dev, ret, "failed to add MFD devices\n"); + +- if (device_property_read_bool(dev, "rockchip,system-power-controller")) { ++ if (device_property_read_bool(dev, "rockchip,system-power-controller") || ++ device_property_read_bool(dev, "system-power-controller")) { + ret = devm_register_sys_off_handler(dev, + SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH, + &rk808_power_off, rk808); diff --git a/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch b/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch new file mode 100644 index 00000000000000..2ac0ff537e5817 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch @@ -0,0 +1,29 @@ +From b0227e7081404448a0059b8698fdffd2dec280d2 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Thu, 19 Oct 2023 18:57:26 +0200 +Subject: [PATCH] mfd: rk8xx: Add support for RK806 power off + +Use DEV_OFF bit to power off the RK806 PMIC, when system-power-controller +is used in DTS. + +Signed-off-by: Ondrej Jirman +Reviewed-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20231019165732.3818789-5-megi@xff.cz +Signed-off-by: Lee Jones +--- + drivers/mfd/rk8xx-core.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mfd/rk8xx-core.c ++++ b/drivers/mfd/rk8xx-core.c +@@ -517,6 +517,10 @@ static int rk808_power_off(struct sys_of + reg = RK805_DEV_CTRL_REG; + bit = DEV_OFF; + break; ++ case RK806_ID: ++ reg = RK806_SYS_CFG3; ++ bit = DEV_OFF; ++ break; + case RK808_ID: + reg = RK808_DEVCTRL_REG, + bit = DEV_OFF_RST; diff --git a/target/linux/rockchip/patches-6.6/032-01-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch b/target/linux/rockchip/patches-6.6/032-01-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch new file mode 100644 index 00000000000000..69b44deba397c1 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-01-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch @@ -0,0 +1,1670 @@ +From 2f70bbddeb457580cef3ceb574506083b9272188 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 9 Apr 2024 00:50:29 +0200 +Subject: [PATCH] phy: rockchip: add usbdp combo phy driver + +This adds a new USBDP combo PHY with Samsung IP block driver. + +The driver get lane mux and mapping info in 2 ways, supporting +DisplayPort alternate mode or parsing from DT. When parsing from DT, +the property "rockchip,dp-lane-mux" provide the DP mux and mapping +info. This is needed when the PHY is not used with TypeC Alt-Mode. +For example if the USB3 interface of the PHY is connected to a USB +Type A connector and the DP interface is connected to a DisplayPort +connector. + +When do DP link training, need to set lane number, link rate, swing, +and pre-emphasis via PHY configure interface. + +Co-developed-by: Heiko Stuebner +Signed-off-by: Heiko Stuebner +Co-developed-by: Zhang Yubing +Signed-off-by: Zhang Yubing +Co-developed-by: Frank Wang +Signed-off-by: Frank Wang +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240408225109.128953-3-sebastian.reichel@collabora.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/Kconfig | 12 + + drivers/phy/rockchip/Makefile | 1 + + drivers/phy/rockchip/phy-rockchip-usbdp.c | 1608 +++++++++++++++++++++ + 3 files changed, 1621 insertions(+) + create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c + +--- a/drivers/phy/rockchip/Kconfig ++++ b/drivers/phy/rockchip/Kconfig +@@ -107,3 +107,15 @@ config PHY_ROCKCHIP_USB + select GENERIC_PHY + help + Enable this to support the Rockchip USB 2.0 PHY. ++ ++config PHY_ROCKCHIP_USBDP ++ tristate "Rockchip USBDP COMBO PHY Driver" ++ depends on ARCH_ROCKCHIP && OF ++ select GENERIC_PHY ++ select TYPEC ++ help ++ Enable this to support the Rockchip USB3.0/DP combo PHY with ++ Samsung IP block. This is required for USB3 support on RK3588. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called phy-rockchip-usbdp +--- a/drivers/phy/rockchip/Makefile ++++ b/drivers/phy/rockchip/Makefile +@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy- + obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o + obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o + obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o ++obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o +--- /dev/null ++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c +@@ -0,0 +1,1608 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Rockchip USBDP Combo PHY with Samsung IP block driver ++ * ++ * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd ++ * Copyright (C) 2024 Collabora Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* USBDP PHY Register Definitions */ ++#define UDPHY_PCS 0x4000 ++#define UDPHY_PMA 0x8000 ++ ++/* VO0 GRF Registers */ ++#define DP_SINK_HPD_CFG BIT(11) ++#define DP_SINK_HPD_SEL BIT(10) ++#define DP_AUX_DIN_SEL BIT(9) ++#define DP_AUX_DOUT_SEL BIT(8) ++#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) ++#define DP_LANE_SEL_ALL GENMASK(7, 0) ++ ++/* PMA CMN Registers */ ++#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ ++#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) ++#define CMN_DP_LANE_EN_N(n) BIT(n) ++#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) ++#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) ++ ++#define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */ ++#define CMN_DP_TX_LINK_BW GENMASK(6, 5) ++#define CMN_DP_TX_LANE_SWAP_EN BIT(2) ++ ++#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ ++#define CMN_ROPLL_SSC_EN BIT(1) ++#define CMN_LCPLL_SSC_EN BIT(0) ++ ++#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ ++#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) ++#define CMN_ANA_LCPLL_AFC_DONE BIT(6) ++ ++#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ ++#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) ++#define CMN_ANA_ROPLL_AFC_DONE BIT(0) ++ ++#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ ++#define CMN_DP_INIT_RSTN BIT(3) ++#define CMN_DP_CMN_RSTN BIT(2) ++#define CMN_CDR_WTCHDG_EN BIT(1) ++#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) ++ ++#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ ++#define LN_ANA_TX_SER_TXCLK_INV BIT(1) ++ ++#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ ++#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) ++ ++#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ ++#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) ++ ++#define BIT_WRITEABLE_SHIFT 16 ++#define PHY_AUX_DP_DATA_POL_NORMAL 0 ++#define PHY_AUX_DP_DATA_POL_INVERT 1 ++#define PHY_LANE_MUX_USB 0 ++#define PHY_LANE_MUX_DP 1 ++ ++enum { ++ DP_BW_RBR, ++ DP_BW_HBR, ++ DP_BW_HBR2, ++ DP_BW_HBR3, ++}; ++ ++enum { ++ UDPHY_MODE_NONE = 0, ++ UDPHY_MODE_USB = BIT(0), ++ UDPHY_MODE_DP = BIT(1), ++ UDPHY_MODE_DP_USB = BIT(1) | BIT(0), ++}; ++ ++struct rk_udphy_grf_reg { ++ unsigned int offset; ++ unsigned int disable; ++ unsigned int enable; ++}; ++ ++#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \ ++{\ ++ offset, \ ++ FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \ ++ FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \ ++} ++ ++#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \ ++ _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable) ++ ++struct rk_udphy_grf_cfg { ++ /* u2phy-grf */ ++ struct rk_udphy_grf_reg bvalid_phy_con; ++ struct rk_udphy_grf_reg bvalid_grf_con; ++ ++ /* usb-grf */ ++ struct rk_udphy_grf_reg usb3otg0_cfg; ++ struct rk_udphy_grf_reg usb3otg1_cfg; ++ ++ /* usbdpphy-grf */ ++ struct rk_udphy_grf_reg low_pwrn; ++ struct rk_udphy_grf_reg rx_lfps; ++}; ++ ++struct rk_udphy_vogrf_cfg { ++ /* vo-grf */ ++ struct rk_udphy_grf_reg hpd_trigger; ++ u32 dp_lane_reg; ++}; ++ ++struct rk_udphy_dp_tx_drv_ctrl { ++ u32 trsv_reg0204; ++ u32 trsv_reg0205; ++ u32 trsv_reg0206; ++ u32 trsv_reg0207; ++}; ++ ++struct rk_udphy_cfg { ++ unsigned int num_phys; ++ unsigned int phy_ids[2]; ++ /* resets to be requested */ ++ const char * const *rst_list; ++ int num_rsts; ++ ++ struct rk_udphy_grf_cfg grfcfg; ++ struct rk_udphy_vogrf_cfg vogrfcfg[2]; ++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; ++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4]; ++}; ++ ++struct rk_udphy { ++ struct device *dev; ++ struct regmap *pma_regmap; ++ struct regmap *u2phygrf; ++ struct regmap *udphygrf; ++ struct regmap *usbgrf; ++ struct regmap *vogrf; ++ struct typec_switch_dev *sw; ++ struct typec_mux_dev *mux; ++ struct mutex mutex; /* mutex to protect access to individual PHYs */ ++ ++ /* clocks and rests */ ++ int num_clks; ++ struct clk_bulk_data *clks; ++ struct clk *refclk; ++ int num_rsts; ++ struct reset_control_bulk_data *rsts; ++ ++ /* PHY status management */ ++ bool flip; ++ bool mode_change; ++ u8 mode; ++ u8 status; ++ ++ /* utilized for USB */ ++ bool hs; /* flag for high-speed */ ++ ++ /* utilized for DP */ ++ struct gpio_desc *sbu1_dc_gpio; ++ struct gpio_desc *sbu2_dc_gpio; ++ u32 lane_mux_sel[4]; ++ u32 dp_lane_sel[4]; ++ u32 dp_aux_dout_sel; ++ u32 dp_aux_din_sel; ++ bool dp_sink_hpd_sel; ++ bool dp_sink_hpd_cfg; ++ u8 bw; ++ int id; ++ ++ bool dp_in_use; ++ ++ /* PHY const config */ ++ const struct rk_udphy_cfg *cfgs; ++ ++ /* PHY devices */ ++ struct phy *phy_dp; ++ struct phy *phy_u3; ++}; ++ ++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { ++ /* voltage swing 0, pre-emphasis 0->3 */ ++ { ++ { 0x20, 0x10, 0x42, 0xe5 }, ++ { 0x26, 0x14, 0x42, 0xe5 }, ++ { 0x29, 0x18, 0x42, 0xe5 }, ++ { 0x2b, 0x1c, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 1, pre-emphasis 0->2 */ ++ { ++ { 0x23, 0x10, 0x42, 0xe7 }, ++ { 0x2a, 0x17, 0x43, 0xe7 }, ++ { 0x2b, 0x1a, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 2, pre-emphasis 0->1 */ ++ { ++ { 0x27, 0x10, 0x42, 0xe7 }, ++ { 0x2b, 0x17, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 3, pre-emphasis 0 */ ++ { ++ { 0x29, 0x10, 0x43, 0xe7 }, ++ }, ++}; ++ ++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = { ++ /* voltage swing 0, pre-emphasis 0->3 */ ++ { ++ { 0x20, 0x10, 0x42, 0xe5 }, ++ { 0x26, 0x14, 0x42, 0xe5 }, ++ { 0x29, 0x18, 0x42, 0xe5 }, ++ { 0x2b, 0x1c, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 1, pre-emphasis 0->2 */ ++ { ++ { 0x23, 0x10, 0x42, 0xe7 }, ++ { 0x2a, 0x17, 0x43, 0xe7 }, ++ { 0x2b, 0x1a, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 2, pre-emphasis 0->1 */ ++ { ++ { 0x27, 0x10, 0x43, 0x67 }, ++ { 0x2b, 0x17, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 3, pre-emphasis 0 */ ++ { ++ { 0x29, 0x10, 0x43, 0xe7 }, ++ }, ++}; ++ ++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { ++ /* voltage swing 0, pre-emphasis 0->3 */ ++ { ++ { 0x21, 0x10, 0x42, 0xe5 }, ++ { 0x26, 0x14, 0x42, 0xe5 }, ++ { 0x26, 0x16, 0x43, 0xe5 }, ++ { 0x2a, 0x19, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 1, pre-emphasis 0->2 */ ++ { ++ { 0x24, 0x10, 0x42, 0xe7 }, ++ { 0x2a, 0x17, 0x43, 0xe7 }, ++ { 0x2b, 0x1a, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 2, pre-emphasis 0->1 */ ++ { ++ { 0x28, 0x10, 0x42, 0xe7 }, ++ { 0x2b, 0x17, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 3, pre-emphasis 0 */ ++ { ++ { 0x28, 0x10, 0x43, 0xe7 }, ++ }, ++}; ++ ++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { ++ /* voltage swing 0, pre-emphasis 0->3 */ ++ { ++ { 0x21, 0x10, 0x42, 0xe5 }, ++ { 0x26, 0x14, 0x42, 0xe5 }, ++ { 0x26, 0x16, 0x43, 0xe5 }, ++ { 0x29, 0x18, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 1, pre-emphasis 0->2 */ ++ { ++ { 0x24, 0x10, 0x42, 0xe7 }, ++ { 0x2a, 0x18, 0x43, 0xe7 }, ++ { 0x2b, 0x1b, 0x43, 0xe7 } ++ }, ++ ++ /* voltage swing 2, pre-emphasis 0->1 */ ++ { ++ { 0x27, 0x10, 0x42, 0xe7 }, ++ { 0x2b, 0x18, 0x43, 0xe7 } ++ }, ++ ++ /* voltage swing 3, pre-emphasis 0 */ ++ { ++ { 0x28, 0x10, 0x43, 0xe7 }, ++ }, ++}; ++ ++static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = { ++ {0x0090, 0x68}, {0x0094, 0x68}, ++ {0x0128, 0x24}, {0x012c, 0x44}, ++ {0x0130, 0x3f}, {0x0134, 0x44}, ++ {0x015c, 0xa9}, {0x0160, 0x71}, ++ {0x0164, 0x71}, {0x0168, 0xa9}, ++ {0x0174, 0xa9}, {0x0178, 0x71}, ++ {0x017c, 0x71}, {0x0180, 0xa9}, ++ {0x018c, 0x41}, {0x0190, 0x00}, ++ {0x0194, 0x05}, {0x01ac, 0x2a}, ++ {0x01b0, 0x17}, {0x01b4, 0x17}, ++ {0x01b8, 0x2a}, {0x01c8, 0x04}, ++ {0x01cc, 0x08}, {0x01d0, 0x08}, ++ {0x01d4, 0x04}, {0x01d8, 0x20}, ++ {0x01dc, 0x01}, {0x01e0, 0x09}, ++ {0x01e4, 0x03}, {0x01f0, 0x29}, ++ {0x01f4, 0x02}, {0x01f8, 0x02}, ++ {0x01fc, 0x29}, {0x0208, 0x2a}, ++ {0x020c, 0x17}, {0x0210, 0x17}, ++ {0x0214, 0x2a}, {0x0224, 0x20}, ++ {0x03f0, 0x0a}, {0x03f4, 0x07}, ++ {0x03f8, 0x07}, {0x03fc, 0x0c}, ++ {0x0404, 0x12}, {0x0408, 0x1a}, ++ {0x040c, 0x1a}, {0x0410, 0x3f}, ++ {0x0ce0, 0x68}, {0x0ce8, 0xd0}, ++ {0x0cf0, 0x87}, {0x0cf8, 0x70}, ++ {0x0d00, 0x70}, {0x0d08, 0xa9}, ++ {0x1ce0, 0x68}, {0x1ce8, 0xd0}, ++ {0x1cf0, 0x87}, {0x1cf8, 0x70}, ++ {0x1d00, 0x70}, {0x1d08, 0xa9}, ++ {0x0a3c, 0xd0}, {0x0a44, 0xd0}, ++ {0x0a48, 0x01}, {0x0a4c, 0x0d}, ++ {0x0a54, 0xe0}, {0x0a5c, 0xe0}, ++ {0x0a64, 0xa8}, {0x1a3c, 0xd0}, ++ {0x1a44, 0xd0}, {0x1a48, 0x01}, ++ {0x1a4c, 0x0d}, {0x1a54, 0xe0}, ++ {0x1a5c, 0xe0}, {0x1a64, 0xa8} ++}; ++ ++static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = { ++ {0x0830, 0x07}, {0x085c, 0x80}, ++ {0x1030, 0x07}, {0x105c, 0x80}, ++ {0x1830, 0x07}, {0x185c, 0x80}, ++ {0x2030, 0x07}, {0x205c, 0x80}, ++ {0x0228, 0x38}, {0x0104, 0x44}, ++ {0x0248, 0x44}, {0x038c, 0x02}, ++ {0x0878, 0x04}, {0x1878, 0x04}, ++ {0x0898, 0x77}, {0x1898, 0x77}, ++ {0x0054, 0x01}, {0x00e0, 0x38}, ++ {0x0060, 0x24}, {0x0064, 0x77}, ++ {0x0070, 0x76}, {0x0234, 0xe8}, ++ {0x0af4, 0x15}, {0x1af4, 0x15}, ++ {0x081c, 0xe5}, {0x181c, 0xe5}, ++ {0x099c, 0x48}, {0x199c, 0x48}, ++ {0x09a4, 0x07}, {0x09a8, 0x22}, ++ {0x19a4, 0x07}, {0x19a8, 0x22}, ++ {0x09b8, 0x3e}, {0x19b8, 0x3e}, ++ {0x09e4, 0x02}, {0x19e4, 0x02}, ++ {0x0a34, 0x1e}, {0x1a34, 0x1e}, ++ {0x0a98, 0x2f}, {0x1a98, 0x2f}, ++ {0x0c30, 0x0e}, {0x0c48, 0x06}, ++ {0x1c30, 0x0e}, {0x1c48, 0x06}, ++ {0x028c, 0x18}, {0x0af0, 0x00}, ++ {0x1af0, 0x00} ++}; ++ ++static const struct reg_sequence rk_udphy_init_sequence[] = { ++ {0x0104, 0x44}, {0x0234, 0xe8}, ++ {0x0248, 0x44}, {0x028c, 0x18}, ++ {0x081c, 0xe5}, {0x0878, 0x00}, ++ {0x0994, 0x1c}, {0x0af0, 0x00}, ++ {0x181c, 0xe5}, {0x1878, 0x00}, ++ {0x1994, 0x1c}, {0x1af0, 0x00}, ++ {0x0428, 0x60}, {0x0d58, 0x33}, ++ {0x1d58, 0x33}, {0x0990, 0x74}, ++ {0x0d64, 0x17}, {0x08c8, 0x13}, ++ {0x1990, 0x74}, {0x1d64, 0x17}, ++ {0x18c8, 0x13}, {0x0d90, 0x40}, ++ {0x0da8, 0x40}, {0x0dc0, 0x40}, ++ {0x0dd8, 0x40}, {0x1d90, 0x40}, ++ {0x1da8, 0x40}, {0x1dc0, 0x40}, ++ {0x1dd8, 0x40}, {0x03c0, 0x30}, ++ {0x03c4, 0x06}, {0x0e10, 0x00}, ++ {0x1e10, 0x00}, {0x043c, 0x0f}, ++ {0x0d2c, 0xff}, {0x1d2c, 0xff}, ++ {0x0d34, 0x0f}, {0x1d34, 0x0f}, ++ {0x08fc, 0x2a}, {0x0914, 0x28}, ++ {0x0a30, 0x03}, {0x0e38, 0x03}, ++ {0x0ecc, 0x27}, {0x0ed0, 0x22}, ++ {0x0ed4, 0x26}, {0x18fc, 0x2a}, ++ {0x1914, 0x28}, {0x1a30, 0x03}, ++ {0x1e38, 0x03}, {0x1ecc, 0x27}, ++ {0x1ed0, 0x22}, {0x1ed4, 0x26}, ++ {0x0048, 0x0f}, {0x0060, 0x3c}, ++ {0x0064, 0xf7}, {0x006c, 0x20}, ++ {0x0070, 0x7d}, {0x0074, 0x68}, ++ {0x0af4, 0x1a}, {0x1af4, 0x1a}, ++ {0x0440, 0x3f}, {0x10d4, 0x08}, ++ {0x20d4, 0x08}, {0x00d4, 0x30}, ++ {0x0024, 0x6e}, ++}; ++ ++static inline int rk_udphy_grfreg_write(struct regmap *base, ++ const struct rk_udphy_grf_reg *reg, bool en) ++{ ++ return regmap_write(base, reg->offset, en ? reg->enable : reg->disable); ++} ++ ++static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev) ++{ ++ int i; ++ ++ udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks); ++ if (udphy->num_clks < 1) ++ return -ENODEV; ++ ++ /* used for configure phy reference clock frequency */ ++ for (i = 0; i < udphy->num_clks; i++) { ++ if (!strncmp(udphy->clks[i].id, "refclk", 6)) { ++ udphy->refclk = udphy->clks[i].clk; ++ break; ++ } ++ } ++ ++ if (!udphy->refclk) ++ return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n"); ++ ++ return 0; ++} ++ ++static int rk_udphy_reset_assert_all(struct rk_udphy *udphy) ++{ ++ return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts); ++} ++ ++static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy) ++{ ++ return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts); ++} ++ ++static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name) ++{ ++ struct reset_control_bulk_data *list = udphy->rsts; ++ int idx; ++ ++ for (idx = 0; idx < udphy->num_rsts; idx++) { ++ if (!strcmp(list[idx].id, name)) ++ return reset_control_deassert(list[idx].rstc); ++ } ++ ++ return -EINVAL; ++} ++ ++static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ int idx; ++ ++ udphy->num_rsts = cfg->num_rsts; ++ udphy->rsts = devm_kcalloc(dev, udphy->num_rsts, ++ sizeof(*udphy->rsts), GFP_KERNEL); ++ if (!udphy->rsts) ++ return -ENOMEM; ++ ++ for (idx = 0; idx < cfg->num_rsts; idx++) ++ udphy->rsts[idx].id = cfg->rst_list[idx]; ++ ++ return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts, ++ udphy->rsts); ++} ++ ++static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ const struct rk_udphy_grf_reg *preg; ++ ++ preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; ++ rk_udphy_grfreg_write(udphy->usbgrf, preg, disable); ++} ++ ++static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ ++ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); ++ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); ++} ++ ++/* ++ * In usb/dp combo phy driver, here are 2 ways to mapping lanes. ++ * ++ * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) ++ * --------------------------------------------------------------------------- ++ * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 ++ * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) ++ * C/E(Normal) dpln3 dpln2 dpln0 dpln1 ++ * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 ++ * D/F(Normal) usbrx usbtx dpln0 dpln1 ++ * D/F(Flip ) dpln0 dpln1 usbrx usbtx ++ * A(Normal ) dpln3 dpln1 dpln2 dpln0 ++ * A(Flip ) dpln2 dpln0 dpln3 dpln1 ++ * B(Normal ) usbrx usbtx dpln1 dpln0 ++ * B(Flip ) dpln1 dpln0 usbrx usbtx ++ * --------------------------------------------------------------------------- ++ * ++ * 2 Mapping the lanes in dtsi ++ * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = ; ++ * sample as follow: ++ * --------------------------------------------------------------------------- ++ * B11-B10 A2-A3 A11-A10 B2-B3 ++ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) ++ * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 ++ * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 ++ * --------------------------------------------------------------------------- ++ * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = ; ++ * sample as follow: ++ * --------------------------------------------------------------------------- ++ * B11-B10 A2-A3 A11-A10 B2-B3 ++ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) ++ * <0 1> dpln0 dpln1 usbrx usbtx ++ * <2 3> usbrx usbtx dpln0 dpln1 ++ * --------------------------------------------------------------------------- ++ */ ++ ++static void rk_udphy_dplane_select(struct rk_udphy *udphy) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ u32 value = 0; ++ ++ switch (udphy->mode) { ++ case UDPHY_MODE_DP: ++ value |= 2 << udphy->dp_lane_sel[2] * 2; ++ value |= 3 << udphy->dp_lane_sel[3] * 2; ++ fallthrough; ++ ++ case UDPHY_MODE_DP_USB: ++ value |= 0 << udphy->dp_lane_sel[0] * 2; ++ value |= 1 << udphy->dp_lane_sel[1] * 2; ++ break; ++ ++ case UDPHY_MODE_USB: ++ break; ++ ++ default: ++ break; ++ } ++ ++ regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, ++ ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | ++ FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | ++ FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); ++} ++ ++static int rk_udphy_dplane_get(struct rk_udphy *udphy) ++{ ++ int dp_lanes; ++ ++ switch (udphy->mode) { ++ case UDPHY_MODE_DP: ++ dp_lanes = 4; ++ break; ++ ++ case UDPHY_MODE_DP_USB: ++ dp_lanes = 2; ++ break; ++ ++ case UDPHY_MODE_USB: ++ default: ++ dp_lanes = 0; ++ break; ++ } ++ ++ return dp_lanes; ++} ++ ++static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes) ++{ ++ u32 val = 0; ++ int i; ++ ++ for (i = 0; i < dp_lanes; i++) ++ val |= BIT(udphy->dp_lane_sel[i]); ++ ++ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, ++ FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); ++ ++ if (!dp_lanes) ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); ++} ++ ++static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ ++ udphy->dp_sink_hpd_sel = true; ++ udphy->dp_sink_hpd_cfg = hpd; ++ ++ if (!udphy->dp_in_use) ++ return; ++ ++ rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd); ++} ++ ++static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy) ++{ ++ if (udphy->flip) { ++ udphy->dp_lane_sel[0] = 0; ++ udphy->dp_lane_sel[1] = 1; ++ udphy->dp_lane_sel[2] = 3; ++ udphy->dp_lane_sel[3] = 2; ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; ++ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; ++ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; ++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1); ++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); ++ } else { ++ udphy->dp_lane_sel[0] = 2; ++ udphy->dp_lane_sel[1] = 3; ++ udphy->dp_lane_sel[2] = 1; ++ udphy->dp_lane_sel[3] = 0; ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; ++ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; ++ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; ++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); ++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1); ++ } ++ ++ udphy->mode = UDPHY_MODE_DP_USB; ++} ++ ++static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, ++ enum typec_orientation orien) ++{ ++ struct rk_udphy *udphy = typec_switch_get_drvdata(sw); ++ ++ mutex_lock(&udphy->mutex); ++ ++ if (orien == TYPEC_ORIENTATION_NONE) { ++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); ++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); ++ /* unattached */ ++ rk_udphy_usb_bvalid_enable(udphy, false); ++ goto unlock_ret; ++ } ++ ++ udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false; ++ rk_udphy_set_typec_default_mapping(udphy); ++ rk_udphy_usb_bvalid_enable(udphy, true); ++ ++unlock_ret: ++ mutex_unlock(&udphy->mutex); ++ return 0; ++} ++ ++static void rk_udphy_orien_switch_unregister(void *data) ++{ ++ struct rk_udphy *udphy = data; ++ ++ typec_switch_unregister(udphy->sw); ++} ++ ++static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) ++{ ++ struct typec_switch_desc sw_desc = { }; ++ ++ sw_desc.drvdata = udphy; ++ sw_desc.fwnode = dev_fwnode(udphy->dev); ++ sw_desc.set = rk_udphy_orien_sw_set; ++ ++ udphy->sw = typec_switch_register(udphy->dev, &sw_desc); ++ if (IS_ERR(udphy->sw)) { ++ dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", ++ PTR_ERR(udphy->sw)); ++ return PTR_ERR(udphy->sw); ++ } ++ ++ return devm_add_action_or_reset(udphy->dev, ++ rk_udphy_orien_switch_unregister, udphy); ++} ++ ++static int rk_udphy_refclk_set(struct rk_udphy *udphy) ++{ ++ unsigned long rate; ++ int ret; ++ ++ /* configure phy reference clock */ ++ rate = clk_get_rate(udphy->refclk); ++ dev_dbg(udphy->dev, "refclk freq %ld\n", rate); ++ ++ switch (rate) { ++ case 24000000: ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg, ++ ARRAY_SIZE(rk_udphy_24m_refclk_cfg)); ++ if (ret) ++ return ret; ++ break; ++ ++ case 26000000: ++ /* register default is 26MHz */ ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg, ++ ARRAY_SIZE(rk_udphy_26m_refclk_cfg)); ++ if (ret) ++ return ret; ++ break; ++ ++ default: ++ dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rk_udphy_status_check(struct rk_udphy *udphy) ++{ ++ unsigned int val; ++ int ret; ++ ++ /* LCPLL check */ ++ if (udphy->mode & UDPHY_MODE_USB) { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, ++ val, (val & CMN_ANA_LCPLL_AFC_DONE) && ++ (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); ++ if (ret) { ++ dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); ++ /* ++ * If earlier software (U-Boot) enabled USB once already ++ * the PLL may have problems locking on the first try. ++ * It will be successful on the second try, so for the ++ * time being a -EPROBE_DEFER will solve the issue. ++ * ++ * This requires further investigation to understand the ++ * root cause, especially considering that the driver is ++ * asserting all reset lines at probe time. ++ */ ++ return -EPROBE_DEFER; ++ } ++ ++ if (!udphy->flip) { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, ++ TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, ++ val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, ++ 200, 100000); ++ if (ret) ++ dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); ++ } else { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, ++ TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, ++ val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, ++ 200, 100000); ++ if (ret) ++ dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static int rk_udphy_init(struct rk_udphy *udphy) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ int ret; ++ ++ rk_udphy_reset_assert_all(udphy); ++ usleep_range(10000, 11000); ++ ++ /* enable rx lfps for usb */ ++ if (udphy->mode & UDPHY_MODE_USB) ++ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); ++ ++ /* Step 1: power on pma and deassert apb rstn */ ++ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); ++ ++ rk_udphy_reset_deassert(udphy, "pma_apb"); ++ rk_udphy_reset_deassert(udphy, "pcs_apb"); ++ ++ /* Step 2: set init sequence and phy refclk */ ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence, ++ ARRAY_SIZE(rk_udphy_init_sequence)); ++ if (ret) { ++ dev_err(udphy->dev, "init sequence set error %d\n", ret); ++ goto assert_resets; ++ } ++ ++ ret = rk_udphy_refclk_set(udphy); ++ if (ret) { ++ dev_err(udphy->dev, "refclk set error %d\n", ret); ++ goto assert_resets; ++ } ++ ++ /* Step 3: configure lane mux */ ++ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, ++ CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, ++ FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | ++ FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); ++ ++ /* Step 4: deassert init rstn and wait for 200ns from datasheet */ ++ if (udphy->mode & UDPHY_MODE_USB) ++ rk_udphy_reset_deassert(udphy, "init"); ++ ++ if (udphy->mode & UDPHY_MODE_DP) { ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_INIT_RSTN, ++ FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); ++ } ++ ++ udelay(1); ++ ++ /* Step 5: deassert cmn/lane rstn */ ++ if (udphy->mode & UDPHY_MODE_USB) { ++ rk_udphy_reset_deassert(udphy, "cmn"); ++ rk_udphy_reset_deassert(udphy, "lane"); ++ } ++ ++ /* Step 6: wait for lock done of pll */ ++ ret = rk_udphy_status_check(udphy); ++ if (ret) ++ goto assert_resets; ++ ++ return 0; ++ ++assert_resets: ++ rk_udphy_reset_assert_all(udphy); ++ return ret; ++} ++ ++static int rk_udphy_setup(struct rk_udphy *udphy) ++{ ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); ++ if (ret) { ++ dev_err(udphy->dev, "failed to enable clk\n"); ++ return ret; ++ } ++ ++ ret = rk_udphy_init(udphy); ++ if (ret) { ++ dev_err(udphy->dev, "failed to init combophy\n"); ++ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rk_udphy_disable(struct rk_udphy *udphy) ++{ ++ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); ++ rk_udphy_reset_assert_all(udphy); ++} ++ ++static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy) ++{ ++ int ret, i, num_lanes; ++ ++ num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); ++ if (num_lanes < 0) { ++ dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n"); ++ udphy->mode = UDPHY_MODE_USB; ++ return 0; ++ } ++ ++ if (num_lanes != 2 && num_lanes != 4) ++ return dev_err_probe(udphy->dev, -EINVAL, ++ "invalid number of lane mux\n"); ++ ++ ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux", ++ udphy->dp_lane_sel, num_lanes); ++ if (ret) ++ return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n"); ++ ++ for (i = 0; i < num_lanes; i++) { ++ int j; ++ ++ if (udphy->dp_lane_sel[i] > 3) ++ return dev_err_probe(udphy->dev, -EINVAL, ++ "lane mux between 0 and 3, exceeding the range\n"); ++ ++ udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; ++ ++ for (j = i + 1; j < num_lanes; j++) { ++ if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) ++ return dev_err_probe(udphy->dev, -EINVAL, ++ "set repeat lane mux value\n"); ++ } ++ } ++ ++ udphy->mode = UDPHY_MODE_DP; ++ if (num_lanes == 2) { ++ udphy->mode |= UDPHY_MODE_USB; ++ udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP); ++ } ++ ++ return 0; ++} ++ ++static int rk_udphy_get_initial_status(struct rk_udphy *udphy) ++{ ++ int ret; ++ u32 value; ++ ++ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); ++ if (ret) { ++ dev_err(udphy->dev, "failed to enable clk\n"); ++ return ret; ++ } ++ ++ rk_udphy_reset_deassert_all(udphy); ++ ++ regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value); ++ if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value)) ++ udphy->status = UDPHY_MODE_DP; ++ else ++ rk_udphy_disable(udphy); ++ ++ return 0; ++} ++ ++static int rk_udphy_parse_dt(struct rk_udphy *udphy) ++{ ++ struct device *dev = udphy->dev; ++ struct device_node *np = dev_of_node(dev); ++ enum usb_device_speed maximum_speed; ++ int ret; ++ ++ udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf"); ++ if (IS_ERR(udphy->u2phygrf)) ++ return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n"); ++ ++ udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf"); ++ if (IS_ERR(udphy->udphygrf)) ++ return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n"); ++ ++ udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf"); ++ if (IS_ERR(udphy->usbgrf)) ++ return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n"); ++ ++ udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf"); ++ if (IS_ERR(udphy->vogrf)) ++ return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n"); ++ ++ ret = rk_udphy_parse_lane_mux_data(udphy); ++ if (ret) ++ return ret; ++ ++ udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW); ++ if (IS_ERR(udphy->sbu1_dc_gpio)) ++ return PTR_ERR(udphy->sbu1_dc_gpio); ++ ++ udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW); ++ if (IS_ERR(udphy->sbu2_dc_gpio)) ++ return PTR_ERR(udphy->sbu2_dc_gpio); ++ ++ if (device_property_present(dev, "maximum-speed")) { ++ maximum_speed = usb_get_maximum_speed(dev); ++ udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; ++ } ++ ++ ret = rk_udphy_clk_init(udphy, dev); ++ if (ret) ++ return ret; ++ ++ return rk_udphy_reset_init(udphy, dev); ++} ++ ++static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode) ++{ ++ int ret; ++ ++ if (!(udphy->mode & mode)) { ++ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); ++ return 0; ++ } ++ ++ if (udphy->status == UDPHY_MODE_NONE) { ++ udphy->mode_change = false; ++ ret = rk_udphy_setup(udphy); ++ if (ret) ++ return ret; ++ ++ if (udphy->mode & UDPHY_MODE_USB) ++ rk_udphy_u3_port_disable(udphy, false); ++ } else if (udphy->mode_change) { ++ udphy->mode_change = false; ++ udphy->status = UDPHY_MODE_NONE; ++ if (udphy->mode == UDPHY_MODE_DP) ++ rk_udphy_u3_port_disable(udphy, true); ++ ++ rk_udphy_disable(udphy); ++ ret = rk_udphy_setup(udphy); ++ if (ret) ++ return ret; ++ } ++ ++ udphy->status |= mode; ++ ++ return 0; ++} ++ ++static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode) ++{ ++ if (!(udphy->mode & mode)) { ++ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); ++ return; ++ } ++ ++ if (!udphy->status) ++ return; ++ ++ udphy->status &= ~mode; ++ ++ if (udphy->status == UDPHY_MODE_NONE) ++ rk_udphy_disable(udphy); ++} ++ ++static int rk_udphy_dp_phy_init(struct phy *phy) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ ++ mutex_lock(&udphy->mutex); ++ ++ udphy->dp_in_use = true; ++ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); ++ ++ mutex_unlock(&udphy->mutex); ++ ++ return 0; ++} ++ ++static int rk_udphy_dp_phy_exit(struct phy *phy) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ ++ mutex_lock(&udphy->mutex); ++ udphy->dp_in_use = false; ++ mutex_unlock(&udphy->mutex); ++ return 0; ++} ++ ++static int rk_udphy_dp_phy_power_on(struct phy *phy) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ int ret, dp_lanes; ++ ++ mutex_lock(&udphy->mutex); ++ ++ dp_lanes = rk_udphy_dplane_get(udphy); ++ phy_set_bus_width(phy, dp_lanes); ++ ++ ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP); ++ if (ret) ++ goto unlock; ++ ++ rk_udphy_dplane_enable(udphy, dp_lanes); ++ ++ rk_udphy_dplane_select(udphy); ++ ++unlock: ++ mutex_unlock(&udphy->mutex); ++ /* ++ * If data send by aux channel too fast after phy power on, ++ * the aux may be not ready which will cause aux error. Adding ++ * delay to avoid this issue. ++ */ ++ usleep_range(10000, 11000); ++ return ret; ++} ++ ++static int rk_udphy_dp_phy_power_off(struct phy *phy) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ ++ mutex_lock(&udphy->mutex); ++ rk_udphy_dplane_enable(udphy, 0); ++ rk_udphy_power_off(udphy, UDPHY_MODE_DP); ++ mutex_unlock(&udphy->mutex); ++ ++ return 0; ++} ++ ++static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate) ++{ ++ switch (link_rate) { ++ case 1620: ++ case 2700: ++ case 5400: ++ case 8100: ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy, ++ struct phy_configure_opts_dp *dp) ++{ ++ int i, ret; ++ ++ /* If changing link rate was required, verify it's supported. */ ++ ret = rk_udphy_dp_phy_verify_link_rate(dp->link_rate); ++ if (ret) ++ return ret; ++ ++ /* Verify lane count. */ ++ switch (dp->lanes) { ++ case 1: ++ case 2: ++ case 4: ++ /* valid lane count. */ ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ /* ++ * If changing voltages is required, check swing and pre-emphasis ++ * levels, per-lane. ++ */ ++ if (dp->set_voltages) { ++ /* Lane count verified previously. */ ++ for (i = 0; i < dp->lanes; i++) { ++ if (dp->voltage[i] > 3 || dp->pre[i] > 3) ++ return -EINVAL; ++ ++ /* ++ * Sum of voltage swing and pre-emphasis levels cannot ++ * exceed 3. ++ */ ++ if (dp->voltage[i] + dp->pre[i] > 3) ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw, ++ u32 voltage, u32 pre, u32 lane) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4]; ++ u32 offset = 0x800 * lane; ++ u32 val; ++ ++ if (udphy->mux) ++ dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw]; ++ else ++ dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0204; ++ regmap_write(udphy->pma_regmap, 0x0810 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0205; ++ regmap_write(udphy->pma_regmap, 0x0814 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0206; ++ regmap_write(udphy->pma_regmap, 0x0818 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0207; ++ regmap_write(udphy->pma_regmap, 0x081c + offset, val); ++} ++ ++static int rk_udphy_dp_phy_configure(struct phy *phy, ++ union phy_configure_opts *opts) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ struct phy_configure_opts_dp *dp = &opts->dp; ++ u32 i, val, lane; ++ int ret; ++ ++ ret = rk_udphy_dp_phy_verify_config(udphy, dp); ++ if (ret) ++ return ret; ++ ++ if (dp->set_rate) { ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); ++ ++ switch (dp->link_rate) { ++ case 1620: ++ udphy->bw = DP_BW_RBR; ++ break; ++ ++ case 2700: ++ udphy->bw = DP_BW_HBR; ++ break; ++ ++ case 5400: ++ udphy->bw = DP_BW_HBR2; ++ break; ++ ++ case 8100: ++ udphy->bw = DP_BW_HBR3; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, ++ FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); ++ regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, ++ FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, ++ FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); ++ ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, ++ FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && ++ FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), ++ 0, 1000); ++ if (ret) { ++ dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n"); ++ return ret; ++ } ++ } ++ ++ if (dp->set_voltages) { ++ for (i = 0; i < dp->lanes; i++) { ++ lane = udphy->dp_lane_sel[i]; ++ switch (dp->link_rate) { ++ case 1620: ++ case 2700: ++ regmap_update_bits(udphy->pma_regmap, ++ TRSV_ANA_TX_CLK_OFFSET_N(lane), ++ LN_ANA_TX_SER_TXCLK_INV, ++ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, ++ udphy->lane_mux_sel[lane])); ++ break; ++ ++ case 5400: ++ case 8100: ++ regmap_update_bits(udphy->pma_regmap, ++ TRSV_ANA_TX_CLK_OFFSET_N(lane), ++ LN_ANA_TX_SER_TXCLK_INV, ++ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); ++ break; ++ } ++ ++ rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i], ++ dp->pre[i], lane); ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct phy_ops rk_udphy_dp_phy_ops = { ++ .init = rk_udphy_dp_phy_init, ++ .exit = rk_udphy_dp_phy_exit, ++ .power_on = rk_udphy_dp_phy_power_on, ++ .power_off = rk_udphy_dp_phy_power_off, ++ .configure = rk_udphy_dp_phy_configure, ++ .owner = THIS_MODULE, ++}; ++ ++static int rk_udphy_usb3_phy_init(struct phy *phy) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ int ret; ++ ++ mutex_lock(&udphy->mutex); ++ /* DP only or high-speed, disable U3 port */ ++ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { ++ rk_udphy_u3_port_disable(udphy, true); ++ goto unlock; ++ } ++ ++ ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB); ++ ++unlock: ++ mutex_unlock(&udphy->mutex); ++ return ret; ++} ++ ++static int rk_udphy_usb3_phy_exit(struct phy *phy) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ ++ mutex_lock(&udphy->mutex); ++ /* DP only or high-speed */ ++ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) ++ goto unlock; ++ ++ rk_udphy_power_off(udphy, UDPHY_MODE_USB); ++ ++unlock: ++ mutex_unlock(&udphy->mutex); ++ return 0; ++} ++ ++static const struct phy_ops rk_udphy_usb3_phy_ops = { ++ .init = rk_udphy_usb3_phy_init, ++ .exit = rk_udphy_usb3_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux, ++ struct typec_mux_state *state) ++{ ++ struct rk_udphy *udphy = typec_mux_get_drvdata(mux); ++ u8 mode; ++ ++ mutex_lock(&udphy->mutex); ++ ++ switch (state->mode) { ++ case TYPEC_DP_STATE_C: ++ case TYPEC_DP_STATE_E: ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; ++ mode = UDPHY_MODE_DP; ++ break; ++ ++ case TYPEC_DP_STATE_D: ++ default: ++ if (udphy->flip) { ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; ++ } else { ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; ++ } ++ mode = UDPHY_MODE_DP_USB; ++ break; ++ } ++ ++ if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) { ++ struct typec_displayport_data *data = state->data; ++ ++ if (!data) { ++ rk_udphy_dp_hpd_event_trigger(udphy, false); ++ } else if (data->status & DP_STATUS_IRQ_HPD) { ++ rk_udphy_dp_hpd_event_trigger(udphy, false); ++ usleep_range(750, 800); ++ rk_udphy_dp_hpd_event_trigger(udphy, true); ++ } else if (data->status & DP_STATUS_HPD_STATE) { ++ if (udphy->mode != mode) { ++ udphy->mode = mode; ++ udphy->mode_change = true; ++ } ++ rk_udphy_dp_hpd_event_trigger(udphy, true); ++ } else { ++ rk_udphy_dp_hpd_event_trigger(udphy, false); ++ } ++ } ++ ++ mutex_unlock(&udphy->mutex); ++ return 0; ++} ++ ++static void rk_udphy_typec_mux_unregister(void *data) ++{ ++ struct rk_udphy *udphy = data; ++ ++ typec_mux_unregister(udphy->mux); ++} ++ ++static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy) ++{ ++ struct typec_mux_desc mux_desc = {}; ++ ++ mux_desc.drvdata = udphy; ++ mux_desc.fwnode = dev_fwnode(udphy->dev); ++ mux_desc.set = rk_udphy_typec_mux_set; ++ ++ udphy->mux = typec_mux_register(udphy->dev, &mux_desc); ++ if (IS_ERR(udphy->mux)) { ++ dev_err(udphy->dev, "Error register typec mux: %ld\n", ++ PTR_ERR(udphy->mux)); ++ return PTR_ERR(udphy->mux); ++ } ++ ++ return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister, ++ udphy); ++} ++ ++static const struct regmap_config rk_udphy_pma_regmap_cfg = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .fast_io = true, ++ .max_register = 0x20dc, ++}; ++ ++static struct phy *rk_udphy_phy_xlate(struct device *dev, struct of_phandle_args *args) ++{ ++ struct rk_udphy *udphy = dev_get_drvdata(dev); ++ ++ if (args->args_count == 0) ++ return ERR_PTR(-EINVAL); ++ ++ switch (args->args[0]) { ++ case PHY_TYPE_USB3: ++ return udphy->phy_u3; ++ case PHY_TYPE_DP: ++ return udphy->phy_dp; ++ } ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++static int rk_udphy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct phy_provider *phy_provider; ++ struct resource *res; ++ struct rk_udphy *udphy; ++ void __iomem *base; ++ int id, ret; ++ ++ udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL); ++ if (!udphy) ++ return -ENOMEM; ++ ++ udphy->cfgs = device_get_match_data(dev); ++ if (!udphy->cfgs) ++ return dev_err_probe(dev, -EINVAL, "missing match data\n"); ++ ++ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ /* find the phy-id from the io address */ ++ udphy->id = -ENODEV; ++ for (id = 0; id < udphy->cfgs->num_phys; id++) { ++ if (res->start == udphy->cfgs->phy_ids[id]) { ++ udphy->id = id; ++ break; ++ } ++ } ++ ++ if (udphy->id < 0) ++ return dev_err_probe(dev, -ENODEV, "no matching device found\n"); ++ ++ udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA, ++ &rk_udphy_pma_regmap_cfg); ++ if (IS_ERR(udphy->pma_regmap)) ++ return PTR_ERR(udphy->pma_regmap); ++ ++ udphy->dev = dev; ++ ret = rk_udphy_parse_dt(udphy); ++ if (ret) ++ return ret; ++ ++ ret = rk_udphy_get_initial_status(udphy); ++ if (ret) ++ return ret; ++ ++ mutex_init(&udphy->mutex); ++ platform_set_drvdata(pdev, udphy); ++ ++ if (device_property_present(dev, "orientation-switch")) { ++ ret = rk_udphy_setup_orien_switch(udphy); ++ if (ret) ++ return ret; ++ } ++ ++ if (device_property_present(dev, "mode-switch")) { ++ ret = rk_udphy_setup_typec_mux(udphy); ++ if (ret) ++ return ret; ++ } ++ ++ udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops); ++ if (IS_ERR(udphy->phy_u3)) { ++ ret = PTR_ERR(udphy->phy_u3); ++ return dev_err_probe(dev, ret, "failed to create USB3 phy\n"); ++ } ++ phy_set_drvdata(udphy->phy_u3, udphy); ++ ++ udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops); ++ if (IS_ERR(udphy->phy_dp)) { ++ ret = PTR_ERR(udphy->phy_dp); ++ return dev_err_probe(dev, ret, "failed to create DP phy\n"); ++ } ++ phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy)); ++ udphy->phy_dp->attrs.max_link_rate = 8100; ++ phy_set_drvdata(udphy->phy_dp, udphy); ++ ++ phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate); ++ if (IS_ERR(phy_provider)) { ++ ret = PTR_ERR(phy_provider); ++ return dev_err_probe(dev, ret, "failed to register phy provider\n"); ++ } ++ ++ return 0; ++} ++ ++static int __maybe_unused rk_udphy_resume(struct device *dev) ++{ ++ struct rk_udphy *udphy = dev_get_drvdata(dev); ++ ++ if (udphy->dp_sink_hpd_sel) ++ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops rk_udphy_pm_ops = { ++ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume) ++}; ++ ++static const char * const rk_udphy_rst_list[] = { ++ "init", "cmn", "lane", "pcs_apb", "pma_apb" ++}; ++ ++static const struct rk_udphy_cfg rk3588_udphy_cfgs = { ++ .num_phys = 2, ++ .phy_ids = { ++ 0xfed80000, ++ 0xfed90000, ++ }, ++ .num_rsts = ARRAY_SIZE(rk_udphy_rst_list), ++ .rst_list = rk_udphy_rst_list, ++ .grfcfg = { ++ /* u2phy-grf */ ++ .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3), ++ .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3), ++ ++ /* usb-grf */ ++ .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188), ++ .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188), ++ ++ /* usbdpphy-grf */ ++ .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1), ++ .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1), ++ }, ++ .vogrfcfg = { ++ { ++ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3), ++ .dp_lane_reg = 0x0000, ++ }, ++ { ++ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3), ++ .dp_lane_reg = 0x0008, ++ }, ++ }, ++ .dp_tx_ctrl_cfg = { ++ rk3588_dp_tx_drv_ctrl_rbr_hbr, ++ rk3588_dp_tx_drv_ctrl_rbr_hbr, ++ rk3588_dp_tx_drv_ctrl_hbr2, ++ rk3588_dp_tx_drv_ctrl_hbr3, ++ }, ++ .dp_tx_ctrl_cfg_typec = { ++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, ++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, ++ rk3588_dp_tx_drv_ctrl_hbr2, ++ rk3588_dp_tx_drv_ctrl_hbr3, ++ }, ++}; ++ ++static const struct of_device_id rk_udphy_dt_match[] = { ++ { ++ .compatible = "rockchip,rk3588-usbdp-phy", ++ .data = &rk3588_udphy_cfgs ++ }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, rk_udphy_dt_match); ++ ++static struct platform_driver rk_udphy_driver = { ++ .probe = rk_udphy_probe, ++ .driver = { ++ .name = "rockchip-usbdp-phy", ++ .of_match_table = rk_udphy_dt_match, ++ .pm = &rk_udphy_pm_ops, ++ }, ++}; ++module_platform_driver(rk_udphy_driver); ++ ++MODULE_AUTHOR("Frank Wang "); ++MODULE_AUTHOR("Zhang Yubing "); ++MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch b/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch new file mode 100644 index 00000000000000..65bd8a7ed83232 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch @@ -0,0 +1,35 @@ +From c9342d1a351ee1249fa98d936f756299a83d5684 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 16 Apr 2024 16:51:23 +0200 +Subject: [PATCH] phy: rockchip: usbdp: fix uninitialized variable + +The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if +the PHY is not using USB3 mode. + +Since the DisplayPort part is handled separately and the PHY does not +support USB2 (which is routed to another PHY on Rockchip RK3588), the +right exit code for this case is 0. Thus let's initialize the variable +accordingly. + +Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver") +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/ +Signed-off-by: Sebastian Reichel +Reviewed-by: Muhammad Usama Anjum +Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c ++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c +@@ -1285,7 +1285,7 @@ static const struct phy_ops rk_udphy_dp_ + static int rk_udphy_usb3_phy_init(struct phy *phy) + { + struct rk_udphy *udphy = phy_get_drvdata(phy); +- int ret; ++ int ret = 0; + + mutex_lock(&udphy->mutex); + /* DP only or high-speed, disable U3 port */ diff --git a/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch b/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch new file mode 100644 index 00000000000000..a8b9aa15fc87db --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch @@ -0,0 +1,43 @@ +From 9c79b779643e56d4253bd3ba6998c58c819943af Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Mon, 15 Apr 2024 19:42:25 +0200 +Subject: [PATCH] phy: rockchip: fix CONFIG_TYPEC dependency + +The newly added driver causes a warning about missing dependencies +by selecting CONFIG_TYPEC unconditionally: + +WARNING: unmet direct dependencies detected for TYPEC + Depends on [n]: USB_SUPPORT [=n] + Selected by [y]: + - PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y] + +WARNING: unmet direct dependencies detected for USB_COMMON + Depends on [n]: USB_SUPPORT [=n] + Selected by [y]: + - EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y] + +Since that is a user-visible option, it should not really be selected +in the first place. Replace the 'select' with a 'depends on' as +we have for similar drivers. + +Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver") +Signed-off-by: Arnd Bergmann +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/phy/rockchip/Kconfig ++++ b/drivers/phy/rockchip/Kconfig +@@ -111,8 +111,8 @@ config PHY_ROCKCHIP_USB + config PHY_ROCKCHIP_USBDP + tristate "Rockchip USBDP COMBO PHY Driver" + depends on ARCH_ROCKCHIP && OF ++ depends on TYPEC + select GENERIC_PHY +- select TYPEC + help + Enable this to support the Rockchip USB3.0/DP combo PHY with + Samsung IP block. This is required for USB3 support on RK3588. diff --git a/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-Fix-typo-in-function-names.patch b/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-Fix-typo-in-function-names.patch new file mode 100644 index 00000000000000..9495dd2b108839 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-Fix-typo-in-function-names.patch @@ -0,0 +1,79 @@ +From 9b6bfad9070a95d19973be17177e5d9220cbbf1f Mon Sep 17 00:00:00 2001 +From: Rick Wertenbroek +Date: Thu, 7 Mar 2024 10:53:18 +0100 +Subject: [PATCH] phy: rockchip: Fix typo in function names + +Several functions had "rochchip" instead of "rockchip" in their name. +Replace "rochchip" by "rockchip". + +Signed-off-By: Rick Wertenbroek +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++-- + drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 12 ++++++------ + 2 files changed, 8 insertions(+), 8 deletions(-) + +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -248,7 +248,7 @@ static int rockchip_combphy_exit(struct + return 0; + } + +-static const struct phy_ops rochchip_combphy_ops = { ++static const struct phy_ops rockchip_combphy_ops = { + .init = rockchip_combphy_init, + .exit = rockchip_combphy_exit, + .owner = THIS_MODULE, +@@ -364,7 +364,7 @@ static int rockchip_combphy_probe(struct + return ret; + } + +- priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); ++ priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); +--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c ++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +@@ -182,7 +182,7 @@ static const struct rockchip_p3phy_ops r + .phy_init = rockchip_p3phy_rk3588_init, + }; + +-static int rochchip_p3phy_init(struct phy *phy) ++static int rockchip_p3phy_init(struct phy *phy) + { + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + int ret; +@@ -205,7 +205,7 @@ static int rochchip_p3phy_init(struct ph + return ret; + } + +-static int rochchip_p3phy_exit(struct phy *phy) ++static int rockchip_p3phy_exit(struct phy *phy) + { + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + +@@ -214,9 +214,9 @@ static int rochchip_p3phy_exit(struct ph + return 0; + } + +-static const struct phy_ops rochchip_p3phy_ops = { +- .init = rochchip_p3phy_init, +- .exit = rochchip_p3phy_exit, ++static const struct phy_ops rockchip_p3phy_ops = { ++ .init = rockchip_p3phy_init, ++ .exit = rockchip_p3phy_exit, + .set_mode = rockchip_p3phy_set_mode, + .owner = THIS_MODULE, + }; +@@ -275,7 +275,7 @@ static int rockchip_p3phy_probe(struct p + return priv->num_lanes; + } + +- priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); ++ priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); diff --git a/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch b/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch new file mode 100644 index 00000000000000..61c3e0e53c0dff --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch @@ -0,0 +1,106 @@ +From a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Mon Sep 17 00:00:00 2001 +From: Niklas Cassel +Date: Fri, 12 Apr 2024 14:58:16 +0200 +Subject: [PATCH] phy: rockchip-snps-pcie3: add support for + rockchip,rx-common-refclk-mode + +>From the RK3588 Technical Reference Manual, Part1, +section 6.19 PCIe3PHY_GRF Register Description: +"rxX_cmn_refclk_mode" +RX common reference clock mode for lane X. This mode should be enabled +only when the far-end and near-end devices are running with a common +reference clock. + +The hardware reset value for this field is 0x1 (enabled). +Note that this register field is only available on RK3588, not on RK3568. + +The link training either fails or is highly unstable (link state will jump +continuously between L0 and recovery) when this mode is enabled while +using an endpoint running in Separate Reference Clock with No SSC (SRNS) +mode or Separate Reference Clock with SSC (SRIS) mode. +(Which is usually the case when using a real SoC as endpoint, e.g. the +RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) + +Add support for the device tree property rockchip,rx-common-refclk-mode, +such that the PCIe PHY can be used in configurations where the Root +Complex and Endpoint are not using a common reference clock. + +Signed-off-by: Niklas Cassel +Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org +Signed-off-by: Vinod Koul +--- + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++ + 1 file changed, 37 insertions(+) + +--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c ++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +@@ -35,11 +35,17 @@ + #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 + #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 + #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 ++#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004 ++#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104 ++#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004 ++#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104 + #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) + + #define RK3588_BIFURCATION_LANE_0_1 BIT(0) + #define RK3588_BIFURCATION_LANE_2_3 BIT(1) + #define RK3588_LANE_AGGREGATION BIT(2) ++#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7)) ++#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16) + #define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16) + #define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16) + +@@ -60,6 +66,7 @@ struct rockchip_p3phy_priv { + int num_clks; + int num_lanes; + u32 lanes[4]; ++ u32 rx_cmn_refclk_mode[4]; + }; + + struct rockchip_p3phy_ops { +@@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(st + u8 mode = RK3588_LANE_AGGREGATION; /* default */ + int ret; + ++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1, ++ priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN : ++ RK3588_RX_CMN_REFCLK_MODE_DIS); ++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1, ++ priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN : ++ RK3588_RX_CMN_REFCLK_MODE_DIS); ++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1, ++ priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN : ++ RK3588_RX_CMN_REFCLK_MODE_DIS); ++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1, ++ priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN : ++ RK3588_RX_CMN_REFCLK_MODE_DIS); ++ + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); + +@@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct p + return priv->num_lanes; + } + ++ ret = of_property_read_variable_u32_array(dev->of_node, ++ "rockchip,rx-common-refclk-mode", ++ priv->rx_cmn_refclk_mode, 1, ++ ARRAY_SIZE(priv->rx_cmn_refclk_mode)); ++ /* ++ * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in ++ * order to be DT backwards compatible. (Since HW reset val is enabled.) ++ */ ++ if (ret == -EINVAL) { ++ for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++) ++ priv->rx_cmn_refclk_mode[i] = 1; ++ } else if (ret < 0) { ++ dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n", ++ ret); ++ return ret; ++ } ++ + priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); diff --git a/target/linux/rockchip/patches-6.6/034-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch b/target/linux/rockchip/patches-6.6/034-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch new file mode 100644 index 00000000000000..0583b70f89fb47 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/034-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch @@ -0,0 +1,91 @@ +From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 20 Oct 2023 16:11:41 +0200 +Subject: [PATCH] usb: dwc3: add optional PHY interface clocks + +On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and +requires two extra clocks to be enabled. Without these extra clocks +hot-plugging USB devices is broken. + +Signed-off-by: Sebastian Reichel +Acked-by: Thinh Nguyen +Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++ + drivers/usb/dwc3/core.h | 4 ++++ + 2 files changed, 32 insertions(+) + +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -839,8 +839,20 @@ static int dwc3_clk_enable(struct dwc3 * + if (ret) + goto disable_ref_clk; + ++ ret = clk_prepare_enable(dwc->utmi_clk); ++ if (ret) ++ goto disable_susp_clk; ++ ++ ret = clk_prepare_enable(dwc->pipe_clk); ++ if (ret) ++ goto disable_utmi_clk; ++ + return 0; + ++disable_utmi_clk: ++ clk_disable_unprepare(dwc->utmi_clk); ++disable_susp_clk: ++ clk_disable_unprepare(dwc->susp_clk); + disable_ref_clk: + clk_disable_unprepare(dwc->ref_clk); + disable_bus_clk: +@@ -850,6 +862,8 @@ disable_bus_clk: + + static void dwc3_clk_disable(struct dwc3 *dwc) + { ++ clk_disable_unprepare(dwc->pipe_clk); ++ clk_disable_unprepare(dwc->utmi_clk); + clk_disable_unprepare(dwc->susp_clk); + clk_disable_unprepare(dwc->ref_clk); + clk_disable_unprepare(dwc->bus_clk); +@@ -1878,6 +1892,20 @@ static int dwc3_get_clocks(struct dwc3 * + } + } + ++ /* specific to Rockchip RK3588 */ ++ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); ++ if (IS_ERR(dwc->utmi_clk)) { ++ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), ++ "could not get utmi clock\n"); ++ } ++ ++ /* specific to Rockchip RK3588 */ ++ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); ++ if (IS_ERR(dwc->pipe_clk)) { ++ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), ++ "could not get pipe clock\n"); ++ } ++ + return 0; + } + +--- a/drivers/usb/dwc3/core.h ++++ b/drivers/usb/dwc3/core.h +@@ -997,6 +997,8 @@ struct dwc3_scratchpad_array { + * @bus_clk: clock for accessing the registers + * @ref_clk: reference clock + * @susp_clk: clock used when the SS phy is in low power (S3) state ++ * @utmi_clk: clock used for USB2 PHY communication ++ * @pipe_clk: clock used for USB3 PHY communication + * @reset: reset control + * @regs: base address for our registers + * @regs_size: address space size +@@ -1167,6 +1169,8 @@ struct dwc3 { + struct clk *bus_clk; + struct clk *ref_clk; + struct clk *susp_clk; ++ struct clk *utmi_clk; ++ struct clk *pipe_clk; + + struct reset_control *reset; + diff --git a/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch new file mode 100644 index 00000000000000..fcbec5f63a455f --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch @@ -0,0 +1,35 @@ +From 3eaf2abd11aa7f3b2fb04d60c64b2c756fe030eb Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Mon, 9 Oct 2023 22:27:26 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add sfc node to rk3588s + +Add SFC (SPI Flash) to RK3588S SOC. + +Reviewed-by: Dhruva Gole +Signed-off-by: Muhammed Efe Cetin +Link: https://lore.kernel.org/r/d36a64edfaede92ce2e158b0d9dc4f5998e019e3.1696878787.git.efectn@6tel.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1425,6 +1425,17 @@ + }; + }; + ++ sfc: spi@fe2b0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xfe2b0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk3588s.patch new file mode 100644 index 00000000000000..25526ba23ccce9 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk3588s.patch @@ -0,0 +1,58 @@ +From bf012368bb0ab69167d49715789fac34dfcd457e Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sun, 8 Oct 2023 15:04:59 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s + +This is used on Orange Pi 5 Plus. + +Signed-off-by: Ondrej Jirman +Link: https://lore.kernel.org/r/20231008130515.1155664-2-megi@xff.cz +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 35 +++++++++++++++++++ + 1 file changed, 35 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +@@ -1350,6 +1350,41 @@ + + i2s2 { + /omit-if-no-ref/ ++ i2s2m0_lrck: i2s2m0-lrck { ++ rockchip,pins = ++ /* i2s2m0_lrck */ ++ <2 RK_PC0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_mclk: i2s2m0-mclk { ++ rockchip,pins = ++ /* i2s2m0_mclk */ ++ <2 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sclk: i2s2m0-sclk { ++ rockchip,pins = ++ /* i2s2m0_sclk */ ++ <2 RK_PB7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdi: i2s2m0-sdi { ++ rockchip,pins = ++ /* i2s2m0_sdi */ ++ <2 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdo: i2s2m0-sdo { ++ rockchip,pins = ++ /* i2s2m0_sdo */ ++ <4 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2m1_lrck */ diff --git a/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-rk3588.patch b/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-rk3588.patch new file mode 100644 index 00000000000000..4a9cb6ea395228 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-rk3588.patch @@ -0,0 +1,32 @@ +From 3d77a3e51b0faed820a8db985dce5af1cc4eae32 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sun, 8 Oct 2023 15:05:00 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s + +This is used on Orange Pi 5 Plus. + +Signed-off-by: Ondrej Jirman +Link: https://lore.kernel.org/r/20231008130515.1155664-3-megi@xff.cz +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +@@ -3343,6 +3343,15 @@ + + uart9 { + /omit-if-no-ref/ ++ uart9m0_xfer: uart9m0-xfer { ++ rockchip,pins = ++ /* uart9_rx_m0 */ ++ <2 RK_PC4 10 &pcfg_pull_up>, ++ /* uart9_tx_m0 */ ++ <2 RK_PC2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ diff --git a/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-Add-AV1-decoder-node-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-Add-AV1-decoder-node-to-rk3588s.patch new file mode 100644 index 00000000000000..6fce4f0f4c45d0 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-Add-AV1-decoder-node-to-rk3588s.patch @@ -0,0 +1,37 @@ +From dd6dc0c4c1265129c229e26917bf4de1d97ff91f Mon Sep 17 00:00:00 2001 +From: Benjamin Gaignard +Date: Fri, 6 Oct 2023 08:53:34 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add AV1 decoder node to rk3588s + +Add node for AV1 video decoder. + +Signed-off-by: Benjamin Gaignard +Reviewed-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20231006065334.8117-1-benjamin.gaignard@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -2314,6 +2314,19 @@ + #interrupt-cells = <2>; + }; + }; ++ ++ av1d: video-codec@fdc70000 { ++ compatible = "rockchip,rk3588-av1-vpu"; ++ reg = <0x0 0xfdc70000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "vdpu"; ++ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; ++ assigned-clock-rates = <400000000>, <400000000>; ++ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; ++ clock-names = "aclk", "hclk"; ++ power-domains = <&power RK3588_PD_AV1>; ++ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; ++ }; + }; + + #include "rk3588s-pinctrl.dtsi" diff --git a/target/linux/rockchip/patches-6.6/050-05-v6.8-arm64-dts-rockchip-Add-DFI-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-05-v6.8-arm64-dts-rockchip-Add-DFI-to-rk3588s.patch new file mode 100644 index 00000000000000..714dc4883b5b84 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-05-v6.8-arm64-dts-rockchip-Add-DFI-to-rk3588s.patch @@ -0,0 +1,50 @@ +From 5a6976b1040a2f99ab84eddbfa7cd072ac5d10fc Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 18 Oct 2023 08:17:14 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add DFI to rk3588s + +The DFI unit can be used to measure DRAM utilization using perf. Add the +node to the device tree. The DFI needs a rockchip,pmu phandle to the pmu +containing registers for SDRAM configuration details. This is added in +this patch as well. + +Reviewed-by: Sebastian Reichel +Signed-off-by: Sascha Hauer +Link: https://lore.kernel.org/r/20231018061714.3553817-27-s.hauer@pengutronix.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -443,6 +443,11 @@ + status = "disabled"; + }; + ++ pmu1grf: syscon@fd58a000 { ++ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd58a000 0x0 0x10000>; ++ }; ++ + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x0 0xfd58c000 0x0 0x1000>; +@@ -1330,6 +1335,17 @@ + }; + }; + ++ dfi: dfi@fe060000 { ++ reg = <0x00 0xfe060000 0x00 0x10000>; ++ compatible = "rockchip,rk3588-dfi"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "ch0", "ch1", "ch2", "ch3"; ++ rockchip,pmu = <&pmu1grf>; ++ }; ++ + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/050-06-v6.8-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch b/target/linux/rockchip/patches-6.6/050-06-v6.8-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch new file mode 100644 index 00000000000000..f4e835a9f5d686 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-06-v6.8-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch @@ -0,0 +1,48 @@ +From bbd3778da16b3d448832b843f80bcde1aff26290 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 20 Oct 2023 16:11:42 +0200 +Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 host controller + +RK3588 has three USB3 controllers. This adds the host-only controller, +which is using the naneng-combphy shared with PCIe and SATA. + +The other two are dual-role and using a different PHY that is not yet +supported upstream. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20231020150022.48725-4-sebastian.reichel@collabora.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -443,6 +443,27 @@ + status = "disabled"; + }; + ++ usb_host2_xhci: usb@fcd00000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfcd00000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, ++ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, ++ <&cru CLK_PIPEPHY2_PIPE_U3_G>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; ++ dr_mode = "host"; ++ phys = <&combphy2_psu PHY_TYPE_USB3>; ++ phy-names = "usb3-phy"; ++ phy_type = "utmi_wide"; ++ resets = <&cru SRST_A_USB3OTG2>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,dis_rxdet_inp3_quirk; ++ status = "disabled"; ++ }; ++ + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/050-07-v6.7-arm64-dts-rockchip-drop-interrupt-names-property-from.patch b/target/linux/rockchip/patches-6.6/050-07-v6.7-arm64-dts-rockchip-drop-interrupt-names-property-from.patch new file mode 100644 index 00000000000000..9076ca2d13de4e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-07-v6.7-arm64-dts-rockchip-drop-interrupt-names-property-from.patch @@ -0,0 +1,27 @@ +From 815f986f33eeb06652d59d8a4d405d4fdb4e59a8 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Fri, 1 Dec 2023 14:48:59 +0100 +Subject: [PATCH] arm64: dts: rockchip: drop interrupt-names property from + rk3588s dfi + +The dfi binding does not specify interrupt names, with the interrupts +just specifying channels 0-x. So drop the unspecified property. + +Fixes: 5a6976b1040a ("arm64: dts: rockchip: Add DFI to rk3588s") +Reported-by: Jagan Teki +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20231201134859.322491-1-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1363,7 +1363,6 @@ + , + , + ; +- interrupt-names = "ch0", "ch1", "ch2", "ch3"; + rockchip,pmu = <&pmu1grf>; + }; + diff --git a/target/linux/rockchip/patches-6.6/050-08-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-08-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch new file mode 100644 index 00000000000000..60c2b269b50074 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-08-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch @@ -0,0 +1,139 @@ +From 9918d10d16665527e59fdb87c5acac70cc1cfe8f Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:39 +0100 +Subject: [PATCH] arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi + +The serial ports on rk3588 are named uart0 - uart9. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. + +To prevent each board repeating their list of serial aliases, move them +to the soc dtsi, as all previous Rockchip soc do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-2-heiko@sntech.de +--- + .../boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts | 4 ---- + .../boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts | 4 ---- + arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 - + .../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 -- + .../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 1 - + .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++ + 13 files changed, 13 insertions(+), 19 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts +@@ -12,10 +12,6 @@ + compatible = "edgeble,neural-compute-module-6a-io", + "edgeble,neural-compute-module-6a", "rockchip,rk3588"; + +- aliases { +- serial2 = &uart2; +- }; +- + chosen { + stdout-path = "serial2:1500000n8"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts +@@ -12,10 +12,6 @@ + compatible = "edgeble,neural-compute-module-6b-io", + "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + +- aliases { +- serial2 = &uart2; +- }; +- + chosen { + stdout-path = "serial2:1500000n8"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -16,7 +16,6 @@ + + aliases { + mmc0 = &sdhci; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts +@@ -19,7 +19,6 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -12,7 +12,6 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +@@ -15,7 +15,6 @@ + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -12,7 +12,6 @@ + + aliases { + mmc0 = &sdhci; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -14,7 +14,6 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; +- serial2 = &uart2; + }; + + analog-sound { +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -18,6 +18,19 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial5 = &uart5; ++ serial6 = &uart6; ++ serial7 = &uart7; ++ serial8 = &uart8; ++ serial9 = &uart9; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/rockchip/patches-6.6/050-09-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-09-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch new file mode 100644 index 00000000000000..2daaec395351f2 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-09-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch @@ -0,0 +1,38 @@ +From 328e901b7b03d292c1520ffb38e9164feef4f1ea Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:40 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi + +The i2c controllers on rk3588 are named i2c0 - i2c8. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace i2c access is a thing afterall. + +To prevent each board repeating their list of i2c aliases, define them +in the soc dtsi, as all previous Rockchip soc do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-3-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -19,6 +19,15 @@ + #size-cells = <2>; + + aliases { ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c7 = &i2c7; ++ i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; diff --git a/target/linux/rockchip/patches-6.6/050-10-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-10-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch new file mode 100644 index 00000000000000..19e6c6a4f5cac2 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-10-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch @@ -0,0 +1,34 @@ +From a024abedbca99a20aeb96f5beec9ded13c85dcb3 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:41 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi + +The gpio controllers on rk3588 are named gpio0 - gpio4. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace gpio access is a thing afterall. + +To prevent each board repeating their list of gpio aliases, define them +in the soc dtsi, as previous Rockchip soc like the rk356x do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-4-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -19,6 +19,11 @@ + #size-cells = <2>; + + aliases { ++ gpio0 = &gpio0; ++ gpio1 = &gpio1; ++ gpio2 = &gpio2; ++ gpio3 = &gpio3; ++ gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; diff --git a/target/linux/rockchip/patches-6.6/050-11-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-11-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch new file mode 100644 index 00000000000000..6a66d996680c21 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-11-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch @@ -0,0 +1,34 @@ +From a86e88043de929da76f7f6cf0990ba92aed8391a Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:42 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi + +The spi controllers on rk3588 are named spi0 - spi4. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace spi access is a thing afterall. + +To prevent each board repeating their list of spi aliases, define them +in the soc dtsi, as previous Rockchip soc like the rk356x do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-5-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -43,6 +43,11 @@ + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ spi4 = &spi4; + }; + + cpus { diff --git a/target/linux/rockchip/patches-6.6/050-12-v6.8-arm64-dts-rockchip-Add-vop-on-rk3588.patch b/target/linux/rockchip/patches-6.6/050-12-v6.8-arm64-dts-rockchip-Add-vop-on-rk3588.patch new file mode 100644 index 00000000000000..3936df7a73a0db --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-12-v6.8-arm64-dts-rockchip-Add-vop-on-rk3588.patch @@ -0,0 +1,120 @@ +From d895dbef3f3a31ab50491bb48552e798cf555987 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Mon, 11 Dec 2023 20:00:04 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add vop on rk3588 + +Add vop dt node for rk3588. + +Signed-off-by: Andy Yan +Link: https://lore.kernel.org/r/20231211120004.1785616-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 83 +++++++++++++++++++++++ + 1 file changed, 83 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -394,6 +394,11 @@ + #clock-cells = <0>; + }; + ++ display_subsystem: display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <&vop_out>; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = , +@@ -506,6 +511,16 @@ + reg = <0x0 0xfd58c000 0x0 0x1000>; + }; + ++ vop_grf: syscon@fd5a4000 { ++ compatible = "rockchip,rk3588-vop-grf", "syscon"; ++ reg = <0x0 0xfd5a4000 0x0 0x2000>; ++ }; ++ ++ vo1_grf: syscon@fd5a8000 { ++ compatible = "rockchip,rk3588-vo-grf", "syscon"; ++ reg = <0x0 0xfd5a8000 0x0 0x100>; ++ }; ++ + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; +@@ -625,6 +640,74 @@ + status = "disabled"; + }; + ++ vop: vop@fdd90000 { ++ compatible = "rockchip,rk3588-vop"; ++ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; ++ reg-names = "vop", "gamma-lut"; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru PCLK_VOP_ROOT>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "pclk_vop"; ++ iommus = <&vop_mmu>; ++ power-domains = <&power RK3588_PD_VOP>; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vop-grf = <&vop_grf>; ++ rockchip,vo1-grf = <&vo1_grf>; ++ rockchip,pmu = <&pmu>; ++ status = "disabled"; ++ ++ vop_out: ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vp0: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ vp1: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ vp2: port@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ ++ vp3: port@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ }; ++ }; ++ }; ++ ++ vop_mmu: iommu@fdd97e00 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; ++ clock-names = "aclk", "iface"; ++ #iommu-cells = <0>; ++ power-domains = <&power RK3588_PD_VOP>; ++ status = "disabled"; ++ }; ++ + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.6/050-13-v6.9-arm64-dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch b/target/linux/rockchip/patches-6.6/050-13-v6.9-arm64-dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch new file mode 100644 index 00000000000000..d9bd3ab01965b7 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-13-v6.9-arm64-dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch @@ -0,0 +1,51 @@ +From 11d28971aaaf5de6f50790fb21f1113fee21d320 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Mon, 19 Feb 2024 22:46:25 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add HDMI0 PHY to rk3588 + +Add DT nodes for HDMI0 PHY and related syscon found on RK3588 SoC. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20240219204626.284399-1-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -586,6 +586,11 @@ + }; + }; + ++ hdptxphy0_grf: syscon@fd5e0000 { ++ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; ++ reg = <0x0 0xfd5e0000 0x0 0x100>; ++ }; ++ + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; +@@ -2358,6 +2363,22 @@ + #dma-cells = <1>; + }; + ++ hdptxphy_hdmi0: phy@fed60000 { ++ compatible = "rockchip,rk3588-hdptx-phy"; ++ reg = <0x0 0xfed60000 0x0 0x2000>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; ++ clock-names = "ref", "apb"; ++ #phy-cells = <0>; ++ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, ++ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, ++ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, ++ <&cru SRST_HDPTX0_LCPLL>; ++ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", ++ "lcpll"; ++ rockchip,grf = <&hdptxphy0_grf>; ++ status = "disabled"; ++ }; ++ + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.6/050-14-v6.9-arm64-dts-rockchip-add-clock-to-vo1-grf-syscon-on-rk3588.patch b/target/linux/rockchip/patches-6.6/050-14-v6.9-arm64-dts-rockchip-add-clock-to-vo1-grf-syscon-on-rk3588.patch new file mode 100644 index 00000000000000..6ffc2c751a74b1 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-14-v6.9-arm64-dts-rockchip-add-clock-to-vo1-grf-syscon-on-rk3588.patch @@ -0,0 +1,25 @@ +From 2047366b9eff8fada2a118588b0478de6e92d02c Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 27 Feb 2024 22:05:21 +0100 +Subject: [PATCH] arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588 + +The VO*-general-register-files need a clock, so add the correct one. + +Cc: Sebastian Reichel +Reviewed-by: Sebastian Reichel +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20240227210521.724754-1-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -519,6 +519,7 @@ + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; ++ clocks = <&cru PCLK_VO1GRF>; + }; + + php_grf: syscon@fd5b0000 { diff --git a/target/linux/rockchip/patches-6.6/050-15-v6.10-arm64-dts-rockchip-Add-rk3588-GPU-node.patch b/target/linux/rockchip/patches-6.6/050-15-v6.10-arm64-dts-rockchip-Add-rk3588-GPU-node.patch new file mode 100644 index 00000000000000..dafdd69d68e054 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-15-v6.10-arm64-dts-rockchip-Add-rk3588-GPU-node.patch @@ -0,0 +1,81 @@ +From 6fca4edb93d335f29f81e484936f38a5eed6a9b1 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Tue, 26 Mar 2024 17:52:06 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add rk3588 GPU node + +Add Mali GPU Node to the RK3588 SoC DT including GPU clock +operating points + +Signed-off-by: Boris Brezillon +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 56 +++++++++++++++++++++++ + 1 file changed, 56 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -501,6 +501,62 @@ + status = "disabled"; + }; + ++ gpu: gpu@fb000000 { ++ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; ++ reg = <0x0 0xfb000000 0x0 0x200000>; ++ #cooling-cells = <2>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; ++ assigned-clock-rates = <200000000>; ++ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, ++ <&cru CLK_GPU_STACKS>; ++ clock-names = "core", "coregroup", "stacks"; ++ dynamic-power-coefficient = <2982>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "job", "mmu", "gpu"; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3588_PD_GPU>; ++ status = "disabled"; ++ ++ gpu_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-700000000 { ++ opp-hz = /bits/ 64 <700000000>; ++ opp-microvolt = <700000 700000 850000>; ++ }; ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-900000000 { ++ opp-hz = /bits/ 64 <900000000>; ++ opp-microvolt = <800000 800000 850000>; ++ }; ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <850000 850000 850000>; ++ }; ++ }; ++ }; ++ + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/050-16-v6.10-arm64-dts-rockchip-Fix-ordering-of-nodes-on-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-16-v6.10-arm64-dts-rockchip-Fix-ordering-of-nodes-on-rk3588s.patch new file mode 100644 index 00000000000000..7b69e0a195be38 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-16-v6.10-arm64-dts-rockchip-Fix-ordering-of-nodes-on-rk3588s.patch @@ -0,0 +1,384 @@ +From cbb97fe18e299ece1c0074924c630de6a19b320f Mon Sep 17 00:00:00 2001 +From: Diederik de Haas +Date: Sat, 6 Apr 2024 19:28:04 +0200 +Subject: [PATCH] arm64: dts: rockchip: Fix ordering of nodes on rk3588s + +Fix the ordering of the main nodes by sorting them alphabetically and +then the ones with a memory address sequentially by that address. + +Signed-off-by: Diederik de Haas +Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 304 +++++++++++----------- + 1 file changed, 152 insertions(+), 152 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -347,6 +347,11 @@ + }; + }; + ++ display_subsystem: display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <&vop_out>; ++ }; ++ + firmware { + optee: optee { + compatible = "linaro,optee-tz"; +@@ -394,11 +399,6 @@ + #clock-cells = <0>; + }; + +- display_subsystem: display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vop_out>; +- }; +- + timer { + compatible = "arm,armv8-timer"; + interrupts = , +@@ -436,6 +436,62 @@ + }; + }; + ++ gpu: gpu@fb000000 { ++ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; ++ reg = <0x0 0xfb000000 0x0 0x200000>; ++ #cooling-cells = <2>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; ++ assigned-clock-rates = <200000000>; ++ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, ++ <&cru CLK_GPU_STACKS>; ++ clock-names = "core", "coregroup", "stacks"; ++ dynamic-power-coefficient = <2982>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "job", "mmu", "gpu"; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3588_PD_GPU>; ++ status = "disabled"; ++ ++ gpu_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-700000000 { ++ opp-hz = /bits/ 64 <700000000>; ++ opp-microvolt = <700000 700000 850000>; ++ }; ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-900000000 { ++ opp-hz = /bits/ 64 <900000000>; ++ opp-microvolt = <800000 800000 850000>; ++ }; ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <850000 850000 850000>; ++ }; ++ }; ++ }; ++ + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; +@@ -501,62 +557,6 @@ + status = "disabled"; + }; + +- gpu: gpu@fb000000 { +- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; +- reg = <0x0 0xfb000000 0x0 0x200000>; +- #cooling-cells = <2>; +- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, +- <&cru CLK_GPU_STACKS>; +- clock-names = "core", "coregroup", "stacks"; +- dynamic-power-coefficient = <2982>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- operating-points-v2 = <&gpu_opp_table>; +- power-domains = <&power RK3588_PD_GPU>; +- status = "disabled"; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <700000 700000 850000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <750000 750000 850000>; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <800000 800000 850000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <850000 850000 850000>; +- }; +- }; +- }; +- + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; +@@ -702,74 +702,6 @@ + status = "disabled"; + }; + +- vop: vop@fdd90000 { +- compatible = "rockchip,rk3588-vop"; +- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; +- reg-names = "vop", "gamma-lut"; +- interrupts = ; +- clocks = <&cru ACLK_VOP>, +- <&cru HCLK_VOP>, +- <&cru DCLK_VOP0>, +- <&cru DCLK_VOP1>, +- <&cru DCLK_VOP2>, +- <&cru DCLK_VOP3>, +- <&cru PCLK_VOP_ROOT>; +- clock-names = "aclk", +- "hclk", +- "dclk_vp0", +- "dclk_vp1", +- "dclk_vp2", +- "dclk_vp3", +- "pclk_vop"; +- iommus = <&vop_mmu>; +- power-domains = <&power RK3588_PD_VOP>; +- rockchip,grf = <&sys_grf>; +- rockchip,vop-grf = <&vop_grf>; +- rockchip,vo1-grf = <&vo1_grf>; +- rockchip,pmu = <&pmu>; +- status = "disabled"; +- +- vop_out: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vp0: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- vp1: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- vp2: port@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- vp3: port@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- }; +- +- vop_mmu: iommu@fdd97e00 { +- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; +- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- power-domains = <&power RK3588_PD_VOP>; +- status = "disabled"; +- }; +- + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; +@@ -1140,6 +1072,87 @@ + }; + }; + ++ av1d: video-codec@fdc70000 { ++ compatible = "rockchip,rk3588-av1-vpu"; ++ reg = <0x0 0xfdc70000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "vdpu"; ++ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; ++ assigned-clock-rates = <400000000>, <400000000>; ++ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; ++ clock-names = "aclk", "hclk"; ++ power-domains = <&power RK3588_PD_AV1>; ++ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; ++ }; ++ ++ vop: vop@fdd90000 { ++ compatible = "rockchip,rk3588-vop"; ++ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; ++ reg-names = "vop", "gamma-lut"; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru PCLK_VOP_ROOT>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "pclk_vop"; ++ iommus = <&vop_mmu>; ++ power-domains = <&power RK3588_PD_VOP>; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vop-grf = <&vop_grf>; ++ rockchip,vo1-grf = <&vo1_grf>; ++ rockchip,pmu = <&pmu>; ++ status = "disabled"; ++ ++ vop_out: ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vp0: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ vp1: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ vp2: port@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ ++ vp3: port@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ }; ++ }; ++ }; ++ ++ vop_mmu: iommu@fdd97e00 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; ++ clock-names = "aclk", "iface"; ++ #iommu-cells = <0>; ++ power-domains = <&power RK3588_PD_VOP>; ++ status = "disabled"; ++ }; ++ + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; +@@ -1431,6 +1444,16 @@ + reg = <0x0 0xfdf82200 0x0 0x20>; + }; + ++ dfi: dfi@fe060000 { ++ reg = <0x00 0xfe060000 0x00 0x10000>; ++ compatible = "rockchip,rk3588-dfi"; ++ interrupts = , ++ , ++ , ++ ; ++ rockchip,pmu = <&pmu1grf>; ++ }; ++ + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x30 0x3f>; +@@ -1533,16 +1556,6 @@ + }; + }; + +- dfi: dfi@fe060000 { +- reg = <0x00 0xfe060000 0x00 0x10000>; +- compatible = "rockchip,rk3588-dfi"; +- interrupts = , +- , +- , +- ; +- rockchip,pmu = <&pmu1grf>; +- }; +- + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; +@@ -2543,19 +2556,6 @@ + #interrupt-cells = <2>; + }; + }; +- +- av1d: video-codec@fdc70000 { +- compatible = "rockchip,rk3588-av1-vpu"; +- reg = <0x0 0xfdc70000 0x0 0x800>; +- interrupts = ; +- interrupt-names = "vdpu"; +- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; +- assigned-clock-rates = <400000000>, <400000000>; +- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; +- clock-names = "aclk", "hclk"; +- power-domains = <&power RK3588_PD_AV1>; +- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; +- }; + }; + + #include "rk3588s-pinctrl.dtsi" diff --git a/target/linux/rockchip/patches-6.6/050-17-v6.10-arm64-dts-rockchip-fix-usb2phy-nodename-for-rk3588.patch b/target/linux/rockchip/patches-6.6/050-17-v6.10-arm64-dts-rockchip-fix-usb2phy-nodename-for-rk3588.patch new file mode 100644 index 00000000000000..065cb4b41093fa --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-17-v6.10-arm64-dts-rockchip-fix-usb2phy-nodename-for-rk3588.patch @@ -0,0 +1,35 @@ +From 4e07a95f7402de092cd71b2cb96c69f85c98f251 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 9 Apr 2024 00:50:31 +0200 +Subject: [PATCH] arm64: dts: rockchip: fix usb2phy nodename for rk3588 + +usb2-phy should be named usb2phy according to the DT binding, +so let's fix it up accordingly. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -599,7 +599,7 @@ + #address-cells = <1>; + #size-cells = <1>; + +- u2phy2: usb2-phy@8000 { ++ u2phy2: usb2phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = ; +@@ -624,7 +624,7 @@ + #address-cells = <1>; + #size-cells = <1>; + +- u2phy3: usb2-phy@c000 { ++ u2phy3: usb2phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = ; diff --git a/target/linux/rockchip/patches-6.6/050-18-v6.10-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch b/target/linux/rockchip/patches-6.6/050-18-v6.10-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch new file mode 100644 index 00000000000000..81e8ed1011e606 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-18-v6.10-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch @@ -0,0 +1,53 @@ +From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 9 Apr 2024 00:50:32 +0200 +Subject: [PATCH] arm64: dts: rockchip: reorder usb2phy properties for rk3588 + +Reorder common DT properties alphabetically for usb2phy, according +to latest DT style rules. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -602,13 +602,13 @@ + u2phy2: usb2phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; +- interrupts = ; +- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; +- reset-names = "phy", "apb"; ++ #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; +- #clock-cells = <0>; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; ++ reset-names = "phy", "apb"; + status = "disabled"; + + u2phy2_host: host-port { +@@ -627,13 +627,13 @@ + u2phy3: usb2phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; +- interrupts = ; +- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; +- reset-names = "phy", "apb"; ++ #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; +- #clock-cells = <0>; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; ++ reset-names = "phy", "apb"; + status = "disabled"; + + u2phy3_host: host-port { diff --git a/target/linux/rockchip/patches-6.6/050-19-v6.10-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch b/target/linux/rockchip/patches-6.6/050-19-v6.10-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch new file mode 100644 index 00000000000000..985a799df132d7 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-19-v6.10-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch @@ -0,0 +1,175 @@ +From e18e5e8188f2671abf63abe7db5f21555705130f Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 9 Apr 2024 00:50:33 +0200 +Subject: [PATCH] arm64: dts: rockchip: add USBDP phys on rk3588 + +Add both USB3-DisplayPort PHYs to RK3588 SoC DT. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 52 +++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++ + 2 files changed, 115 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -17,6 +17,36 @@ + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + ++ usbdpphy1_grf: syscon@fd5cc000 { ++ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; ++ reg = <0x0 0xfd5cc000 0x0 0x4000>; ++ }; ++ ++ usb2phy1_grf: syscon@fd5d4000 { ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd5d4000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy1: usb2phy@4000 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x4000 0x10>; ++ #clock-cells = <0>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy1"; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; ++ reset-names = "phy", "apb"; ++ status = "disabled"; ++ ++ u2phy1_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; +@@ -310,6 +340,28 @@ + }; + }; + ++ usbdp_phy1: phy@fed90000 { ++ compatible = "rockchip,rk3588-usbdp-phy"; ++ reg = <0x0 0xfed90000 0x0 0x10000>; ++ #phy-cells = <1>; ++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, ++ <&cru CLK_USBDP_PHY1_IMMORTAL>, ++ <&cru PCLK_USBDPPHY1>, ++ <&u2phy1>; ++ clock-names = "refclk", "immortal", "pclk", "utmi"; ++ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, ++ <&cru SRST_USBDP_COMBO_PHY1_CMN>, ++ <&cru SRST_USBDP_COMBO_PHY1_LANE>, ++ <&cru SRST_USBDP_COMBO_PHY1_PCS>, ++ <&cru SRST_P_USBDPPHY1>; ++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ rockchip,u2phy-grf = <&usb2phy1_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy1_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ status = "disabled"; ++ }; ++ + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -572,12 +572,23 @@ + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + ++ vo0_grf: syscon@fd5a6000 { ++ compatible = "rockchip,rk3588-vo-grf", "syscon"; ++ reg = <0x0 0xfd5a6000 0x0 0x2000>; ++ clocks = <&cru PCLK_VO0GRF>; ++ }; ++ + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <&cru PCLK_VO1GRF>; + }; + ++ usb_grf: syscon@fd5ac000 { ++ compatible = "rockchip,rk3588-usb-grf", "syscon"; ++ reg = <0x0 0xfd5ac000 0x0 0x4000>; ++ }; ++ + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; +@@ -593,6 +604,36 @@ + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + ++ usbdpphy0_grf: syscon@fd5c8000 { ++ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; ++ reg = <0x0 0xfd5c8000 0x0 0x4000>; ++ }; ++ ++ usb2phy0_grf: syscon@fd5d0000 { ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd5d0000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy0: usb2phy@0 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x0 0x10>; ++ #clock-cells = <0>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy0"; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; ++ reset-names = "phy", "apb"; ++ status = "disabled"; ++ ++ u2phy0_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; +@@ -2449,6 +2490,28 @@ + status = "disabled"; + }; + ++ usbdp_phy0: phy@fed80000 { ++ compatible = "rockchip,rk3588-usbdp-phy"; ++ reg = <0x0 0xfed80000 0x0 0x10000>; ++ #phy-cells = <1>; ++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, ++ <&cru CLK_USBDP_PHY0_IMMORTAL>, ++ <&cru PCLK_USBDPPHY0>, ++ <&u2phy0>; ++ clock-names = "refclk", "immortal", "pclk", "utmi"; ++ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, ++ <&cru SRST_USBDP_COMBO_PHY0_CMN>, ++ <&cru SRST_USBDP_COMBO_PHY0_LANE>, ++ <&cru SRST_USBDP_COMBO_PHY0_PCS>, ++ <&cru SRST_P_USBDPPHY0>; ++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ rockchip,u2phy-grf = <&usb2phy0_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ status = "disabled"; ++ }; ++ + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.6/050-20-v6.10-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch b/target/linux/rockchip/patches-6.6/050-20-v6.10-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch new file mode 100644 index 00000000000000..7bfa205514ba7c --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-20-v6.10-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch @@ -0,0 +1,75 @@ +From 33f393a2a990e16f56931ca708295f31d2b44415 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 9 Apr 2024 00:50:34 +0200 +Subject: [PATCH] arm64: dts: rockchip: add USB3 DRD controllers on rk3588 + +Add both USB3 dual-role controllers to the RK3588 devicetree. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++ + 2 files changed, 42 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -7,6 +7,26 @@ + #include "rk3588-pinctrl.dtsi" + + / { ++ usb_host1_xhci: usb@fc400000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfc400000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, ++ <&cru ACLK_USB3OTG1>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk"; ++ dr_mode = "otg"; ++ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3588_PD_USB>; ++ resets = <&cru SRST_A_USB3OTG1>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ status = "disabled"; ++ }; ++ + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -492,6 +492,28 @@ + }; + }; + ++ usb_host0_xhci: usb@fc000000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfc000000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, ++ <&cru ACLK_USB3OTG0>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk"; ++ dr_mode = "otg"; ++ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3588_PD_USB>; ++ resets = <&cru SRST_A_USB3OTG0>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u1-entry-quirk; ++ snps,dis-u2-entry-quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ status = "disabled"; ++ }; ++ + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; diff --git a/target/linux/rockchip/patches-6.6/050-21-v6.10-arm64-dts-rockchip-add-rk3588-pcie-and-php-IOMMUs.patch b/target/linux/rockchip/patches-6.6/050-21-v6.10-arm64-dts-rockchip-add-rk3588-pcie-and-php-IOMMUs.patch new file mode 100644 index 00000000000000..fa98e5ec7007ad --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-21-v6.10-arm64-dts-rockchip-add-rk3588-pcie-and-php-IOMMUs.patch @@ -0,0 +1,74 @@ +From cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 Mon Sep 17 00:00:00 2001 +From: Niklas Cassel +Date: Thu, 2 May 2024 16:02:32 +0200 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs + +The mmu600_pcie is connected with the five PCIe controllers. +The mmu600_php is connected with the USB3 controller, the GMAC +controllers, and the SATA controllers. + +See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual). + +The IOMMUs are disabled by default, as further patches are needed to +program the SID/SSIDs in to the IOMMUs. + +iommu: Default domain type: Translated +iommu: DMA domain TLB invalidation policy: strict mode +arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf) +arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq +arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq +arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs + +Additionally, the IOMMU correctly triggers an IOMMU fault when +a PCIe device performs a write (since the device hasn't been +assigned a SID/SSID): +arm-smmu-v3 fc900000.iommu: event 0x02 received: +arm-smmu-v3 fc900000.iommu: 0x0000010000000002 +arm-smmu-v3 fc900000.iommu: 0x0000000000000000 +arm-smmu-v3 fc900000.iommu: 0x0000000000000000 +arm-smmu-v3 fc900000.iommu: 0x0000000000000000 + +While this doesn't provide much value as is, having the devices as +disabled in the device tree will allow developers to see that the rk3588 +actually has IOMMUs on the SoC. + +Signed-off-by: Niklas Cassel +Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 24 +++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -579,6 +579,30 @@ + status = "disabled"; + }; + ++ mmu600_pcie: iommu@fc900000 { ++ compatible = "arm,smmu-v3"; ++ reg = <0x0 0xfc900000 0x0 0x200000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; ++ #iommu-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ mmu600_php: iommu@fcb00000 { ++ compatible = "arm,smmu-v3"; ++ reg = <0x0 0xfcb00000 0x0 0x200000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; ++ #iommu-cells = <1>; ++ status = "disabled"; ++ }; ++ + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/050-22-v6.11-arm64-dts-rockchip-Prepare-RK3588-SoC-dtsi-files-for.patch b/target/linux/rockchip/patches-6.6/050-22-v6.11-arm64-dts-rockchip-Prepare-RK3588-SoC-dtsi-files-for.patch new file mode 100644 index 00000000000000..08460b5b41beeb --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-22-v6.11-arm64-dts-rockchip-Prepare-RK3588-SoC-dtsi-files-for.patch @@ -0,0 +1,14208 @@ +From def88eb4d8365a4aa064d28405d03550a9d0a3be Mon Sep 17 00:00:00 2001 +From: Dragan Simic +Date: Sun, 9 Jun 2024 10:58:19 +0200 +Subject: [PATCH] arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for + per-variant OPPs + +Rename the Rockchip RK3588 SoC dtsi files and, consequently, adjust their +contents appropriately, to prepare them for the ability to specify different +CPU and GPU OPPs for each of the supported RK3588 SoC variants. + +As already discussed, [1][2][3][4] some of the RK3588 SoC variants require +different OPPs, and it makes more sense to have the OPPs already defined when +a board dts(i) file includes one of the SoC variant dtsi files (rk3588.dtsi, +rk3588j.dtsi or rk3588s.dtsi), rather than requiring the board dts(i) file +to also include a separate rk3588*-opp.dtsi file. The choice of the SoC +variant is already made by the inclusion of the SoC dtsi file into the board +dts(i) file, and it doesn't make much sense to, effectively, allow the board +dts(i) file to include and use an incompatible set of OPPs for the already +selected RK3588 SoC variant. + +The new naming scheme for the RK3588 SoC dtsi files uses "-base" and "-extra" +suffixes to denote the DT data shared between all RK5588 SoC variants, and +the DT data shared between the unrestricted SoC variants, respectively. +For example, the DT data for the RK3588 includes both rk3588-base.dtsi and +rk3588-extra.dtsi, because it's an unrestricted SoC variant, while the DT +data for the RK3588S variant includes rk3588-base.dtsi only, because it's +a restricted SoC variant, feature- and interface-wise. This achieves a more +logical naming of the RK3588 SoC dtsi files, which reflects the way DT data +for the SoC variants is built by "stacking" the SoC variant features made +available through the "-base" and "-extra" SoC dtsi files. Additionally, +the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi and rk3588s.dtsi) are +no longer parents to any other SoC variant dtsi files, which should help with +making the new "stacking" approach cleaner and easier to follow. + +The RK3588 pinctrl dtsi files are also renamed in the same way, for the sake +of consistency. This also keeps the "-base" and "-extra" groups of the dtsi +files together when looked at in a directory listing, which is helpful. + +The per-SoC-variant OPPs should go directly into the SoC dtsi files, if no +more than one SoC variant uses those OPPs, or be put into a separate "-opp" +dtsi file that's shared between and included from two or more SoC variant +dtsi files. An example for the former is the non-shared OPP data that should +go directly into the RK3588J SoC variant dtsi file (i.e. rk3588j.dtsi), and +an example for the latter is the shared OPP data that should be put into +rk3588-opp.dtsi and be included from the RK3588 and RK3588S SoC variant dtsi +files (i.e. rk3588.dtsi and rk3588s.dtsi, respectively). Consequently, if +the OPPs for the RK3588 and RK3588S SoC variants are ever made different, +the shared rk3588-opp.dtsi file should be deleted and the new OPPs should +be put directly into rk3588.dtsi and rk3588s.dtsi. [4] + +No functional changes are introduced, which was validated by decompiling and +comparing all affected dtb files before and after these changes. + +As a side note, due to the nature of introduced changes, this commit is best +viewed using the --break-rewrites option for git-log(1). + +[1] https://lore.kernel.org/linux-rockchip/646a33e0-5c1b-471c-8183-2c0df40ea51a@cherry.de/ +[2] https://lore.kernel.org/linux-rockchip/CABjd4Yxi=+3gkNnH3BysUzzYsji-=-yROtzEc8jM_g0roKB0-w@mail.gmail.com/ +[3] https://lore.kernel.org/linux-rockchip/035a274be262528012173d463e25b55f@manjaro.org/ +[4] https://lore.kernel.org/linux-rockchip/673dcf47596e7bc8ba065034e339bb1bbf9cdcb0.1716948159.git.dsimic@manjaro.org/T/#u + +Signed-off-by: Dragan Simic +Link: https://lore.kernel.org/r/9ffedc0e2ca7f167d9d795b2a8f43cb9f56a653b.1717923308.git.dsimic@manjaro.org +Signed-off-by: Heiko Stuebner +--- + ...-pinctrl.dtsi => rk3588-base-pinctrl.dtsi} | 0 + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2670 +++++++++++++++++ + ...pinctrl.dtsi => rk3588-extra-pinctrl.dtsi} | 0 + .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 413 +++ + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 412 +-- + arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 2 +- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2669 +--------------- + 7 files changed, 3090 insertions(+), 3076 deletions(-) + rename arch/arm64/boot/dts/rockchip/{rk3588s-pinctrl.dtsi => rk3588-base-pinctrl.dtsi} (100%) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi + rename arch/arm64/boot/dts/rockchip/{rk3588-pinctrl.dtsi => rk3588-extra-pinctrl.dtsi} (100%) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -0,0 +1,2670 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ compatible = "rockchip,rk3588"; ++ ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ aliases { ++ gpio0 = &gpio0; ++ gpio1 = &gpio1; ++ gpio2 = &gpio2; ++ gpio3 = &gpio3; ++ gpio4 = &gpio4; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c7 = &i2c7; ++ i2c8 = &i2c8; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial5 = &uart5; ++ serial6 = &uart6; ++ serial7 = &uart7; ++ serial8 = &uart8; ++ serial9 = &uart9; ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ spi4 = &spi4; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&cpu_l0>; ++ }; ++ core1 { ++ cpu = <&cpu_l1>; ++ }; ++ core2 { ++ cpu = <&cpu_l2>; ++ }; ++ core3 { ++ cpu = <&cpu_l3>; ++ }; ++ }; ++ cluster1 { ++ core0 { ++ cpu = <&cpu_b0>; ++ }; ++ core1 { ++ cpu = <&cpu_b1>; ++ }; ++ }; ++ cluster2 { ++ core0 { ++ cpu = <&cpu_b2>; ++ }; ++ core1 { ++ cpu = <&cpu_b3>; ++ }; ++ }; ++ }; ++ ++ cpu_l0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x0>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <530>; ++ clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ assigned-clock-rates = <816000000>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <32768>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <32768>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l2_cache_l0>; ++ dynamic-power-coefficient = <228>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_l1: cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <530>; ++ clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <32768>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <32768>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l2_cache_l1>; ++ dynamic-power-coefficient = <228>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_l2: cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x200>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <530>; ++ clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <32768>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <32768>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l2_cache_l2>; ++ dynamic-power-coefficient = <228>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_l3: cpu@300 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x300>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <530>; ++ clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <32768>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <32768>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l2_cache_l3>; ++ dynamic-power-coefficient = <228>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_b0: cpu@400 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x400>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ assigned-clock-rates = <816000000>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <65536>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <65536>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache_b0>; ++ dynamic-power-coefficient = <416>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_b1: cpu@500 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x500>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <65536>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <65536>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache_b1>; ++ dynamic-power-coefficient = <416>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_b2: cpu@600 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x600>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ assigned-clock-rates = <816000000>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <65536>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <65536>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache_b2>; ++ dynamic-power-coefficient = <416>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_b3: cpu@700 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x700>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <65536>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <65536>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache_b3>; ++ dynamic-power-coefficient = <416>; ++ #cooling-cells = <2>; ++ }; ++ ++ idle-states { ++ entry-method = "psci"; ++ CPU_SLEEP: cpu-sleep { ++ compatible = "arm,idle-state"; ++ local-timer-stop; ++ arm,psci-suspend-param = <0x0010000>; ++ entry-latency-us = <100>; ++ exit-latency-us = <120>; ++ min-residency-us = <1000>; ++ }; ++ }; ++ ++ l2_cache_l0: l2-cache-l0 { ++ compatible = "cache"; ++ cache-size = <131072>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l1: l2-cache-l1 { ++ compatible = "cache"; ++ cache-size = <131072>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l2: l2-cache-l2 { ++ compatible = "cache"; ++ cache-size = <131072>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l3: l2-cache-l3 { ++ compatible = "cache"; ++ cache-size = <131072>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_b0: l2-cache-b0 { ++ compatible = "cache"; ++ cache-size = <524288>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_b1: l2-cache-b1 { ++ compatible = "cache"; ++ cache-size = <524288>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_b2: l2-cache-b2 { ++ compatible = "cache"; ++ cache-size = <524288>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_b3: l2-cache-b3 { ++ compatible = "cache"; ++ cache-size = <524288>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l3_cache: l3-cache { ++ compatible = "cache"; ++ cache-size = <3145728>; ++ cache-line-size = <64>; ++ cache-sets = <4096>; ++ cache-level = <3>; ++ cache-unified; ++ }; ++ }; ++ ++ display_subsystem: display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <&vop_out>; ++ }; ++ ++ firmware { ++ optee: optee { ++ compatible = "linaro,optee-tz"; ++ method = "smc"; ++ }; ++ ++ scmi: scmi { ++ compatible = "arm,scmi-smc"; ++ arm,smc-id = <0x82000010>; ++ shmem = <&scmi_shmem>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ scmi_clk: protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <1>; ++ }; ++ ++ scmi_reset: protocol@16 { ++ reg = <0x16>; ++ #reset-cells = <1>; ++ }; ++ }; ++ }; ++ ++ pmu-a55 { ++ compatible = "arm,cortex-a55-pmu"; ++ interrupts = ; ++ }; ++ ++ pmu-a76 { ++ compatible = "arm,cortex-a76-pmu"; ++ interrupts = ; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ spll: clock-0 { ++ compatible = "fixed-clock"; ++ clock-frequency = <702000000>; ++ clock-output-names = "spll"; ++ #clock-cells = <0>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; ++ }; ++ ++ xin24m: clock-1 { ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "xin24m"; ++ #clock-cells = <0>; ++ }; ++ ++ xin32k: clock-2 { ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "xin32k"; ++ #clock-cells = <0>; ++ }; ++ ++ pmu_sram: sram@10f000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0x0010f000 0x0 0x100>; ++ ranges = <0 0x0 0x0010f000 0x100>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ scmi_shmem: sram@0 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x0 0x100>; ++ }; ++ }; ++ ++ gpu: gpu@fb000000 { ++ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; ++ reg = <0x0 0xfb000000 0x0 0x200000>; ++ #cooling-cells = <2>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; ++ assigned-clock-rates = <200000000>; ++ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, ++ <&cru CLK_GPU_STACKS>; ++ clock-names = "core", "coregroup", "stacks"; ++ dynamic-power-coefficient = <2982>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "job", "mmu", "gpu"; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3588_PD_GPU>; ++ status = "disabled"; ++ ++ gpu_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-700000000 { ++ opp-hz = /bits/ 64 <700000000>; ++ opp-microvolt = <700000 700000 850000>; ++ }; ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-900000000 { ++ opp-hz = /bits/ 64 <900000000>; ++ opp-microvolt = <800000 800000 850000>; ++ }; ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <850000 850000 850000>; ++ }; ++ }; ++ }; ++ ++ usb_host0_xhci: usb@fc000000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfc000000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, ++ <&cru ACLK_USB3OTG0>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk"; ++ dr_mode = "otg"; ++ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3588_PD_USB>; ++ resets = <&cru SRST_A_USB3OTG0>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u1-entry-quirk; ++ snps,dis-u2-entry-quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ status = "disabled"; ++ }; ++ ++ usb_host0_ehci: usb@fc800000 { ++ compatible = "rockchip,rk3588-ehci", "generic-ehci"; ++ reg = <0x0 0xfc800000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; ++ phys = <&u2phy2_host>; ++ phy-names = "usb"; ++ power-domains = <&power RK3588_PD_USB>; ++ status = "disabled"; ++ }; ++ ++ usb_host0_ohci: usb@fc840000 { ++ compatible = "rockchip,rk3588-ohci", "generic-ohci"; ++ reg = <0x0 0xfc840000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; ++ phys = <&u2phy2_host>; ++ phy-names = "usb"; ++ power-domains = <&power RK3588_PD_USB>; ++ status = "disabled"; ++ }; ++ ++ usb_host1_ehci: usb@fc880000 { ++ compatible = "rockchip,rk3588-ehci", "generic-ehci"; ++ reg = <0x0 0xfc880000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; ++ phys = <&u2phy3_host>; ++ phy-names = "usb"; ++ power-domains = <&power RK3588_PD_USB>; ++ status = "disabled"; ++ }; ++ ++ usb_host1_ohci: usb@fc8c0000 { ++ compatible = "rockchip,rk3588-ohci", "generic-ohci"; ++ reg = <0x0 0xfc8c0000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; ++ phys = <&u2phy3_host>; ++ phy-names = "usb"; ++ power-domains = <&power RK3588_PD_USB>; ++ status = "disabled"; ++ }; ++ ++ usb_host2_xhci: usb@fcd00000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfcd00000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, ++ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, ++ <&cru CLK_PIPEPHY2_PIPE_U3_G>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; ++ dr_mode = "host"; ++ phys = <&combphy2_psu PHY_TYPE_USB3>; ++ phy-names = "usb3-phy"; ++ phy_type = "utmi_wide"; ++ resets = <&cru SRST_A_USB3OTG2>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,dis_rxdet_inp3_quirk; ++ status = "disabled"; ++ }; ++ ++ mmu600_pcie: iommu@fc900000 { ++ compatible = "arm,smmu-v3"; ++ reg = <0x0 0xfc900000 0x0 0x200000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; ++ #iommu-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ mmu600_php: iommu@fcb00000 { ++ compatible = "arm,smmu-v3"; ++ reg = <0x0 0xfcb00000 0x0 0x200000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; ++ #iommu-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ pmu1grf: syscon@fd58a000 { ++ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd58a000 0x0 0x10000>; ++ }; ++ ++ sys_grf: syscon@fd58c000 { ++ compatible = "rockchip,rk3588-sys-grf", "syscon"; ++ reg = <0x0 0xfd58c000 0x0 0x1000>; ++ }; ++ ++ vop_grf: syscon@fd5a4000 { ++ compatible = "rockchip,rk3588-vop-grf", "syscon"; ++ reg = <0x0 0xfd5a4000 0x0 0x2000>; ++ }; ++ ++ vo0_grf: syscon@fd5a6000 { ++ compatible = "rockchip,rk3588-vo-grf", "syscon"; ++ reg = <0x0 0xfd5a6000 0x0 0x2000>; ++ clocks = <&cru PCLK_VO0GRF>; ++ }; ++ ++ vo1_grf: syscon@fd5a8000 { ++ compatible = "rockchip,rk3588-vo-grf", "syscon"; ++ reg = <0x0 0xfd5a8000 0x0 0x100>; ++ clocks = <&cru PCLK_VO1GRF>; ++ }; ++ ++ usb_grf: syscon@fd5ac000 { ++ compatible = "rockchip,rk3588-usb-grf", "syscon"; ++ reg = <0x0 0xfd5ac000 0x0 0x4000>; ++ }; ++ ++ php_grf: syscon@fd5b0000 { ++ compatible = "rockchip,rk3588-php-grf", "syscon"; ++ reg = <0x0 0xfd5b0000 0x0 0x1000>; ++ }; ++ ++ pipe_phy0_grf: syscon@fd5bc000 { ++ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfd5bc000 0x0 0x100>; ++ }; ++ ++ pipe_phy2_grf: syscon@fd5c4000 { ++ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfd5c4000 0x0 0x100>; ++ }; ++ ++ usbdpphy0_grf: syscon@fd5c8000 { ++ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; ++ reg = <0x0 0xfd5c8000 0x0 0x4000>; ++ }; ++ ++ usb2phy0_grf: syscon@fd5d0000 { ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd5d0000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy0: usb2phy@0 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x0 0x10>; ++ #clock-cells = <0>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy0"; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; ++ reset-names = "phy", "apb"; ++ status = "disabled"; ++ ++ u2phy0_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ usb2phy2_grf: syscon@fd5d8000 { ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd5d8000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy2: usb2phy@8000 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x8000 0x10>; ++ #clock-cells = <0>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy2"; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; ++ reset-names = "phy", "apb"; ++ status = "disabled"; ++ ++ u2phy2_host: host-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ usb2phy3_grf: syscon@fd5dc000 { ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd5dc000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy3: usb2phy@c000 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0xc000 0x10>; ++ #clock-cells = <0>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy3"; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; ++ reset-names = "phy", "apb"; ++ status = "disabled"; ++ ++ u2phy3_host: host-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ hdptxphy0_grf: syscon@fd5e0000 { ++ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; ++ reg = <0x0 0xfd5e0000 0x0 0x100>; ++ }; ++ ++ ioc: syscon@fd5f0000 { ++ compatible = "rockchip,rk3588-ioc", "syscon"; ++ reg = <0x0 0xfd5f0000 0x0 0x10000>; ++ }; ++ ++ system_sram1: sram@fd600000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0xfd600000 0x0 0x100000>; ++ ranges = <0x0 0x0 0xfd600000 0x100000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ ++ cru: clock-controller@fd7c0000 { ++ compatible = "rockchip,rk3588-cru"; ++ reg = <0x0 0xfd7c0000 0x0 0x5c000>; ++ assigned-clocks = ++ <&cru PLL_PPLL>, <&cru PLL_AUPLL>, ++ <&cru PLL_NPLL>, <&cru PLL_GPLL>, ++ <&cru ACLK_CENTER_ROOT>, ++ <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, ++ <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, ++ <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, ++ <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, ++ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, ++ <&cru CLK_GPU>; ++ assigned-clock-rates = ++ <1100000000>, <786432000>, ++ <850000000>, <1188000000>, ++ <702000000>, ++ <400000000>, <500000000>, ++ <800000000>, <100000000>, ++ <400000000>, <100000000>, ++ <200000000>, <500000000>, ++ <375000000>, <150000000>, ++ <200000000>; ++ rockchip,grf = <&php_grf>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ i2c0: i2c@fd880000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfd880000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-0 = <&i2c0m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart0: serial@fd890000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfd890000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 6>, <&dmac0 7>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart0m1_xfer>; ++ pinctrl-names = "default"; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ pwm0: pwm@fd8b0000 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfd8b0000 0x0 0x10>; ++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm0m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@fd8b0010 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfd8b0010 0x0 0x10>; ++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm1m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@fd8b0020 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfd8b0020 0x0 0x10>; ++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm2m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@fd8b0030 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfd8b0030 0x0 0x10>; ++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm3m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pmu: power-management@fd8d8000 { ++ compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd8d8000 0x0 0x400>; ++ ++ power: power-controller { ++ compatible = "rockchip,rk3588-power-controller"; ++ #address-cells = <1>; ++ #power-domain-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ /* These power domains are grouped by VD_NPU */ ++ power-domain@RK3588_PD_NPU { ++ reg = ; ++ #power-domain-cells = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3588_PD_NPUTOP { ++ reg = ; ++ clocks = <&cru HCLK_NPU_ROOT>, ++ <&cru PCLK_NPU_ROOT>, ++ <&cru CLK_NPU_DSU0>, ++ <&cru HCLK_NPU_CM0_ROOT>; ++ pm_qos = <&qos_npu0_mwr>, ++ <&qos_npu0_mro>, ++ <&qos_mcu_npu>; ++ #power-domain-cells = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3588_PD_NPU1 { ++ reg = ; ++ clocks = <&cru HCLK_NPU_ROOT>, ++ <&cru PCLK_NPU_ROOT>, ++ <&cru CLK_NPU_DSU0>; ++ pm_qos = <&qos_npu1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_NPU2 { ++ reg = ; ++ clocks = <&cru HCLK_NPU_ROOT>, ++ <&cru PCLK_NPU_ROOT>, ++ <&cru CLK_NPU_DSU0>; ++ pm_qos = <&qos_npu2>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ /* These power domains are grouped by VD_GPU */ ++ power-domain@RK3588_PD_GPU { ++ reg = ; ++ clocks = <&cru CLK_GPU>, ++ <&cru CLK_GPU_COREGROUP>, ++ <&cru CLK_GPU_STACKS>; ++ pm_qos = <&qos_gpu_m0>, ++ <&qos_gpu_m1>, ++ <&qos_gpu_m2>, ++ <&qos_gpu_m3>; ++ #power-domain-cells = <0>; ++ }; ++ /* These power domains are grouped by VD_VCODEC */ ++ power-domain@RK3588_PD_VCODEC { ++ reg = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ power-domain@RK3588_PD_RKVDEC0 { ++ reg = ; ++ clocks = <&cru HCLK_RKVDEC0>, ++ <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_ROOT>, ++ <&cru ACLK_RKVDEC0>, ++ <&cru ACLK_RKVDEC_CCU>; ++ pm_qos = <&qos_rkvdec0>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_RKVDEC1 { ++ reg = ; ++ clocks = <&cru HCLK_RKVDEC1>, ++ <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_ROOT>, ++ <&cru ACLK_RKVDEC1>; ++ pm_qos = <&qos_rkvdec1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_VENC0 { ++ reg = ; ++ clocks = <&cru HCLK_RKVENC0>, ++ <&cru ACLK_RKVENC0>; ++ pm_qos = <&qos_rkvenc0_m0ro>, ++ <&qos_rkvenc0_m1ro>, ++ <&qos_rkvenc0_m2wo>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ power-domain@RK3588_PD_VENC1 { ++ reg = ; ++ clocks = <&cru HCLK_RKVENC1>, ++ <&cru HCLK_RKVENC0>, ++ <&cru ACLK_RKVENC0>, ++ <&cru ACLK_RKVENC1>; ++ pm_qos = <&qos_rkvenc1_m0ro>, ++ <&qos_rkvenc1_m1ro>, ++ <&qos_rkvenc1_m2wo>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ /* These power domains are grouped by VD_LOGIC */ ++ power-domain@RK3588_PD_VDPU { ++ reg = ; ++ clocks = <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_LOW_ROOT>, ++ <&cru ACLK_VDPU_ROOT>, ++ <&cru ACLK_JPEG_DECODER_ROOT>, ++ <&cru ACLK_IEP2P0>, ++ <&cru HCLK_IEP2P0>, ++ <&cru ACLK_JPEG_ENCODER0>, ++ <&cru HCLK_JPEG_ENCODER0>, ++ <&cru ACLK_JPEG_ENCODER1>, ++ <&cru HCLK_JPEG_ENCODER1>, ++ <&cru ACLK_JPEG_ENCODER2>, ++ <&cru HCLK_JPEG_ENCODER2>, ++ <&cru ACLK_JPEG_ENCODER3>, ++ <&cru HCLK_JPEG_ENCODER3>, ++ <&cru ACLK_JPEG_DECODER>, ++ <&cru HCLK_JPEG_DECODER>, ++ <&cru ACLK_RGA2>, ++ <&cru HCLK_RGA2>; ++ pm_qos = <&qos_iep>, ++ <&qos_jpeg_dec>, ++ <&qos_jpeg_enc0>, ++ <&qos_jpeg_enc1>, ++ <&qos_jpeg_enc2>, ++ <&qos_jpeg_enc3>, ++ <&qos_rga2_mro>, ++ <&qos_rga2_mwo>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ ++ power-domain@RK3588_PD_AV1 { ++ reg = ; ++ clocks = <&cru PCLK_AV1>, ++ <&cru ACLK_AV1>, ++ <&cru HCLK_VDPU_ROOT>; ++ pm_qos = <&qos_av1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_RKVDEC0 { ++ reg = ; ++ clocks = <&cru HCLK_RKVDEC0>, ++ <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_ROOT>, ++ <&cru ACLK_RKVDEC0>; ++ pm_qos = <&qos_rkvdec0>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_RKVDEC1 { ++ reg = ; ++ clocks = <&cru HCLK_RKVDEC1>, ++ <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_ROOT>; ++ pm_qos = <&qos_rkvdec1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_RGA30 { ++ reg = ; ++ clocks = <&cru ACLK_RGA3_0>, ++ <&cru HCLK_RGA3_0>; ++ pm_qos = <&qos_rga3_0>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ power-domain@RK3588_PD_VOP { ++ reg = ; ++ clocks = <&cru PCLK_VOP_ROOT>, ++ <&cru HCLK_VOP_ROOT>, ++ <&cru ACLK_VOP>; ++ pm_qos = <&qos_vop_m0>, ++ <&qos_vop_m1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ power-domain@RK3588_PD_VO0 { ++ reg = ; ++ clocks = <&cru PCLK_VO0_ROOT>, ++ <&cru PCLK_VO0_S_ROOT>, ++ <&cru HCLK_VO0_S_ROOT>, ++ <&cru ACLK_VO0_ROOT>, ++ <&cru HCLK_HDCP0>, ++ <&cru ACLK_HDCP0>, ++ <&cru HCLK_VOP_ROOT>; ++ pm_qos = <&qos_hdcp0>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ power-domain@RK3588_PD_VO1 { ++ reg = ; ++ clocks = <&cru PCLK_VO1_ROOT>, ++ <&cru PCLK_VO1_S_ROOT>, ++ <&cru HCLK_VO1_S_ROOT>, ++ <&cru HCLK_HDCP1>, ++ <&cru ACLK_HDCP1>, ++ <&cru ACLK_HDMIRX_ROOT>, ++ <&cru HCLK_VO1USB_TOP_ROOT>; ++ pm_qos = <&qos_hdcp1>, ++ <&qos_hdmirx>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_VI { ++ reg = ; ++ clocks = <&cru HCLK_VI_ROOT>, ++ <&cru PCLK_VI_ROOT>, ++ <&cru HCLK_ISP0>, ++ <&cru ACLK_ISP0>, ++ <&cru HCLK_VICAP>, ++ <&cru ACLK_VICAP>; ++ pm_qos = <&qos_isp0_mro>, ++ <&qos_isp0_mwo>, ++ <&qos_vicap_m0>, ++ <&qos_vicap_m1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ power-domain@RK3588_PD_ISP1 { ++ reg = ; ++ clocks = <&cru HCLK_ISP1>, ++ <&cru ACLK_ISP1>, ++ <&cru HCLK_VI_ROOT>, ++ <&cru PCLK_VI_ROOT>; ++ pm_qos = <&qos_isp1_mwo>, ++ <&qos_isp1_mro>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_FEC { ++ reg = ; ++ clocks = <&cru HCLK_FISHEYE0>, ++ <&cru ACLK_FISHEYE0>, ++ <&cru HCLK_FISHEYE1>, ++ <&cru ACLK_FISHEYE1>, ++ <&cru PCLK_VI_ROOT>; ++ pm_qos = <&qos_fisheye0>, ++ <&qos_fisheye1>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ power-domain@RK3588_PD_RGA31 { ++ reg = ; ++ clocks = <&cru HCLK_RGA3_1>, ++ <&cru ACLK_RGA3_1>; ++ pm_qos = <&qos_rga3_1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_USB { ++ reg = ; ++ clocks = <&cru PCLK_PHP_ROOT>, ++ <&cru ACLK_USB_ROOT>, ++ <&cru ACLK_USB>, ++ <&cru HCLK_USB_ROOT>, ++ <&cru HCLK_HOST0>, ++ <&cru HCLK_HOST_ARB0>, ++ <&cru HCLK_HOST1>, ++ <&cru HCLK_HOST_ARB1>; ++ pm_qos = <&qos_usb3_0>, ++ <&qos_usb3_1>, ++ <&qos_usb2host_0>, ++ <&qos_usb2host_1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_GMAC { ++ reg = ; ++ clocks = <&cru PCLK_PHP_ROOT>, ++ <&cru ACLK_PCIE_ROOT>, ++ <&cru ACLK_PHP_ROOT>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_PCIE { ++ reg = ; ++ clocks = <&cru PCLK_PHP_ROOT>, ++ <&cru ACLK_PCIE_ROOT>, ++ <&cru ACLK_PHP_ROOT>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_SDIO { ++ reg = ; ++ clocks = <&cru HCLK_SDIO>, ++ <&cru HCLK_NVM_ROOT>; ++ pm_qos = <&qos_sdio>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_AUDIO { ++ reg = ; ++ clocks = <&cru HCLK_AUDIO_ROOT>, ++ <&cru PCLK_AUDIO_ROOT>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_SDMMC { ++ reg = ; ++ pm_qos = <&qos_sdmmc>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ ++ av1d: video-codec@fdc70000 { ++ compatible = "rockchip,rk3588-av1-vpu"; ++ reg = <0x0 0xfdc70000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "vdpu"; ++ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; ++ assigned-clock-rates = <400000000>, <400000000>; ++ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; ++ clock-names = "aclk", "hclk"; ++ power-domains = <&power RK3588_PD_AV1>; ++ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; ++ }; ++ ++ vop: vop@fdd90000 { ++ compatible = "rockchip,rk3588-vop"; ++ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; ++ reg-names = "vop", "gamma-lut"; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru PCLK_VOP_ROOT>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "pclk_vop"; ++ iommus = <&vop_mmu>; ++ power-domains = <&power RK3588_PD_VOP>; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vop-grf = <&vop_grf>; ++ rockchip,vo1-grf = <&vo1_grf>; ++ rockchip,pmu = <&pmu>; ++ status = "disabled"; ++ ++ vop_out: ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vp0: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ vp1: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ vp2: port@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ ++ vp3: port@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ }; ++ }; ++ }; ++ ++ vop_mmu: iommu@fdd97e00 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; ++ clock-names = "aclk", "iface"; ++ #iommu-cells = <0>; ++ power-domains = <&power RK3588_PD_VOP>; ++ status = "disabled"; ++ }; ++ ++ i2s4_8ch: i2s@fddc0000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddc0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 0>; ++ dma-names = "tx"; ++ power-domains = <&power RK3588_PD_VO0>; ++ resets = <&cru SRST_M_I2S4_8CH_TX>; ++ reset-names = "tx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s5_8ch: i2s@fddf0000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddf0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 2>; ++ dma-names = "tx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S5_8CH_TX>; ++ reset-names = "tx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s9_8ch: i2s@fddfc000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddfc000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 23>; ++ dma-names = "rx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S9_8CH_RX>; ++ reset-names = "rx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ qos_gpu_m0: qos@fdf35000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf35000 0x0 0x20>; ++ }; ++ ++ qos_gpu_m1: qos@fdf35200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf35200 0x0 0x20>; ++ }; ++ ++ qos_gpu_m2: qos@fdf35400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf35400 0x0 0x20>; ++ }; ++ ++ qos_gpu_m3: qos@fdf35600 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf35600 0x0 0x20>; ++ }; ++ ++ qos_rga3_1: qos@fdf36000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf36000 0x0 0x20>; ++ }; ++ ++ qos_sdio: qos@fdf39000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf39000 0x0 0x20>; ++ }; ++ ++ qos_sdmmc: qos@fdf3d800 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3d800 0x0 0x20>; ++ }; ++ ++ qos_usb3_1: qos@fdf3e000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3e000 0x0 0x20>; ++ }; ++ ++ qos_usb3_0: qos@fdf3e200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3e200 0x0 0x20>; ++ }; ++ ++ qos_usb2host_0: qos@fdf3e400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3e400 0x0 0x20>; ++ }; ++ ++ qos_usb2host_1: qos@fdf3e600 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3e600 0x0 0x20>; ++ }; ++ ++ qos_fisheye0: qos@fdf40000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40000 0x0 0x20>; ++ }; ++ ++ qos_fisheye1: qos@fdf40200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40200 0x0 0x20>; ++ }; ++ ++ qos_isp0_mro: qos@fdf40400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40400 0x0 0x20>; ++ }; ++ ++ qos_isp0_mwo: qos@fdf40500 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40500 0x0 0x20>; ++ }; ++ ++ qos_vicap_m0: qos@fdf40600 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40600 0x0 0x20>; ++ }; ++ ++ qos_vicap_m1: qos@fdf40800 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40800 0x0 0x20>; ++ }; ++ ++ qos_isp1_mwo: qos@fdf41000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf41000 0x0 0x20>; ++ }; ++ ++ qos_isp1_mro: qos@fdf41100 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf41100 0x0 0x20>; ++ }; ++ ++ qos_rkvenc0_m0ro: qos@fdf60000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf60000 0x0 0x20>; ++ }; ++ ++ qos_rkvenc0_m1ro: qos@fdf60200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf60200 0x0 0x20>; ++ }; ++ ++ qos_rkvenc0_m2wo: qos@fdf60400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf60400 0x0 0x20>; ++ }; ++ ++ qos_rkvenc1_m0ro: qos@fdf61000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf61000 0x0 0x20>; ++ }; ++ ++ qos_rkvenc1_m1ro: qos@fdf61200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf61200 0x0 0x20>; ++ }; ++ ++ qos_rkvenc1_m2wo: qos@fdf61400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf61400 0x0 0x20>; ++ }; ++ ++ qos_rkvdec0: qos@fdf62000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf62000 0x0 0x20>; ++ }; ++ ++ qos_rkvdec1: qos@fdf63000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf63000 0x0 0x20>; ++ }; ++ ++ qos_av1: qos@fdf64000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf64000 0x0 0x20>; ++ }; ++ ++ qos_iep: qos@fdf66000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66000 0x0 0x20>; ++ }; ++ ++ qos_jpeg_dec: qos@fdf66200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66200 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc0: qos@fdf66400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66400 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc1: qos@fdf66600 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66600 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc2: qos@fdf66800 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66800 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc3: qos@fdf66a00 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66a00 0x0 0x20>; ++ }; ++ ++ qos_rga2_mro: qos@fdf66c00 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66c00 0x0 0x20>; ++ }; ++ ++ qos_rga2_mwo: qos@fdf66e00 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66e00 0x0 0x20>; ++ }; ++ ++ qos_rga3_0: qos@fdf67000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf67000 0x0 0x20>; ++ }; ++ ++ qos_vdpu: qos@fdf67200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf67200 0x0 0x20>; ++ }; ++ ++ qos_npu1: qos@fdf70000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf70000 0x0 0x20>; ++ }; ++ ++ qos_npu2: qos@fdf71000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf71000 0x0 0x20>; ++ }; ++ ++ qos_npu0_mwr: qos@fdf72000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf72000 0x0 0x20>; ++ }; ++ ++ qos_npu0_mro: qos@fdf72200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf72200 0x0 0x20>; ++ }; ++ ++ qos_mcu_npu: qos@fdf72400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf72400 0x0 0x20>; ++ }; ++ ++ qos_hdcp0: qos@fdf80000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf80000 0x0 0x20>; ++ }; ++ ++ qos_hdcp1: qos@fdf81000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf81000 0x0 0x20>; ++ }; ++ ++ qos_hdmirx: qos@fdf81200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf81200 0x0 0x20>; ++ }; ++ ++ qos_vop_m0: qos@fdf82000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf82000 0x0 0x20>; ++ }; ++ ++ qos_vop_m1: qos@fdf82200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf82200 0x0 0x20>; ++ }; ++ ++ dfi: dfi@fe060000 { ++ reg = <0x00 0xfe060000 0x00 0x10000>; ++ compatible = "rockchip,rk3588-dfi"; ++ interrupts = , ++ , ++ , ++ ; ++ rockchip,pmu = <&pmu1grf>; ++ }; ++ ++ pcie2x1l1: pcie@fe180000 { ++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; ++ bus-range = <0x30 0x3f>; ++ clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, ++ <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, ++ <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", ++ "aux", "pipe"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, ++ <0 0 0 2 &pcie2x1l1_intc 1>, ++ <0 0 0 3 &pcie2x1l1_intc 2>, ++ <0 0 0 4 &pcie2x1l1_intc 3>; ++ linux,pci-domain = <3>; ++ max-link-speed = <2>; ++ msi-map = <0x3000 &its0 0x3000 0x1000>; ++ num-lanes = <1>; ++ phys = <&combphy2_psu PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3588_PD_PCIE>; ++ ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, ++ <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, ++ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; ++ reg = <0xa 0x40c00000 0x0 0x00400000>, ++ <0x0 0xfe180000 0x0 0x00010000>, ++ <0x0 0xf3000000 0x0 0x00100000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; ++ reset-names = "pwr", "pipe"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ status = "disabled"; ++ ++ pcie2x1l1_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ pcie2x1l2: pcie@fe190000 { ++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; ++ bus-range = <0x40 0x4f>; ++ clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, ++ <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, ++ <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", ++ "aux", "pipe"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, ++ <0 0 0 2 &pcie2x1l2_intc 1>, ++ <0 0 0 3 &pcie2x1l2_intc 2>, ++ <0 0 0 4 &pcie2x1l2_intc 3>; ++ linux,pci-domain = <4>; ++ max-link-speed = <2>; ++ msi-map = <0x4000 &its0 0x4000 0x1000>; ++ num-lanes = <1>; ++ phys = <&combphy0_ps PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3588_PD_PCIE>; ++ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, ++ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, ++ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; ++ reg = <0xa 0x41000000 0x0 0x00400000>, ++ <0x0 0xfe190000 0x0 0x00010000>, ++ <0x0 0xf4000000 0x0 0x00100000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; ++ reset-names = "pwr", "pipe"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ status = "disabled"; ++ ++ pcie2x1l2_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ gmac1: ethernet@fe1c0000 { ++ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0xfe1c0000 0x0 0x10000>; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, ++ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, ++ <&cru CLK_GMAC1_PTP_REF>; ++ clock-names = "stmmaceth", "clk_mac_ref", ++ "pclk_mac", "aclk_mac", ++ "ptp_ref"; ++ power-domains = <&power RK3588_PD_GMAC>; ++ resets = <&cru SRST_A_GMAC1>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,php-grf = <&php_grf>; ++ snps,axi-config = <&gmac1_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio1: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac1_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,wr_osr_lmt = <4>; ++ snps,rd_osr_lmt = <8>; ++ }; ++ ++ gmac1_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <2>; ++ queue0 {}; ++ queue1 {}; ++ }; ++ ++ gmac1_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <2>; ++ queue0 {}; ++ queue1 {}; ++ }; ++ }; ++ ++ sata0: sata@fe210000 { ++ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfe210000 0 0x1000>; ++ interrupts = ; ++ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, ++ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, ++ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; ++ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; ++ ports-implemented = <0x1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata-port@0 { ++ reg = <0>; ++ hba-port-cap = ; ++ phys = <&combphy0_ps PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ snps,rx-ts-max = <32>; ++ snps,tx-ts-max = <32>; ++ }; ++ }; ++ ++ sata2: sata@fe230000 { ++ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfe230000 0 0x1000>; ++ interrupts = ; ++ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, ++ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, ++ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; ++ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; ++ ports-implemented = <0x1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata-port@0 { ++ reg = <0>; ++ hba-port-cap = ; ++ phys = <&combphy2_psu PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ snps,rx-ts-max = <32>; ++ snps,tx-ts-max = <32>; ++ }; ++ }; ++ ++ sfc: spi@fe2b0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xfe2b0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ sdmmc: mmc@fe2c0000 { ++ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xfe2c0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, ++ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; ++ power-domains = <&power RK3588_PD_SDMMC>; ++ status = "disabled"; ++ }; ++ ++ sdio: mmc@fe2d0000 { ++ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x00 0xfe2d0000 0x00 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, ++ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdiom1_pins>; ++ power-domains = <&power RK3588_PD_SDIO>; ++ status = "disabled"; ++ }; ++ ++ sdhci: mmc@fe2e0000 { ++ compatible = "rockchip,rk3588-dwcmshc"; ++ reg = <0x0 0xfe2e0000 0x0 0x10000>; ++ interrupts = ; ++ assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; ++ assigned-clock-rates = <200000000>, <24000000>, <200000000>; ++ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, ++ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, ++ <&cru TMCLK_EMMC>; ++ clock-names = "core", "bus", "axi", "block", "timer"; ++ max-frequency = <200000000>; ++ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, ++ <&emmc_cmd>, <&emmc_data_strobe>; ++ pinctrl-names = "default"; ++ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, ++ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, ++ <&cru SRST_T_EMMC>; ++ reset-names = "core", "bus", "axi", "block", "timer"; ++ status = "disabled"; ++ }; ++ ++ i2s0_8ch: i2s@fe470000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfe470000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; ++ dmas = <&dmac0 0>, <&dmac0 1>; ++ dma-names = "tx", "rx"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,trcm-sync-tx-only; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdi1 ++ &i2s0_sdi2 ++ &i2s0_sdi3 ++ &i2s0_sdo0 ++ &i2s0_sdo1 ++ &i2s0_sdo2 ++ &i2s0_sdo3>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s1_8ch: i2s@fe480000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfe480000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac0 2>, <&dmac0 3>; ++ dma-names = "tx", "rx"; ++ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,trcm-sync-tx-only; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_lrck ++ &i2s1m0_sclk ++ &i2s1m0_sdi0 ++ &i2s1m0_sdi1 ++ &i2s1m0_sdi2 ++ &i2s1m0_sdi3 ++ &i2s1m0_sdo0 ++ &i2s1m0_sdo1 ++ &i2s1m0_sdo2 ++ &i2s1m0_sdo3>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s2_2ch: i2s@fe490000 { ++ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; ++ reg = <0x0 0xfe490000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; ++ clock-names = "i2s_clk", "i2s_hclk"; ++ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac1 0>, <&dmac1 1>; ++ dma-names = "tx", "rx"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s2m1_lrck ++ &i2s2m1_sclk ++ &i2s2m1_sdi ++ &i2s2m1_sdo>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s3_2ch: i2s@fe4a0000 { ++ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; ++ reg = <0x0 0xfe4a0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; ++ clock-names = "i2s_clk", "i2s_hclk"; ++ assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac1 2>, <&dmac1 3>; ++ dma-names = "tx", "rx"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s3_lrck ++ &i2s3_sclk ++ &i2s3_sdi ++ &i2s3_sdo>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ gic: interrupt-controller@fe600000 { ++ compatible = "arm,gic-v3"; ++ reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ ++ <0x0 0xfe680000 0 0x100000>; /* GICR */ ++ interrupts = ; ++ interrupt-controller; ++ mbi-alias = <0x0 0xfe610000>; ++ mbi-ranges = <424 56>; ++ msi-controller; ++ ranges; ++ #address-cells = <2>; ++ #interrupt-cells = <4>; ++ #size-cells = <2>; ++ ++ its0: msi-controller@fe640000 { ++ compatible = "arm,gic-v3-its"; ++ reg = <0x0 0xfe640000 0x0 0x20000>; ++ msi-controller; ++ #msi-cells = <1>; ++ }; ++ ++ its1: msi-controller@fe660000 { ++ compatible = "arm,gic-v3-its"; ++ reg = <0x0 0xfe660000 0x0 0x20000>; ++ msi-controller; ++ #msi-cells = <1>; ++ }; ++ ++ ppi-partitions { ++ ppi_partition0: interrupt-partition-0 { ++ affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; ++ }; ++ ++ ppi_partition1: interrupt-partition-1 { ++ affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; ++ }; ++ }; ++ }; ++ ++ dmac0: dma-controller@fea10000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0xfea10000 0x0 0x4000>; ++ interrupts = , ++ ; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC0>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ ++ dmac1: dma-controller@fea30000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0xfea30000 0x0 0x4000>; ++ interrupts = , ++ ; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC1>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ ++ i2c1: i2c@fea90000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfea90000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c1m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@feaa0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfeaa0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c2m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@feab0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfeab0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c3m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@feac0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfeac0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c4m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@fead0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfead0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c5m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ timer0: timer@feae0000 { ++ compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; ++ reg = <0x0 0xfeae0000 0x0 0x20>; ++ interrupts = ; ++ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; ++ clock-names = "pclk", "timer"; ++ }; ++ ++ wdt: watchdog@feaf0000 { ++ compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; ++ reg = <0x0 0xfeaf0000 0x0 0x100>; ++ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; ++ clock-names = "tclk", "pclk"; ++ interrupts = ; ++ }; ++ ++ spi0: spi@feb00000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfeb00000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 14>, <&dmac0 15>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@feb10000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfeb10000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 16>, <&dmac0 17>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@feb20000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfeb20000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac1 15>, <&dmac1 16>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi3: spi@feb30000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfeb30000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac1 17>, <&dmac1 18>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@feb40000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb40000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 8>, <&dmac0 9>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart1m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@feb50000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb50000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 10>, <&dmac0 11>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart2m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@feb60000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb60000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 12>, <&dmac0 13>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart3m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@feb70000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb70000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 9>, <&dmac1 10>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart4m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@feb80000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb80000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 11>, <&dmac1 12>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart5m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart6: serial@feb90000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb90000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 13>, <&dmac1 14>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart6m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart7: serial@feba0000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeba0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 7>, <&dmac2 8>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart7m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart8: serial@febb0000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfebb0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 9>, <&dmac2 10>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart8m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart9: serial@febc0000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfebc0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 11>, <&dmac2 12>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart9m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm4: pwm@febd0000 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebd0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm4m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@febd0010 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebd0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm5m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@febd0020 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebd0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm6m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm7: pwm@febd0030 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebd0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm7m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm8: pwm@febe0000 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebe0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm8m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm9: pwm@febe0010 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebe0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm9m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm10: pwm@febe0020 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebe0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm10m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm11: pwm@febe0030 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebe0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm11m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm12: pwm@febf0000 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebf0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm12m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm13: pwm@febf0010 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebf0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm13m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm14: pwm@febf0020 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebf0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm14m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm15: pwm@febf0030 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebf0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm15m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ tsadc: tsadc@fec00000 { ++ compatible = "rockchip,rk3588-tsadc"; ++ reg = <0x0 0xfec00000 0x0 0x400>; ++ interrupts = ; ++ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; ++ clock-names = "tsadc", "apb_pclk"; ++ assigned-clocks = <&cru CLK_TSADC>; ++ assigned-clock-rates = <2000000>; ++ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; ++ reset-names = "tsadc-apb", "tsadc"; ++ rockchip,hw-tshut-temp = <120000>; ++ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ ++ pinctrl-0 = <&tsadc_gpio_func>; ++ pinctrl-1 = <&tsadc_shut>; ++ pinctrl-names = "gpio", "otpout"; ++ #thermal-sensor-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ saradc: adc@fec10000 { ++ compatible = "rockchip,rk3588-saradc"; ++ reg = <0x0 0xfec10000 0x0 0x10000>; ++ interrupts = ; ++ #io-channel-cells = <1>; ++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; ++ clock-names = "saradc", "apb_pclk"; ++ resets = <&cru SRST_P_SARADC>; ++ reset-names = "saradc-apb"; ++ status = "disabled"; ++ }; ++ ++ i2c6: i2c@fec80000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfec80000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c6m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c7: i2c@fec90000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfec90000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c7m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c8: i2c@feca0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfeca0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c8m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi4: spi@fecb0000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfecb0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac2 13>, <&dmac2 14>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ otp: efuse@fecc0000 { ++ compatible = "rockchip,rk3588-otp"; ++ reg = <0x0 0xfecc0000 0x0 0x400>; ++ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, ++ <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; ++ clock-names = "otp", "apb_pclk", "phy", "arb"; ++ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, ++ <&cru SRST_OTPC_ARB>; ++ reset-names = "otp", "apb", "arb"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpu_code: cpu-code@2 { ++ reg = <0x02 0x2>; ++ }; ++ ++ otp_id: id@7 { ++ reg = <0x07 0x10>; ++ }; ++ ++ cpub0_leakage: cpu-leakage@17 { ++ reg = <0x17 0x1>; ++ }; ++ ++ cpub1_leakage: cpu-leakage@18 { ++ reg = <0x18 0x1>; ++ }; ++ ++ cpul_leakage: cpu-leakage@19 { ++ reg = <0x19 0x1>; ++ }; ++ ++ log_leakage: log-leakage@1a { ++ reg = <0x1a 0x1>; ++ }; ++ ++ gpu_leakage: gpu-leakage@1b { ++ reg = <0x1b 0x1>; ++ }; ++ ++ otp_cpu_version: cpu-version@1c { ++ reg = <0x1c 0x1>; ++ bits = <3 3>; ++ }; ++ ++ npu_leakage: npu-leakage@28 { ++ reg = <0x28 0x1>; ++ }; ++ ++ codec_leakage: codec-leakage@29 { ++ reg = <0x29 0x1>; ++ }; ++ }; ++ ++ dmac2: dma-controller@fed10000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0xfed10000 0x0 0x4000>; ++ interrupts = , ++ ; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC2>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ ++ hdptxphy_hdmi0: phy@fed60000 { ++ compatible = "rockchip,rk3588-hdptx-phy"; ++ reg = <0x0 0xfed60000 0x0 0x2000>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; ++ clock-names = "ref", "apb"; ++ #phy-cells = <0>; ++ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, ++ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, ++ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, ++ <&cru SRST_HDPTX0_LCPLL>; ++ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", ++ "lcpll"; ++ rockchip,grf = <&hdptxphy0_grf>; ++ status = "disabled"; ++ }; ++ ++ usbdp_phy0: phy@fed80000 { ++ compatible = "rockchip,rk3588-usbdp-phy"; ++ reg = <0x0 0xfed80000 0x0 0x10000>; ++ #phy-cells = <1>; ++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, ++ <&cru CLK_USBDP_PHY0_IMMORTAL>, ++ <&cru PCLK_USBDPPHY0>, ++ <&u2phy0>; ++ clock-names = "refclk", "immortal", "pclk", "utmi"; ++ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, ++ <&cru SRST_USBDP_COMBO_PHY0_CMN>, ++ <&cru SRST_USBDP_COMBO_PHY0_LANE>, ++ <&cru SRST_USBDP_COMBO_PHY0_PCS>, ++ <&cru SRST_P_USBDPPHY0>; ++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ rockchip,u2phy-grf = <&usb2phy0_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ status = "disabled"; ++ }; ++ ++ combphy0_ps: phy@fee00000 { ++ compatible = "rockchip,rk3588-naneng-combphy"; ++ reg = <0x0 0xfee00000 0x0 0x100>; ++ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, ++ <&cru PCLK_PHP_ROOT>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; ++ assigned-clock-rates = <100000000>; ++ #phy-cells = <1>; ++ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; ++ reset-names = "phy", "apb"; ++ rockchip,pipe-grf = <&php_grf>; ++ rockchip,pipe-phy-grf = <&pipe_phy0_grf>; ++ status = "disabled"; ++ }; ++ ++ combphy2_psu: phy@fee20000 { ++ compatible = "rockchip,rk3588-naneng-combphy"; ++ reg = <0x0 0xfee20000 0x0 0x100>; ++ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, ++ <&cru PCLK_PHP_ROOT>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; ++ assigned-clock-rates = <100000000>; ++ #phy-cells = <1>; ++ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; ++ reset-names = "phy", "apb"; ++ rockchip,pipe-grf = <&php_grf>; ++ rockchip,pipe-phy-grf = <&pipe_phy2_grf>; ++ status = "disabled"; ++ }; ++ ++ system_sram2: sram@ff001000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0xff001000 0x0 0xef000>; ++ ranges = <0x0 0x0 0xff001000 0xef000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ ++ pinctrl: pinctrl { ++ compatible = "rockchip,rk3588-pinctrl"; ++ ranges; ++ rockchip,grf = <&ioc>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ gpio0: gpio@fd8a0000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfd8a0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 0 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio1: gpio@fec20000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfec20000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 32 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio2: gpio@fec30000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfec30000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 64 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio3: gpio@fec40000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfec40000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 96 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio4: gpio@fec50000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfec50000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 128 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ }; ++}; ++ ++#include "rk3588-base-pinctrl.dtsi" +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -0,0 +1,413 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include "rk3588-base.dtsi" ++#include "rk3588-extra-pinctrl.dtsi" ++ ++/ { ++ usb_host1_xhci: usb@fc400000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfc400000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, ++ <&cru ACLK_USB3OTG1>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk"; ++ dr_mode = "otg"; ++ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3588_PD_USB>; ++ resets = <&cru SRST_A_USB3OTG1>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ status = "disabled"; ++ }; ++ ++ pcie30_phy_grf: syscon@fd5b8000 { ++ compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; ++ reg = <0x0 0xfd5b8000 0x0 0x10000>; ++ }; ++ ++ pipe_phy1_grf: syscon@fd5c0000 { ++ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfd5c0000 0x0 0x100>; ++ }; ++ ++ usbdpphy1_grf: syscon@fd5cc000 { ++ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; ++ reg = <0x0 0xfd5cc000 0x0 0x4000>; ++ }; ++ ++ usb2phy1_grf: syscon@fd5d4000 { ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd5d4000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy1: usb2phy@4000 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x4000 0x10>; ++ #clock-cells = <0>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy1"; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; ++ reset-names = "phy", "apb"; ++ status = "disabled"; ++ ++ u2phy1_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ i2s8_8ch: i2s@fddc8000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddc8000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 22>; ++ dma-names = "tx"; ++ power-domains = <&power RK3588_PD_VO0>; ++ resets = <&cru SRST_M_I2S8_8CH_TX>; ++ reset-names = "tx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s6_8ch: i2s@fddf4000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddf4000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 4>; ++ dma-names = "tx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S6_8CH_TX>; ++ reset-names = "tx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s7_8ch: i2s@fddf8000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddf8000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 21>; ++ dma-names = "rx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S7_8CH_RX>; ++ reset-names = "rx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s10_8ch: i2s@fde00000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfde00000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 24>; ++ dma-names = "rx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S10_8CH_RX>; ++ reset-names = "rx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie3x4: pcie@fe150000 { ++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x00 0x0f>; ++ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, ++ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, ++ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", ++ "aux", "pipe"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, ++ <0 0 0 2 &pcie3x4_intc 1>, ++ <0 0 0 3 &pcie3x4_intc 2>, ++ <0 0 0 4 &pcie3x4_intc 3>; ++ linux,pci-domain = <0>; ++ max-link-speed = <3>; ++ msi-map = <0x0000 &its1 0x0000 0x1000>; ++ num-lanes = <4>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3588_PD_PCIE>; ++ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, ++ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, ++ <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; ++ reg = <0xa 0x40000000 0x0 0x00400000>, ++ <0x0 0xfe150000 0x0 0x00010000>, ++ <0x0 0xf0000000 0x0 0x00100000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; ++ reset-names = "pwr", "pipe"; ++ status = "disabled"; ++ ++ pcie3x4_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ pcie3x2: pcie@fe160000 { ++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x10 0x1f>; ++ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, ++ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, ++ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", ++ "aux", "pipe"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, ++ <0 0 0 2 &pcie3x2_intc 1>, ++ <0 0 0 3 &pcie3x2_intc 2>, ++ <0 0 0 4 &pcie3x2_intc 3>; ++ linux,pci-domain = <1>; ++ max-link-speed = <3>; ++ msi-map = <0x1000 &its1 0x1000 0x1000>; ++ num-lanes = <2>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3588_PD_PCIE>; ++ ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, ++ <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, ++ <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; ++ reg = <0xa 0x40400000 0x0 0x00400000>, ++ <0x0 0xfe160000 0x0 0x00010000>, ++ <0x0 0xf1000000 0x0 0x00100000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; ++ reset-names = "pwr", "pipe"; ++ status = "disabled"; ++ ++ pcie3x2_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ pcie2x1l0: pcie@fe170000 { ++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; ++ bus-range = <0x20 0x2f>; ++ clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, ++ <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, ++ <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", ++ "aux", "pipe"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, ++ <0 0 0 2 &pcie2x1l0_intc 1>, ++ <0 0 0 3 &pcie2x1l0_intc 2>, ++ <0 0 0 4 &pcie2x1l0_intc 3>; ++ linux,pci-domain = <2>; ++ max-link-speed = <2>; ++ msi-map = <0x2000 &its0 0x2000 0x1000>; ++ num-lanes = <1>; ++ phys = <&combphy1_ps PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3588_PD_PCIE>; ++ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, ++ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, ++ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; ++ reg = <0xa 0x40800000 0x0 0x00400000>, ++ <0x0 0xfe170000 0x0 0x00010000>, ++ <0x0 0xf2000000 0x0 0x00100000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; ++ reset-names = "pwr", "pipe"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ status = "disabled"; ++ ++ pcie2x1l0_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ gmac0: ethernet@fe1b0000 { ++ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0xfe1b0000 0x0 0x10000>; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, ++ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, ++ <&cru CLK_GMAC0_PTP_REF>; ++ clock-names = "stmmaceth", "clk_mac_ref", ++ "pclk_mac", "aclk_mac", ++ "ptp_ref"; ++ power-domains = <&power RK3588_PD_GMAC>; ++ resets = <&cru SRST_A_GMAC0>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,php-grf = <&php_grf>; ++ snps,axi-config = <&gmac0_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio0: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac0_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,wr_osr_lmt = <4>; ++ snps,rd_osr_lmt = <8>; ++ }; ++ ++ gmac0_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <2>; ++ queue0 {}; ++ queue1 {}; ++ }; ++ ++ gmac0_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <2>; ++ queue0 {}; ++ queue1 {}; ++ }; ++ }; ++ ++ sata1: sata@fe220000 { ++ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfe220000 0 0x1000>; ++ interrupts = ; ++ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, ++ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, ++ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; ++ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; ++ ports-implemented = <0x1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata-port@0 { ++ reg = <0>; ++ hba-port-cap = ; ++ phys = <&combphy1_ps PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ snps,rx-ts-max = <32>; ++ snps,tx-ts-max = <32>; ++ }; ++ }; ++ ++ usbdp_phy1: phy@fed90000 { ++ compatible = "rockchip,rk3588-usbdp-phy"; ++ reg = <0x0 0xfed90000 0x0 0x10000>; ++ #phy-cells = <1>; ++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, ++ <&cru CLK_USBDP_PHY1_IMMORTAL>, ++ <&cru PCLK_USBDPPHY1>, ++ <&u2phy1>; ++ clock-names = "refclk", "immortal", "pclk", "utmi"; ++ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, ++ <&cru SRST_USBDP_COMBO_PHY1_CMN>, ++ <&cru SRST_USBDP_COMBO_PHY1_LANE>, ++ <&cru SRST_USBDP_COMBO_PHY1_PCS>, ++ <&cru SRST_P_USBDPPHY1>; ++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ rockchip,u2phy-grf = <&usb2phy1_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy1_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ status = "disabled"; ++ }; ++ ++ combphy1_ps: phy@fee10000 { ++ compatible = "rockchip,rk3588-naneng-combphy"; ++ reg = <0x0 0xfee10000 0x0 0x100>; ++ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, ++ <&cru PCLK_PHP_ROOT>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; ++ assigned-clock-rates = <100000000>; ++ #phy-cells = <1>; ++ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; ++ reset-names = "phy", "apb"; ++ rockchip,pipe-grf = <&php_grf>; ++ rockchip,pipe-phy-grf = <&pipe_phy1_grf>; ++ status = "disabled"; ++ }; ++ ++ pcie30phy: phy@fee80000 { ++ compatible = "rockchip,rk3588-pcie3-phy"; ++ reg = <0x0 0xfee80000 0x0 0x20000>; ++ #phy-cells = <0>; ++ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; ++ clock-names = "pclk"; ++ resets = <&cru SRST_PCIE30_PHY>; ++ reset-names = "phy"; ++ rockchip,pipe-grf = <&php_grf>; ++ rockchip,phy-grf = <&pcie30_phy_grf>; ++ status = "disabled"; ++ }; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -1,413 +1,7 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* +- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd. ++ * + */ + +-#include "rk3588s.dtsi" +-#include "rk3588-pinctrl.dtsi" +- +-/ { +- usb_host1_xhci: usb@fc400000 { +- compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; +- reg = <0x0 0xfc400000 0x0 0x400000>; +- interrupts = ; +- clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, +- <&cru ACLK_USB3OTG1>; +- clock-names = "ref_clk", "suspend_clk", "bus_clk"; +- dr_mode = "otg"; +- phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; +- phy-names = "usb2-phy", "usb3-phy"; +- phy_type = "utmi_wide"; +- power-domains = <&power RK3588_PD_USB>; +- resets = <&cru SRST_A_USB3OTG1>; +- snps,dis_enblslpm_quirk; +- snps,dis-u2-freeclk-exists-quirk; +- snps,dis-del-phy-power-chg-quirk; +- snps,dis-tx-ipgap-linecheck-quirk; +- status = "disabled"; +- }; +- +- pcie30_phy_grf: syscon@fd5b8000 { +- compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; +- reg = <0x0 0xfd5b8000 0x0 0x10000>; +- }; +- +- pipe_phy1_grf: syscon@fd5c0000 { +- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; +- reg = <0x0 0xfd5c0000 0x0 0x100>; +- }; +- +- usbdpphy1_grf: syscon@fd5cc000 { +- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; +- reg = <0x0 0xfd5cc000 0x0 0x4000>; +- }; +- +- usb2phy1_grf: syscon@fd5d4000 { +- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xfd5d4000 0x0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u2phy1: usb2phy@4000 { +- compatible = "rockchip,rk3588-usb2phy"; +- reg = <0x4000 0x10>; +- #clock-cells = <0>; +- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; +- clock-names = "phyclk"; +- clock-output-names = "usb480m_phy1"; +- interrupts = ; +- resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; +- reset-names = "phy", "apb"; +- status = "disabled"; +- +- u2phy1_otg: otg-port { +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- i2s8_8ch: i2s@fddc8000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfddc8000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac2 22>; +- dma-names = "tx"; +- power-domains = <&power RK3588_PD_VO0>; +- resets = <&cru SRST_M_I2S8_8CH_TX>; +- reset-names = "tx-m"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s6_8ch: i2s@fddf4000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfddf4000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac2 4>; +- dma-names = "tx"; +- power-domains = <&power RK3588_PD_VO1>; +- resets = <&cru SRST_M_I2S6_8CH_TX>; +- reset-names = "tx-m"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s7_8ch: i2s@fddf8000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfddf8000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac2 21>; +- dma-names = "rx"; +- power-domains = <&power RK3588_PD_VO1>; +- resets = <&cru SRST_M_I2S7_8CH_RX>; +- reset-names = "rx-m"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s10_8ch: i2s@fde00000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfde00000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac2 24>; +- dma-names = "rx"; +- power-domains = <&power RK3588_PD_VO1>; +- resets = <&cru SRST_M_I2S10_8CH_RX>; +- reset-names = "rx-m"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- pcie3x4: pcie@fe150000 { +- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x00 0x0f>; +- clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, +- <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, +- <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; +- clock-names = "aclk_mst", "aclk_slv", +- "aclk_dbi", "pclk", +- "aux", "pipe"; +- device_type = "pci"; +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, +- <0 0 0 2 &pcie3x4_intc 1>, +- <0 0 0 3 &pcie3x4_intc 2>, +- <0 0 0 4 &pcie3x4_intc 3>; +- linux,pci-domain = <0>; +- max-link-speed = <3>; +- msi-map = <0x0000 &its1 0x0000 0x1000>; +- num-lanes = <4>; +- phys = <&pcie30phy>; +- phy-names = "pcie-phy"; +- power-domains = <&power RK3588_PD_PCIE>; +- ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, +- <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, +- <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; +- reg = <0xa 0x40000000 0x0 0x00400000>, +- <0x0 0xfe150000 0x0 0x00010000>, +- <0x0 0xf0000000 0x0 0x00100000>; +- reg-names = "dbi", "apb", "config"; +- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; +- reset-names = "pwr", "pipe"; +- status = "disabled"; +- +- pcie3x4_intc: legacy-interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pcie3x2: pcie@fe160000 { +- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; +- #address-cells = <3>; +- #size-cells = <2>; +- bus-range = <0x10 0x1f>; +- clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, +- <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, +- <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; +- clock-names = "aclk_mst", "aclk_slv", +- "aclk_dbi", "pclk", +- "aux", "pipe"; +- device_type = "pci"; +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, +- <0 0 0 2 &pcie3x2_intc 1>, +- <0 0 0 3 &pcie3x2_intc 2>, +- <0 0 0 4 &pcie3x2_intc 3>; +- linux,pci-domain = <1>; +- max-link-speed = <3>; +- msi-map = <0x1000 &its1 0x1000 0x1000>; +- num-lanes = <2>; +- phys = <&pcie30phy>; +- phy-names = "pcie-phy"; +- power-domains = <&power RK3588_PD_PCIE>; +- ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, +- <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, +- <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; +- reg = <0xa 0x40400000 0x0 0x00400000>, +- <0x0 0xfe160000 0x0 0x00010000>, +- <0x0 0xf1000000 0x0 0x00100000>; +- reg-names = "dbi", "apb", "config"; +- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; +- reset-names = "pwr", "pipe"; +- status = "disabled"; +- +- pcie3x2_intc: legacy-interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pcie2x1l0: pcie@fe170000 { +- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; +- bus-range = <0x20 0x2f>; +- clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, +- <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, +- <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; +- clock-names = "aclk_mst", "aclk_slv", +- "aclk_dbi", "pclk", +- "aux", "pipe"; +- device_type = "pci"; +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, +- <0 0 0 2 &pcie2x1l0_intc 1>, +- <0 0 0 3 &pcie2x1l0_intc 2>, +- <0 0 0 4 &pcie2x1l0_intc 3>; +- linux,pci-domain = <2>; +- max-link-speed = <2>; +- msi-map = <0x2000 &its0 0x2000 0x1000>; +- num-lanes = <1>; +- phys = <&combphy1_ps PHY_TYPE_PCIE>; +- phy-names = "pcie-phy"; +- power-domains = <&power RK3588_PD_PCIE>; +- ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, +- <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, +- <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; +- reg = <0xa 0x40800000 0x0 0x00400000>, +- <0x0 0xfe170000 0x0 0x00010000>, +- <0x0 0xf2000000 0x0 0x00100000>; +- reg-names = "dbi", "apb", "config"; +- resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; +- reset-names = "pwr", "pipe"; +- #address-cells = <3>; +- #size-cells = <2>; +- status = "disabled"; +- +- pcie2x1l0_intc: legacy-interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- gmac0: ethernet@fe1b0000 { +- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; +- reg = <0x0 0xfe1b0000 0x0 0x10000>; +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_wake_irq"; +- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, +- <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, +- <&cru CLK_GMAC0_PTP_REF>; +- clock-names = "stmmaceth", "clk_mac_ref", +- "pclk_mac", "aclk_mac", +- "ptp_ref"; +- power-domains = <&power RK3588_PD_GMAC>; +- resets = <&cru SRST_A_GMAC0>; +- reset-names = "stmmaceth"; +- rockchip,grf = <&sys_grf>; +- rockchip,php-grf = <&php_grf>; +- snps,axi-config = <&gmac0_stmmac_axi_setup>; +- snps,mixed-burst; +- snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; +- snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; +- snps,tso; +- status = "disabled"; +- +- mdio0: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- }; +- +- gmac0_stmmac_axi_setup: stmmac-axi-config { +- snps,blen = <0 0 0 0 16 8 4>; +- snps,wr_osr_lmt = <4>; +- snps,rd_osr_lmt = <8>; +- }; +- +- gmac0_mtl_rx_setup: rx-queues-config { +- snps,rx-queues-to-use = <2>; +- queue0 {}; +- queue1 {}; +- }; +- +- gmac0_mtl_tx_setup: tx-queues-config { +- snps,tx-queues-to-use = <2>; +- queue0 {}; +- queue1 {}; +- }; +- }; +- +- sata1: sata@fe220000 { +- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; +- reg = <0 0xfe220000 0 0x1000>; +- interrupts = ; +- clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, +- <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, +- <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; +- clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; +- ports-implemented = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata-port@0 { +- reg = <0>; +- hba-port-cap = ; +- phys = <&combphy1_ps PHY_TYPE_SATA>; +- phy-names = "sata-phy"; +- snps,rx-ts-max = <32>; +- snps,tx-ts-max = <32>; +- }; +- }; +- +- usbdp_phy1: phy@fed90000 { +- compatible = "rockchip,rk3588-usbdp-phy"; +- reg = <0x0 0xfed90000 0x0 0x10000>; +- #phy-cells = <1>; +- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, +- <&cru CLK_USBDP_PHY1_IMMORTAL>, +- <&cru PCLK_USBDPPHY1>, +- <&u2phy1>; +- clock-names = "refclk", "immortal", "pclk", "utmi"; +- resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, +- <&cru SRST_USBDP_COMBO_PHY1_CMN>, +- <&cru SRST_USBDP_COMBO_PHY1_LANE>, +- <&cru SRST_USBDP_COMBO_PHY1_PCS>, +- <&cru SRST_P_USBDPPHY1>; +- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; +- rockchip,u2phy-grf = <&usb2phy1_grf>; +- rockchip,usb-grf = <&usb_grf>; +- rockchip,usbdpphy-grf = <&usbdpphy1_grf>; +- rockchip,vo-grf = <&vo0_grf>; +- status = "disabled"; +- }; +- +- combphy1_ps: phy@fee10000 { +- compatible = "rockchip,rk3588-naneng-combphy"; +- reg = <0x0 0xfee10000 0x0 0x100>; +- clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, +- <&cru PCLK_PHP_ROOT>; +- clock-names = "ref", "apb", "pipe"; +- assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; +- assigned-clock-rates = <100000000>; +- #phy-cells = <1>; +- resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; +- reset-names = "phy", "apb"; +- rockchip,pipe-grf = <&php_grf>; +- rockchip,pipe-phy-grf = <&pipe_phy1_grf>; +- status = "disabled"; +- }; +- +- pcie30phy: phy@fee80000 { +- compatible = "rockchip,rk3588-pcie3-phy"; +- reg = <0x0 0xfee80000 0x0 0x20000>; +- #phy-cells = <0>; +- clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; +- clock-names = "pclk"; +- resets = <&cru SRST_PCIE30_PHY>; +- reset-names = "phy"; +- rockchip,pipe-grf = <&php_grf>; +- rockchip,phy-grf = <&pcie30_phy_grf>; +- status = "disabled"; +- }; +-}; ++#include "rk3588-extra.dtsi" +--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +@@ -4,4 +4,4 @@ + * + */ + +-#include "rk3588.dtsi" ++#include "rk3588-extra.dtsi" +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1,2670 +1,7 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* +- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd. ++ * + */ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "rockchip,rk3588"; +- +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- aliases { +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- gpio2 = &gpio2; +- gpio3 = &gpio3; +- gpio4 = &gpio4; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- i2c7 = &i2c7; +- i2c8 = &i2c8; +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- serial5 = &uart5; +- serial6 = &uart6; +- serial7 = &uart7; +- serial8 = &uart8; +- serial9 = &uart9; +- spi0 = &spi0; +- spi1 = &spi1; +- spi2 = &spi2; +- spi3 = &spi3; +- spi4 = &spi4; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&cpu_l0>; +- }; +- core1 { +- cpu = <&cpu_l1>; +- }; +- core2 { +- cpu = <&cpu_l2>; +- }; +- core3 { +- cpu = <&cpu_l3>; +- }; +- }; +- cluster1 { +- core0 { +- cpu = <&cpu_b0>; +- }; +- core1 { +- cpu = <&cpu_b1>; +- }; +- }; +- cluster2 { +- core0 { +- cpu = <&cpu_b2>; +- }; +- core1 { +- cpu = <&cpu_b3>; +- }; +- }; +- }; +- +- cpu_l0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x0>; +- enable-method = "psci"; +- capacity-dmips-mhz = <530>; +- clocks = <&scmi_clk SCMI_CLK_CPUL>; +- assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; +- assigned-clock-rates = <816000000>; +- cpu-idle-states = <&CPU_SLEEP>; +- i-cache-size = <32768>; +- i-cache-line-size = <64>; +- i-cache-sets = <128>; +- d-cache-size = <32768>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&l2_cache_l0>; +- dynamic-power-coefficient = <228>; +- #cooling-cells = <2>; +- }; +- +- cpu_l1: cpu@100 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x100>; +- enable-method = "psci"; +- capacity-dmips-mhz = <530>; +- clocks = <&scmi_clk SCMI_CLK_CPUL>; +- cpu-idle-states = <&CPU_SLEEP>; +- i-cache-size = <32768>; +- i-cache-line-size = <64>; +- i-cache-sets = <128>; +- d-cache-size = <32768>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&l2_cache_l1>; +- dynamic-power-coefficient = <228>; +- #cooling-cells = <2>; +- }; +- +- cpu_l2: cpu@200 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x200>; +- enable-method = "psci"; +- capacity-dmips-mhz = <530>; +- clocks = <&scmi_clk SCMI_CLK_CPUL>; +- cpu-idle-states = <&CPU_SLEEP>; +- i-cache-size = <32768>; +- i-cache-line-size = <64>; +- i-cache-sets = <128>; +- d-cache-size = <32768>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&l2_cache_l2>; +- dynamic-power-coefficient = <228>; +- #cooling-cells = <2>; +- }; +- +- cpu_l3: cpu@300 { +- device_type = "cpu"; +- compatible = "arm,cortex-a55"; +- reg = <0x300>; +- enable-method = "psci"; +- capacity-dmips-mhz = <530>; +- clocks = <&scmi_clk SCMI_CLK_CPUL>; +- cpu-idle-states = <&CPU_SLEEP>; +- i-cache-size = <32768>; +- i-cache-line-size = <64>; +- i-cache-sets = <128>; +- d-cache-size = <32768>; +- d-cache-line-size = <64>; +- d-cache-sets = <128>; +- next-level-cache = <&l2_cache_l3>; +- dynamic-power-coefficient = <228>; +- #cooling-cells = <2>; +- }; +- +- cpu_b0: cpu@400 { +- device_type = "cpu"; +- compatible = "arm,cortex-a76"; +- reg = <0x400>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk SCMI_CLK_CPUB01>; +- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; +- assigned-clock-rates = <816000000>; +- cpu-idle-states = <&CPU_SLEEP>; +- i-cache-size = <65536>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_cache_b0>; +- dynamic-power-coefficient = <416>; +- #cooling-cells = <2>; +- }; +- +- cpu_b1: cpu@500 { +- device_type = "cpu"; +- compatible = "arm,cortex-a76"; +- reg = <0x500>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk SCMI_CLK_CPUB01>; +- cpu-idle-states = <&CPU_SLEEP>; +- i-cache-size = <65536>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_cache_b1>; +- dynamic-power-coefficient = <416>; +- #cooling-cells = <2>; +- }; +- +- cpu_b2: cpu@600 { +- device_type = "cpu"; +- compatible = "arm,cortex-a76"; +- reg = <0x600>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk SCMI_CLK_CPUB23>; +- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; +- assigned-clock-rates = <816000000>; +- cpu-idle-states = <&CPU_SLEEP>; +- i-cache-size = <65536>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_cache_b2>; +- dynamic-power-coefficient = <416>; +- #cooling-cells = <2>; +- }; +- +- cpu_b3: cpu@700 { +- device_type = "cpu"; +- compatible = "arm,cortex-a76"; +- reg = <0x700>; +- enable-method = "psci"; +- capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk SCMI_CLK_CPUB23>; +- cpu-idle-states = <&CPU_SLEEP>; +- i-cache-size = <65536>; +- i-cache-line-size = <64>; +- i-cache-sets = <256>; +- d-cache-size = <65536>; +- d-cache-line-size = <64>; +- d-cache-sets = <256>; +- next-level-cache = <&l2_cache_b3>; +- dynamic-power-coefficient = <416>; +- #cooling-cells = <2>; +- }; +- +- idle-states { +- entry-method = "psci"; +- CPU_SLEEP: cpu-sleep { +- compatible = "arm,idle-state"; +- local-timer-stop; +- arm,psci-suspend-param = <0x0010000>; +- entry-latency-us = <100>; +- exit-latency-us = <120>; +- min-residency-us = <1000>; +- }; +- }; +- +- l2_cache_l0: l2-cache-l0 { +- compatible = "cache"; +- cache-size = <131072>; +- cache-line-size = <64>; +- cache-sets = <512>; +- cache-level = <2>; +- cache-unified; +- next-level-cache = <&l3_cache>; +- }; +- +- l2_cache_l1: l2-cache-l1 { +- compatible = "cache"; +- cache-size = <131072>; +- cache-line-size = <64>; +- cache-sets = <512>; +- cache-level = <2>; +- cache-unified; +- next-level-cache = <&l3_cache>; +- }; +- +- l2_cache_l2: l2-cache-l2 { +- compatible = "cache"; +- cache-size = <131072>; +- cache-line-size = <64>; +- cache-sets = <512>; +- cache-level = <2>; +- cache-unified; +- next-level-cache = <&l3_cache>; +- }; +- +- l2_cache_l3: l2-cache-l3 { +- compatible = "cache"; +- cache-size = <131072>; +- cache-line-size = <64>; +- cache-sets = <512>; +- cache-level = <2>; +- cache-unified; +- next-level-cache = <&l3_cache>; +- }; +- +- l2_cache_b0: l2-cache-b0 { +- compatible = "cache"; +- cache-size = <524288>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- cache-unified; +- next-level-cache = <&l3_cache>; +- }; +- +- l2_cache_b1: l2-cache-b1 { +- compatible = "cache"; +- cache-size = <524288>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- cache-unified; +- next-level-cache = <&l3_cache>; +- }; +- +- l2_cache_b2: l2-cache-b2 { +- compatible = "cache"; +- cache-size = <524288>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- cache-unified; +- next-level-cache = <&l3_cache>; +- }; +- +- l2_cache_b3: l2-cache-b3 { +- compatible = "cache"; +- cache-size = <524288>; +- cache-line-size = <64>; +- cache-sets = <1024>; +- cache-level = <2>; +- cache-unified; +- next-level-cache = <&l3_cache>; +- }; +- +- l3_cache: l3-cache { +- compatible = "cache"; +- cache-size = <3145728>; +- cache-line-size = <64>; +- cache-sets = <4096>; +- cache-level = <3>; +- cache-unified; +- }; +- }; +- +- display_subsystem: display-subsystem { +- compatible = "rockchip,display-subsystem"; +- ports = <&vop_out>; +- }; +- +- firmware { +- optee: optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- +- scmi: scmi { +- compatible = "arm,scmi-smc"; +- arm,smc-id = <0x82000010>; +- shmem = <&scmi_shmem>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- scmi_clk: protocol@14 { +- reg = <0x14>; +- #clock-cells = <1>; +- }; +- +- scmi_reset: protocol@16 { +- reg = <0x16>; +- #reset-cells = <1>; +- }; +- }; +- }; +- +- pmu-a55 { +- compatible = "arm,cortex-a55-pmu"; +- interrupts = ; +- }; +- +- pmu-a76 { +- compatible = "arm,cortex-a76-pmu"; +- interrupts = ; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- spll: clock-0 { +- compatible = "fixed-clock"; +- clock-frequency = <702000000>; +- clock-output-names = "spll"; +- #clock-cells = <0>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; +- }; +- +- xin24m: clock-1 { +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "xin24m"; +- #clock-cells = <0>; +- }; +- +- xin32k: clock-2 { +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "xin32k"; +- #clock-cells = <0>; +- }; +- +- pmu_sram: sram@10f000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x0010f000 0x0 0x100>; +- ranges = <0 0x0 0x0010f000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- scmi_shmem: sram@0 { +- compatible = "arm,scmi-shmem"; +- reg = <0x0 0x100>; +- }; +- }; +- +- gpu: gpu@fb000000 { +- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; +- reg = <0x0 0xfb000000 0x0 0x200000>; +- #cooling-cells = <2>; +- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; +- assigned-clock-rates = <200000000>; +- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, +- <&cru CLK_GPU_STACKS>; +- clock-names = "core", "coregroup", "stacks"; +- dynamic-power-coefficient = <2982>; +- interrupts = , +- , +- ; +- interrupt-names = "job", "mmu", "gpu"; +- operating-points-v2 = <&gpu_opp_table>; +- power-domains = <&power RK3588_PD_GPU>; +- status = "disabled"; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <700000 700000 850000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <750000 750000 850000>; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <800000 800000 850000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <850000 850000 850000>; +- }; +- }; +- }; +- +- usb_host0_xhci: usb@fc000000 { +- compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; +- reg = <0x0 0xfc000000 0x0 0x400000>; +- interrupts = ; +- clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, +- <&cru ACLK_USB3OTG0>; +- clock-names = "ref_clk", "suspend_clk", "bus_clk"; +- dr_mode = "otg"; +- phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; +- phy-names = "usb2-phy", "usb3-phy"; +- phy_type = "utmi_wide"; +- power-domains = <&power RK3588_PD_USB>; +- resets = <&cru SRST_A_USB3OTG0>; +- snps,dis_enblslpm_quirk; +- snps,dis-u1-entry-quirk; +- snps,dis-u2-entry-quirk; +- snps,dis-u2-freeclk-exists-quirk; +- snps,dis-del-phy-power-chg-quirk; +- snps,dis-tx-ipgap-linecheck-quirk; +- status = "disabled"; +- }; +- +- usb_host0_ehci: usb@fc800000 { +- compatible = "rockchip,rk3588-ehci", "generic-ehci"; +- reg = <0x0 0xfc800000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; +- phys = <&u2phy2_host>; +- phy-names = "usb"; +- power-domains = <&power RK3588_PD_USB>; +- status = "disabled"; +- }; +- +- usb_host0_ohci: usb@fc840000 { +- compatible = "rockchip,rk3588-ohci", "generic-ohci"; +- reg = <0x0 0xfc840000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; +- phys = <&u2phy2_host>; +- phy-names = "usb"; +- power-domains = <&power RK3588_PD_USB>; +- status = "disabled"; +- }; +- +- usb_host1_ehci: usb@fc880000 { +- compatible = "rockchip,rk3588-ehci", "generic-ehci"; +- reg = <0x0 0xfc880000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; +- phys = <&u2phy3_host>; +- phy-names = "usb"; +- power-domains = <&power RK3588_PD_USB>; +- status = "disabled"; +- }; +- +- usb_host1_ohci: usb@fc8c0000 { +- compatible = "rockchip,rk3588-ohci", "generic-ohci"; +- reg = <0x0 0xfc8c0000 0x0 0x40000>; +- interrupts = ; +- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; +- phys = <&u2phy3_host>; +- phy-names = "usb"; +- power-domains = <&power RK3588_PD_USB>; +- status = "disabled"; +- }; +- +- usb_host2_xhci: usb@fcd00000 { +- compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; +- reg = <0x0 0xfcd00000 0x0 0x400000>; +- interrupts = ; +- clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, +- <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, +- <&cru CLK_PIPEPHY2_PIPE_U3_G>; +- clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; +- dr_mode = "host"; +- phys = <&combphy2_psu PHY_TYPE_USB3>; +- phy-names = "usb3-phy"; +- phy_type = "utmi_wide"; +- resets = <&cru SRST_A_USB3OTG2>; +- snps,dis_enblslpm_quirk; +- snps,dis-u2-freeclk-exists-quirk; +- snps,dis-del-phy-power-chg-quirk; +- snps,dis-tx-ipgap-linecheck-quirk; +- snps,dis_rxdet_inp3_quirk; +- status = "disabled"; +- }; +- +- mmu600_pcie: iommu@fc900000 { +- compatible = "arm,smmu-v3"; +- reg = <0x0 0xfc900000 0x0 0x200000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- mmu600_php: iommu@fcb00000 { +- compatible = "arm,smmu-v3"; +- reg = <0x0 0xfcb00000 0x0 0x200000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; +- #iommu-cells = <1>; +- status = "disabled"; +- }; +- +- pmu1grf: syscon@fd58a000 { +- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; +- reg = <0x0 0xfd58a000 0x0 0x10000>; +- }; +- +- sys_grf: syscon@fd58c000 { +- compatible = "rockchip,rk3588-sys-grf", "syscon"; +- reg = <0x0 0xfd58c000 0x0 0x1000>; +- }; +- +- vop_grf: syscon@fd5a4000 { +- compatible = "rockchip,rk3588-vop-grf", "syscon"; +- reg = <0x0 0xfd5a4000 0x0 0x2000>; +- }; +- +- vo0_grf: syscon@fd5a6000 { +- compatible = "rockchip,rk3588-vo-grf", "syscon"; +- reg = <0x0 0xfd5a6000 0x0 0x2000>; +- clocks = <&cru PCLK_VO0GRF>; +- }; +- +- vo1_grf: syscon@fd5a8000 { +- compatible = "rockchip,rk3588-vo-grf", "syscon"; +- reg = <0x0 0xfd5a8000 0x0 0x100>; +- clocks = <&cru PCLK_VO1GRF>; +- }; +- +- usb_grf: syscon@fd5ac000 { +- compatible = "rockchip,rk3588-usb-grf", "syscon"; +- reg = <0x0 0xfd5ac000 0x0 0x4000>; +- }; +- +- php_grf: syscon@fd5b0000 { +- compatible = "rockchip,rk3588-php-grf", "syscon"; +- reg = <0x0 0xfd5b0000 0x0 0x1000>; +- }; +- +- pipe_phy0_grf: syscon@fd5bc000 { +- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; +- reg = <0x0 0xfd5bc000 0x0 0x100>; +- }; +- +- pipe_phy2_grf: syscon@fd5c4000 { +- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; +- reg = <0x0 0xfd5c4000 0x0 0x100>; +- }; +- +- usbdpphy0_grf: syscon@fd5c8000 { +- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; +- reg = <0x0 0xfd5c8000 0x0 0x4000>; +- }; +- +- usb2phy0_grf: syscon@fd5d0000 { +- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xfd5d0000 0x0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u2phy0: usb2phy@0 { +- compatible = "rockchip,rk3588-usb2phy"; +- reg = <0x0 0x10>; +- #clock-cells = <0>; +- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; +- clock-names = "phyclk"; +- clock-output-names = "usb480m_phy0"; +- interrupts = ; +- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; +- reset-names = "phy", "apb"; +- status = "disabled"; +- +- u2phy0_otg: otg-port { +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- usb2phy2_grf: syscon@fd5d8000 { +- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xfd5d8000 0x0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u2phy2: usb2phy@8000 { +- compatible = "rockchip,rk3588-usb2phy"; +- reg = <0x8000 0x10>; +- #clock-cells = <0>; +- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; +- clock-names = "phyclk"; +- clock-output-names = "usb480m_phy2"; +- interrupts = ; +- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; +- reset-names = "phy", "apb"; +- status = "disabled"; +- +- u2phy2_host: host-port { +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- usb2phy3_grf: syscon@fd5dc000 { +- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; +- reg = <0x0 0xfd5dc000 0x0 0x4000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- u2phy3: usb2phy@c000 { +- compatible = "rockchip,rk3588-usb2phy"; +- reg = <0xc000 0x10>; +- #clock-cells = <0>; +- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; +- clock-names = "phyclk"; +- clock-output-names = "usb480m_phy3"; +- interrupts = ; +- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; +- reset-names = "phy", "apb"; +- status = "disabled"; +- +- u2phy3_host: host-port { +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- }; +- +- hdptxphy0_grf: syscon@fd5e0000 { +- compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; +- reg = <0x0 0xfd5e0000 0x0 0x100>; +- }; +- +- ioc: syscon@fd5f0000 { +- compatible = "rockchip,rk3588-ioc", "syscon"; +- reg = <0x0 0xfd5f0000 0x0 0x10000>; +- }; +- +- system_sram1: sram@fd600000 { +- compatible = "mmio-sram"; +- reg = <0x0 0xfd600000 0x0 0x100000>; +- ranges = <0x0 0x0 0xfd600000 0x100000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- cru: clock-controller@fd7c0000 { +- compatible = "rockchip,rk3588-cru"; +- reg = <0x0 0xfd7c0000 0x0 0x5c000>; +- assigned-clocks = +- <&cru PLL_PPLL>, <&cru PLL_AUPLL>, +- <&cru PLL_NPLL>, <&cru PLL_GPLL>, +- <&cru ACLK_CENTER_ROOT>, +- <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, +- <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, +- <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, +- <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, +- <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, +- <&cru CLK_GPU>; +- assigned-clock-rates = +- <1100000000>, <786432000>, +- <850000000>, <1188000000>, +- <702000000>, +- <400000000>, <500000000>, +- <800000000>, <100000000>, +- <400000000>, <100000000>, +- <200000000>, <500000000>, +- <375000000>, <150000000>, +- <200000000>; +- rockchip,grf = <&php_grf>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- i2c0: i2c@fd880000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfd880000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; +- clock-names = "i2c", "pclk"; +- pinctrl-0 = <&i2c0m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart0: serial@fd890000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfd890000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 6>, <&dmac0 7>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart0m1_xfer>; +- pinctrl-names = "default"; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- pwm0: pwm@fd8b0000 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfd8b0000 0x0 0x10>; +- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm0m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm1: pwm@fd8b0010 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfd8b0010 0x0 0x10>; +- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm1m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm2: pwm@fd8b0020 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfd8b0020 0x0 0x10>; +- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm2m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm3: pwm@fd8b0030 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfd8b0030 0x0 0x10>; +- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm3m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pmu: power-management@fd8d8000 { +- compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; +- reg = <0x0 0xfd8d8000 0x0 0x400>; +- +- power: power-controller { +- compatible = "rockchip,rk3588-power-controller"; +- #address-cells = <1>; +- #power-domain-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- /* These power domains are grouped by VD_NPU */ +- power-domain@RK3588_PD_NPU { +- reg = ; +- #power-domain-cells = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3588_PD_NPUTOP { +- reg = ; +- clocks = <&cru HCLK_NPU_ROOT>, +- <&cru PCLK_NPU_ROOT>, +- <&cru CLK_NPU_DSU0>, +- <&cru HCLK_NPU_CM0_ROOT>; +- pm_qos = <&qos_npu0_mwr>, +- <&qos_npu0_mro>, +- <&qos_mcu_npu>; +- #power-domain-cells = <0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- power-domain@RK3588_PD_NPU1 { +- reg = ; +- clocks = <&cru HCLK_NPU_ROOT>, +- <&cru PCLK_NPU_ROOT>, +- <&cru CLK_NPU_DSU0>; +- pm_qos = <&qos_npu1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_NPU2 { +- reg = ; +- clocks = <&cru HCLK_NPU_ROOT>, +- <&cru PCLK_NPU_ROOT>, +- <&cru CLK_NPU_DSU0>; +- pm_qos = <&qos_npu2>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- /* These power domains are grouped by VD_GPU */ +- power-domain@RK3588_PD_GPU { +- reg = ; +- clocks = <&cru CLK_GPU>, +- <&cru CLK_GPU_COREGROUP>, +- <&cru CLK_GPU_STACKS>; +- pm_qos = <&qos_gpu_m0>, +- <&qos_gpu_m1>, +- <&qos_gpu_m2>, +- <&qos_gpu_m3>; +- #power-domain-cells = <0>; +- }; +- /* These power domains are grouped by VD_VCODEC */ +- power-domain@RK3588_PD_VCODEC { +- reg = ; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- power-domain@RK3588_PD_RKVDEC0 { +- reg = ; +- clocks = <&cru HCLK_RKVDEC0>, +- <&cru HCLK_VDPU_ROOT>, +- <&cru ACLK_VDPU_ROOT>, +- <&cru ACLK_RKVDEC0>, +- <&cru ACLK_RKVDEC_CCU>; +- pm_qos = <&qos_rkvdec0>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_RKVDEC1 { +- reg = ; +- clocks = <&cru HCLK_RKVDEC1>, +- <&cru HCLK_VDPU_ROOT>, +- <&cru ACLK_VDPU_ROOT>, +- <&cru ACLK_RKVDEC1>; +- pm_qos = <&qos_rkvdec1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_VENC0 { +- reg = ; +- clocks = <&cru HCLK_RKVENC0>, +- <&cru ACLK_RKVENC0>; +- pm_qos = <&qos_rkvenc0_m0ro>, +- <&qos_rkvenc0_m1ro>, +- <&qos_rkvenc0_m2wo>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- power-domain@RK3588_PD_VENC1 { +- reg = ; +- clocks = <&cru HCLK_RKVENC1>, +- <&cru HCLK_RKVENC0>, +- <&cru ACLK_RKVENC0>, +- <&cru ACLK_RKVENC1>; +- pm_qos = <&qos_rkvenc1_m0ro>, +- <&qos_rkvenc1_m1ro>, +- <&qos_rkvenc1_m2wo>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- /* These power domains are grouped by VD_LOGIC */ +- power-domain@RK3588_PD_VDPU { +- reg = ; +- clocks = <&cru HCLK_VDPU_ROOT>, +- <&cru ACLK_VDPU_LOW_ROOT>, +- <&cru ACLK_VDPU_ROOT>, +- <&cru ACLK_JPEG_DECODER_ROOT>, +- <&cru ACLK_IEP2P0>, +- <&cru HCLK_IEP2P0>, +- <&cru ACLK_JPEG_ENCODER0>, +- <&cru HCLK_JPEG_ENCODER0>, +- <&cru ACLK_JPEG_ENCODER1>, +- <&cru HCLK_JPEG_ENCODER1>, +- <&cru ACLK_JPEG_ENCODER2>, +- <&cru HCLK_JPEG_ENCODER2>, +- <&cru ACLK_JPEG_ENCODER3>, +- <&cru HCLK_JPEG_ENCODER3>, +- <&cru ACLK_JPEG_DECODER>, +- <&cru HCLK_JPEG_DECODER>, +- <&cru ACLK_RGA2>, +- <&cru HCLK_RGA2>; +- pm_qos = <&qos_iep>, +- <&qos_jpeg_dec>, +- <&qos_jpeg_enc0>, +- <&qos_jpeg_enc1>, +- <&qos_jpeg_enc2>, +- <&qos_jpeg_enc3>, +- <&qos_rga2_mro>, +- <&qos_rga2_mwo>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- +- power-domain@RK3588_PD_AV1 { +- reg = ; +- clocks = <&cru PCLK_AV1>, +- <&cru ACLK_AV1>, +- <&cru HCLK_VDPU_ROOT>; +- pm_qos = <&qos_av1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_RKVDEC0 { +- reg = ; +- clocks = <&cru HCLK_RKVDEC0>, +- <&cru HCLK_VDPU_ROOT>, +- <&cru ACLK_VDPU_ROOT>, +- <&cru ACLK_RKVDEC0>; +- pm_qos = <&qos_rkvdec0>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_RKVDEC1 { +- reg = ; +- clocks = <&cru HCLK_RKVDEC1>, +- <&cru HCLK_VDPU_ROOT>, +- <&cru ACLK_VDPU_ROOT>; +- pm_qos = <&qos_rkvdec1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_RGA30 { +- reg = ; +- clocks = <&cru ACLK_RGA3_0>, +- <&cru HCLK_RGA3_0>; +- pm_qos = <&qos_rga3_0>; +- #power-domain-cells = <0>; +- }; +- }; +- power-domain@RK3588_PD_VOP { +- reg = ; +- clocks = <&cru PCLK_VOP_ROOT>, +- <&cru HCLK_VOP_ROOT>, +- <&cru ACLK_VOP>; +- pm_qos = <&qos_vop_m0>, +- <&qos_vop_m1>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- power-domain@RK3588_PD_VO0 { +- reg = ; +- clocks = <&cru PCLK_VO0_ROOT>, +- <&cru PCLK_VO0_S_ROOT>, +- <&cru HCLK_VO0_S_ROOT>, +- <&cru ACLK_VO0_ROOT>, +- <&cru HCLK_HDCP0>, +- <&cru ACLK_HDCP0>, +- <&cru HCLK_VOP_ROOT>; +- pm_qos = <&qos_hdcp0>; +- #power-domain-cells = <0>; +- }; +- }; +- power-domain@RK3588_PD_VO1 { +- reg = ; +- clocks = <&cru PCLK_VO1_ROOT>, +- <&cru PCLK_VO1_S_ROOT>, +- <&cru HCLK_VO1_S_ROOT>, +- <&cru HCLK_HDCP1>, +- <&cru ACLK_HDCP1>, +- <&cru ACLK_HDMIRX_ROOT>, +- <&cru HCLK_VO1USB_TOP_ROOT>; +- pm_qos = <&qos_hdcp1>, +- <&qos_hdmirx>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_VI { +- reg = ; +- clocks = <&cru HCLK_VI_ROOT>, +- <&cru PCLK_VI_ROOT>, +- <&cru HCLK_ISP0>, +- <&cru ACLK_ISP0>, +- <&cru HCLK_VICAP>, +- <&cru ACLK_VICAP>; +- pm_qos = <&qos_isp0_mro>, +- <&qos_isp0_mwo>, +- <&qos_vicap_m0>, +- <&qos_vicap_m1>; +- #address-cells = <1>; +- #size-cells = <0>; +- #power-domain-cells = <0>; +- +- power-domain@RK3588_PD_ISP1 { +- reg = ; +- clocks = <&cru HCLK_ISP1>, +- <&cru ACLK_ISP1>, +- <&cru HCLK_VI_ROOT>, +- <&cru PCLK_VI_ROOT>; +- pm_qos = <&qos_isp1_mwo>, +- <&qos_isp1_mro>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_FEC { +- reg = ; +- clocks = <&cru HCLK_FISHEYE0>, +- <&cru ACLK_FISHEYE0>, +- <&cru HCLK_FISHEYE1>, +- <&cru ACLK_FISHEYE1>, +- <&cru PCLK_VI_ROOT>; +- pm_qos = <&qos_fisheye0>, +- <&qos_fisheye1>; +- #power-domain-cells = <0>; +- }; +- }; +- power-domain@RK3588_PD_RGA31 { +- reg = ; +- clocks = <&cru HCLK_RGA3_1>, +- <&cru ACLK_RGA3_1>; +- pm_qos = <&qos_rga3_1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_USB { +- reg = ; +- clocks = <&cru PCLK_PHP_ROOT>, +- <&cru ACLK_USB_ROOT>, +- <&cru ACLK_USB>, +- <&cru HCLK_USB_ROOT>, +- <&cru HCLK_HOST0>, +- <&cru HCLK_HOST_ARB0>, +- <&cru HCLK_HOST1>, +- <&cru HCLK_HOST_ARB1>; +- pm_qos = <&qos_usb3_0>, +- <&qos_usb3_1>, +- <&qos_usb2host_0>, +- <&qos_usb2host_1>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_GMAC { +- reg = ; +- clocks = <&cru PCLK_PHP_ROOT>, +- <&cru ACLK_PCIE_ROOT>, +- <&cru ACLK_PHP_ROOT>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_PCIE { +- reg = ; +- clocks = <&cru PCLK_PHP_ROOT>, +- <&cru ACLK_PCIE_ROOT>, +- <&cru ACLK_PHP_ROOT>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_SDIO { +- reg = ; +- clocks = <&cru HCLK_SDIO>, +- <&cru HCLK_NVM_ROOT>; +- pm_qos = <&qos_sdio>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_AUDIO { +- reg = ; +- clocks = <&cru HCLK_AUDIO_ROOT>, +- <&cru PCLK_AUDIO_ROOT>; +- #power-domain-cells = <0>; +- }; +- power-domain@RK3588_PD_SDMMC { +- reg = ; +- pm_qos = <&qos_sdmmc>; +- #power-domain-cells = <0>; +- }; +- }; +- }; +- +- av1d: video-codec@fdc70000 { +- compatible = "rockchip,rk3588-av1-vpu"; +- reg = <0x0 0xfdc70000 0x0 0x800>; +- interrupts = ; +- interrupt-names = "vdpu"; +- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; +- assigned-clock-rates = <400000000>, <400000000>; +- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; +- clock-names = "aclk", "hclk"; +- power-domains = <&power RK3588_PD_AV1>; +- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; +- }; +- +- vop: vop@fdd90000 { +- compatible = "rockchip,rk3588-vop"; +- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; +- reg-names = "vop", "gamma-lut"; +- interrupts = ; +- clocks = <&cru ACLK_VOP>, +- <&cru HCLK_VOP>, +- <&cru DCLK_VOP0>, +- <&cru DCLK_VOP1>, +- <&cru DCLK_VOP2>, +- <&cru DCLK_VOP3>, +- <&cru PCLK_VOP_ROOT>; +- clock-names = "aclk", +- "hclk", +- "dclk_vp0", +- "dclk_vp1", +- "dclk_vp2", +- "dclk_vp3", +- "pclk_vop"; +- iommus = <&vop_mmu>; +- power-domains = <&power RK3588_PD_VOP>; +- rockchip,grf = <&sys_grf>; +- rockchip,vop-grf = <&vop_grf>; +- rockchip,vo1-grf = <&vo1_grf>; +- rockchip,pmu = <&pmu>; +- status = "disabled"; +- +- vop_out: ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- vp0: port@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- }; +- +- vp1: port@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- vp2: port@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- +- vp3: port@3 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <3>; +- }; +- }; +- }; +- +- vop_mmu: iommu@fdd97e00 { +- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; +- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; +- interrupts = ; +- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; +- clock-names = "aclk", "iface"; +- #iommu-cells = <0>; +- power-domains = <&power RK3588_PD_VOP>; +- status = "disabled"; +- }; +- +- i2s4_8ch: i2s@fddc0000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfddc0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac2 0>; +- dma-names = "tx"; +- power-domains = <&power RK3588_PD_VO0>; +- resets = <&cru SRST_M_I2S4_8CH_TX>; +- reset-names = "tx-m"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s5_8ch: i2s@fddf0000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfddf0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac2 2>; +- dma-names = "tx"; +- power-domains = <&power RK3588_PD_VO1>; +- resets = <&cru SRST_M_I2S5_8CH_TX>; +- reset-names = "tx-m"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s9_8ch: i2s@fddfc000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfddfc000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac2 23>; +- dma-names = "rx"; +- power-domains = <&power RK3588_PD_VO1>; +- resets = <&cru SRST_M_I2S9_8CH_RX>; +- reset-names = "rx-m"; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- qos_gpu_m0: qos@fdf35000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf35000 0x0 0x20>; +- }; +- +- qos_gpu_m1: qos@fdf35200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf35200 0x0 0x20>; +- }; +- +- qos_gpu_m2: qos@fdf35400 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf35400 0x0 0x20>; +- }; +- +- qos_gpu_m3: qos@fdf35600 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf35600 0x0 0x20>; +- }; +- +- qos_rga3_1: qos@fdf36000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf36000 0x0 0x20>; +- }; +- +- qos_sdio: qos@fdf39000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf39000 0x0 0x20>; +- }; +- +- qos_sdmmc: qos@fdf3d800 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf3d800 0x0 0x20>; +- }; +- +- qos_usb3_1: qos@fdf3e000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf3e000 0x0 0x20>; +- }; +- +- qos_usb3_0: qos@fdf3e200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf3e200 0x0 0x20>; +- }; +- +- qos_usb2host_0: qos@fdf3e400 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf3e400 0x0 0x20>; +- }; +- +- qos_usb2host_1: qos@fdf3e600 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf3e600 0x0 0x20>; +- }; +- +- qos_fisheye0: qos@fdf40000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf40000 0x0 0x20>; +- }; +- +- qos_fisheye1: qos@fdf40200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf40200 0x0 0x20>; +- }; +- +- qos_isp0_mro: qos@fdf40400 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf40400 0x0 0x20>; +- }; +- +- qos_isp0_mwo: qos@fdf40500 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf40500 0x0 0x20>; +- }; +- +- qos_vicap_m0: qos@fdf40600 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf40600 0x0 0x20>; +- }; +- +- qos_vicap_m1: qos@fdf40800 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf40800 0x0 0x20>; +- }; +- +- qos_isp1_mwo: qos@fdf41000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf41000 0x0 0x20>; +- }; +- +- qos_isp1_mro: qos@fdf41100 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf41100 0x0 0x20>; +- }; +- +- qos_rkvenc0_m0ro: qos@fdf60000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf60000 0x0 0x20>; +- }; +- +- qos_rkvenc0_m1ro: qos@fdf60200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf60200 0x0 0x20>; +- }; +- +- qos_rkvenc0_m2wo: qos@fdf60400 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf60400 0x0 0x20>; +- }; +- +- qos_rkvenc1_m0ro: qos@fdf61000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf61000 0x0 0x20>; +- }; +- +- qos_rkvenc1_m1ro: qos@fdf61200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf61200 0x0 0x20>; +- }; +- +- qos_rkvenc1_m2wo: qos@fdf61400 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf61400 0x0 0x20>; +- }; +- +- qos_rkvdec0: qos@fdf62000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf62000 0x0 0x20>; +- }; +- +- qos_rkvdec1: qos@fdf63000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf63000 0x0 0x20>; +- }; +- +- qos_av1: qos@fdf64000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf64000 0x0 0x20>; +- }; +- +- qos_iep: qos@fdf66000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf66000 0x0 0x20>; +- }; +- +- qos_jpeg_dec: qos@fdf66200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf66200 0x0 0x20>; +- }; +- +- qos_jpeg_enc0: qos@fdf66400 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf66400 0x0 0x20>; +- }; +- +- qos_jpeg_enc1: qos@fdf66600 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf66600 0x0 0x20>; +- }; +- +- qos_jpeg_enc2: qos@fdf66800 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf66800 0x0 0x20>; +- }; +- +- qos_jpeg_enc3: qos@fdf66a00 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf66a00 0x0 0x20>; +- }; +- +- qos_rga2_mro: qos@fdf66c00 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf66c00 0x0 0x20>; +- }; +- +- qos_rga2_mwo: qos@fdf66e00 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf66e00 0x0 0x20>; +- }; +- +- qos_rga3_0: qos@fdf67000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf67000 0x0 0x20>; +- }; +- +- qos_vdpu: qos@fdf67200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf67200 0x0 0x20>; +- }; +- +- qos_npu1: qos@fdf70000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf70000 0x0 0x20>; +- }; +- +- qos_npu2: qos@fdf71000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf71000 0x0 0x20>; +- }; +- +- qos_npu0_mwr: qos@fdf72000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf72000 0x0 0x20>; +- }; +- +- qos_npu0_mro: qos@fdf72200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf72200 0x0 0x20>; +- }; +- +- qos_mcu_npu: qos@fdf72400 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf72400 0x0 0x20>; +- }; +- +- qos_hdcp0: qos@fdf80000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf80000 0x0 0x20>; +- }; +- +- qos_hdcp1: qos@fdf81000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf81000 0x0 0x20>; +- }; +- +- qos_hdmirx: qos@fdf81200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf81200 0x0 0x20>; +- }; +- +- qos_vop_m0: qos@fdf82000 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf82000 0x0 0x20>; +- }; +- +- qos_vop_m1: qos@fdf82200 { +- compatible = "rockchip,rk3588-qos", "syscon"; +- reg = <0x0 0xfdf82200 0x0 0x20>; +- }; +- +- dfi: dfi@fe060000 { +- reg = <0x00 0xfe060000 0x00 0x10000>; +- compatible = "rockchip,rk3588-dfi"; +- interrupts = , +- , +- , +- ; +- rockchip,pmu = <&pmu1grf>; +- }; +- +- pcie2x1l1: pcie@fe180000 { +- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; +- bus-range = <0x30 0x3f>; +- clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, +- <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, +- <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; +- clock-names = "aclk_mst", "aclk_slv", +- "aclk_dbi", "pclk", +- "aux", "pipe"; +- device_type = "pci"; +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, +- <0 0 0 2 &pcie2x1l1_intc 1>, +- <0 0 0 3 &pcie2x1l1_intc 2>, +- <0 0 0 4 &pcie2x1l1_intc 3>; +- linux,pci-domain = <3>; +- max-link-speed = <2>; +- msi-map = <0x3000 &its0 0x3000 0x1000>; +- num-lanes = <1>; +- phys = <&combphy2_psu PHY_TYPE_PCIE>; +- phy-names = "pcie-phy"; +- power-domains = <&power RK3588_PD_PCIE>; +- ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, +- <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, +- <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; +- reg = <0xa 0x40c00000 0x0 0x00400000>, +- <0x0 0xfe180000 0x0 0x00010000>, +- <0x0 0xf3000000 0x0 0x00100000>; +- reg-names = "dbi", "apb", "config"; +- resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; +- reset-names = "pwr", "pipe"; +- #address-cells = <3>; +- #size-cells = <2>; +- status = "disabled"; +- +- pcie2x1l1_intc: legacy-interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- pcie2x1l2: pcie@fe190000 { +- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; +- bus-range = <0x40 0x4f>; +- clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, +- <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, +- <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; +- clock-names = "aclk_mst", "aclk_slv", +- "aclk_dbi", "pclk", +- "aux", "pipe"; +- device_type = "pci"; +- interrupts = , +- , +- , +- , +- ; +- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, +- <0 0 0 2 &pcie2x1l2_intc 1>, +- <0 0 0 3 &pcie2x1l2_intc 2>, +- <0 0 0 4 &pcie2x1l2_intc 3>; +- linux,pci-domain = <4>; +- max-link-speed = <2>; +- msi-map = <0x4000 &its0 0x4000 0x1000>; +- num-lanes = <1>; +- phys = <&combphy0_ps PHY_TYPE_PCIE>; +- phy-names = "pcie-phy"; +- power-domains = <&power RK3588_PD_PCIE>; +- ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, +- <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, +- <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; +- reg = <0xa 0x41000000 0x0 0x00400000>, +- <0x0 0xfe190000 0x0 0x00010000>, +- <0x0 0xf4000000 0x0 0x00100000>; +- reg-names = "dbi", "apb", "config"; +- resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; +- reset-names = "pwr", "pipe"; +- #address-cells = <3>; +- #size-cells = <2>; +- status = "disabled"; +- +- pcie2x1l2_intc: legacy-interrupt-controller { +- interrupt-controller; +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- }; +- }; +- +- gmac1: ethernet@fe1c0000 { +- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; +- reg = <0x0 0xfe1c0000 0x0 0x10000>; +- interrupts = , +- ; +- interrupt-names = "macirq", "eth_wake_irq"; +- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, +- <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, +- <&cru CLK_GMAC1_PTP_REF>; +- clock-names = "stmmaceth", "clk_mac_ref", +- "pclk_mac", "aclk_mac", +- "ptp_ref"; +- power-domains = <&power RK3588_PD_GMAC>; +- resets = <&cru SRST_A_GMAC1>; +- reset-names = "stmmaceth"; +- rockchip,grf = <&sys_grf>; +- rockchip,php-grf = <&php_grf>; +- snps,axi-config = <&gmac1_stmmac_axi_setup>; +- snps,mixed-burst; +- snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; +- snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; +- snps,tso; +- status = "disabled"; +- +- mdio1: mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- }; +- +- gmac1_stmmac_axi_setup: stmmac-axi-config { +- snps,blen = <0 0 0 0 16 8 4>; +- snps,wr_osr_lmt = <4>; +- snps,rd_osr_lmt = <8>; +- }; +- +- gmac1_mtl_rx_setup: rx-queues-config { +- snps,rx-queues-to-use = <2>; +- queue0 {}; +- queue1 {}; +- }; +- +- gmac1_mtl_tx_setup: tx-queues-config { +- snps,tx-queues-to-use = <2>; +- queue0 {}; +- queue1 {}; +- }; +- }; +- +- sata0: sata@fe210000 { +- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; +- reg = <0 0xfe210000 0 0x1000>; +- interrupts = ; +- clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, +- <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, +- <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; +- clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; +- ports-implemented = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata-port@0 { +- reg = <0>; +- hba-port-cap = ; +- phys = <&combphy0_ps PHY_TYPE_SATA>; +- phy-names = "sata-phy"; +- snps,rx-ts-max = <32>; +- snps,tx-ts-max = <32>; +- }; +- }; +- +- sata2: sata@fe230000 { +- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; +- reg = <0 0xfe230000 0 0x1000>; +- interrupts = ; +- clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, +- <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, +- <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; +- clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; +- ports-implemented = <0x1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata-port@0 { +- reg = <0>; +- hba-port-cap = ; +- phys = <&combphy2_psu PHY_TYPE_SATA>; +- phy-names = "sata-phy"; +- snps,rx-ts-max = <32>; +- snps,tx-ts-max = <32>; +- }; +- }; +- +- sfc: spi@fe2b0000 { +- compatible = "rockchip,sfc"; +- reg = <0x0 0xfe2b0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; +- clock-names = "clk_sfc", "hclk_sfc"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- sdmmc: mmc@fe2c0000 { +- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x0 0xfe2c0000 0x0 0x4000>; +- interrupts = ; +- clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, +- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; +- power-domains = <&power RK3588_PD_SDMMC>; +- status = "disabled"; +- }; +- +- sdio: mmc@fe2d0000 { +- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; +- reg = <0x00 0xfe2d0000 0x00 0x4000>; +- interrupts = ; +- clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, +- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; +- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; +- fifo-depth = <0x100>; +- max-frequency = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdiom1_pins>; +- power-domains = <&power RK3588_PD_SDIO>; +- status = "disabled"; +- }; +- +- sdhci: mmc@fe2e0000 { +- compatible = "rockchip,rk3588-dwcmshc"; +- reg = <0x0 0xfe2e0000 0x0 0x10000>; +- interrupts = ; +- assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; +- assigned-clock-rates = <200000000>, <24000000>, <200000000>; +- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, +- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, +- <&cru TMCLK_EMMC>; +- clock-names = "core", "bus", "axi", "block", "timer"; +- max-frequency = <200000000>; +- pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, +- <&emmc_cmd>, <&emmc_data_strobe>; +- pinctrl-names = "default"; +- resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, +- <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, +- <&cru SRST_T_EMMC>; +- reset-names = "core", "bus", "axi", "block", "timer"; +- status = "disabled"; +- }; +- +- i2s0_8ch: i2s@fe470000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfe470000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; +- dmas = <&dmac0 0>, <&dmac0 1>; +- dma-names = "tx", "rx"; +- power-domains = <&power RK3588_PD_AUDIO>; +- resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; +- reset-names = "tx-m", "rx-m"; +- rockchip,trcm-sync-tx-only; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_lrck +- &i2s0_sclk +- &i2s0_sdi0 +- &i2s0_sdi1 +- &i2s0_sdi2 +- &i2s0_sdi3 +- &i2s0_sdo0 +- &i2s0_sdo1 +- &i2s0_sdo2 +- &i2s0_sdo3>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s1_8ch: i2s@fe480000 { +- compatible = "rockchip,rk3588-i2s-tdm"; +- reg = <0x0 0xfe480000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; +- clock-names = "mclk_tx", "mclk_rx", "hclk"; +- dmas = <&dmac0 2>, <&dmac0 3>; +- dma-names = "tx", "rx"; +- resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; +- reset-names = "tx-m", "rx-m"; +- rockchip,trcm-sync-tx-only; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s1m0_lrck +- &i2s1m0_sclk +- &i2s1m0_sdi0 +- &i2s1m0_sdi1 +- &i2s1m0_sdi2 +- &i2s1m0_sdi3 +- &i2s1m0_sdo0 +- &i2s1m0_sdo1 +- &i2s1m0_sdo2 +- &i2s1m0_sdo3>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s2_2ch: i2s@fe490000 { +- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xfe490000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; +- clock-names = "i2s_clk", "i2s_hclk"; +- assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac1 0>, <&dmac1 1>; +- dma-names = "tx", "rx"; +- power-domains = <&power RK3588_PD_AUDIO>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s2m1_lrck +- &i2s2m1_sclk +- &i2s2m1_sdi +- &i2s2m1_sdo>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- i2s3_2ch: i2s@fe4a0000 { +- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; +- reg = <0x0 0xfe4a0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; +- clock-names = "i2s_clk", "i2s_hclk"; +- assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; +- assigned-clock-parents = <&cru PLL_AUPLL>; +- dmas = <&dmac1 2>, <&dmac1 3>; +- dma-names = "tx", "rx"; +- power-domains = <&power RK3588_PD_AUDIO>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s3_lrck +- &i2s3_sclk +- &i2s3_sdi +- &i2s3_sdo>; +- #sound-dai-cells = <0>; +- status = "disabled"; +- }; +- +- gic: interrupt-controller@fe600000 { +- compatible = "arm,gic-v3"; +- reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ +- <0x0 0xfe680000 0 0x100000>; /* GICR */ +- interrupts = ; +- interrupt-controller; +- mbi-alias = <0x0 0xfe610000>; +- mbi-ranges = <424 56>; +- msi-controller; +- ranges; +- #address-cells = <2>; +- #interrupt-cells = <4>; +- #size-cells = <2>; +- +- its0: msi-controller@fe640000 { +- compatible = "arm,gic-v3-its"; +- reg = <0x0 0xfe640000 0x0 0x20000>; +- msi-controller; +- #msi-cells = <1>; +- }; +- +- its1: msi-controller@fe660000 { +- compatible = "arm,gic-v3-its"; +- reg = <0x0 0xfe660000 0x0 0x20000>; +- msi-controller; +- #msi-cells = <1>; +- }; +- +- ppi-partitions { +- ppi_partition0: interrupt-partition-0 { +- affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; +- }; +- +- ppi_partition1: interrupt-partition-1 { +- affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; +- }; +- }; +- }; +- +- dmac0: dma-controller@fea10000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xfea10000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC0>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- dmac1: dma-controller@fea30000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xfea30000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC1>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- i2c1: i2c@fea90000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfea90000 0x0 0x1000>; +- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-0 = <&i2c1m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@feaa0000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfeaa0000 0x0 0x1000>; +- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-0 = <&i2c2m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c3: i2c@feab0000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfeab0000 0x0 0x1000>; +- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-0 = <&i2c3m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@feac0000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfeac0000 0x0 0x1000>; +- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-0 = <&i2c4m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@fead0000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfead0000 0x0 0x1000>; +- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-0 = <&i2c5m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- timer0: timer@feae0000 { +- compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; +- reg = <0x0 0xfeae0000 0x0 0x20>; +- interrupts = ; +- clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; +- clock-names = "pclk", "timer"; +- }; +- +- wdt: watchdog@feaf0000 { +- compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; +- reg = <0x0 0xfeaf0000 0x0 0x100>; +- clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; +- clock-names = "tclk", "pclk"; +- interrupts = ; +- }; +- +- spi0: spi@feb00000 { +- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xfeb00000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac0 14>, <&dmac0 15>; +- dma-names = "tx", "rx"; +- num-cs = <2>; +- pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi1: spi@feb10000 { +- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xfeb10000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac0 16>, <&dmac0 17>; +- dma-names = "tx", "rx"; +- num-cs = <2>; +- pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi2: spi@feb20000 { +- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xfeb20000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac1 15>, <&dmac1 16>; +- dma-names = "tx", "rx"; +- num-cs = <2>; +- pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi3: spi@feb30000 { +- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xfeb30000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac1 17>, <&dmac1 18>; +- dma-names = "tx", "rx"; +- num-cs = <2>; +- pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- uart1: serial@feb40000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfeb40000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 8>, <&dmac0 9>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart1m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart2: serial@feb50000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfeb50000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 10>, <&dmac0 11>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart2m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart3: serial@feb60000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfeb60000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac0 12>, <&dmac0 13>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart3m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart4: serial@feb70000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfeb70000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac1 9>, <&dmac1 10>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart4m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart5: serial@feb80000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfeb80000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac1 11>, <&dmac1 12>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart5m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart6: serial@feb90000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfeb90000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac1 13>, <&dmac1 14>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart6m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart7: serial@feba0000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfeba0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac2 7>, <&dmac2 8>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart7m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart8: serial@febb0000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfebb0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac2 9>, <&dmac2 10>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart8m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart9: serial@febc0000 { +- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xfebc0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; +- clock-names = "baudclk", "apb_pclk"; +- dmas = <&dmac2 11>, <&dmac2 12>; +- dma-names = "tx", "rx"; +- pinctrl-0 = <&uart9m1_xfer>; +- pinctrl-names = "default"; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- pwm4: pwm@febd0000 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebd0000 0x0 0x10>; +- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm4m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm5: pwm@febd0010 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebd0010 0x0 0x10>; +- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm5m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm6: pwm@febd0020 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebd0020 0x0 0x10>; +- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm6m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm7: pwm@febd0030 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebd0030 0x0 0x10>; +- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm7m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm8: pwm@febe0000 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebe0000 0x0 0x10>; +- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm8m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm9: pwm@febe0010 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebe0010 0x0 0x10>; +- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm9m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm10: pwm@febe0020 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebe0020 0x0 0x10>; +- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm10m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm11: pwm@febe0030 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebe0030 0x0 0x10>; +- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm11m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm12: pwm@febf0000 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebf0000 0x0 0x10>; +- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm12m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm13: pwm@febf0010 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebf0010 0x0 0x10>; +- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm13m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm14: pwm@febf0020 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebf0020 0x0 0x10>; +- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm14m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm15: pwm@febf0030 { +- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; +- reg = <0x0 0xfebf0030 0x0 0x10>; +- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; +- clock-names = "pwm", "pclk"; +- pinctrl-0 = <&pwm15m0_pins>; +- pinctrl-names = "default"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- tsadc: tsadc@fec00000 { +- compatible = "rockchip,rk3588-tsadc"; +- reg = <0x0 0xfec00000 0x0 0x400>; +- interrupts = ; +- clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; +- clock-names = "tsadc", "apb_pclk"; +- assigned-clocks = <&cru CLK_TSADC>; +- assigned-clock-rates = <2000000>; +- resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; +- reset-names = "tsadc-apb", "tsadc"; +- rockchip,hw-tshut-temp = <120000>; +- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ +- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ +- pinctrl-0 = <&tsadc_gpio_func>; +- pinctrl-1 = <&tsadc_shut>; +- pinctrl-names = "gpio", "otpout"; +- #thermal-sensor-cells = <1>; +- status = "disabled"; +- }; +- +- saradc: adc@fec10000 { +- compatible = "rockchip,rk3588-saradc"; +- reg = <0x0 0xfec10000 0x0 0x10000>; +- interrupts = ; +- #io-channel-cells = <1>; +- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; +- clock-names = "saradc", "apb_pclk"; +- resets = <&cru SRST_P_SARADC>; +- reset-names = "saradc-apb"; +- status = "disabled"; +- }; +- +- i2c6: i2c@fec80000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfec80000 0x0 0x1000>; +- clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-0 = <&i2c6m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c7: i2c@fec90000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfec90000 0x0 0x1000>; +- clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-0 = <&i2c7m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c8: i2c@feca0000 { +- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; +- reg = <0x0 0xfeca0000 0x0 0x1000>; +- clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; +- clock-names = "i2c", "pclk"; +- interrupts = ; +- pinctrl-0 = <&i2c8m0_xfer>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- spi4: spi@fecb0000 { +- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; +- reg = <0x0 0xfecb0000 0x0 0x1000>; +- interrupts = ; +- clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; +- clock-names = "spiclk", "apb_pclk"; +- dmas = <&dmac2 13>, <&dmac2 14>; +- dma-names = "tx", "rx"; +- num-cs = <2>; +- pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; +- pinctrl-names = "default"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- otp: efuse@fecc0000 { +- compatible = "rockchip,rk3588-otp"; +- reg = <0x0 0xfecc0000 0x0 0x400>; +- clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, +- <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; +- clock-names = "otp", "apb_pclk", "phy", "arb"; +- resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, +- <&cru SRST_OTPC_ARB>; +- reset-names = "otp", "apb", "arb"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpu_code: cpu-code@2 { +- reg = <0x02 0x2>; +- }; +- +- otp_id: id@7 { +- reg = <0x07 0x10>; +- }; +- +- cpub0_leakage: cpu-leakage@17 { +- reg = <0x17 0x1>; +- }; +- +- cpub1_leakage: cpu-leakage@18 { +- reg = <0x18 0x1>; +- }; +- +- cpul_leakage: cpu-leakage@19 { +- reg = <0x19 0x1>; +- }; +- +- log_leakage: log-leakage@1a { +- reg = <0x1a 0x1>; +- }; +- +- gpu_leakage: gpu-leakage@1b { +- reg = <0x1b 0x1>; +- }; +- +- otp_cpu_version: cpu-version@1c { +- reg = <0x1c 0x1>; +- bits = <3 3>; +- }; +- +- npu_leakage: npu-leakage@28 { +- reg = <0x28 0x1>; +- }; +- +- codec_leakage: codec-leakage@29 { +- reg = <0x29 0x1>; +- }; +- }; +- +- dmac2: dma-controller@fed10000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x0 0xfed10000 0x0 0x4000>; +- interrupts = , +- ; +- arm,pl330-periph-burst; +- clocks = <&cru ACLK_DMAC2>; +- clock-names = "apb_pclk"; +- #dma-cells = <1>; +- }; +- +- hdptxphy_hdmi0: phy@fed60000 { +- compatible = "rockchip,rk3588-hdptx-phy"; +- reg = <0x0 0xfed60000 0x0 0x2000>; +- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; +- clock-names = "ref", "apb"; +- #phy-cells = <0>; +- resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, +- <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, +- <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, +- <&cru SRST_HDPTX0_LCPLL>; +- reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", +- "lcpll"; +- rockchip,grf = <&hdptxphy0_grf>; +- status = "disabled"; +- }; +- +- usbdp_phy0: phy@fed80000 { +- compatible = "rockchip,rk3588-usbdp-phy"; +- reg = <0x0 0xfed80000 0x0 0x10000>; +- #phy-cells = <1>; +- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, +- <&cru CLK_USBDP_PHY0_IMMORTAL>, +- <&cru PCLK_USBDPPHY0>, +- <&u2phy0>; +- clock-names = "refclk", "immortal", "pclk", "utmi"; +- resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, +- <&cru SRST_USBDP_COMBO_PHY0_CMN>, +- <&cru SRST_USBDP_COMBO_PHY0_LANE>, +- <&cru SRST_USBDP_COMBO_PHY0_PCS>, +- <&cru SRST_P_USBDPPHY0>; +- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; +- rockchip,u2phy-grf = <&usb2phy0_grf>; +- rockchip,usb-grf = <&usb_grf>; +- rockchip,usbdpphy-grf = <&usbdpphy0_grf>; +- rockchip,vo-grf = <&vo0_grf>; +- status = "disabled"; +- }; +- +- combphy0_ps: phy@fee00000 { +- compatible = "rockchip,rk3588-naneng-combphy"; +- reg = <0x0 0xfee00000 0x0 0x100>; +- clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, +- <&cru PCLK_PHP_ROOT>; +- clock-names = "ref", "apb", "pipe"; +- assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; +- assigned-clock-rates = <100000000>; +- #phy-cells = <1>; +- resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; +- reset-names = "phy", "apb"; +- rockchip,pipe-grf = <&php_grf>; +- rockchip,pipe-phy-grf = <&pipe_phy0_grf>; +- status = "disabled"; +- }; +- +- combphy2_psu: phy@fee20000 { +- compatible = "rockchip,rk3588-naneng-combphy"; +- reg = <0x0 0xfee20000 0x0 0x100>; +- clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, +- <&cru PCLK_PHP_ROOT>; +- clock-names = "ref", "apb", "pipe"; +- assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; +- assigned-clock-rates = <100000000>; +- #phy-cells = <1>; +- resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; +- reset-names = "phy", "apb"; +- rockchip,pipe-grf = <&php_grf>; +- rockchip,pipe-phy-grf = <&pipe_phy2_grf>; +- status = "disabled"; +- }; +- +- system_sram2: sram@ff001000 { +- compatible = "mmio-sram"; +- reg = <0x0 0xff001000 0x0 0xef000>; +- ranges = <0x0 0x0 0xff001000 0xef000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- pinctrl: pinctrl { +- compatible = "rockchip,rk3588-pinctrl"; +- ranges; +- rockchip,grf = <&ioc>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- gpio0: gpio@fd8a0000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfd8a0000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; +- gpio-controller; +- gpio-ranges = <&pinctrl 0 0 32>; +- interrupt-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +- +- gpio1: gpio@fec20000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfec20000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; +- gpio-controller; +- gpio-ranges = <&pinctrl 0 32 32>; +- interrupt-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +- +- gpio2: gpio@fec30000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfec30000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; +- gpio-controller; +- gpio-ranges = <&pinctrl 0 64 32>; +- interrupt-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +- +- gpio3: gpio@fec40000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfec40000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; +- gpio-controller; +- gpio-ranges = <&pinctrl 0 96 32>; +- interrupt-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +- +- gpio4: gpio@fec50000 { +- compatible = "rockchip,gpio-bank"; +- reg = <0x0 0xfec50000 0x0 0x100>; +- interrupts = ; +- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; +- gpio-controller; +- gpio-ranges = <&pinctrl 0 128 32>; +- interrupt-controller; +- #gpio-cells = <2>; +- #interrupt-cells = <2>; +- }; +- }; +-}; +- +-#include "rk3588s-pinctrl.dtsi" ++#include "rk3588-base.dtsi" +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi +@@ -0,0 +1,3447 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include "rockchip-pinconf.dtsi" ++ ++/* ++ * This file is auto generated by pin2dts tool, please keep these code ++ * by adding changes at end of this file. ++ */ ++&pinctrl { ++ auddsm { ++ /omit-if-no-ref/ ++ auddsm_pins: auddsm-pins { ++ rockchip,pins = ++ /* auddsm_ln */ ++ <3 RK_PA1 4 &pcfg_pull_none>, ++ /* auddsm_lp */ ++ <3 RK_PA2 4 &pcfg_pull_none>, ++ /* auddsm_rn */ ++ <3 RK_PA3 4 &pcfg_pull_none>, ++ /* auddsm_rp */ ++ <3 RK_PA4 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ bt1120 { ++ /omit-if-no-ref/ ++ bt1120_pins: bt1120-pins { ++ rockchip,pins = ++ /* bt1120_clkout */ ++ <4 RK_PB0 2 &pcfg_pull_none>, ++ /* bt1120_d0 */ ++ <4 RK_PA0 2 &pcfg_pull_none>, ++ /* bt1120_d1 */ ++ <4 RK_PA1 2 &pcfg_pull_none>, ++ /* bt1120_d2 */ ++ <4 RK_PA2 2 &pcfg_pull_none>, ++ /* bt1120_d3 */ ++ <4 RK_PA3 2 &pcfg_pull_none>, ++ /* bt1120_d4 */ ++ <4 RK_PA4 2 &pcfg_pull_none>, ++ /* bt1120_d5 */ ++ <4 RK_PA5 2 &pcfg_pull_none>, ++ /* bt1120_d6 */ ++ <4 RK_PA6 2 &pcfg_pull_none>, ++ /* bt1120_d7 */ ++ <4 RK_PA7 2 &pcfg_pull_none>, ++ /* bt1120_d8 */ ++ <4 RK_PB2 2 &pcfg_pull_none>, ++ /* bt1120_d9 */ ++ <4 RK_PB3 2 &pcfg_pull_none>, ++ /* bt1120_d10 */ ++ <4 RK_PB4 2 &pcfg_pull_none>, ++ /* bt1120_d11 */ ++ <4 RK_PB5 2 &pcfg_pull_none>, ++ /* bt1120_d12 */ ++ <4 RK_PB6 2 &pcfg_pull_none>, ++ /* bt1120_d13 */ ++ <4 RK_PB7 2 &pcfg_pull_none>, ++ /* bt1120_d14 */ ++ <4 RK_PC0 2 &pcfg_pull_none>, ++ /* bt1120_d15 */ ++ <4 RK_PC1 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ can0 { ++ /omit-if-no-ref/ ++ can0m0_pins: can0m0-pins { ++ rockchip,pins = ++ /* can0_rx_m0 */ ++ <0 RK_PC0 11 &pcfg_pull_none>, ++ /* can0_tx_m0 */ ++ <0 RK_PB7 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can0m1_pins: can0m1-pins { ++ rockchip,pins = ++ /* can0_rx_m1 */ ++ <4 RK_PD5 9 &pcfg_pull_none>, ++ /* can0_tx_m1 */ ++ <4 RK_PD4 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ can1 { ++ /omit-if-no-ref/ ++ can1m0_pins: can1m0-pins { ++ rockchip,pins = ++ /* can1_rx_m0 */ ++ <3 RK_PB5 9 &pcfg_pull_none>, ++ /* can1_tx_m0 */ ++ <3 RK_PB6 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can1m1_pins: can1m1-pins { ++ rockchip,pins = ++ /* can1_rx_m1 */ ++ <4 RK_PB2 12 &pcfg_pull_none>, ++ /* can1_tx_m1 */ ++ <4 RK_PB3 12 &pcfg_pull_none>; ++ }; ++ }; ++ ++ can2 { ++ /omit-if-no-ref/ ++ can2m0_pins: can2m0-pins { ++ rockchip,pins = ++ /* can2_rx_m0 */ ++ <3 RK_PC4 9 &pcfg_pull_none>, ++ /* can2_tx_m0 */ ++ <3 RK_PC5 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can2m1_pins: can2m1-pins { ++ rockchip,pins = ++ /* can2_rx_m1 */ ++ <0 RK_PD4 10 &pcfg_pull_none>, ++ /* can2_tx_m1 */ ++ <0 RK_PD5 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cif { ++ /omit-if-no-ref/ ++ cif_clk: cif-clk { ++ rockchip,pins = ++ /* cif_clkout */ ++ <4 RK_PB4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cif_dvp_clk: cif-dvp-clk { ++ rockchip,pins = ++ /* cif_clkin */ ++ <4 RK_PB0 1 &pcfg_pull_none>, ++ /* cif_href */ ++ <4 RK_PB2 1 &pcfg_pull_none>, ++ /* cif_vsync */ ++ <4 RK_PB3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cif_dvp_bus16: cif-dvp-bus16 { ++ rockchip,pins = ++ /* cif_d8 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* cif_d9 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* cif_d10 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* cif_d11 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* cif_d12 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* cif_d13 */ ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ /* cif_d14 */ ++ <3 RK_PD2 1 &pcfg_pull_none>, ++ /* cif_d15 */ ++ <3 RK_PD3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cif_dvp_bus8: cif-dvp-bus8 { ++ rockchip,pins = ++ /* cif_d0 */ ++ <4 RK_PA0 1 &pcfg_pull_none>, ++ /* cif_d1 */ ++ <4 RK_PA1 1 &pcfg_pull_none>, ++ /* cif_d2 */ ++ <4 RK_PA2 1 &pcfg_pull_none>, ++ /* cif_d3 */ ++ <4 RK_PA3 1 &pcfg_pull_none>, ++ /* cif_d4 */ ++ <4 RK_PA4 1 &pcfg_pull_none>, ++ /* cif_d5 */ ++ <4 RK_PA5 1 &pcfg_pull_none>, ++ /* cif_d6 */ ++ <4 RK_PA6 1 &pcfg_pull_none>, ++ /* cif_d7 */ ++ <4 RK_PA7 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ clk32k { ++ /omit-if-no-ref/ ++ clk32k_in: clk32k-in { ++ rockchip,pins = ++ /* clk32k_in */ ++ <0 RK_PB2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ clk32k_out0: clk32k-out0 { ++ rockchip,pins = ++ /* clk32k_out0 */ ++ <0 RK_PB2 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cpu { ++ /omit-if-no-ref/ ++ cpu_pins: cpu-pins { ++ rockchip,pins = ++ /* cpu_big0_avs */ ++ <0 RK_PD1 2 &pcfg_pull_none>, ++ /* cpu_big1_avs */ ++ <0 RK_PD5 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ddrphych0 { ++ /omit-if-no-ref/ ++ ddrphych0_pins: ddrphych0-pins { ++ rockchip,pins = ++ /* ddrphych0_dtb0 */ ++ <4 RK_PA0 7 &pcfg_pull_none>, ++ /* ddrphych0_dtb1 */ ++ <4 RK_PA1 7 &pcfg_pull_none>, ++ /* ddrphych0_dtb2 */ ++ <4 RK_PA2 7 &pcfg_pull_none>, ++ /* ddrphych0_dtb3 */ ++ <4 RK_PA3 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ddrphych1 { ++ /omit-if-no-ref/ ++ ddrphych1_pins: ddrphych1-pins { ++ rockchip,pins = ++ /* ddrphych1_dtb0 */ ++ <4 RK_PA4 7 &pcfg_pull_none>, ++ /* ddrphych1_dtb1 */ ++ <4 RK_PA5 7 &pcfg_pull_none>, ++ /* ddrphych1_dtb2 */ ++ <4 RK_PA6 7 &pcfg_pull_none>, ++ /* ddrphych1_dtb3 */ ++ <4 RK_PA7 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ddrphych2 { ++ /omit-if-no-ref/ ++ ddrphych2_pins: ddrphych2-pins { ++ rockchip,pins = ++ /* ddrphych2_dtb0 */ ++ <4 RK_PB0 7 &pcfg_pull_none>, ++ /* ddrphych2_dtb1 */ ++ <4 RK_PB1 7 &pcfg_pull_none>, ++ /* ddrphych2_dtb2 */ ++ <4 RK_PB2 7 &pcfg_pull_none>, ++ /* ddrphych2_dtb3 */ ++ <4 RK_PB3 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ddrphych3 { ++ /omit-if-no-ref/ ++ ddrphych3_pins: ddrphych3-pins { ++ rockchip,pins = ++ /* ddrphych3_dtb0 */ ++ <4 RK_PB4 7 &pcfg_pull_none>, ++ /* ddrphych3_dtb1 */ ++ <4 RK_PB5 7 &pcfg_pull_none>, ++ /* ddrphych3_dtb2 */ ++ <4 RK_PB6 7 &pcfg_pull_none>, ++ /* ddrphych3_dtb3 */ ++ <4 RK_PB7 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dp0 { ++ /omit-if-no-ref/ ++ dp0m0_pins: dp0m0-pins { ++ rockchip,pins = ++ /* dp0_hpdin_m0 */ ++ <4 RK_PB4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dp0m1_pins: dp0m1-pins { ++ rockchip,pins = ++ /* dp0_hpdin_m1 */ ++ <0 RK_PC4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dp0m2_pins: dp0m2-pins { ++ rockchip,pins = ++ /* dp0_hpdin_m2 */ ++ <1 RK_PA0 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dp1 { ++ /omit-if-no-ref/ ++ dp1m0_pins: dp1m0-pins { ++ rockchip,pins = ++ /* dp1_hpdin_m0 */ ++ <3 RK_PD5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dp1m1_pins: dp1m1-pins { ++ rockchip,pins = ++ /* dp1_hpdin_m1 */ ++ <0 RK_PC5 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dp1m2_pins: dp1m2-pins { ++ rockchip,pins = ++ /* dp1_hpdin_m2 */ ++ <1 RK_PA1 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ emmc { ++ /omit-if-no-ref/ ++ emmc_rstnout: emmc-rstnout { ++ rockchip,pins = ++ /* emmc_rstn */ ++ <2 RK_PA3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_bus8: emmc-bus8 { ++ rockchip,pins = ++ /* emmc_d0 */ ++ <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d1 */ ++ <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d2 */ ++ <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d3 */ ++ <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d4 */ ++ <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d5 */ ++ <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d6 */ ++ <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d7 */ ++ <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_clk: emmc-clk { ++ rockchip,pins = ++ /* emmc_clkout */ ++ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_cmd: emmc-cmd { ++ rockchip,pins = ++ /* emmc_cmd */ ++ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_data_strobe: emmc-data-strobe { ++ rockchip,pins = ++ /* emmc_data_strobe */ ++ <2 RK_PA2 1 &pcfg_pull_down>; ++ }; ++ }; ++ ++ eth1 { ++ /omit-if-no-ref/ ++ eth1_pins: eth1-pins { ++ rockchip,pins = ++ /* eth1_refclko_25m */ ++ <3 RK_PA6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ fspi { ++ /omit-if-no-ref/ ++ fspim0_pins: fspim0-pins { ++ rockchip,pins = ++ /* fspi_clk_m0 */ ++ <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_cs0n_m0 */ ++ <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d0_m0 */ ++ <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d1_m0 */ ++ <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d2_m0 */ ++ <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d3_m0 */ ++ <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspim0_cs1: fspim0-cs1 { ++ rockchip,pins = ++ /* fspi_cs1n_m0 */ ++ <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspim2_pins: fspim2-pins { ++ rockchip,pins = ++ /* fspi_clk_m2 */ ++ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, ++ /* fspi_cs0n_m2 */ ++ <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d0_m2 */ ++ <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d1_m2 */ ++ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d2_m2 */ ++ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d3_m2 */ ++ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspim2_cs1: fspim2-cs1 { ++ rockchip,pins = ++ /* fspi_cs1n_m2 */ ++ <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ }; ++ ++ gmac1 { ++ /omit-if-no-ref/ ++ gmac1_miim: gmac1-miim { ++ rockchip,pins = ++ /* gmac1_mdc */ ++ <3 RK_PC2 1 &pcfg_pull_none>, ++ /* gmac1_mdio */ ++ <3 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_clkinout: gmac1-clkinout { ++ rockchip,pins = ++ /* gmac1_mclkinout */ ++ <3 RK_PB6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_rx_bus2: gmac1-rx-bus2 { ++ rockchip,pins = ++ /* gmac1_rxd0 */ ++ <3 RK_PA7 1 &pcfg_pull_none>, ++ /* gmac1_rxd1 */ ++ <3 RK_PB0 1 &pcfg_pull_none>, ++ /* gmac1_rxdv_crs */ ++ <3 RK_PB1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_tx_bus2: gmac1-tx-bus2 { ++ rockchip,pins = ++ /* gmac1_txd0 */ ++ <3 RK_PB3 1 &pcfg_pull_none>, ++ /* gmac1_txd1 */ ++ <3 RK_PB4 1 &pcfg_pull_none>, ++ /* gmac1_txen */ ++ <3 RK_PB5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_rgmii_clk: gmac1-rgmii-clk { ++ rockchip,pins = ++ /* gmac1_rxclk */ ++ <3 RK_PA5 1 &pcfg_pull_none>, ++ /* gmac1_txclk */ ++ <3 RK_PA4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_rgmii_bus: gmac1-rgmii-bus { ++ rockchip,pins = ++ /* gmac1_rxd2 */ ++ <3 RK_PA2 1 &pcfg_pull_none>, ++ /* gmac1_rxd3 */ ++ <3 RK_PA3 1 &pcfg_pull_none>, ++ /* gmac1_txd2 */ ++ <3 RK_PA0 1 &pcfg_pull_none>, ++ /* gmac1_txd3 */ ++ <3 RK_PA1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_ppsclk: gmac1-ppsclk { ++ rockchip,pins = ++ /* gmac1_ppsclk */ ++ <3 RK_PC1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_ppstrig: gmac1-ppstrig { ++ rockchip,pins = ++ /* gmac1_ppstrig */ ++ <3 RK_PC0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { ++ rockchip,pins = ++ /* gmac1_ptp_ref_clk */ ++ <3 RK_PB7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_txer: gmac1-txer { ++ rockchip,pins = ++ /* gmac1_txer */ ++ <3 RK_PB2 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ gpu { ++ /omit-if-no-ref/ ++ gpu_pins: gpu-pins { ++ rockchip,pins = ++ /* gpu_avs */ ++ <0 RK_PC5 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ hdmi { ++ /omit-if-no-ref/ ++ hdmim0_rx_cec: hdmim0-rx-cec { ++ rockchip,pins = ++ /* hdmim0_rx_cec */ ++ <4 RK_PB5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_rx_hpdin: hdmim0-rx-hpdin { ++ rockchip,pins = ++ /* hdmim0_rx_hpdin */ ++ <4 RK_PB6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_rx_scl: hdmim0-rx-scl { ++ rockchip,pins = ++ /* hdmim0_rx_scl */ ++ <0 RK_PD2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_rx_sda: hdmim0-rx-sda { ++ rockchip,pins = ++ /* hdmim0_rx_sda */ ++ <0 RK_PD1 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx0_cec: hdmim0-tx0-cec { ++ rockchip,pins = ++ /* hdmim0_tx0_cec */ ++ <4 RK_PC1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx0_hpd: hdmim0-tx0-hpd { ++ rockchip,pins = ++ /* hdmim0_tx0_hpd */ ++ <1 RK_PA5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx0_scl: hdmim0-tx0-scl { ++ rockchip,pins = ++ /* hdmim0_tx0_scl */ ++ <4 RK_PB7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx0_sda: hdmim0-tx0-sda { ++ rockchip,pins = ++ /* hdmim0_tx0_sda */ ++ <4 RK_PC0 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx1_hpd: hdmim0-tx1-hpd { ++ rockchip,pins = ++ /* hdmim0_tx1_hpd */ ++ <1 RK_PA6 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ hdmim1_rx_cec: hdmim1-rx-cec { ++ rockchip,pins = ++ /* hdmim1_rx_cec */ ++ <3 RK_PD1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_rx_hpdin: hdmim1-rx-hpdin { ++ rockchip,pins = ++ /* hdmim1_rx_hpdin */ ++ <3 RK_PD4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_rx_scl: hdmim1-rx-scl { ++ rockchip,pins = ++ /* hdmim1_rx_scl */ ++ <3 RK_PD2 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_rx_sda: hdmim1-rx-sda { ++ rockchip,pins = ++ /* hdmim1_rx_sda */ ++ <3 RK_PD3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx0_cec: hdmim1-tx0-cec { ++ rockchip,pins = ++ /* hdmim1_tx0_cec */ ++ <0 RK_PD1 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx0_hpd: hdmim1-tx0-hpd { ++ rockchip,pins = ++ /* hdmim1_tx0_hpd */ ++ <3 RK_PD4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx0_scl: hdmim1-tx0-scl { ++ rockchip,pins = ++ /* hdmim1_tx0_scl */ ++ <0 RK_PD5 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx0_sda: hdmim1-tx0-sda { ++ rockchip,pins = ++ /* hdmim1_tx0_sda */ ++ <0 RK_PD4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx1_cec: hdmim1-tx1-cec { ++ rockchip,pins = ++ /* hdmim1_tx1_cec */ ++ <0 RK_PD2 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx1_hpd: hdmim1-tx1-hpd { ++ rockchip,pins = ++ /* hdmim1_tx1_hpd */ ++ <3 RK_PB7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx1_scl: hdmim1-tx1-scl { ++ rockchip,pins = ++ /* hdmim1_tx1_scl */ ++ <3 RK_PC6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx1_sda: hdmim1-tx1-sda { ++ rockchip,pins = ++ /* hdmim1_tx1_sda */ ++ <3 RK_PC5 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ hdmim2_rx_cec: hdmim2-rx-cec { ++ rockchip,pins = ++ /* hdmim2_rx_cec */ ++ <1 RK_PB7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_rx_hpdin: hdmim2-rx-hpdin { ++ rockchip,pins = ++ /* hdmim2_rx_hpdin */ ++ <1 RK_PB6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_rx_scl: hdmim2-rx-scl { ++ rockchip,pins = ++ /* hdmim2_rx_scl */ ++ <1 RK_PD6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_rx_sda: hdmim2-rx-sda { ++ rockchip,pins = ++ /* hdmim2_rx_sda */ ++ <1 RK_PD7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx0_scl: hdmim2-tx0-scl { ++ rockchip,pins = ++ /* hdmim2_tx0_scl */ ++ <3 RK_PC7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx0_sda: hdmim2-tx0-sda { ++ rockchip,pins = ++ /* hdmim2_tx0_sda */ ++ <3 RK_PD0 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx1_cec: hdmim2-tx1-cec { ++ rockchip,pins = ++ /* hdmim2_tx1_cec */ ++ <3 RK_PC4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx1_scl: hdmim2-tx1-scl { ++ rockchip,pins = ++ /* hdmim2_tx1_scl */ ++ <1 RK_PA4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx1_sda: hdmim2-tx1-sda { ++ rockchip,pins = ++ /* hdmim2_tx1_sda */ ++ <1 RK_PA3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug0: hdmi-debug0 { ++ rockchip,pins = ++ /* hdmi_debug0 */ ++ <1 RK_PA7 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug1: hdmi-debug1 { ++ rockchip,pins = ++ /* hdmi_debug1 */ ++ <1 RK_PB0 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug2: hdmi-debug2 { ++ rockchip,pins = ++ /* hdmi_debug2 */ ++ <1 RK_PB1 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug3: hdmi-debug3 { ++ rockchip,pins = ++ /* hdmi_debug3 */ ++ <1 RK_PB2 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug4: hdmi-debug4 { ++ rockchip,pins = ++ /* hdmi_debug4 */ ++ <1 RK_PB3 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug5: hdmi-debug5 { ++ rockchip,pins = ++ /* hdmi_debug5 */ ++ <1 RK_PB4 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug6: hdmi-debug6 { ++ rockchip,pins = ++ /* hdmi_debug6 */ ++ <1 RK_PA0 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2c0 { ++ /omit-if-no-ref/ ++ i2c0m0_xfer: i2c0m0-xfer { ++ rockchip,pins = ++ /* i2c0_scl_m0 */ ++ <0 RK_PB3 2 &pcfg_pull_none_smt>, ++ /* i2c0_sda_m0 */ ++ <0 RK_PA6 2 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c0m2_xfer: i2c0m2-xfer { ++ rockchip,pins = ++ /* i2c0_scl_m2 */ ++ <0 RK_PD1 3 &pcfg_pull_none_smt>, ++ /* i2c0_sda_m2 */ ++ <0 RK_PD2 3 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c1 { ++ /omit-if-no-ref/ ++ i2c1m0_xfer: i2c1m0-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m0 */ ++ <0 RK_PB5 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m0 */ ++ <0 RK_PB6 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m1_xfer: i2c1m1-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m1 */ ++ <0 RK_PB0 2 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m1 */ ++ <0 RK_PB1 2 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m2_xfer: i2c1m2-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m2 */ ++ <0 RK_PD4 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m2 */ ++ <0 RK_PD5 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m3_xfer: i2c1m3-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m3 */ ++ <2 RK_PD4 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m3 */ ++ <2 RK_PD5 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m4_xfer: i2c1m4-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m4 */ ++ <1 RK_PD2 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m4 */ ++ <1 RK_PD3 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c2 { ++ /omit-if-no-ref/ ++ i2c2m0_xfer: i2c2m0-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m0 */ ++ <0 RK_PB7 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m0 */ ++ <0 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m2_xfer: i2c2m2-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m2 */ ++ <2 RK_PA3 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m2 */ ++ <2 RK_PA2 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m3_xfer: i2c2m3-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m3 */ ++ <1 RK_PC5 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m3 */ ++ <1 RK_PC4 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m4_xfer: i2c2m4-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m4 */ ++ <1 RK_PA1 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m4 */ ++ <1 RK_PA0 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c3 { ++ /omit-if-no-ref/ ++ i2c3m0_xfer: i2c3m0-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m0 */ ++ <1 RK_PC1 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m0 */ ++ <1 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m1_xfer: i2c3m1-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m1 */ ++ <3 RK_PB7 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m1 */ ++ <3 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m2_xfer: i2c3m2-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m2 */ ++ <4 RK_PA4 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m2 */ ++ <4 RK_PA5 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m4_xfer: i2c3m4-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m4 */ ++ <4 RK_PD0 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m4 */ ++ <4 RK_PD1 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c4 { ++ /omit-if-no-ref/ ++ i2c4m0_xfer: i2c4m0-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m0 */ ++ <3 RK_PA6 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m0 */ ++ <3 RK_PA5 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m2_xfer: i2c4m2-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m2 */ ++ <0 RK_PC5 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m2 */ ++ <0 RK_PC4 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m3_xfer: i2c4m3-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m3 */ ++ <1 RK_PA3 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m3 */ ++ <1 RK_PA2 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m4_xfer: i2c4m4-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m4 */ ++ <1 RK_PC7 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m4 */ ++ <1 RK_PC6 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c5 { ++ /omit-if-no-ref/ ++ i2c5m0_xfer: i2c5m0-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m0 */ ++ <3 RK_PC7 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m0 */ ++ <3 RK_PD0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m1_xfer: i2c5m1-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m1 */ ++ <4 RK_PB6 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m1 */ ++ <4 RK_PB7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m2_xfer: i2c5m2-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m2 */ ++ <4 RK_PA6 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m2 */ ++ <4 RK_PA7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m3_xfer: i2c5m3-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m3 */ ++ <1 RK_PB6 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m3 */ ++ <1 RK_PB7 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c6 { ++ /omit-if-no-ref/ ++ i2c6m0_xfer: i2c6m0-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m0 */ ++ <0 RK_PD0 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m0 */ ++ <0 RK_PC7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m1_xfer: i2c6m1-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m1 */ ++ <1 RK_PC3 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m1 */ ++ <1 RK_PC2 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m3_xfer: i2c6m3-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m3 */ ++ <4 RK_PB1 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m3 */ ++ <4 RK_PB0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m4_xfer: i2c6m4-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m4 */ ++ <3 RK_PA1 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m4 */ ++ <3 RK_PA0 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c7 { ++ /omit-if-no-ref/ ++ i2c7m0_xfer: i2c7m0-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m0 */ ++ <1 RK_PD0 9 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m0 */ ++ <1 RK_PD1 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c7m2_xfer: i2c7m2-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m2 */ ++ <3 RK_PD2 9 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m2 */ ++ <3 RK_PD3 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c7m3_xfer: i2c7m3-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m3 */ ++ <4 RK_PB2 9 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m3 */ ++ <4 RK_PB3 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c8 { ++ /omit-if-no-ref/ ++ i2c8m0_xfer: i2c8m0-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m0 */ ++ <4 RK_PD2 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m0 */ ++ <4 RK_PD3 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m2_xfer: i2c8m2-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m2 */ ++ <1 RK_PD6 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m2 */ ++ <1 RK_PD7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m3_xfer: i2c8m3-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m3 */ ++ <4 RK_PC0 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m3 */ ++ <4 RK_PC1 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m4_xfer: i2c8m4-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m4 */ ++ <3 RK_PC2 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m4 */ ++ <3 RK_PC3 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2s0 { ++ /omit-if-no-ref/ ++ i2s0_lrck: i2s0-lrck { ++ rockchip,pins = ++ /* i2s0_lrck */ ++ <1 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_mclk: i2s0-mclk { ++ rockchip,pins = ++ /* i2s0_mclk */ ++ <1 RK_PC2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sclk: i2s0-sclk { ++ rockchip,pins = ++ /* i2s0_sclk */ ++ <1 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdi0: i2s0-sdi0 { ++ rockchip,pins = ++ /* i2s0_sdi0 */ ++ <1 RK_PD4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdi1: i2s0-sdi1 { ++ rockchip,pins = ++ /* i2s0_sdi1 */ ++ <1 RK_PD3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdi2: i2s0-sdi2 { ++ rockchip,pins = ++ /* i2s0_sdi2 */ ++ <1 RK_PD2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdi3: i2s0-sdi3 { ++ rockchip,pins = ++ /* i2s0_sdi3 */ ++ <1 RK_PD1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdo0: i2s0-sdo0 { ++ rockchip,pins = ++ /* i2s0_sdo0 */ ++ <1 RK_PC7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdo1: i2s0-sdo1 { ++ rockchip,pins = ++ /* i2s0_sdo1 */ ++ <1 RK_PD0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdo2: i2s0-sdo2 { ++ rockchip,pins = ++ /* i2s0_sdo2 */ ++ <1 RK_PD1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdo3: i2s0-sdo3 { ++ rockchip,pins = ++ /* i2s0_sdo3 */ ++ <1 RK_PD2 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2s1 { ++ /omit-if-no-ref/ ++ i2s1m0_lrck: i2s1m0-lrck { ++ rockchip,pins = ++ /* i2s1m0_lrck */ ++ <4 RK_PA2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_mclk: i2s1m0-mclk { ++ rockchip,pins = ++ /* i2s1m0_mclk */ ++ <4 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sclk: i2s1m0-sclk { ++ rockchip,pins = ++ /* i2s1m0_sclk */ ++ <4 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdi0: i2s1m0-sdi0 { ++ rockchip,pins = ++ /* i2s1m0_sdi0 */ ++ <4 RK_PA5 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdi1: i2s1m0-sdi1 { ++ rockchip,pins = ++ /* i2s1m0_sdi1 */ ++ <4 RK_PA6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdi2: i2s1m0-sdi2 { ++ rockchip,pins = ++ /* i2s1m0_sdi2 */ ++ <4 RK_PA7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdi3: i2s1m0-sdi3 { ++ rockchip,pins = ++ /* i2s1m0_sdi3 */ ++ <4 RK_PB0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdo0: i2s1m0-sdo0 { ++ rockchip,pins = ++ /* i2s1m0_sdo0 */ ++ <4 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdo1: i2s1m0-sdo1 { ++ rockchip,pins = ++ /* i2s1m0_sdo1 */ ++ <4 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdo2: i2s1m0-sdo2 { ++ rockchip,pins = ++ /* i2s1m0_sdo2 */ ++ <4 RK_PB3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdo3: i2s1m0-sdo3 { ++ rockchip,pins = ++ /* i2s1m0_sdo3 */ ++ <4 RK_PB4 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ i2s1m1_lrck: i2s1m1-lrck { ++ rockchip,pins = ++ /* i2s1m1_lrck */ ++ <0 RK_PB7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_mclk: i2s1m1-mclk { ++ rockchip,pins = ++ /* i2s1m1_mclk */ ++ <0 RK_PB5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sclk: i2s1m1-sclk { ++ rockchip,pins = ++ /* i2s1m1_sclk */ ++ <0 RK_PB6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdi0: i2s1m1-sdi0 { ++ rockchip,pins = ++ /* i2s1m1_sdi0 */ ++ <0 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdi1: i2s1m1-sdi1 { ++ rockchip,pins = ++ /* i2s1m1_sdi1 */ ++ <0 RK_PC6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdi2: i2s1m1-sdi2 { ++ rockchip,pins = ++ /* i2s1m1_sdi2 */ ++ <0 RK_PC7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdi3: i2s1m1-sdi3 { ++ rockchip,pins = ++ /* i2s1m1_sdi3 */ ++ <0 RK_PD0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdo0: i2s1m1-sdo0 { ++ rockchip,pins = ++ /* i2s1m1_sdo0 */ ++ <0 RK_PD1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdo1: i2s1m1-sdo1 { ++ rockchip,pins = ++ /* i2s1m1_sdo1 */ ++ <0 RK_PD2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdo2: i2s1m1-sdo2 { ++ rockchip,pins = ++ /* i2s1m1_sdo2 */ ++ <0 RK_PD4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdo3: i2s1m1-sdo3 { ++ rockchip,pins = ++ /* i2s1m1_sdo3 */ ++ <0 RK_PD5 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2s2 { ++ /omit-if-no-ref/ ++ i2s2m0_lrck: i2s2m0-lrck { ++ rockchip,pins = ++ /* i2s2m0_lrck */ ++ <2 RK_PC0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_mclk: i2s2m0-mclk { ++ rockchip,pins = ++ /* i2s2m0_mclk */ ++ <2 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sclk: i2s2m0-sclk { ++ rockchip,pins = ++ /* i2s2m0_sclk */ ++ <2 RK_PB7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdi: i2s2m0-sdi { ++ rockchip,pins = ++ /* i2s2m0_sdi */ ++ <2 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdo: i2s2m0-sdo { ++ rockchip,pins = ++ /* i2s2m0_sdo */ ++ <4 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_lrck: i2s2m1-lrck { ++ rockchip,pins = ++ /* i2s2m1_lrck */ ++ <3 RK_PB6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_mclk: i2s2m1-mclk { ++ rockchip,pins = ++ /* i2s2m1_mclk */ ++ <3 RK_PB4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_sclk: i2s2m1-sclk { ++ rockchip,pins = ++ /* i2s2m1_sclk */ ++ <3 RK_PB5 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_sdi: i2s2m1-sdi { ++ rockchip,pins = ++ /* i2s2m1_sdi */ ++ <3 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_sdo: i2s2m1-sdo { ++ rockchip,pins = ++ /* i2s2m1_sdo */ ++ <3 RK_PB3 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2s3 { ++ /omit-if-no-ref/ ++ i2s3_lrck: i2s3-lrck { ++ rockchip,pins = ++ /* i2s3_lrck */ ++ <3 RK_PA2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s3_mclk: i2s3-mclk { ++ rockchip,pins = ++ /* i2s3_mclk */ ++ <3 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s3_sclk: i2s3-sclk { ++ rockchip,pins = ++ /* i2s3_sclk */ ++ <3 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s3_sdi: i2s3-sdi { ++ rockchip,pins = ++ /* i2s3_sdi */ ++ <3 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s3_sdo: i2s3-sdo { ++ rockchip,pins = ++ /* i2s3_sdo */ ++ <3 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ jtag { ++ /omit-if-no-ref/ ++ jtagm0_pins: jtagm0-pins { ++ rockchip,pins = ++ /* jtag_tck_m0 */ ++ <4 RK_PD2 5 &pcfg_pull_none>, ++ /* jtag_tms_m0 */ ++ <4 RK_PD3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ jtagm1_pins: jtagm1-pins { ++ rockchip,pins = ++ /* jtag_tck_m1 */ ++ <4 RK_PD0 5 &pcfg_pull_none>, ++ /* jtag_tms_m1 */ ++ <4 RK_PD1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ jtagm2_pins: jtagm2-pins { ++ rockchip,pins = ++ /* jtag_tck_m2 */ ++ <0 RK_PB5 2 &pcfg_pull_none>, ++ /* jtag_tms_m2 */ ++ <0 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ litcpu { ++ /omit-if-no-ref/ ++ litcpu_pins: litcpu-pins { ++ rockchip,pins = ++ /* litcpu_avs */ ++ <0 RK_PD3 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ mcu { ++ /omit-if-no-ref/ ++ mcum0_pins: mcum0-pins { ++ rockchip,pins = ++ /* mcu_jtag_tck_m0 */ ++ <4 RK_PD4 5 &pcfg_pull_none>, ++ /* mcu_jtag_tms_m0 */ ++ <4 RK_PD5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mcum1_pins: mcum1-pins { ++ rockchip,pins = ++ /* mcu_jtag_tck_m1 */ ++ <3 RK_PD4 6 &pcfg_pull_none>, ++ /* mcu_jtag_tms_m1 */ ++ <3 RK_PD5 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ mipi { ++ /omit-if-no-ref/ ++ mipim0_camera0_clk: mipim0-camera0-clk { ++ rockchip,pins = ++ /* mipim0_camera0_clk */ ++ <4 RK_PB1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim0_camera1_clk: mipim0-camera1-clk { ++ rockchip,pins = ++ /* mipim0_camera1_clk */ ++ <1 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim0_camera2_clk: mipim0-camera2-clk { ++ rockchip,pins = ++ /* mipim0_camera2_clk */ ++ <1 RK_PB7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim0_camera3_clk: mipim0-camera3-clk { ++ rockchip,pins = ++ /* mipim0_camera3_clk */ ++ <1 RK_PD6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim0_camera4_clk: mipim0-camera4-clk { ++ rockchip,pins = ++ /* mipim0_camera4_clk */ ++ <1 RK_PD7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera0_clk: mipim1-camera0-clk { ++ rockchip,pins = ++ /* mipim1_camera0_clk */ ++ <3 RK_PA5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera1_clk: mipim1-camera1-clk { ++ rockchip,pins = ++ /* mipim1_camera1_clk */ ++ <3 RK_PA6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera2_clk: mipim1-camera2-clk { ++ rockchip,pins = ++ /* mipim1_camera2_clk */ ++ <3 RK_PA7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera3_clk: mipim1-camera3-clk { ++ rockchip,pins = ++ /* mipim1_camera3_clk */ ++ <3 RK_PB0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera4_clk: mipim1-camera4-clk { ++ rockchip,pins = ++ /* mipim1_camera4_clk */ ++ <3 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipi_te0: mipi-te0 { ++ rockchip,pins = ++ /* mipi_te0 */ ++ <3 RK_PC2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipi_te1: mipi-te1 { ++ rockchip,pins = ++ /* mipi_te1 */ ++ <3 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ npu { ++ /omit-if-no-ref/ ++ npu_pins: npu-pins { ++ rockchip,pins = ++ /* npu_avs */ ++ <0 RK_PC6 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie20x1 { ++ /omit-if-no-ref/ ++ pcie20x1m0_pins: pcie20x1m0-pins { ++ rockchip,pins = ++ /* pcie20x1_2_clkreqn_m0 */ ++ <3 RK_PC7 4 &pcfg_pull_none>, ++ /* pcie20x1_2_perstn_m0 */ ++ <3 RK_PD1 4 &pcfg_pull_none>, ++ /* pcie20x1_2_waken_m0 */ ++ <3 RK_PD0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie20x1m1_pins: pcie20x1m1-pins { ++ rockchip,pins = ++ /* pcie20x1_2_clkreqn_m1 */ ++ <4 RK_PB7 4 &pcfg_pull_none>, ++ /* pcie20x1_2_perstn_m1 */ ++ <4 RK_PC1 4 &pcfg_pull_none>, ++ /* pcie20x1_2_waken_m1 */ ++ <4 RK_PC0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { ++ rockchip,pins = ++ /* pcie20x1_2_button_rstn */ ++ <4 RK_PB3 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30phy { ++ /omit-if-no-ref/ ++ pcie30phy_pins: pcie30phy-pins { ++ rockchip,pins = ++ /* pcie30phy_dtb0 */ ++ <1 RK_PC4 4 &pcfg_pull_none>, ++ /* pcie30phy_dtb1 */ ++ <1 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30x1 { ++ /omit-if-no-ref/ ++ pcie30x1m0_pins: pcie30x1m0-pins { ++ rockchip,pins = ++ /* pcie30x1_0_clkreqn_m0 */ ++ <0 RK_PC0 12 &pcfg_pull_none>, ++ /* pcie30x1_0_perstn_m0 */ ++ <0 RK_PC5 12 &pcfg_pull_none>, ++ /* pcie30x1_0_waken_m0 */ ++ <0 RK_PC4 12 &pcfg_pull_none>, ++ /* pcie30x1_1_clkreqn_m0 */ ++ <0 RK_PB5 12 &pcfg_pull_none>, ++ /* pcie30x1_1_perstn_m0 */ ++ <0 RK_PB7 12 &pcfg_pull_none>, ++ /* pcie30x1_1_waken_m0 */ ++ <0 RK_PB6 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m1_pins: pcie30x1m1-pins { ++ rockchip,pins = ++ /* pcie30x1_0_clkreqn_m1 */ ++ <4 RK_PA3 4 &pcfg_pull_none>, ++ /* pcie30x1_0_perstn_m1 */ ++ <4 RK_PA5 4 &pcfg_pull_none>, ++ /* pcie30x1_0_waken_m1 */ ++ <4 RK_PA4 4 &pcfg_pull_none>, ++ /* pcie30x1_1_clkreqn_m1 */ ++ <4 RK_PA0 4 &pcfg_pull_none>, ++ /* pcie30x1_1_perstn_m1 */ ++ <4 RK_PA2 4 &pcfg_pull_none>, ++ /* pcie30x1_1_waken_m1 */ ++ <4 RK_PA1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m2_pins: pcie30x1m2-pins { ++ rockchip,pins = ++ /* pcie30x1_0_clkreqn_m2 */ ++ <1 RK_PB5 4 &pcfg_pull_none>, ++ /* pcie30x1_0_perstn_m2 */ ++ <1 RK_PB4 4 &pcfg_pull_none>, ++ /* pcie30x1_0_waken_m2 */ ++ <1 RK_PB3 4 &pcfg_pull_none>, ++ /* pcie30x1_1_clkreqn_m2 */ ++ <1 RK_PA0 4 &pcfg_pull_none>, ++ /* pcie30x1_1_perstn_m2 */ ++ <1 RK_PA7 4 &pcfg_pull_none>, ++ /* pcie30x1_1_waken_m2 */ ++ <1 RK_PA1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { ++ rockchip,pins = ++ /* pcie30x1_0_button_rstn */ ++ <4 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { ++ rockchip,pins = ++ /* pcie30x1_1_button_rstn */ ++ <4 RK_PB2 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30x2 { ++ /omit-if-no-ref/ ++ pcie30x2m0_pins: pcie30x2m0-pins { ++ rockchip,pins = ++ /* pcie30x2_clkreqn_m0 */ ++ <0 RK_PD1 12 &pcfg_pull_none>, ++ /* pcie30x2_perstn_m0 */ ++ <0 RK_PD4 12 &pcfg_pull_none>, ++ /* pcie30x2_waken_m0 */ ++ <0 RK_PD2 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m1_pins: pcie30x2m1-pins { ++ rockchip,pins = ++ /* pcie30x2_clkreqn_m1 */ ++ <4 RK_PA6 4 &pcfg_pull_none>, ++ /* pcie30x2_perstn_m1 */ ++ <4 RK_PB0 4 &pcfg_pull_none>, ++ /* pcie30x2_waken_m1 */ ++ <4 RK_PA7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m2_pins: pcie30x2m2-pins { ++ rockchip,pins = ++ /* pcie30x2_clkreqn_m2 */ ++ <3 RK_PD2 4 &pcfg_pull_none>, ++ /* pcie30x2_perstn_m2 */ ++ <3 RK_PD4 4 &pcfg_pull_none>, ++ /* pcie30x2_waken_m2 */ ++ <3 RK_PD3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m3_pins: pcie30x2m3-pins { ++ rockchip,pins = ++ /* pcie30x2_clkreqn_m3 */ ++ <1 RK_PD7 4 &pcfg_pull_none>, ++ /* pcie30x2_perstn_m3 */ ++ <1 RK_PB7 4 &pcfg_pull_none>, ++ /* pcie30x2_waken_m3 */ ++ <1 RK_PB6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2_button_rstn: pcie30x2-button-rstn { ++ rockchip,pins = ++ /* pcie30x2_button_rstn */ ++ <3 RK_PC1 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30x4 { ++ /omit-if-no-ref/ ++ pcie30x4m0_pins: pcie30x4m0-pins { ++ rockchip,pins = ++ /* pcie30x4_clkreqn_m0 */ ++ <0 RK_PC6 12 &pcfg_pull_none>, ++ /* pcie30x4_perstn_m0 */ ++ <0 RK_PD0 12 &pcfg_pull_none>, ++ /* pcie30x4_waken_m0 */ ++ <0 RK_PC7 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m1_pins: pcie30x4m1-pins { ++ rockchip,pins = ++ /* pcie30x4_clkreqn_m1 */ ++ <4 RK_PB4 4 &pcfg_pull_none>, ++ /* pcie30x4_perstn_m1 */ ++ <4 RK_PB6 4 &pcfg_pull_none>, ++ /* pcie30x4_waken_m1 */ ++ <4 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m2_pins: pcie30x4m2-pins { ++ rockchip,pins = ++ /* pcie30x4_clkreqn_m2 */ ++ <3 RK_PC4 4 &pcfg_pull_none>, ++ /* pcie30x4_perstn_m2 */ ++ <3 RK_PC6 4 &pcfg_pull_none>, ++ /* pcie30x4_waken_m2 */ ++ <3 RK_PC5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m3_pins: pcie30x4m3-pins { ++ rockchip,pins = ++ /* pcie30x4_clkreqn_m3 */ ++ <1 RK_PB0 4 &pcfg_pull_none>, ++ /* pcie30x4_perstn_m3 */ ++ <1 RK_PB2 4 &pcfg_pull_none>, ++ /* pcie30x4_waken_m3 */ ++ <1 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4_button_rstn: pcie30x4-button-rstn { ++ rockchip,pins = ++ /* pcie30x4_button_rstn */ ++ <3 RK_PD5 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pdm0 { ++ /omit-if-no-ref/ ++ pdm0m0_clk: pdm0m0-clk { ++ rockchip,pins = ++ /* pdm0_clk0_m0 */ ++ <1 RK_PC6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_clk1: pdm0m0-clk1 { ++ rockchip,pins = ++ /* pdm0m0_clk1 */ ++ <1 RK_PC4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi0: pdm0m0-sdi0 { ++ rockchip,pins = ++ /* pdm0m0_sdi0 */ ++ <1 RK_PD5 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi1: pdm0m0-sdi1 { ++ rockchip,pins = ++ /* pdm0m0_sdi1 */ ++ <1 RK_PD1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi2: pdm0m0-sdi2 { ++ rockchip,pins = ++ /* pdm0m0_sdi2 */ ++ <1 RK_PD2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi3: pdm0m0-sdi3 { ++ rockchip,pins = ++ /* pdm0m0_sdi3 */ ++ <1 RK_PD3 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ pdm0m1_clk: pdm0m1-clk { ++ rockchip,pins = ++ /* pdm0_clk0_m1 */ ++ <0 RK_PC0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_clk1: pdm0m1-clk1 { ++ rockchip,pins = ++ /* pdm0m1_clk1 */ ++ <0 RK_PC4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi0: pdm0m1-sdi0 { ++ rockchip,pins = ++ /* pdm0m1_sdi0 */ ++ <0 RK_PC7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi1: pdm0m1-sdi1 { ++ rockchip,pins = ++ /* pdm0m1_sdi1 */ ++ <0 RK_PD0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi2: pdm0m1-sdi2 { ++ rockchip,pins = ++ /* pdm0m1_sdi2 */ ++ <0 RK_PD4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi3: pdm0m1-sdi3 { ++ rockchip,pins = ++ /* pdm0m1_sdi3 */ ++ <0 RK_PD6 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pdm1 { ++ /omit-if-no-ref/ ++ pdm1m0_clk: pdm1m0-clk { ++ rockchip,pins = ++ /* pdm1_clk0_m0 */ ++ <4 RK_PD5 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_clk1: pdm1m0-clk1 { ++ rockchip,pins = ++ /* pdm1m0_clk1 */ ++ <4 RK_PD4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi0: pdm1m0-sdi0 { ++ rockchip,pins = ++ /* pdm1m0_sdi0 */ ++ <4 RK_PD3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi1: pdm1m0-sdi1 { ++ rockchip,pins = ++ /* pdm1m0_sdi1 */ ++ <4 RK_PD2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi2: pdm1m0-sdi2 { ++ rockchip,pins = ++ /* pdm1m0_sdi2 */ ++ <4 RK_PD1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi3: pdm1m0-sdi3 { ++ rockchip,pins = ++ /* pdm1m0_sdi3 */ ++ <4 RK_PD0 2 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ pdm1m1_clk: pdm1m1-clk { ++ rockchip,pins = ++ /* pdm1_clk0_m1 */ ++ <1 RK_PB4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_clk1: pdm1m1-clk1 { ++ rockchip,pins = ++ /* pdm1m1_clk1 */ ++ <1 RK_PB3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi0: pdm1m1-sdi0 { ++ rockchip,pins = ++ /* pdm1m1_sdi0 */ ++ <1 RK_PA7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi1: pdm1m1-sdi1 { ++ rockchip,pins = ++ /* pdm1m1_sdi1 */ ++ <1 RK_PB0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi2: pdm1m1-sdi2 { ++ rockchip,pins = ++ /* pdm1m1_sdi2 */ ++ <1 RK_PB1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi3: pdm1m1-sdi3 { ++ rockchip,pins = ++ /* pdm1m1_sdi3 */ ++ <1 RK_PB2 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ /omit-if-no-ref/ ++ pmic_pins: pmic-pins { ++ rockchip,pins = ++ /* pmic_int_l */ ++ <0 RK_PA7 0 &pcfg_pull_up>, ++ /* pmic_sleep1 */ ++ <0 RK_PA2 1 &pcfg_pull_none>, ++ /* pmic_sleep2 */ ++ <0 RK_PA3 1 &pcfg_pull_none>, ++ /* pmic_sleep3 */ ++ <0 RK_PC1 1 &pcfg_pull_none>, ++ /* pmic_sleep4 */ ++ <0 RK_PC2 1 &pcfg_pull_none>, ++ /* pmic_sleep5 */ ++ <0 RK_PC3 1 &pcfg_pull_none>, ++ /* pmic_sleep6 */ ++ <0 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmu { ++ /omit-if-no-ref/ ++ pmu_pins: pmu-pins { ++ rockchip,pins = ++ /* pmu_debug */ ++ <0 RK_PA5 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm0 { ++ /omit-if-no-ref/ ++ pwm0m0_pins: pwm0m0-pins { ++ rockchip,pins = ++ /* pwm0_m0 */ ++ <0 RK_PB7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m1_pins: pwm0m1-pins { ++ rockchip,pins = ++ /* pwm0_m1 */ ++ <1 RK_PD2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m2_pins: pwm0m2-pins { ++ rockchip,pins = ++ /* pwm0_m2 */ ++ <1 RK_PA2 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm1 { ++ /omit-if-no-ref/ ++ pwm1m0_pins: pwm1m0-pins { ++ rockchip,pins = ++ /* pwm1_m0 */ ++ <0 RK_PC0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m1_pins: pwm1m1-pins { ++ rockchip,pins = ++ /* pwm1_m1 */ ++ <1 RK_PD3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m2_pins: pwm1m2-pins { ++ rockchip,pins = ++ /* pwm1_m2 */ ++ <1 RK_PA3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm2 { ++ /omit-if-no-ref/ ++ pwm2m0_pins: pwm2m0-pins { ++ rockchip,pins = ++ /* pwm2_m0 */ ++ <0 RK_PC4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_pins: pwm2m1-pins { ++ rockchip,pins = ++ /* pwm2_m1 */ ++ <3 RK_PB1 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm3 { ++ /omit-if-no-ref/ ++ pwm3m0_pins: pwm3m0-pins { ++ rockchip,pins = ++ /* pwm3_ir_m0 */ ++ <0 RK_PD4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3m1_pins: pwm3m1-pins { ++ rockchip,pins = ++ /* pwm3_ir_m1 */ ++ <3 RK_PB2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3m2_pins: pwm3m2-pins { ++ rockchip,pins = ++ /* pwm3_ir_m2 */ ++ <1 RK_PC2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3m3_pins: pwm3m3-pins { ++ rockchip,pins = ++ /* pwm3_ir_m3 */ ++ <1 RK_PA7 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm4 { ++ /omit-if-no-ref/ ++ pwm4m0_pins: pwm4m0-pins { ++ rockchip,pins = ++ /* pwm4_m0 */ ++ <0 RK_PC5 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm5 { ++ /omit-if-no-ref/ ++ pwm5m0_pins: pwm5m0-pins { ++ rockchip,pins = ++ /* pwm5_m0 */ ++ <0 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5m1_pins: pwm5m1-pins { ++ rockchip,pins = ++ /* pwm5_m1 */ ++ <0 RK_PC6 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm6 { ++ /omit-if-no-ref/ ++ pwm6m0_pins: pwm6m0-pins { ++ rockchip,pins = ++ /* pwm6_m0 */ ++ <0 RK_PC7 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6m1_pins: pwm6m1-pins { ++ rockchip,pins = ++ /* pwm6_m1 */ ++ <4 RK_PC1 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm7 { ++ /omit-if-no-ref/ ++ pwm7m0_pins: pwm7m0-pins { ++ rockchip,pins = ++ /* pwm7_ir_m0 */ ++ <0 RK_PD0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7m1_pins: pwm7m1-pins { ++ rockchip,pins = ++ /* pwm7_ir_m1 */ ++ <4 RK_PD4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7m2_pins: pwm7m2-pins { ++ rockchip,pins = ++ /* pwm7_ir_m2 */ ++ <1 RK_PC3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm8 { ++ /omit-if-no-ref/ ++ pwm8m0_pins: pwm8m0-pins { ++ rockchip,pins = ++ /* pwm8_m0 */ ++ <3 RK_PA7 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8m1_pins: pwm8m1-pins { ++ rockchip,pins = ++ /* pwm8_m1 */ ++ <4 RK_PD0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8m2_pins: pwm8m2-pins { ++ rockchip,pins = ++ /* pwm8_m2 */ ++ <3 RK_PD0 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm9 { ++ /omit-if-no-ref/ ++ pwm9m0_pins: pwm9m0-pins { ++ rockchip,pins = ++ /* pwm9_m0 */ ++ <3 RK_PB0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9m1_pins: pwm9m1-pins { ++ rockchip,pins = ++ /* pwm9_m1 */ ++ <4 RK_PD1 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9m2_pins: pwm9m2-pins { ++ rockchip,pins = ++ /* pwm9_m2 */ ++ <3 RK_PD1 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm10 { ++ /omit-if-no-ref/ ++ pwm10m0_pins: pwm10m0-pins { ++ rockchip,pins = ++ /* pwm10_m0 */ ++ <3 RK_PA0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10m1_pins: pwm10m1-pins { ++ rockchip,pins = ++ /* pwm10_m1 */ ++ <4 RK_PD3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10m2_pins: pwm10m2-pins { ++ rockchip,pins = ++ /* pwm10_m2 */ ++ <3 RK_PD3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm11 { ++ /omit-if-no-ref/ ++ pwm11m0_pins: pwm11m0-pins { ++ rockchip,pins = ++ /* pwm11_ir_m0 */ ++ <3 RK_PA1 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11m1_pins: pwm11m1-pins { ++ rockchip,pins = ++ /* pwm11_ir_m1 */ ++ <4 RK_PB4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11m2_pins: pwm11m2-pins { ++ rockchip,pins = ++ /* pwm11_ir_m2 */ ++ <1 RK_PC4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11m3_pins: pwm11m3-pins { ++ rockchip,pins = ++ /* pwm11_ir_m3 */ ++ <3 RK_PD5 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm12 { ++ /omit-if-no-ref/ ++ pwm12m0_pins: pwm12m0-pins { ++ rockchip,pins = ++ /* pwm12_m0 */ ++ <3 RK_PB5 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm12m1_pins: pwm12m1-pins { ++ rockchip,pins = ++ /* pwm12_m1 */ ++ <4 RK_PB5 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm13 { ++ /omit-if-no-ref/ ++ pwm13m0_pins: pwm13m0-pins { ++ rockchip,pins = ++ /* pwm13_m0 */ ++ <3 RK_PB6 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13m1_pins: pwm13m1-pins { ++ rockchip,pins = ++ /* pwm13_m1 */ ++ <4 RK_PB6 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13m2_pins: pwm13m2-pins { ++ rockchip,pins = ++ /* pwm13_m2 */ ++ <1 RK_PB7 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm14 { ++ /omit-if-no-ref/ ++ pwm14m0_pins: pwm14m0-pins { ++ rockchip,pins = ++ /* pwm14_m0 */ ++ <3 RK_PC2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14m1_pins: pwm14m1-pins { ++ rockchip,pins = ++ /* pwm14_m1 */ ++ <4 RK_PB2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14m2_pins: pwm14m2-pins { ++ rockchip,pins = ++ /* pwm14_m2 */ ++ <1 RK_PD6 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm15 { ++ /omit-if-no-ref/ ++ pwm15m0_pins: pwm15m0-pins { ++ rockchip,pins = ++ /* pwm15_ir_m0 */ ++ <3 RK_PC3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15m1_pins: pwm15m1-pins { ++ rockchip,pins = ++ /* pwm15_ir_m1 */ ++ <4 RK_PB3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15m2_pins: pwm15m2-pins { ++ rockchip,pins = ++ /* pwm15_ir_m2 */ ++ <1 RK_PC6 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15m3_pins: pwm15m3-pins { ++ rockchip,pins = ++ /* pwm15_ir_m3 */ ++ <1 RK_PD7 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ refclk { ++ /omit-if-no-ref/ ++ refclk_pins: refclk-pins { ++ rockchip,pins = ++ /* refclk_out */ ++ <0 RK_PA0 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata { ++ /omit-if-no-ref/ ++ sata_pins: sata-pins { ++ rockchip,pins = ++ /* sata_cp_pod */ ++ <0 RK_PC6 13 &pcfg_pull_none>, ++ /* sata_cpdet */ ++ <0 RK_PD4 13 &pcfg_pull_none>, ++ /* sata_mp_switch */ ++ <0 RK_PD5 13 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata0 { ++ /omit-if-no-ref/ ++ sata0m0_pins: sata0m0-pins { ++ rockchip,pins = ++ /* sata0_act_led_m0 */ ++ <4 RK_PB6 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sata0m1_pins: sata0m1-pins { ++ rockchip,pins = ++ /* sata0_act_led_m1 */ ++ <1 RK_PB3 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata1 { ++ /omit-if-no-ref/ ++ sata1m0_pins: sata1m0-pins { ++ rockchip,pins = ++ /* sata1_act_led_m0 */ ++ <4 RK_PB5 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sata1m1_pins: sata1m1-pins { ++ rockchip,pins = ++ /* sata1_act_led_m1 */ ++ <1 RK_PA1 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata2 { ++ /omit-if-no-ref/ ++ sata2m0_pins: sata2m0-pins { ++ rockchip,pins = ++ /* sata2_act_led_m0 */ ++ <4 RK_PB1 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sata2m1_pins: sata2m1-pins { ++ rockchip,pins = ++ /* sata2_act_led_m1 */ ++ <1 RK_PB7 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdio { ++ /omit-if-no-ref/ ++ sdiom1_pins: sdiom1-pins { ++ rockchip,pins = ++ /* sdio_clk_m1 */ ++ <3 RK_PA5 2 &pcfg_pull_none>, ++ /* sdio_cmd_m1 */ ++ <3 RK_PA4 2 &pcfg_pull_none>, ++ /* sdio_d0_m1 */ ++ <3 RK_PA0 2 &pcfg_pull_none>, ++ /* sdio_d1_m1 */ ++ <3 RK_PA1 2 &pcfg_pull_none>, ++ /* sdio_d2_m1 */ ++ <3 RK_PA2 2 &pcfg_pull_none>, ++ /* sdio_d3_m1 */ ++ <3 RK_PA3 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc { ++ /omit-if-no-ref/ ++ sdmmc_bus4: sdmmc-bus4 { ++ rockchip,pins = ++ /* sdmmc_d0 */ ++ <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc_d1 */ ++ <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc_d2 */ ++ <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc_d3 */ ++ <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc_clk: sdmmc-clk { ++ rockchip,pins = ++ /* sdmmc_clk */ ++ <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc_cmd: sdmmc-cmd { ++ rockchip,pins = ++ /* sdmmc_cmd */ ++ <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc_det: sdmmc-det { ++ rockchip,pins = ++ /* sdmmc_det */ ++ <0 RK_PA4 1 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc_pwren: sdmmc-pwren { ++ rockchip,pins = ++ /* sdmmc_pwren */ ++ <0 RK_PA5 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spdif0 { ++ /omit-if-no-ref/ ++ spdif0m0_tx: spdif0m0-tx { ++ rockchip,pins = ++ /* spdif0m0_tx */ ++ <1 RK_PB6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdif0m1_tx: spdif0m1-tx { ++ rockchip,pins = ++ /* spdif0m1_tx */ ++ <4 RK_PB4 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spdif1 { ++ /omit-if-no-ref/ ++ spdif1m0_tx: spdif1m0-tx { ++ rockchip,pins = ++ /* spdif1m0_tx */ ++ <1 RK_PB7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdif1m1_tx: spdif1m1-tx { ++ rockchip,pins = ++ /* spdif1m1_tx */ ++ <4 RK_PB1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdif1m2_tx: spdif1m2-tx { ++ rockchip,pins = ++ /* spdif1m2_tx */ ++ <4 RK_PC1 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi0 { ++ /omit-if-no-ref/ ++ spi0m0_pins: spi0m0-pins { ++ rockchip,pins = ++ /* spi0_clk_m0 */ ++ <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_miso_m0 */ ++ <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_mosi_m0 */ ++ <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m0_cs0: spi0m0-cs0 { ++ rockchip,pins = ++ /* spi0_cs0_m0 */ ++ <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m0_cs1: spi0m0-cs1 { ++ rockchip,pins = ++ /* spi0_cs1_m0 */ ++ <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ /omit-if-no-ref/ ++ spi0m1_pins: spi0m1-pins { ++ rockchip,pins = ++ /* spi0_clk_m1 */ ++ <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_miso_m1 */ ++ <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_mosi_m1 */ ++ <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m1_cs0: spi0m1-cs0 { ++ rockchip,pins = ++ /* spi0_cs0_m1 */ ++ <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m1_cs1: spi0m1-cs1 { ++ rockchip,pins = ++ /* spi0_cs1_m1 */ ++ <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ /omit-if-no-ref/ ++ spi0m2_pins: spi0m2-pins { ++ rockchip,pins = ++ /* spi0_clk_m2 */ ++ <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_miso_m2 */ ++ <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_mosi_m2 */ ++ <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m2_cs0: spi0m2-cs0 { ++ rockchip,pins = ++ /* spi0_cs0_m2 */ ++ <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m2_cs1: spi0m2-cs1 { ++ rockchip,pins = ++ /* spi0_cs1_m2 */ ++ <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ /omit-if-no-ref/ ++ spi0m3_pins: spi0m3-pins { ++ rockchip,pins = ++ /* spi0_clk_m3 */ ++ <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_miso_m3 */ ++ <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_mosi_m3 */ ++ <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m3_cs0: spi0m3-cs0 { ++ rockchip,pins = ++ /* spi0_cs0_m3 */ ++ <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m3_cs1: spi0m3-cs1 { ++ rockchip,pins = ++ /* spi0_cs1_m3 */ ++ <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi1 { ++ /omit-if-no-ref/ ++ spi1m1_pins: spi1m1-pins { ++ rockchip,pins = ++ /* spi1_clk_m1 */ ++ <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_miso_m1 */ ++ <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_mosi_m1 */ ++ <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m1_cs0: spi1m1-cs0 { ++ rockchip,pins = ++ /* spi1_cs0_m1 */ ++ <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m1_cs1: spi1m1-cs1 { ++ rockchip,pins = ++ /* spi1_cs1_m1 */ ++ <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m2_pins: spi1m2-pins { ++ rockchip,pins = ++ /* spi1_clk_m2 */ ++ <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_miso_m2 */ ++ <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_mosi_m2 */ ++ <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m2_cs0: spi1m2-cs0 { ++ rockchip,pins = ++ /* spi1_cs0_m2 */ ++ <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m2_cs1: spi1m2-cs1 { ++ rockchip,pins = ++ /* spi1_cs1_m2 */ ++ <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi2 { ++ /omit-if-no-ref/ ++ spi2m0_pins: spi2m0-pins { ++ rockchip,pins = ++ /* spi2_clk_m0 */ ++ <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi2_miso_m0 */ ++ <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, ++ /* spi2_mosi_m0 */ ++ <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m0_cs0: spi2m0-cs0 { ++ rockchip,pins = ++ /* spi2_cs0_m0 */ ++ <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m0_cs1: spi2m0-cs1 { ++ rockchip,pins = ++ /* spi2_cs1_m0 */ ++ <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m1_pins: spi2m1-pins { ++ rockchip,pins = ++ /* spi2_clk_m1 */ ++ <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi2_miso_m1 */ ++ <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, ++ /* spi2_mosi_m1 */ ++ <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m1_cs0: spi2m1-cs0 { ++ rockchip,pins = ++ /* spi2_cs0_m1 */ ++ <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m1_cs1: spi2m1-cs1 { ++ rockchip,pins = ++ /* spi2_cs1_m1 */ ++ <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m2_pins: spi2m2-pins { ++ rockchip,pins = ++ /* spi2_clk_m2 */ ++ <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, ++ /* spi2_miso_m2 */ ++ <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, ++ /* spi2_mosi_m2 */ ++ <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m2_cs0: spi2m2-cs0 { ++ rockchip,pins = ++ /* spi2_cs0_m2 */ ++ <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m2_cs1: spi2m2-cs1 { ++ rockchip,pins = ++ /* spi2_cs1_m2 */ ++ <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi3 { ++ /omit-if-no-ref/ ++ spi3m1_pins: spi3m1-pins { ++ rockchip,pins = ++ /* spi3_clk_m1 */ ++ <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_miso_m1 */ ++ <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_mosi_m1 */ ++ <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m1_cs0: spi3m1-cs0 { ++ rockchip,pins = ++ /* spi3_cs0_m1 */ ++ <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m1_cs1: spi3m1-cs1 { ++ rockchip,pins = ++ /* spi3_cs1_m1 */ ++ <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m2_pins: spi3m2-pins { ++ rockchip,pins = ++ /* spi3_clk_m2 */ ++ <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_miso_m2 */ ++ <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_mosi_m2 */ ++ <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m2_cs0: spi3m2-cs0 { ++ rockchip,pins = ++ /* spi3_cs0_m2 */ ++ <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m2_cs1: spi3m2-cs1 { ++ rockchip,pins = ++ /* spi3_cs1_m2 */ ++ <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m3_pins: spi3m3-pins { ++ rockchip,pins = ++ /* spi3_clk_m3 */ ++ <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_miso_m3 */ ++ <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_mosi_m3 */ ++ <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m3_cs0: spi3m3-cs0 { ++ rockchip,pins = ++ /* spi3_cs0_m3 */ ++ <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m3_cs1: spi3m3-cs1 { ++ rockchip,pins = ++ /* spi3_cs1_m3 */ ++ <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi4 { ++ /omit-if-no-ref/ ++ spi4m0_pins: spi4m0-pins { ++ rockchip,pins = ++ /* spi4_clk_m0 */ ++ <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_miso_m0 */ ++ <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_mosi_m0 */ ++ <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m0_cs0: spi4m0-cs0 { ++ rockchip,pins = ++ /* spi4_cs0_m0 */ ++ <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m0_cs1: spi4m0-cs1 { ++ rockchip,pins = ++ /* spi4_cs1_m0 */ ++ <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m1_pins: spi4m1-pins { ++ rockchip,pins = ++ /* spi4_clk_m1 */ ++ <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_miso_m1 */ ++ <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_mosi_m1 */ ++ <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m1_cs0: spi4m1-cs0 { ++ rockchip,pins = ++ /* spi4_cs0_m1 */ ++ <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m1_cs1: spi4m1-cs1 { ++ rockchip,pins = ++ /* spi4_cs1_m1 */ ++ <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m2_pins: spi4m2-pins { ++ rockchip,pins = ++ /* spi4_clk_m2 */ ++ <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_miso_m2 */ ++ <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_mosi_m2 */ ++ <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m2_cs0: spi4m2-cs0 { ++ rockchip,pins = ++ /* spi4_cs0_m2 */ ++ <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ tsadc { ++ /omit-if-no-ref/ ++ tsadcm1_shut: tsadcm1-shut { ++ rockchip,pins = ++ /* tsadcm1_shut */ ++ <0 RK_PA2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ tsadc_shut: tsadc-shut { ++ rockchip,pins = ++ /* tsadc_shut */ ++ <0 RK_PA1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ tsadc_shut_org: tsadc-shut-org { ++ rockchip,pins = ++ /* tsadc_shut_org */ ++ <0 RK_PA1 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart0 { ++ /omit-if-no-ref/ ++ uart0m0_xfer: uart0m0-xfer { ++ rockchip,pins = ++ /* uart0_rx_m0 */ ++ <0 RK_PC4 4 &pcfg_pull_up>, ++ /* uart0_tx_m0 */ ++ <0 RK_PC5 4 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0m1_xfer: uart0m1-xfer { ++ rockchip,pins = ++ /* uart0_rx_m1 */ ++ <0 RK_PB0 4 &pcfg_pull_up>, ++ /* uart0_tx_m1 */ ++ <0 RK_PB1 4 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0m2_xfer: uart0m2-xfer { ++ rockchip,pins = ++ /* uart0_rx_m2 */ ++ <4 RK_PA4 10 &pcfg_pull_up>, ++ /* uart0_tx_m2 */ ++ <4 RK_PA3 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0_ctsn: uart0-ctsn { ++ rockchip,pins = ++ /* uart0_ctsn */ ++ <0 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0_rtsn: uart0-rtsn { ++ rockchip,pins = ++ /* uart0_rtsn */ ++ <0 RK_PC6 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart1 { ++ /omit-if-no-ref/ ++ uart1m1_xfer: uart1m1-xfer { ++ rockchip,pins = ++ /* uart1_rx_m1 */ ++ <1 RK_PB7 10 &pcfg_pull_up>, ++ /* uart1_tx_m1 */ ++ <1 RK_PB6 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m1_ctsn: uart1m1-ctsn { ++ rockchip,pins = ++ /* uart1m1_ctsn */ ++ <1 RK_PD7 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m1_rtsn: uart1m1-rtsn { ++ rockchip,pins = ++ /* uart1m1_rtsn */ ++ <1 RK_PD6 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m2_xfer: uart1m2-xfer { ++ rockchip,pins = ++ /* uart1_rx_m2 */ ++ <0 RK_PD2 10 &pcfg_pull_up>, ++ /* uart1_tx_m2 */ ++ <0 RK_PD1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m2_ctsn: uart1m2-ctsn { ++ rockchip,pins = ++ /* uart1m2_ctsn */ ++ <0 RK_PD0 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m2_rtsn: uart1m2-rtsn { ++ rockchip,pins = ++ /* uart1m2_rtsn */ ++ <0 RK_PC7 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart2 { ++ /omit-if-no-ref/ ++ uart2m0_xfer: uart2m0-xfer { ++ rockchip,pins = ++ /* uart2_rx_m0 */ ++ <0 RK_PB6 10 &pcfg_pull_up>, ++ /* uart2_tx_m0 */ ++ <0 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m1_xfer: uart2m1-xfer { ++ rockchip,pins = ++ /* uart2_rx_m1 */ ++ <4 RK_PD1 10 &pcfg_pull_up>, ++ /* uart2_tx_m1 */ ++ <4 RK_PD0 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m2_xfer: uart2m2-xfer { ++ rockchip,pins = ++ /* uart2_rx_m2 */ ++ <3 RK_PB2 10 &pcfg_pull_up>, ++ /* uart2_tx_m2 */ ++ <3 RK_PB1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_ctsn: uart2-ctsn { ++ rockchip,pins = ++ /* uart2_ctsn */ ++ <3 RK_PB4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_rtsn: uart2-rtsn { ++ rockchip,pins = ++ /* uart2_rtsn */ ++ <3 RK_PB3 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart3 { ++ /omit-if-no-ref/ ++ uart3m0_xfer: uart3m0-xfer { ++ rockchip,pins = ++ /* uart3_rx_m0 */ ++ <1 RK_PC0 10 &pcfg_pull_up>, ++ /* uart3_tx_m0 */ ++ <1 RK_PC1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m1_xfer: uart3m1-xfer { ++ rockchip,pins = ++ /* uart3_rx_m1 */ ++ <3 RK_PB6 10 &pcfg_pull_up>, ++ /* uart3_tx_m1 */ ++ <3 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m2_xfer: uart3m2-xfer { ++ rockchip,pins = ++ /* uart3_rx_m2 */ ++ <4 RK_PA6 10 &pcfg_pull_up>, ++ /* uart3_tx_m2 */ ++ <4 RK_PA5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_ctsn: uart3-ctsn { ++ rockchip,pins = ++ /* uart3_ctsn */ ++ <1 RK_PC3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_rtsn: uart3-rtsn { ++ rockchip,pins = ++ /* uart3_rtsn */ ++ <1 RK_PC2 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart4 { ++ /omit-if-no-ref/ ++ uart4m0_xfer: uart4m0-xfer { ++ rockchip,pins = ++ /* uart4_rx_m0 */ ++ <1 RK_PD3 10 &pcfg_pull_up>, ++ /* uart4_tx_m0 */ ++ <1 RK_PD2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4m1_xfer: uart4m1-xfer { ++ rockchip,pins = ++ /* uart4_rx_m1 */ ++ <3 RK_PD0 10 &pcfg_pull_up>, ++ /* uart4_tx_m1 */ ++ <3 RK_PD1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4m2_xfer: uart4m2-xfer { ++ rockchip,pins = ++ /* uart4_rx_m2 */ ++ <1 RK_PB2 10 &pcfg_pull_up>, ++ /* uart4_tx_m2 */ ++ <1 RK_PB3 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_ctsn: uart4-ctsn { ++ rockchip,pins = ++ /* uart4_ctsn */ ++ <1 RK_PC7 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_rtsn: uart4-rtsn { ++ rockchip,pins = ++ /* uart4_rtsn */ ++ <1 RK_PC5 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart5 { ++ /omit-if-no-ref/ ++ uart5m0_xfer: uart5m0-xfer { ++ rockchip,pins = ++ /* uart5_rx_m0 */ ++ <4 RK_PD4 10 &pcfg_pull_up>, ++ /* uart5_tx_m0 */ ++ <4 RK_PD5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m0_ctsn: uart5m0-ctsn { ++ rockchip,pins = ++ /* uart5m0_ctsn */ ++ <4 RK_PD2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m0_rtsn: uart5m0-rtsn { ++ rockchip,pins = ++ /* uart5m0_rtsn */ ++ <4 RK_PD3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m1_xfer: uart5m1-xfer { ++ rockchip,pins = ++ /* uart5_rx_m1 */ ++ <3 RK_PC5 10 &pcfg_pull_up>, ++ /* uart5_tx_m1 */ ++ <3 RK_PC4 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m1_ctsn: uart5m1-ctsn { ++ rockchip,pins = ++ /* uart5m1_ctsn */ ++ <2 RK_PA2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m1_rtsn: uart5m1-rtsn { ++ rockchip,pins = ++ /* uart5m1_rtsn */ ++ <2 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m2_xfer: uart5m2-xfer { ++ rockchip,pins = ++ /* uart5_rx_m2 */ ++ <2 RK_PD4 10 &pcfg_pull_up>, ++ /* uart5_tx_m2 */ ++ <2 RK_PD5 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart6 { ++ /omit-if-no-ref/ ++ uart6m1_xfer: uart6m1-xfer { ++ rockchip,pins = ++ /* uart6_rx_m1 */ ++ <1 RK_PA0 10 &pcfg_pull_up>, ++ /* uart6_tx_m1 */ ++ <1 RK_PA1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m1_ctsn: uart6m1-ctsn { ++ rockchip,pins = ++ /* uart6m1_ctsn */ ++ <1 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m1_rtsn: uart6m1-rtsn { ++ rockchip,pins = ++ /* uart6m1_rtsn */ ++ <1 RK_PA2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m2_xfer: uart6m2-xfer { ++ rockchip,pins = ++ /* uart6_rx_m2 */ ++ <1 RK_PD1 10 &pcfg_pull_up>, ++ /* uart6_tx_m2 */ ++ <1 RK_PD0 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart7 { ++ /omit-if-no-ref/ ++ uart7m1_xfer: uart7m1-xfer { ++ rockchip,pins = ++ /* uart7_rx_m1 */ ++ <3 RK_PC1 10 &pcfg_pull_up>, ++ /* uart7_tx_m1 */ ++ <3 RK_PC0 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m1_ctsn: uart7m1-ctsn { ++ rockchip,pins = ++ /* uart7m1_ctsn */ ++ <3 RK_PC3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m1_rtsn: uart7m1-rtsn { ++ rockchip,pins = ++ /* uart7m1_rtsn */ ++ <3 RK_PC2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m2_xfer: uart7m2-xfer { ++ rockchip,pins = ++ /* uart7_rx_m2 */ ++ <1 RK_PB4 10 &pcfg_pull_up>, ++ /* uart7_tx_m2 */ ++ <1 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart8 { ++ /omit-if-no-ref/ ++ uart8m0_xfer: uart8m0-xfer { ++ rockchip,pins = ++ /* uart8_rx_m0 */ ++ <4 RK_PB1 10 &pcfg_pull_up>, ++ /* uart8_tx_m0 */ ++ <4 RK_PB0 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m0_ctsn: uart8m0-ctsn { ++ rockchip,pins = ++ /* uart8m0_ctsn */ ++ <4 RK_PB3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m0_rtsn: uart8m0-rtsn { ++ rockchip,pins = ++ /* uart8m0_rtsn */ ++ <4 RK_PB2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m1_xfer: uart8m1-xfer { ++ rockchip,pins = ++ /* uart8_rx_m1 */ ++ <3 RK_PA3 10 &pcfg_pull_up>, ++ /* uart8_tx_m1 */ ++ <3 RK_PA2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m1_ctsn: uart8m1-ctsn { ++ rockchip,pins = ++ /* uart8m1_ctsn */ ++ <3 RK_PA5 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m1_rtsn: uart8m1-rtsn { ++ rockchip,pins = ++ /* uart8m1_rtsn */ ++ <3 RK_PA4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8_xfer: uart8-xfer { ++ rockchip,pins = ++ /* uart8_rx_ */ ++ <4 RK_PB1 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart9 { ++ /omit-if-no-ref/ ++ uart9m0_xfer: uart9m0-xfer { ++ rockchip,pins = ++ /* uart9_rx_m0 */ ++ <2 RK_PC4 10 &pcfg_pull_up>, ++ /* uart9_tx_m0 */ ++ <2 RK_PC2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m1_xfer: uart9m1-xfer { ++ rockchip,pins = ++ /* uart9_rx_m1 */ ++ <4 RK_PB5 10 &pcfg_pull_up>, ++ /* uart9_tx_m1 */ ++ <4 RK_PB4 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m1_ctsn: uart9m1-ctsn { ++ rockchip,pins = ++ /* uart9m1_ctsn */ ++ <4 RK_PA1 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m1_rtsn: uart9m1-rtsn { ++ rockchip,pins = ++ /* uart9m1_rtsn */ ++ <4 RK_PA0 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m2_xfer: uart9m2-xfer { ++ rockchip,pins = ++ /* uart9_rx_m2 */ ++ <3 RK_PD4 10 &pcfg_pull_up>, ++ /* uart9_tx_m2 */ ++ <3 RK_PD5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m2_ctsn: uart9m2-ctsn { ++ rockchip,pins = ++ /* uart9m2_ctsn */ ++ <3 RK_PD3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m2_rtsn: uart9m2-rtsn { ++ rockchip,pins = ++ /* uart9m2_rtsn */ ++ <3 RK_PD2 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vop { ++ /omit-if-no-ref/ ++ vop_pins: vop-pins { ++ rockchip,pins = ++ /* vop_post_empty */ ++ <1 RK_PA2 1 &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++/* ++ * This part is edited handly. ++ */ ++&pinctrl { ++ bt656 { ++ /omit-if-no-ref/ ++ bt656_pins: bt656-pins { ++ rockchip,pins = ++ /* bt1120_clkout */ ++ <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d0 */ ++ <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d1 */ ++ <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d2 */ ++ <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d3 */ ++ <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d4 */ ++ <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d5 */ ++ <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d6 */ ++ <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d7 */ ++ <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; ++ }; ++ }; ++ ++ gpio-func { ++ /omit-if-no-ref/ ++ tsadc_gpio_func: tsadc-gpio-func { ++ rockchip,pins = ++ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi +@@ -0,0 +1,516 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include "rockchip-pinconf.dtsi" ++ ++/* ++ * This file is auto generated by pin2dts tool, please keep these code ++ * by adding changes at end of this file. ++ */ ++&pinctrl { ++ clk32k { ++ /omit-if-no-ref/ ++ clk32k_out1: clk32k-out1 { ++ rockchip,pins = ++ /* clk32k_out1 */ ++ <2 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ }; ++ ++ eth0 { ++ /omit-if-no-ref/ ++ eth0_pins: eth0-pins { ++ rockchip,pins = ++ /* eth0_refclko_25m */ ++ <2 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ }; ++ ++ fspi { ++ /omit-if-no-ref/ ++ fspim1_pins: fspim1-pins { ++ rockchip,pins = ++ /* fspi_clk_m1 */ ++ <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_cs0n_m1 */ ++ <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d0_m1 */ ++ <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d1_m1 */ ++ <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d2_m1 */ ++ <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d3_m1 */ ++ <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspim1_cs1: fspim1-cs1 { ++ rockchip,pins = ++ /* fspi_cs1n_m1 */ ++ <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; ++ }; ++ }; ++ ++ gmac0 { ++ /omit-if-no-ref/ ++ gmac0_miim: gmac0-miim { ++ rockchip,pins = ++ /* gmac0_mdc */ ++ <4 RK_PC4 1 &pcfg_pull_none>, ++ /* gmac0_mdio */ ++ <4 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_clkinout: gmac0-clkinout { ++ rockchip,pins = ++ /* gmac0_mclkinout */ ++ <4 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_rx_bus2: gmac0-rx-bus2 { ++ rockchip,pins = ++ /* gmac0_rxd0 */ ++ <2 RK_PC1 1 &pcfg_pull_none>, ++ /* gmac0_rxd1 */ ++ <2 RK_PC2 1 &pcfg_pull_none>, ++ /* gmac0_rxdv_crs */ ++ <4 RK_PC2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_tx_bus2: gmac0-tx-bus2 { ++ rockchip,pins = ++ /* gmac0_txd0 */ ++ <2 RK_PB6 1 &pcfg_pull_none>, ++ /* gmac0_txd1 */ ++ <2 RK_PB7 1 &pcfg_pull_none>, ++ /* gmac0_txen */ ++ <2 RK_PC0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_rgmii_clk: gmac0-rgmii-clk { ++ rockchip,pins = ++ /* gmac0_rxclk */ ++ <2 RK_PB0 1 &pcfg_pull_none>, ++ /* gmac0_txclk */ ++ <2 RK_PB3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_rgmii_bus: gmac0-rgmii-bus { ++ rockchip,pins = ++ /* gmac0_rxd2 */ ++ <2 RK_PA6 1 &pcfg_pull_none>, ++ /* gmac0_rxd3 */ ++ <2 RK_PA7 1 &pcfg_pull_none>, ++ /* gmac0_txd2 */ ++ <2 RK_PB1 1 &pcfg_pull_none>, ++ /* gmac0_txd3 */ ++ <2 RK_PB2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_ppsclk: gmac0-ppsclk { ++ rockchip,pins = ++ /* gmac0_ppsclk */ ++ <2 RK_PC4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_ppstring: gmac0-ppstring { ++ rockchip,pins = ++ /* gmac0_ppstring */ ++ <2 RK_PB5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_ptp_refclk: gmac0-ptp-refclk { ++ rockchip,pins = ++ /* gmac0_ptp_refclk */ ++ <2 RK_PB4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_txer: gmac0-txer { ++ rockchip,pins = ++ /* gmac0_txer */ ++ <4 RK_PC6 1 &pcfg_pull_none>; ++ }; ++ ++ }; ++ ++ hdmi { ++ /omit-if-no-ref/ ++ hdmim0_tx1_cec: hdmim0-tx1-cec { ++ rockchip,pins = ++ /* hdmim0_tx1_cec */ ++ <2 RK_PC4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx1_scl: hdmim0-tx1-scl { ++ rockchip,pins = ++ /* hdmim0_tx1_scl */ ++ <2 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx1_sda: hdmim0-tx1-sda { ++ rockchip,pins = ++ /* hdmim0_tx1_sda */ ++ <2 RK_PB4 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2c0 { ++ /omit-if-no-ref/ ++ i2c0m1_xfer: i2c0m1-xfer { ++ rockchip,pins = ++ /* i2c0_scl_m1 */ ++ <4 RK_PC5 9 &pcfg_pull_none_smt>, ++ /* i2c0_sda_m1 */ ++ <4 RK_PC6 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c2 { ++ /omit-if-no-ref/ ++ i2c2m1_xfer: i2c2m1-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m1 */ ++ <2 RK_PC1 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m1 */ ++ <2 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c3 { ++ /omit-if-no-ref/ ++ i2c3m3_xfer: i2c3m3-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m3 */ ++ <2 RK_PB2 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m3 */ ++ <2 RK_PB3 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c4 { ++ /omit-if-no-ref/ ++ i2c4m1_xfer: i2c4m1-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m1 */ ++ <2 RK_PB5 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m1 */ ++ <2 RK_PB4 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c5 { ++ /omit-if-no-ref/ ++ i2c5m4_xfer: i2c5m4-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m4 */ ++ <2 RK_PB6 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m4 */ ++ <2 RK_PB7 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c6 { ++ /omit-if-no-ref/ ++ i2c6m2_xfer: i2c6m2-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m2 */ ++ <2 RK_PC3 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m2 */ ++ <2 RK_PC2 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c7 { ++ /omit-if-no-ref/ ++ i2c7m1_xfer: i2c7m1-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m1 */ ++ <4 RK_PC3 9 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m1 */ ++ <4 RK_PC4 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c8 { ++ /omit-if-no-ref/ ++ i2c8m1_xfer: i2c8m1-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m1 */ ++ <2 RK_PB0 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m1 */ ++ <2 RK_PB1 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2s2 { ++ /omit-if-no-ref/ ++ i2s2m0_lrck: i2s2m0-lrck { ++ rockchip,pins = ++ /* i2s2m0_lrck */ ++ <2 RK_PC0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_mclk: i2s2m0-mclk { ++ rockchip,pins = ++ /* i2s2m0_mclk */ ++ <2 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sclk: i2s2m0-sclk { ++ rockchip,pins = ++ /* i2s2m0_sclk */ ++ <2 RK_PB7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdi: i2s2m0-sdi { ++ rockchip,pins = ++ /* i2s2m0_sdi */ ++ <2 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdo: i2s2m0-sdo { ++ rockchip,pins = ++ /* i2s2m0_sdo */ ++ <4 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm2 { ++ /omit-if-no-ref/ ++ pwm2m2_pins: pwm2m2-pins { ++ rockchip,pins = ++ /* pwm2_m2 */ ++ <4 RK_PC2 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm4 { ++ /omit-if-no-ref/ ++ pwm4m1_pins: pwm4m1-pins { ++ rockchip,pins = ++ /* pwm4_m1 */ ++ <4 RK_PC3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm5 { ++ /omit-if-no-ref/ ++ pwm5m2_pins: pwm5m2-pins { ++ rockchip,pins = ++ /* pwm5_m2 */ ++ <4 RK_PC4 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm6 { ++ /omit-if-no-ref/ ++ pwm6m2_pins: pwm6m2-pins { ++ rockchip,pins = ++ /* pwm6_m2 */ ++ <4 RK_PC5 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm7 { ++ /omit-if-no-ref/ ++ pwm7m3_pins: pwm7m3-pins { ++ rockchip,pins = ++ /* pwm7_ir_m3 */ ++ <4 RK_PC6 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdio { ++ /omit-if-no-ref/ ++ sdiom0_pins: sdiom0-pins { ++ rockchip,pins = ++ /* sdio_clk_m0 */ ++ <2 RK_PB3 2 &pcfg_pull_none>, ++ /* sdio_cmd_m0 */ ++ <2 RK_PB2 2 &pcfg_pull_none>, ++ /* sdio_d0_m0 */ ++ <2 RK_PA6 2 &pcfg_pull_none>, ++ /* sdio_d1_m0 */ ++ <2 RK_PA7 2 &pcfg_pull_none>, ++ /* sdio_d2_m0 */ ++ <2 RK_PB0 2 &pcfg_pull_none>, ++ /* sdio_d3_m0 */ ++ <2 RK_PB1 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi1 { ++ /omit-if-no-ref/ ++ spi1m0_pins: spi1m0-pins { ++ rockchip,pins = ++ /* spi1_clk_m0 */ ++ <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_miso_m0 */ ++ <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_mosi_m0 */ ++ <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m0_cs0: spi1m0-cs0 { ++ rockchip,pins = ++ /* spi1_cs0_m0 */ ++ <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m0_cs1: spi1m0-cs1 { ++ rockchip,pins = ++ /* spi1_cs1_m0 */ ++ <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi3 { ++ /omit-if-no-ref/ ++ spi3m0_pins: spi3m0-pins { ++ rockchip,pins = ++ /* spi3_clk_m0 */ ++ <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_miso_m0 */ ++ <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_mosi_m0 */ ++ <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m0_cs0: spi3m0-cs0 { ++ rockchip,pins = ++ /* spi3_cs0_m0 */ ++ <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m0_cs1: spi3m0-cs1 { ++ rockchip,pins = ++ /* spi3_cs1_m0 */ ++ <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ uart1 { ++ /omit-if-no-ref/ ++ uart1m0_xfer: uart1m0-xfer { ++ rockchip,pins = ++ /* uart1_rx_m0 */ ++ <2 RK_PB6 10 &pcfg_pull_up>, ++ /* uart1_tx_m0 */ ++ <2 RK_PB7 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m0_ctsn: uart1m0-ctsn { ++ rockchip,pins = ++ /* uart1m0_ctsn */ ++ <2 RK_PC1 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m0_rtsn: uart1m0-rtsn { ++ rockchip,pins = ++ /* uart1m0_rtsn */ ++ <2 RK_PC0 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart6 { ++ /omit-if-no-ref/ ++ uart6m0_xfer: uart6m0-xfer { ++ rockchip,pins = ++ /* uart6_rx_m0 */ ++ <2 RK_PA6 10 &pcfg_pull_up>, ++ /* uart6_tx_m0 */ ++ <2 RK_PA7 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m0_ctsn: uart6m0-ctsn { ++ rockchip,pins = ++ /* uart6m0_ctsn */ ++ <2 RK_PB1 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m0_rtsn: uart6m0-rtsn { ++ rockchip,pins = ++ /* uart6m0_rtsn */ ++ <2 RK_PB0 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart7 { ++ /omit-if-no-ref/ ++ uart7m0_xfer: uart7m0-xfer { ++ rockchip,pins = ++ /* uart7_rx_m0 */ ++ <2 RK_PB4 10 &pcfg_pull_up>, ++ /* uart7_tx_m0 */ ++ <2 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m0_ctsn: uart7m0-ctsn { ++ rockchip,pins = ++ /* uart7m0_ctsn */ ++ <4 RK_PC6 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m0_rtsn: uart7m0-rtsn { ++ rockchip,pins = ++ /* uart7m0_rtsn */ ++ <4 RK_PC2 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart9 { ++ /omit-if-no-ref/ ++ uart9m0_xfer: uart9m0-xfer { ++ rockchip,pins = ++ /* uart9_rx_m0 */ ++ <2 RK_PC4 10 &pcfg_pull_up>, ++ /* uart9_tx_m0 */ ++ <2 RK_PC2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m0_ctsn: uart9m0-ctsn { ++ rockchip,pins = ++ /* uart9m0_ctsn */ ++ <4 RK_PC5 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m0_rtsn: uart9m0-rtsn { ++ rockchip,pins = ++ /* uart9m0_rtsn */ ++ <4 RK_PC4 10 &pcfg_pull_none>; ++ }; ++ }; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi ++++ /dev/null +@@ -1,516 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. +- */ +- +-#include +-#include "rockchip-pinconf.dtsi" +- +-/* +- * This file is auto generated by pin2dts tool, please keep these code +- * by adding changes at end of this file. +- */ +-&pinctrl { +- clk32k { +- /omit-if-no-ref/ +- clk32k_out1: clk32k-out1 { +- rockchip,pins = +- /* clk32k_out1 */ +- <2 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- }; +- +- eth0 { +- /omit-if-no-ref/ +- eth0_pins: eth0-pins { +- rockchip,pins = +- /* eth0_refclko_25m */ +- <2 RK_PC3 1 &pcfg_pull_none>; +- }; +- +- }; +- +- fspi { +- /omit-if-no-ref/ +- fspim1_pins: fspim1-pins { +- rockchip,pins = +- /* fspi_clk_m1 */ +- <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, +- /* fspi_cs0n_m1 */ +- <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, +- /* fspi_d0_m1 */ +- <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, +- /* fspi_d1_m1 */ +- <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, +- /* fspi_d2_m1 */ +- <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, +- /* fspi_d3_m1 */ +- <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- fspim1_cs1: fspim1-cs1 { +- rockchip,pins = +- /* fspi_cs1n_m1 */ +- <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; +- }; +- }; +- +- gmac0 { +- /omit-if-no-ref/ +- gmac0_miim: gmac0-miim { +- rockchip,pins = +- /* gmac0_mdc */ +- <4 RK_PC4 1 &pcfg_pull_none>, +- /* gmac0_mdio */ +- <4 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_clkinout: gmac0-clkinout { +- rockchip,pins = +- /* gmac0_mclkinout */ +- <4 RK_PC3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_rx_bus2: gmac0-rx-bus2 { +- rockchip,pins = +- /* gmac0_rxd0 */ +- <2 RK_PC1 1 &pcfg_pull_none>, +- /* gmac0_rxd1 */ +- <2 RK_PC2 1 &pcfg_pull_none>, +- /* gmac0_rxdv_crs */ +- <4 RK_PC2 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_tx_bus2: gmac0-tx-bus2 { +- rockchip,pins = +- /* gmac0_txd0 */ +- <2 RK_PB6 1 &pcfg_pull_none>, +- /* gmac0_txd1 */ +- <2 RK_PB7 1 &pcfg_pull_none>, +- /* gmac0_txen */ +- <2 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_rgmii_clk: gmac0-rgmii-clk { +- rockchip,pins = +- /* gmac0_rxclk */ +- <2 RK_PB0 1 &pcfg_pull_none>, +- /* gmac0_txclk */ +- <2 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_rgmii_bus: gmac0-rgmii-bus { +- rockchip,pins = +- /* gmac0_rxd2 */ +- <2 RK_PA6 1 &pcfg_pull_none>, +- /* gmac0_rxd3 */ +- <2 RK_PA7 1 &pcfg_pull_none>, +- /* gmac0_txd2 */ +- <2 RK_PB1 1 &pcfg_pull_none>, +- /* gmac0_txd3 */ +- <2 RK_PB2 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_ppsclk: gmac0-ppsclk { +- rockchip,pins = +- /* gmac0_ppsclk */ +- <2 RK_PC4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_ppstring: gmac0-ppstring { +- rockchip,pins = +- /* gmac0_ppstring */ +- <2 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_ptp_refclk: gmac0-ptp-refclk { +- rockchip,pins = +- /* gmac0_ptp_refclk */ +- <2 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac0_txer: gmac0-txer { +- rockchip,pins = +- /* gmac0_txer */ +- <4 RK_PC6 1 &pcfg_pull_none>; +- }; +- +- }; +- +- hdmi { +- /omit-if-no-ref/ +- hdmim0_tx1_cec: hdmim0-tx1-cec { +- rockchip,pins = +- /* hdmim0_tx1_cec */ +- <2 RK_PC4 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_tx1_scl: hdmim0-tx1-scl { +- rockchip,pins = +- /* hdmim0_tx1_scl */ +- <2 RK_PB5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_tx1_sda: hdmim0-tx1-sda { +- rockchip,pins = +- /* hdmim0_tx1_sda */ +- <2 RK_PB4 4 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- /omit-if-no-ref/ +- i2c0m1_xfer: i2c0m1-xfer { +- rockchip,pins = +- /* i2c0_scl_m1 */ +- <4 RK_PC5 9 &pcfg_pull_none_smt>, +- /* i2c0_sda_m1 */ +- <4 RK_PC6 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c2 { +- /omit-if-no-ref/ +- i2c2m1_xfer: i2c2m1-xfer { +- rockchip,pins = +- /* i2c2_scl_m1 */ +- <2 RK_PC1 9 &pcfg_pull_none_smt>, +- /* i2c2_sda_m1 */ +- <2 RK_PC0 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c3 { +- /omit-if-no-ref/ +- i2c3m3_xfer: i2c3m3-xfer { +- rockchip,pins = +- /* i2c3_scl_m3 */ +- <2 RK_PB2 9 &pcfg_pull_none_smt>, +- /* i2c3_sda_m3 */ +- <2 RK_PB3 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c4 { +- /omit-if-no-ref/ +- i2c4m1_xfer: i2c4m1-xfer { +- rockchip,pins = +- /* i2c4_scl_m1 */ +- <2 RK_PB5 9 &pcfg_pull_none_smt>, +- /* i2c4_sda_m1 */ +- <2 RK_PB4 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c5 { +- /omit-if-no-ref/ +- i2c5m4_xfer: i2c5m4-xfer { +- rockchip,pins = +- /* i2c5_scl_m4 */ +- <2 RK_PB6 9 &pcfg_pull_none_smt>, +- /* i2c5_sda_m4 */ +- <2 RK_PB7 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c6 { +- /omit-if-no-ref/ +- i2c6m2_xfer: i2c6m2-xfer { +- rockchip,pins = +- /* i2c6_scl_m2 */ +- <2 RK_PC3 9 &pcfg_pull_none_smt>, +- /* i2c6_sda_m2 */ +- <2 RK_PC2 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c7 { +- /omit-if-no-ref/ +- i2c7m1_xfer: i2c7m1-xfer { +- rockchip,pins = +- /* i2c7_scl_m1 */ +- <4 RK_PC3 9 &pcfg_pull_none_smt>, +- /* i2c7_sda_m1 */ +- <4 RK_PC4 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c8 { +- /omit-if-no-ref/ +- i2c8m1_xfer: i2c8m1-xfer { +- rockchip,pins = +- /* i2c8_scl_m1 */ +- <2 RK_PB0 9 &pcfg_pull_none_smt>, +- /* i2c8_sda_m1 */ +- <2 RK_PB1 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2s2 { +- /omit-if-no-ref/ +- i2s2m0_lrck: i2s2m0-lrck { +- rockchip,pins = +- /* i2s2m0_lrck */ +- <2 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_mclk: i2s2m0-mclk { +- rockchip,pins = +- /* i2s2m0_mclk */ +- <2 RK_PB6 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sclk: i2s2m0-sclk { +- rockchip,pins = +- /* i2s2m0_sclk */ +- <2 RK_PB7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sdi: i2s2m0-sdi { +- rockchip,pins = +- /* i2s2m0_sdi */ +- <2 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sdo: i2s2m0-sdo { +- rockchip,pins = +- /* i2s2m0_sdo */ +- <4 RK_PC3 2 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- /omit-if-no-ref/ +- pwm2m2_pins: pwm2m2-pins { +- rockchip,pins = +- /* pwm2_m2 */ +- <4 RK_PC2 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm4 { +- /omit-if-no-ref/ +- pwm4m1_pins: pwm4m1-pins { +- rockchip,pins = +- /* pwm4_m1 */ +- <4 RK_PC3 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm5 { +- /omit-if-no-ref/ +- pwm5m2_pins: pwm5m2-pins { +- rockchip,pins = +- /* pwm5_m2 */ +- <4 RK_PC4 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm6 { +- /omit-if-no-ref/ +- pwm6m2_pins: pwm6m2-pins { +- rockchip,pins = +- /* pwm6_m2 */ +- <4 RK_PC5 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm7 { +- /omit-if-no-ref/ +- pwm7m3_pins: pwm7m3-pins { +- rockchip,pins = +- /* pwm7_ir_m3 */ +- <4 RK_PC6 11 &pcfg_pull_none>; +- }; +- }; +- +- sdio { +- /omit-if-no-ref/ +- sdiom0_pins: sdiom0-pins { +- rockchip,pins = +- /* sdio_clk_m0 */ +- <2 RK_PB3 2 &pcfg_pull_none>, +- /* sdio_cmd_m0 */ +- <2 RK_PB2 2 &pcfg_pull_none>, +- /* sdio_d0_m0 */ +- <2 RK_PA6 2 &pcfg_pull_none>, +- /* sdio_d1_m0 */ +- <2 RK_PA7 2 &pcfg_pull_none>, +- /* sdio_d2_m0 */ +- <2 RK_PB0 2 &pcfg_pull_none>, +- /* sdio_d3_m0 */ +- <2 RK_PB1 2 &pcfg_pull_none>; +- }; +- }; +- +- spi1 { +- /omit-if-no-ref/ +- spi1m0_pins: spi1m0-pins { +- rockchip,pins = +- /* spi1_clk_m0 */ +- <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, +- /* spi1_miso_m0 */ +- <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, +- /* spi1_mosi_m0 */ +- <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m0_cs0: spi1m0-cs0 { +- rockchip,pins = +- /* spi1_cs0_m0 */ +- <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m0_cs1: spi1m0-cs1 { +- rockchip,pins = +- /* spi1_cs1_m0 */ +- <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- spi3 { +- /omit-if-no-ref/ +- spi3m0_pins: spi3m0-pins { +- rockchip,pins = +- /* spi3_clk_m0 */ +- <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, +- /* spi3_miso_m0 */ +- <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, +- /* spi3_mosi_m0 */ +- <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m0_cs0: spi3m0-cs0 { +- rockchip,pins = +- /* spi3_cs0_m0 */ +- <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m0_cs1: spi3m0-cs1 { +- rockchip,pins = +- /* spi3_cs1_m0 */ +- <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- uart1 { +- /omit-if-no-ref/ +- uart1m0_xfer: uart1m0-xfer { +- rockchip,pins = +- /* uart1_rx_m0 */ +- <2 RK_PB6 10 &pcfg_pull_up>, +- /* uart1_tx_m0 */ +- <2 RK_PB7 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart1m0_ctsn: uart1m0-ctsn { +- rockchip,pins = +- /* uart1m0_ctsn */ +- <2 RK_PC1 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart1m0_rtsn: uart1m0-rtsn { +- rockchip,pins = +- /* uart1m0_rtsn */ +- <2 RK_PC0 10 &pcfg_pull_none>; +- }; +- }; +- +- uart6 { +- /omit-if-no-ref/ +- uart6m0_xfer: uart6m0-xfer { +- rockchip,pins = +- /* uart6_rx_m0 */ +- <2 RK_PA6 10 &pcfg_pull_up>, +- /* uart6_tx_m0 */ +- <2 RK_PA7 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart6m0_ctsn: uart6m0-ctsn { +- rockchip,pins = +- /* uart6m0_ctsn */ +- <2 RK_PB1 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart6m0_rtsn: uart6m0-rtsn { +- rockchip,pins = +- /* uart6m0_rtsn */ +- <2 RK_PB0 10 &pcfg_pull_none>; +- }; +- }; +- +- uart7 { +- /omit-if-no-ref/ +- uart7m0_xfer: uart7m0-xfer { +- rockchip,pins = +- /* uart7_rx_m0 */ +- <2 RK_PB4 10 &pcfg_pull_up>, +- /* uart7_tx_m0 */ +- <2 RK_PB5 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart7m0_ctsn: uart7m0-ctsn { +- rockchip,pins = +- /* uart7m0_ctsn */ +- <4 RK_PC6 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart7m0_rtsn: uart7m0-rtsn { +- rockchip,pins = +- /* uart7m0_rtsn */ +- <4 RK_PC2 10 &pcfg_pull_none>; +- }; +- }; +- +- uart9 { +- /omit-if-no-ref/ +- uart9m0_xfer: uart9m0-xfer { +- rockchip,pins = +- /* uart9_rx_m0 */ +- <2 RK_PC4 10 &pcfg_pull_up>, +- /* uart9_tx_m0 */ +- <2 RK_PC2 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart9m0_ctsn: uart9m0-ctsn { +- rockchip,pins = +- /* uart9m0_ctsn */ +- <4 RK_PC5 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart9m0_rtsn: uart9m0-rtsn { +- rockchip,pins = +- /* uart9m0_rtsn */ +- <4 RK_PC4 10 &pcfg_pull_none>; +- }; +- }; +-}; +--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi ++++ /dev/null +@@ -1,3447 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. +- */ +- +-#include +-#include "rockchip-pinconf.dtsi" +- +-/* +- * This file is auto generated by pin2dts tool, please keep these code +- * by adding changes at end of this file. +- */ +-&pinctrl { +- auddsm { +- /omit-if-no-ref/ +- auddsm_pins: auddsm-pins { +- rockchip,pins = +- /* auddsm_ln */ +- <3 RK_PA1 4 &pcfg_pull_none>, +- /* auddsm_lp */ +- <3 RK_PA2 4 &pcfg_pull_none>, +- /* auddsm_rn */ +- <3 RK_PA3 4 &pcfg_pull_none>, +- /* auddsm_rp */ +- <3 RK_PA4 4 &pcfg_pull_none>; +- }; +- }; +- +- bt1120 { +- /omit-if-no-ref/ +- bt1120_pins: bt1120-pins { +- rockchip,pins = +- /* bt1120_clkout */ +- <4 RK_PB0 2 &pcfg_pull_none>, +- /* bt1120_d0 */ +- <4 RK_PA0 2 &pcfg_pull_none>, +- /* bt1120_d1 */ +- <4 RK_PA1 2 &pcfg_pull_none>, +- /* bt1120_d2 */ +- <4 RK_PA2 2 &pcfg_pull_none>, +- /* bt1120_d3 */ +- <4 RK_PA3 2 &pcfg_pull_none>, +- /* bt1120_d4 */ +- <4 RK_PA4 2 &pcfg_pull_none>, +- /* bt1120_d5 */ +- <4 RK_PA5 2 &pcfg_pull_none>, +- /* bt1120_d6 */ +- <4 RK_PA6 2 &pcfg_pull_none>, +- /* bt1120_d7 */ +- <4 RK_PA7 2 &pcfg_pull_none>, +- /* bt1120_d8 */ +- <4 RK_PB2 2 &pcfg_pull_none>, +- /* bt1120_d9 */ +- <4 RK_PB3 2 &pcfg_pull_none>, +- /* bt1120_d10 */ +- <4 RK_PB4 2 &pcfg_pull_none>, +- /* bt1120_d11 */ +- <4 RK_PB5 2 &pcfg_pull_none>, +- /* bt1120_d12 */ +- <4 RK_PB6 2 &pcfg_pull_none>, +- /* bt1120_d13 */ +- <4 RK_PB7 2 &pcfg_pull_none>, +- /* bt1120_d14 */ +- <4 RK_PC0 2 &pcfg_pull_none>, +- /* bt1120_d15 */ +- <4 RK_PC1 2 &pcfg_pull_none>; +- }; +- }; +- +- can0 { +- /omit-if-no-ref/ +- can0m0_pins: can0m0-pins { +- rockchip,pins = +- /* can0_rx_m0 */ +- <0 RK_PC0 11 &pcfg_pull_none>, +- /* can0_tx_m0 */ +- <0 RK_PB7 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- can0m1_pins: can0m1-pins { +- rockchip,pins = +- /* can0_rx_m1 */ +- <4 RK_PD5 9 &pcfg_pull_none>, +- /* can0_tx_m1 */ +- <4 RK_PD4 9 &pcfg_pull_none>; +- }; +- }; +- +- can1 { +- /omit-if-no-ref/ +- can1m0_pins: can1m0-pins { +- rockchip,pins = +- /* can1_rx_m0 */ +- <3 RK_PB5 9 &pcfg_pull_none>, +- /* can1_tx_m0 */ +- <3 RK_PB6 9 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- can1m1_pins: can1m1-pins { +- rockchip,pins = +- /* can1_rx_m1 */ +- <4 RK_PB2 12 &pcfg_pull_none>, +- /* can1_tx_m1 */ +- <4 RK_PB3 12 &pcfg_pull_none>; +- }; +- }; +- +- can2 { +- /omit-if-no-ref/ +- can2m0_pins: can2m0-pins { +- rockchip,pins = +- /* can2_rx_m0 */ +- <3 RK_PC4 9 &pcfg_pull_none>, +- /* can2_tx_m0 */ +- <3 RK_PC5 9 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- can2m1_pins: can2m1-pins { +- rockchip,pins = +- /* can2_rx_m1 */ +- <0 RK_PD4 10 &pcfg_pull_none>, +- /* can2_tx_m1 */ +- <0 RK_PD5 10 &pcfg_pull_none>; +- }; +- }; +- +- cif { +- /omit-if-no-ref/ +- cif_clk: cif-clk { +- rockchip,pins = +- /* cif_clkout */ +- <4 RK_PB4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- cif_dvp_clk: cif-dvp-clk { +- rockchip,pins = +- /* cif_clkin */ +- <4 RK_PB0 1 &pcfg_pull_none>, +- /* cif_href */ +- <4 RK_PB2 1 &pcfg_pull_none>, +- /* cif_vsync */ +- <4 RK_PB3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- cif_dvp_bus16: cif-dvp-bus16 { +- rockchip,pins = +- /* cif_d8 */ +- <3 RK_PC4 1 &pcfg_pull_none>, +- /* cif_d9 */ +- <3 RK_PC5 1 &pcfg_pull_none>, +- /* cif_d10 */ +- <3 RK_PC6 1 &pcfg_pull_none>, +- /* cif_d11 */ +- <3 RK_PC7 1 &pcfg_pull_none>, +- /* cif_d12 */ +- <3 RK_PD0 1 &pcfg_pull_none>, +- /* cif_d13 */ +- <3 RK_PD1 1 &pcfg_pull_none>, +- /* cif_d14 */ +- <3 RK_PD2 1 &pcfg_pull_none>, +- /* cif_d15 */ +- <3 RK_PD3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- cif_dvp_bus8: cif-dvp-bus8 { +- rockchip,pins = +- /* cif_d0 */ +- <4 RK_PA0 1 &pcfg_pull_none>, +- /* cif_d1 */ +- <4 RK_PA1 1 &pcfg_pull_none>, +- /* cif_d2 */ +- <4 RK_PA2 1 &pcfg_pull_none>, +- /* cif_d3 */ +- <4 RK_PA3 1 &pcfg_pull_none>, +- /* cif_d4 */ +- <4 RK_PA4 1 &pcfg_pull_none>, +- /* cif_d5 */ +- <4 RK_PA5 1 &pcfg_pull_none>, +- /* cif_d6 */ +- <4 RK_PA6 1 &pcfg_pull_none>, +- /* cif_d7 */ +- <4 RK_PA7 1 &pcfg_pull_none>; +- }; +- }; +- +- clk32k { +- /omit-if-no-ref/ +- clk32k_in: clk32k-in { +- rockchip,pins = +- /* clk32k_in */ +- <0 RK_PB2 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- clk32k_out0: clk32k-out0 { +- rockchip,pins = +- /* clk32k_out0 */ +- <0 RK_PB2 2 &pcfg_pull_none>; +- }; +- }; +- +- cpu { +- /omit-if-no-ref/ +- cpu_pins: cpu-pins { +- rockchip,pins = +- /* cpu_big0_avs */ +- <0 RK_PD1 2 &pcfg_pull_none>, +- /* cpu_big1_avs */ +- <0 RK_PD5 2 &pcfg_pull_none>; +- }; +- }; +- +- ddrphych0 { +- /omit-if-no-ref/ +- ddrphych0_pins: ddrphych0-pins { +- rockchip,pins = +- /* ddrphych0_dtb0 */ +- <4 RK_PA0 7 &pcfg_pull_none>, +- /* ddrphych0_dtb1 */ +- <4 RK_PA1 7 &pcfg_pull_none>, +- /* ddrphych0_dtb2 */ +- <4 RK_PA2 7 &pcfg_pull_none>, +- /* ddrphych0_dtb3 */ +- <4 RK_PA3 7 &pcfg_pull_none>; +- }; +- }; +- +- ddrphych1 { +- /omit-if-no-ref/ +- ddrphych1_pins: ddrphych1-pins { +- rockchip,pins = +- /* ddrphych1_dtb0 */ +- <4 RK_PA4 7 &pcfg_pull_none>, +- /* ddrphych1_dtb1 */ +- <4 RK_PA5 7 &pcfg_pull_none>, +- /* ddrphych1_dtb2 */ +- <4 RK_PA6 7 &pcfg_pull_none>, +- /* ddrphych1_dtb3 */ +- <4 RK_PA7 7 &pcfg_pull_none>; +- }; +- }; +- +- ddrphych2 { +- /omit-if-no-ref/ +- ddrphych2_pins: ddrphych2-pins { +- rockchip,pins = +- /* ddrphych2_dtb0 */ +- <4 RK_PB0 7 &pcfg_pull_none>, +- /* ddrphych2_dtb1 */ +- <4 RK_PB1 7 &pcfg_pull_none>, +- /* ddrphych2_dtb2 */ +- <4 RK_PB2 7 &pcfg_pull_none>, +- /* ddrphych2_dtb3 */ +- <4 RK_PB3 7 &pcfg_pull_none>; +- }; +- }; +- +- ddrphych3 { +- /omit-if-no-ref/ +- ddrphych3_pins: ddrphych3-pins { +- rockchip,pins = +- /* ddrphych3_dtb0 */ +- <4 RK_PB4 7 &pcfg_pull_none>, +- /* ddrphych3_dtb1 */ +- <4 RK_PB5 7 &pcfg_pull_none>, +- /* ddrphych3_dtb2 */ +- <4 RK_PB6 7 &pcfg_pull_none>, +- /* ddrphych3_dtb3 */ +- <4 RK_PB7 7 &pcfg_pull_none>; +- }; +- }; +- +- dp0 { +- /omit-if-no-ref/ +- dp0m0_pins: dp0m0-pins { +- rockchip,pins = +- /* dp0_hpdin_m0 */ +- <4 RK_PB4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- dp0m1_pins: dp0m1-pins { +- rockchip,pins = +- /* dp0_hpdin_m1 */ +- <0 RK_PC4 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- dp0m2_pins: dp0m2-pins { +- rockchip,pins = +- /* dp0_hpdin_m2 */ +- <1 RK_PA0 5 &pcfg_pull_none>; +- }; +- }; +- +- dp1 { +- /omit-if-no-ref/ +- dp1m0_pins: dp1m0-pins { +- rockchip,pins = +- /* dp1_hpdin_m0 */ +- <3 RK_PD5 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- dp1m1_pins: dp1m1-pins { +- rockchip,pins = +- /* dp1_hpdin_m1 */ +- <0 RK_PC5 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- dp1m2_pins: dp1m2-pins { +- rockchip,pins = +- /* dp1_hpdin_m2 */ +- <1 RK_PA1 5 &pcfg_pull_none>; +- }; +- }; +- +- emmc { +- /omit-if-no-ref/ +- emmc_rstnout: emmc-rstnout { +- rockchip,pins = +- /* emmc_rstn */ +- <2 RK_PA3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- emmc_bus8: emmc-bus8 { +- rockchip,pins = +- /* emmc_d0 */ +- <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d1 */ +- <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d2 */ +- <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d3 */ +- <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d4 */ +- <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d5 */ +- <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d6 */ +- <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, +- /* emmc_d7 */ +- <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- emmc_clk: emmc-clk { +- rockchip,pins = +- /* emmc_clkout */ +- <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- emmc_cmd: emmc-cmd { +- rockchip,pins = +- /* emmc_cmd */ +- <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- emmc_data_strobe: emmc-data-strobe { +- rockchip,pins = +- /* emmc_data_strobe */ +- <2 RK_PA2 1 &pcfg_pull_down>; +- }; +- }; +- +- eth1 { +- /omit-if-no-ref/ +- eth1_pins: eth1-pins { +- rockchip,pins = +- /* eth1_refclko_25m */ +- <3 RK_PA6 1 &pcfg_pull_none>; +- }; +- }; +- +- fspi { +- /omit-if-no-ref/ +- fspim0_pins: fspim0-pins { +- rockchip,pins = +- /* fspi_clk_m0 */ +- <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, +- /* fspi_cs0n_m0 */ +- <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, +- /* fspi_d0_m0 */ +- <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, +- /* fspi_d1_m0 */ +- <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, +- /* fspi_d2_m0 */ +- <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, +- /* fspi_d3_m0 */ +- <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- fspim0_cs1: fspim0-cs1 { +- rockchip,pins = +- /* fspi_cs1n_m0 */ +- <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- fspim2_pins: fspim2-pins { +- rockchip,pins = +- /* fspi_clk_m2 */ +- <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, +- /* fspi_cs0n_m2 */ +- <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, +- /* fspi_d0_m2 */ +- <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, +- /* fspi_d1_m2 */ +- <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, +- /* fspi_d2_m2 */ +- <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, +- /* fspi_d3_m2 */ +- <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- fspim2_cs1: fspim2-cs1 { +- rockchip,pins = +- /* fspi_cs1n_m2 */ +- <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; +- }; +- }; +- +- gmac1 { +- /omit-if-no-ref/ +- gmac1_miim: gmac1-miim { +- rockchip,pins = +- /* gmac1_mdc */ +- <3 RK_PC2 1 &pcfg_pull_none>, +- /* gmac1_mdio */ +- <3 RK_PC3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_clkinout: gmac1-clkinout { +- rockchip,pins = +- /* gmac1_mclkinout */ +- <3 RK_PB6 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_rx_bus2: gmac1-rx-bus2 { +- rockchip,pins = +- /* gmac1_rxd0 */ +- <3 RK_PA7 1 &pcfg_pull_none>, +- /* gmac1_rxd1 */ +- <3 RK_PB0 1 &pcfg_pull_none>, +- /* gmac1_rxdv_crs */ +- <3 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_tx_bus2: gmac1-tx-bus2 { +- rockchip,pins = +- /* gmac1_txd0 */ +- <3 RK_PB3 1 &pcfg_pull_none>, +- /* gmac1_txd1 */ +- <3 RK_PB4 1 &pcfg_pull_none>, +- /* gmac1_txen */ +- <3 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_rgmii_clk: gmac1-rgmii-clk { +- rockchip,pins = +- /* gmac1_rxclk */ +- <3 RK_PA5 1 &pcfg_pull_none>, +- /* gmac1_txclk */ +- <3 RK_PA4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_rgmii_bus: gmac1-rgmii-bus { +- rockchip,pins = +- /* gmac1_rxd2 */ +- <3 RK_PA2 1 &pcfg_pull_none>, +- /* gmac1_rxd3 */ +- <3 RK_PA3 1 &pcfg_pull_none>, +- /* gmac1_txd2 */ +- <3 RK_PA0 1 &pcfg_pull_none>, +- /* gmac1_txd3 */ +- <3 RK_PA1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_ppsclk: gmac1-ppsclk { +- rockchip,pins = +- /* gmac1_ppsclk */ +- <3 RK_PC1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_ppstrig: gmac1-ppstrig { +- rockchip,pins = +- /* gmac1_ppstrig */ +- <3 RK_PC0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { +- rockchip,pins = +- /* gmac1_ptp_ref_clk */ +- <3 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- gmac1_txer: gmac1-txer { +- rockchip,pins = +- /* gmac1_txer */ +- <3 RK_PB2 1 &pcfg_pull_none>; +- }; +- }; +- +- gpu { +- /omit-if-no-ref/ +- gpu_pins: gpu-pins { +- rockchip,pins = +- /* gpu_avs */ +- <0 RK_PC5 2 &pcfg_pull_none>; +- }; +- }; +- +- hdmi { +- /omit-if-no-ref/ +- hdmim0_rx_cec: hdmim0-rx-cec { +- rockchip,pins = +- /* hdmim0_rx_cec */ +- <4 RK_PB5 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_rx_hpdin: hdmim0-rx-hpdin { +- rockchip,pins = +- /* hdmim0_rx_hpdin */ +- <4 RK_PB6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_rx_scl: hdmim0-rx-scl { +- rockchip,pins = +- /* hdmim0_rx_scl */ +- <0 RK_PD2 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_rx_sda: hdmim0-rx-sda { +- rockchip,pins = +- /* hdmim0_rx_sda */ +- <0 RK_PD1 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_tx0_cec: hdmim0-tx0-cec { +- rockchip,pins = +- /* hdmim0_tx0_cec */ +- <4 RK_PC1 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_tx0_hpd: hdmim0-tx0-hpd { +- rockchip,pins = +- /* hdmim0_tx0_hpd */ +- <1 RK_PA5 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_tx0_scl: hdmim0-tx0-scl { +- rockchip,pins = +- /* hdmim0_tx0_scl */ +- <4 RK_PB7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_tx0_sda: hdmim0-tx0-sda { +- rockchip,pins = +- /* hdmim0_tx0_sda */ +- <4 RK_PC0 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim0_tx1_hpd: hdmim0-tx1-hpd { +- rockchip,pins = +- /* hdmim0_tx1_hpd */ +- <1 RK_PA6 5 &pcfg_pull_none>; +- }; +- /omit-if-no-ref/ +- hdmim1_rx_cec: hdmim1-rx-cec { +- rockchip,pins = +- /* hdmim1_rx_cec */ +- <3 RK_PD1 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_rx_hpdin: hdmim1-rx-hpdin { +- rockchip,pins = +- /* hdmim1_rx_hpdin */ +- <3 RK_PD4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_rx_scl: hdmim1-rx-scl { +- rockchip,pins = +- /* hdmim1_rx_scl */ +- <3 RK_PD2 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_rx_sda: hdmim1-rx-sda { +- rockchip,pins = +- /* hdmim1_rx_sda */ +- <3 RK_PD3 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_tx0_cec: hdmim1-tx0-cec { +- rockchip,pins = +- /* hdmim1_tx0_cec */ +- <0 RK_PD1 13 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_tx0_hpd: hdmim1-tx0-hpd { +- rockchip,pins = +- /* hdmim1_tx0_hpd */ +- <3 RK_PD4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_tx0_scl: hdmim1-tx0-scl { +- rockchip,pins = +- /* hdmim1_tx0_scl */ +- <0 RK_PD5 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_tx0_sda: hdmim1-tx0-sda { +- rockchip,pins = +- /* hdmim1_tx0_sda */ +- <0 RK_PD4 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_tx1_cec: hdmim1-tx1-cec { +- rockchip,pins = +- /* hdmim1_tx1_cec */ +- <0 RK_PD2 13 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_tx1_hpd: hdmim1-tx1-hpd { +- rockchip,pins = +- /* hdmim1_tx1_hpd */ +- <3 RK_PB7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_tx1_scl: hdmim1-tx1-scl { +- rockchip,pins = +- /* hdmim1_tx1_scl */ +- <3 RK_PC6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim1_tx1_sda: hdmim1-tx1-sda { +- rockchip,pins = +- /* hdmim1_tx1_sda */ +- <3 RK_PC5 5 &pcfg_pull_none>; +- }; +- /omit-if-no-ref/ +- hdmim2_rx_cec: hdmim2-rx-cec { +- rockchip,pins = +- /* hdmim2_rx_cec */ +- <1 RK_PB7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim2_rx_hpdin: hdmim2-rx-hpdin { +- rockchip,pins = +- /* hdmim2_rx_hpdin */ +- <1 RK_PB6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim2_rx_scl: hdmim2-rx-scl { +- rockchip,pins = +- /* hdmim2_rx_scl */ +- <1 RK_PD6 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim2_rx_sda: hdmim2-rx-sda { +- rockchip,pins = +- /* hdmim2_rx_sda */ +- <1 RK_PD7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim2_tx0_scl: hdmim2-tx0-scl { +- rockchip,pins = +- /* hdmim2_tx0_scl */ +- <3 RK_PC7 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim2_tx0_sda: hdmim2-tx0-sda { +- rockchip,pins = +- /* hdmim2_tx0_sda */ +- <3 RK_PD0 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim2_tx1_cec: hdmim2-tx1-cec { +- rockchip,pins = +- /* hdmim2_tx1_cec */ +- <3 RK_PC4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim2_tx1_scl: hdmim2-tx1-scl { +- rockchip,pins = +- /* hdmim2_tx1_scl */ +- <1 RK_PA4 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmim2_tx1_sda: hdmim2-tx1-sda { +- rockchip,pins = +- /* hdmim2_tx1_sda */ +- <1 RK_PA3 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmi_debug0: hdmi-debug0 { +- rockchip,pins = +- /* hdmi_debug0 */ +- <1 RK_PA7 7 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmi_debug1: hdmi-debug1 { +- rockchip,pins = +- /* hdmi_debug1 */ +- <1 RK_PB0 7 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmi_debug2: hdmi-debug2 { +- rockchip,pins = +- /* hdmi_debug2 */ +- <1 RK_PB1 7 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmi_debug3: hdmi-debug3 { +- rockchip,pins = +- /* hdmi_debug3 */ +- <1 RK_PB2 7 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmi_debug4: hdmi-debug4 { +- rockchip,pins = +- /* hdmi_debug4 */ +- <1 RK_PB3 7 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmi_debug5: hdmi-debug5 { +- rockchip,pins = +- /* hdmi_debug5 */ +- <1 RK_PB4 7 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- hdmi_debug6: hdmi-debug6 { +- rockchip,pins = +- /* hdmi_debug6 */ +- <1 RK_PA0 7 &pcfg_pull_none>; +- }; +- }; +- +- i2c0 { +- /omit-if-no-ref/ +- i2c0m0_xfer: i2c0m0-xfer { +- rockchip,pins = +- /* i2c0_scl_m0 */ +- <0 RK_PB3 2 &pcfg_pull_none_smt>, +- /* i2c0_sda_m0 */ +- <0 RK_PA6 2 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c0m2_xfer: i2c0m2-xfer { +- rockchip,pins = +- /* i2c0_scl_m2 */ +- <0 RK_PD1 3 &pcfg_pull_none_smt>, +- /* i2c0_sda_m2 */ +- <0 RK_PD2 3 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c1 { +- /omit-if-no-ref/ +- i2c1m0_xfer: i2c1m0-xfer { +- rockchip,pins = +- /* i2c1_scl_m0 */ +- <0 RK_PB5 9 &pcfg_pull_none_smt>, +- /* i2c1_sda_m0 */ +- <0 RK_PB6 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c1m1_xfer: i2c1m1-xfer { +- rockchip,pins = +- /* i2c1_scl_m1 */ +- <0 RK_PB0 2 &pcfg_pull_none_smt>, +- /* i2c1_sda_m1 */ +- <0 RK_PB1 2 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c1m2_xfer: i2c1m2-xfer { +- rockchip,pins = +- /* i2c1_scl_m2 */ +- <0 RK_PD4 9 &pcfg_pull_none_smt>, +- /* i2c1_sda_m2 */ +- <0 RK_PD5 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c1m3_xfer: i2c1m3-xfer { +- rockchip,pins = +- /* i2c1_scl_m3 */ +- <2 RK_PD4 9 &pcfg_pull_none_smt>, +- /* i2c1_sda_m3 */ +- <2 RK_PD5 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c1m4_xfer: i2c1m4-xfer { +- rockchip,pins = +- /* i2c1_scl_m4 */ +- <1 RK_PD2 9 &pcfg_pull_none_smt>, +- /* i2c1_sda_m4 */ +- <1 RK_PD3 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c2 { +- /omit-if-no-ref/ +- i2c2m0_xfer: i2c2m0-xfer { +- rockchip,pins = +- /* i2c2_scl_m0 */ +- <0 RK_PB7 9 &pcfg_pull_none_smt>, +- /* i2c2_sda_m0 */ +- <0 RK_PC0 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c2m2_xfer: i2c2m2-xfer { +- rockchip,pins = +- /* i2c2_scl_m2 */ +- <2 RK_PA3 9 &pcfg_pull_none_smt>, +- /* i2c2_sda_m2 */ +- <2 RK_PA2 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c2m3_xfer: i2c2m3-xfer { +- rockchip,pins = +- /* i2c2_scl_m3 */ +- <1 RK_PC5 9 &pcfg_pull_none_smt>, +- /* i2c2_sda_m3 */ +- <1 RK_PC4 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c2m4_xfer: i2c2m4-xfer { +- rockchip,pins = +- /* i2c2_scl_m4 */ +- <1 RK_PA1 9 &pcfg_pull_none_smt>, +- /* i2c2_sda_m4 */ +- <1 RK_PA0 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c3 { +- /omit-if-no-ref/ +- i2c3m0_xfer: i2c3m0-xfer { +- rockchip,pins = +- /* i2c3_scl_m0 */ +- <1 RK_PC1 9 &pcfg_pull_none_smt>, +- /* i2c3_sda_m0 */ +- <1 RK_PC0 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c3m1_xfer: i2c3m1-xfer { +- rockchip,pins = +- /* i2c3_scl_m1 */ +- <3 RK_PB7 9 &pcfg_pull_none_smt>, +- /* i2c3_sda_m1 */ +- <3 RK_PC0 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c3m2_xfer: i2c3m2-xfer { +- rockchip,pins = +- /* i2c3_scl_m2 */ +- <4 RK_PA4 9 &pcfg_pull_none_smt>, +- /* i2c3_sda_m2 */ +- <4 RK_PA5 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c3m4_xfer: i2c3m4-xfer { +- rockchip,pins = +- /* i2c3_scl_m4 */ +- <4 RK_PD0 9 &pcfg_pull_none_smt>, +- /* i2c3_sda_m4 */ +- <4 RK_PD1 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c4 { +- /omit-if-no-ref/ +- i2c4m0_xfer: i2c4m0-xfer { +- rockchip,pins = +- /* i2c4_scl_m0 */ +- <3 RK_PA6 9 &pcfg_pull_none_smt>, +- /* i2c4_sda_m0 */ +- <3 RK_PA5 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c4m2_xfer: i2c4m2-xfer { +- rockchip,pins = +- /* i2c4_scl_m2 */ +- <0 RK_PC5 9 &pcfg_pull_none_smt>, +- /* i2c4_sda_m2 */ +- <0 RK_PC4 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c4m3_xfer: i2c4m3-xfer { +- rockchip,pins = +- /* i2c4_scl_m3 */ +- <1 RK_PA3 9 &pcfg_pull_none_smt>, +- /* i2c4_sda_m3 */ +- <1 RK_PA2 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c4m4_xfer: i2c4m4-xfer { +- rockchip,pins = +- /* i2c4_scl_m4 */ +- <1 RK_PC7 9 &pcfg_pull_none_smt>, +- /* i2c4_sda_m4 */ +- <1 RK_PC6 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c5 { +- /omit-if-no-ref/ +- i2c5m0_xfer: i2c5m0-xfer { +- rockchip,pins = +- /* i2c5_scl_m0 */ +- <3 RK_PC7 9 &pcfg_pull_none_smt>, +- /* i2c5_sda_m0 */ +- <3 RK_PD0 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c5m1_xfer: i2c5m1-xfer { +- rockchip,pins = +- /* i2c5_scl_m1 */ +- <4 RK_PB6 9 &pcfg_pull_none_smt>, +- /* i2c5_sda_m1 */ +- <4 RK_PB7 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c5m2_xfer: i2c5m2-xfer { +- rockchip,pins = +- /* i2c5_scl_m2 */ +- <4 RK_PA6 9 &pcfg_pull_none_smt>, +- /* i2c5_sda_m2 */ +- <4 RK_PA7 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c5m3_xfer: i2c5m3-xfer { +- rockchip,pins = +- /* i2c5_scl_m3 */ +- <1 RK_PB6 9 &pcfg_pull_none_smt>, +- /* i2c5_sda_m3 */ +- <1 RK_PB7 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c6 { +- /omit-if-no-ref/ +- i2c6m0_xfer: i2c6m0-xfer { +- rockchip,pins = +- /* i2c6_scl_m0 */ +- <0 RK_PD0 9 &pcfg_pull_none_smt>, +- /* i2c6_sda_m0 */ +- <0 RK_PC7 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c6m1_xfer: i2c6m1-xfer { +- rockchip,pins = +- /* i2c6_scl_m1 */ +- <1 RK_PC3 9 &pcfg_pull_none_smt>, +- /* i2c6_sda_m1 */ +- <1 RK_PC2 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c6m3_xfer: i2c6m3-xfer { +- rockchip,pins = +- /* i2c6_scl_m3 */ +- <4 RK_PB1 9 &pcfg_pull_none_smt>, +- /* i2c6_sda_m3 */ +- <4 RK_PB0 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c6m4_xfer: i2c6m4-xfer { +- rockchip,pins = +- /* i2c6_scl_m4 */ +- <3 RK_PA1 9 &pcfg_pull_none_smt>, +- /* i2c6_sda_m4 */ +- <3 RK_PA0 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c7 { +- /omit-if-no-ref/ +- i2c7m0_xfer: i2c7m0-xfer { +- rockchip,pins = +- /* i2c7_scl_m0 */ +- <1 RK_PD0 9 &pcfg_pull_none_smt>, +- /* i2c7_sda_m0 */ +- <1 RK_PD1 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c7m2_xfer: i2c7m2-xfer { +- rockchip,pins = +- /* i2c7_scl_m2 */ +- <3 RK_PD2 9 &pcfg_pull_none_smt>, +- /* i2c7_sda_m2 */ +- <3 RK_PD3 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c7m3_xfer: i2c7m3-xfer { +- rockchip,pins = +- /* i2c7_scl_m3 */ +- <4 RK_PB2 9 &pcfg_pull_none_smt>, +- /* i2c7_sda_m3 */ +- <4 RK_PB3 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2c8 { +- /omit-if-no-ref/ +- i2c8m0_xfer: i2c8m0-xfer { +- rockchip,pins = +- /* i2c8_scl_m0 */ +- <4 RK_PD2 9 &pcfg_pull_none_smt>, +- /* i2c8_sda_m0 */ +- <4 RK_PD3 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c8m2_xfer: i2c8m2-xfer { +- rockchip,pins = +- /* i2c8_scl_m2 */ +- <1 RK_PD6 9 &pcfg_pull_none_smt>, +- /* i2c8_sda_m2 */ +- <1 RK_PD7 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c8m3_xfer: i2c8m3-xfer { +- rockchip,pins = +- /* i2c8_scl_m3 */ +- <4 RK_PC0 9 &pcfg_pull_none_smt>, +- /* i2c8_sda_m3 */ +- <4 RK_PC1 9 &pcfg_pull_none_smt>; +- }; +- +- /omit-if-no-ref/ +- i2c8m4_xfer: i2c8m4-xfer { +- rockchip,pins = +- /* i2c8_scl_m4 */ +- <3 RK_PC2 9 &pcfg_pull_none_smt>, +- /* i2c8_sda_m4 */ +- <3 RK_PC3 9 &pcfg_pull_none_smt>; +- }; +- }; +- +- i2s0 { +- /omit-if-no-ref/ +- i2s0_lrck: i2s0-lrck { +- rockchip,pins = +- /* i2s0_lrck */ +- <1 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_mclk: i2s0-mclk { +- rockchip,pins = +- /* i2s0_mclk */ +- <1 RK_PC2 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sclk: i2s0-sclk { +- rockchip,pins = +- /* i2s0_sclk */ +- <1 RK_PC3 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sdi0: i2s0-sdi0 { +- rockchip,pins = +- /* i2s0_sdi0 */ +- <1 RK_PD4 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sdi1: i2s0-sdi1 { +- rockchip,pins = +- /* i2s0_sdi1 */ +- <1 RK_PD3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sdi2: i2s0-sdi2 { +- rockchip,pins = +- /* i2s0_sdi2 */ +- <1 RK_PD2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sdi3: i2s0-sdi3 { +- rockchip,pins = +- /* i2s0_sdi3 */ +- <1 RK_PD1 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sdo0: i2s0-sdo0 { +- rockchip,pins = +- /* i2s0_sdo0 */ +- <1 RK_PC7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sdo1: i2s0-sdo1 { +- rockchip,pins = +- /* i2s0_sdo1 */ +- <1 RK_PD0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sdo2: i2s0-sdo2 { +- rockchip,pins = +- /* i2s0_sdo2 */ +- <1 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s0_sdo3: i2s0-sdo3 { +- rockchip,pins = +- /* i2s0_sdo3 */ +- <1 RK_PD2 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s1 { +- /omit-if-no-ref/ +- i2s1m0_lrck: i2s1m0-lrck { +- rockchip,pins = +- /* i2s1m0_lrck */ +- <4 RK_PA2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_mclk: i2s1m0-mclk { +- rockchip,pins = +- /* i2s1m0_mclk */ +- <4 RK_PA0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sclk: i2s1m0-sclk { +- rockchip,pins = +- /* i2s1m0_sclk */ +- <4 RK_PA1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdi0: i2s1m0-sdi0 { +- rockchip,pins = +- /* i2s1m0_sdi0 */ +- <4 RK_PA5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdi1: i2s1m0-sdi1 { +- rockchip,pins = +- /* i2s1m0_sdi1 */ +- <4 RK_PA6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdi2: i2s1m0-sdi2 { +- rockchip,pins = +- /* i2s1m0_sdi2 */ +- <4 RK_PA7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdi3: i2s1m0-sdi3 { +- rockchip,pins = +- /* i2s1m0_sdi3 */ +- <4 RK_PB0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdo0: i2s1m0-sdo0 { +- rockchip,pins = +- /* i2s1m0_sdo0 */ +- <4 RK_PB1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdo1: i2s1m0-sdo1 { +- rockchip,pins = +- /* i2s1m0_sdo1 */ +- <4 RK_PB2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdo2: i2s1m0-sdo2 { +- rockchip,pins = +- /* i2s1m0_sdo2 */ +- <4 RK_PB3 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m0_sdo3: i2s1m0-sdo3 { +- rockchip,pins = +- /* i2s1m0_sdo3 */ +- <4 RK_PB4 3 &pcfg_pull_none>; +- }; +- /omit-if-no-ref/ +- i2s1m1_lrck: i2s1m1-lrck { +- rockchip,pins = +- /* i2s1m1_lrck */ +- <0 RK_PB7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_mclk: i2s1m1-mclk { +- rockchip,pins = +- /* i2s1m1_mclk */ +- <0 RK_PB5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sclk: i2s1m1-sclk { +- rockchip,pins = +- /* i2s1m1_sclk */ +- <0 RK_PB6 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdi0: i2s1m1-sdi0 { +- rockchip,pins = +- /* i2s1m1_sdi0 */ +- <0 RK_PC5 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdi1: i2s1m1-sdi1 { +- rockchip,pins = +- /* i2s1m1_sdi1 */ +- <0 RK_PC6 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdi2: i2s1m1-sdi2 { +- rockchip,pins = +- /* i2s1m1_sdi2 */ +- <0 RK_PC7 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdi3: i2s1m1-sdi3 { +- rockchip,pins = +- /* i2s1m1_sdi3 */ +- <0 RK_PD0 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdo0: i2s1m1-sdo0 { +- rockchip,pins = +- /* i2s1m1_sdo0 */ +- <0 RK_PD1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdo1: i2s1m1-sdo1 { +- rockchip,pins = +- /* i2s1m1_sdo1 */ +- <0 RK_PD2 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdo2: i2s1m1-sdo2 { +- rockchip,pins = +- /* i2s1m1_sdo2 */ +- <0 RK_PD4 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s1m1_sdo3: i2s1m1-sdo3 { +- rockchip,pins = +- /* i2s1m1_sdo3 */ +- <0 RK_PD5 1 &pcfg_pull_none>; +- }; +- }; +- +- i2s2 { +- /omit-if-no-ref/ +- i2s2m0_lrck: i2s2m0-lrck { +- rockchip,pins = +- /* i2s2m0_lrck */ +- <2 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_mclk: i2s2m0-mclk { +- rockchip,pins = +- /* i2s2m0_mclk */ +- <2 RK_PB6 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sclk: i2s2m0-sclk { +- rockchip,pins = +- /* i2s2m0_sclk */ +- <2 RK_PB7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sdi: i2s2m0-sdi { +- rockchip,pins = +- /* i2s2m0_sdi */ +- <2 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m0_sdo: i2s2m0-sdo { +- rockchip,pins = +- /* i2s2m0_sdo */ +- <4 RK_PC3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_lrck: i2s2m1-lrck { +- rockchip,pins = +- /* i2s2m1_lrck */ +- <3 RK_PB6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_mclk: i2s2m1-mclk { +- rockchip,pins = +- /* i2s2m1_mclk */ +- <3 RK_PB4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_sclk: i2s2m1-sclk { +- rockchip,pins = +- /* i2s2m1_sclk */ +- <3 RK_PB5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_sdi: i2s2m1-sdi { +- rockchip,pins = +- /* i2s2m1_sdi */ +- <3 RK_PB2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s2m1_sdo: i2s2m1-sdo { +- rockchip,pins = +- /* i2s2m1_sdo */ +- <3 RK_PB3 3 &pcfg_pull_none>; +- }; +- }; +- +- i2s3 { +- /omit-if-no-ref/ +- i2s3_lrck: i2s3-lrck { +- rockchip,pins = +- /* i2s3_lrck */ +- <3 RK_PA2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3_mclk: i2s3-mclk { +- rockchip,pins = +- /* i2s3_mclk */ +- <3 RK_PA0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3_sclk: i2s3-sclk { +- rockchip,pins = +- /* i2s3_sclk */ +- <3 RK_PA1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3_sdi: i2s3-sdi { +- rockchip,pins = +- /* i2s3_sdi */ +- <3 RK_PA4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- i2s3_sdo: i2s3-sdo { +- rockchip,pins = +- /* i2s3_sdo */ +- <3 RK_PA3 3 &pcfg_pull_none>; +- }; +- }; +- +- jtag { +- /omit-if-no-ref/ +- jtagm0_pins: jtagm0-pins { +- rockchip,pins = +- /* jtag_tck_m0 */ +- <4 RK_PD2 5 &pcfg_pull_none>, +- /* jtag_tms_m0 */ +- <4 RK_PD3 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- jtagm1_pins: jtagm1-pins { +- rockchip,pins = +- /* jtag_tck_m1 */ +- <4 RK_PD0 5 &pcfg_pull_none>, +- /* jtag_tms_m1 */ +- <4 RK_PD1 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- jtagm2_pins: jtagm2-pins { +- rockchip,pins = +- /* jtag_tck_m2 */ +- <0 RK_PB5 2 &pcfg_pull_none>, +- /* jtag_tms_m2 */ +- <0 RK_PB6 2 &pcfg_pull_none>; +- }; +- }; +- +- litcpu { +- /omit-if-no-ref/ +- litcpu_pins: litcpu-pins { +- rockchip,pins = +- /* litcpu_avs */ +- <0 RK_PD3 1 &pcfg_pull_none>; +- }; +- }; +- +- mcu { +- /omit-if-no-ref/ +- mcum0_pins: mcum0-pins { +- rockchip,pins = +- /* mcu_jtag_tck_m0 */ +- <4 RK_PD4 5 &pcfg_pull_none>, +- /* mcu_jtag_tms_m0 */ +- <4 RK_PD5 5 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mcum1_pins: mcum1-pins { +- rockchip,pins = +- /* mcu_jtag_tck_m1 */ +- <3 RK_PD4 6 &pcfg_pull_none>, +- /* mcu_jtag_tms_m1 */ +- <3 RK_PD5 6 &pcfg_pull_none>; +- }; +- }; +- +- mipi { +- /omit-if-no-ref/ +- mipim0_camera0_clk: mipim0-camera0-clk { +- rockchip,pins = +- /* mipim0_camera0_clk */ +- <4 RK_PB1 1 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim0_camera1_clk: mipim0-camera1-clk { +- rockchip,pins = +- /* mipim0_camera1_clk */ +- <1 RK_PB6 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim0_camera2_clk: mipim0-camera2-clk { +- rockchip,pins = +- /* mipim0_camera2_clk */ +- <1 RK_PB7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim0_camera3_clk: mipim0-camera3-clk { +- rockchip,pins = +- /* mipim0_camera3_clk */ +- <1 RK_PD6 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim0_camera4_clk: mipim0-camera4-clk { +- rockchip,pins = +- /* mipim0_camera4_clk */ +- <1 RK_PD7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim1_camera0_clk: mipim1-camera0-clk { +- rockchip,pins = +- /* mipim1_camera0_clk */ +- <3 RK_PA5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim1_camera1_clk: mipim1-camera1-clk { +- rockchip,pins = +- /* mipim1_camera1_clk */ +- <3 RK_PA6 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim1_camera2_clk: mipim1-camera2-clk { +- rockchip,pins = +- /* mipim1_camera2_clk */ +- <3 RK_PA7 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim1_camera3_clk: mipim1-camera3-clk { +- rockchip,pins = +- /* mipim1_camera3_clk */ +- <3 RK_PB0 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipim1_camera4_clk: mipim1-camera4-clk { +- rockchip,pins = +- /* mipim1_camera4_clk */ +- <3 RK_PB1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipi_te0: mipi-te0 { +- rockchip,pins = +- /* mipi_te0 */ +- <3 RK_PC2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- mipi_te1: mipi-te1 { +- rockchip,pins = +- /* mipi_te1 */ +- <3 RK_PC3 2 &pcfg_pull_none>; +- }; +- }; +- +- npu { +- /omit-if-no-ref/ +- npu_pins: npu-pins { +- rockchip,pins = +- /* npu_avs */ +- <0 RK_PC6 2 &pcfg_pull_none>; +- }; +- }; +- +- pcie20x1 { +- /omit-if-no-ref/ +- pcie20x1m0_pins: pcie20x1m0-pins { +- rockchip,pins = +- /* pcie20x1_2_clkreqn_m0 */ +- <3 RK_PC7 4 &pcfg_pull_none>, +- /* pcie20x1_2_perstn_m0 */ +- <3 RK_PD1 4 &pcfg_pull_none>, +- /* pcie20x1_2_waken_m0 */ +- <3 RK_PD0 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie20x1m1_pins: pcie20x1m1-pins { +- rockchip,pins = +- /* pcie20x1_2_clkreqn_m1 */ +- <4 RK_PB7 4 &pcfg_pull_none>, +- /* pcie20x1_2_perstn_m1 */ +- <4 RK_PC1 4 &pcfg_pull_none>, +- /* pcie20x1_2_waken_m1 */ +- <4 RK_PC0 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { +- rockchip,pins = +- /* pcie20x1_2_button_rstn */ +- <4 RK_PB3 4 &pcfg_pull_none>; +- }; +- }; +- +- pcie30phy { +- /omit-if-no-ref/ +- pcie30phy_pins: pcie30phy-pins { +- rockchip,pins = +- /* pcie30phy_dtb0 */ +- <1 RK_PC4 4 &pcfg_pull_none>, +- /* pcie30phy_dtb1 */ +- <1 RK_PD1 4 &pcfg_pull_none>; +- }; +- }; +- +- pcie30x1 { +- /omit-if-no-ref/ +- pcie30x1m0_pins: pcie30x1m0-pins { +- rockchip,pins = +- /* pcie30x1_0_clkreqn_m0 */ +- <0 RK_PC0 12 &pcfg_pull_none>, +- /* pcie30x1_0_perstn_m0 */ +- <0 RK_PC5 12 &pcfg_pull_none>, +- /* pcie30x1_0_waken_m0 */ +- <0 RK_PC4 12 &pcfg_pull_none>, +- /* pcie30x1_1_clkreqn_m0 */ +- <0 RK_PB5 12 &pcfg_pull_none>, +- /* pcie30x1_1_perstn_m0 */ +- <0 RK_PB7 12 &pcfg_pull_none>, +- /* pcie30x1_1_waken_m0 */ +- <0 RK_PB6 12 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x1m1_pins: pcie30x1m1-pins { +- rockchip,pins = +- /* pcie30x1_0_clkreqn_m1 */ +- <4 RK_PA3 4 &pcfg_pull_none>, +- /* pcie30x1_0_perstn_m1 */ +- <4 RK_PA5 4 &pcfg_pull_none>, +- /* pcie30x1_0_waken_m1 */ +- <4 RK_PA4 4 &pcfg_pull_none>, +- /* pcie30x1_1_clkreqn_m1 */ +- <4 RK_PA0 4 &pcfg_pull_none>, +- /* pcie30x1_1_perstn_m1 */ +- <4 RK_PA2 4 &pcfg_pull_none>, +- /* pcie30x1_1_waken_m1 */ +- <4 RK_PA1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x1m2_pins: pcie30x1m2-pins { +- rockchip,pins = +- /* pcie30x1_0_clkreqn_m2 */ +- <1 RK_PB5 4 &pcfg_pull_none>, +- /* pcie30x1_0_perstn_m2 */ +- <1 RK_PB4 4 &pcfg_pull_none>, +- /* pcie30x1_0_waken_m2 */ +- <1 RK_PB3 4 &pcfg_pull_none>, +- /* pcie30x1_1_clkreqn_m2 */ +- <1 RK_PA0 4 &pcfg_pull_none>, +- /* pcie30x1_1_perstn_m2 */ +- <1 RK_PA7 4 &pcfg_pull_none>, +- /* pcie30x1_1_waken_m2 */ +- <1 RK_PA1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { +- rockchip,pins = +- /* pcie30x1_0_button_rstn */ +- <4 RK_PB1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { +- rockchip,pins = +- /* pcie30x1_1_button_rstn */ +- <4 RK_PB2 4 &pcfg_pull_none>; +- }; +- }; +- +- pcie30x2 { +- /omit-if-no-ref/ +- pcie30x2m0_pins: pcie30x2m0-pins { +- rockchip,pins = +- /* pcie30x2_clkreqn_m0 */ +- <0 RK_PD1 12 &pcfg_pull_none>, +- /* pcie30x2_perstn_m0 */ +- <0 RK_PD4 12 &pcfg_pull_none>, +- /* pcie30x2_waken_m0 */ +- <0 RK_PD2 12 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x2m1_pins: pcie30x2m1-pins { +- rockchip,pins = +- /* pcie30x2_clkreqn_m1 */ +- <4 RK_PA6 4 &pcfg_pull_none>, +- /* pcie30x2_perstn_m1 */ +- <4 RK_PB0 4 &pcfg_pull_none>, +- /* pcie30x2_waken_m1 */ +- <4 RK_PA7 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x2m2_pins: pcie30x2m2-pins { +- rockchip,pins = +- /* pcie30x2_clkreqn_m2 */ +- <3 RK_PD2 4 &pcfg_pull_none>, +- /* pcie30x2_perstn_m2 */ +- <3 RK_PD4 4 &pcfg_pull_none>, +- /* pcie30x2_waken_m2 */ +- <3 RK_PD3 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x2m3_pins: pcie30x2m3-pins { +- rockchip,pins = +- /* pcie30x2_clkreqn_m3 */ +- <1 RK_PD7 4 &pcfg_pull_none>, +- /* pcie30x2_perstn_m3 */ +- <1 RK_PB7 4 &pcfg_pull_none>, +- /* pcie30x2_waken_m3 */ +- <1 RK_PB6 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x2_button_rstn: pcie30x2-button-rstn { +- rockchip,pins = +- /* pcie30x2_button_rstn */ +- <3 RK_PC1 4 &pcfg_pull_none>; +- }; +- }; +- +- pcie30x4 { +- /omit-if-no-ref/ +- pcie30x4m0_pins: pcie30x4m0-pins { +- rockchip,pins = +- /* pcie30x4_clkreqn_m0 */ +- <0 RK_PC6 12 &pcfg_pull_none>, +- /* pcie30x4_perstn_m0 */ +- <0 RK_PD0 12 &pcfg_pull_none>, +- /* pcie30x4_waken_m0 */ +- <0 RK_PC7 12 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x4m1_pins: pcie30x4m1-pins { +- rockchip,pins = +- /* pcie30x4_clkreqn_m1 */ +- <4 RK_PB4 4 &pcfg_pull_none>, +- /* pcie30x4_perstn_m1 */ +- <4 RK_PB6 4 &pcfg_pull_none>, +- /* pcie30x4_waken_m1 */ +- <4 RK_PB5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x4m2_pins: pcie30x4m2-pins { +- rockchip,pins = +- /* pcie30x4_clkreqn_m2 */ +- <3 RK_PC4 4 &pcfg_pull_none>, +- /* pcie30x4_perstn_m2 */ +- <3 RK_PC6 4 &pcfg_pull_none>, +- /* pcie30x4_waken_m2 */ +- <3 RK_PC5 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x4m3_pins: pcie30x4m3-pins { +- rockchip,pins = +- /* pcie30x4_clkreqn_m3 */ +- <1 RK_PB0 4 &pcfg_pull_none>, +- /* pcie30x4_perstn_m3 */ +- <1 RK_PB2 4 &pcfg_pull_none>, +- /* pcie30x4_waken_m3 */ +- <1 RK_PB1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pcie30x4_button_rstn: pcie30x4-button-rstn { +- rockchip,pins = +- /* pcie30x4_button_rstn */ +- <3 RK_PD5 4 &pcfg_pull_none>; +- }; +- }; +- +- pdm0 { +- /omit-if-no-ref/ +- pdm0m0_clk: pdm0m0-clk { +- rockchip,pins = +- /* pdm0_clk0_m0 */ +- <1 RK_PC6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m0_clk1: pdm0m0-clk1 { +- rockchip,pins = +- /* pdm0m0_clk1 */ +- <1 RK_PC4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m0_sdi0: pdm0m0-sdi0 { +- rockchip,pins = +- /* pdm0m0_sdi0 */ +- <1 RK_PD5 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m0_sdi1: pdm0m0-sdi1 { +- rockchip,pins = +- /* pdm0m0_sdi1 */ +- <1 RK_PD1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m0_sdi2: pdm0m0-sdi2 { +- rockchip,pins = +- /* pdm0m0_sdi2 */ +- <1 RK_PD2 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m0_sdi3: pdm0m0-sdi3 { +- rockchip,pins = +- /* pdm0m0_sdi3 */ +- <1 RK_PD3 3 &pcfg_pull_none>; +- }; +- /omit-if-no-ref/ +- pdm0m1_clk: pdm0m1-clk { +- rockchip,pins = +- /* pdm0_clk0_m1 */ +- <0 RK_PC0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m1_clk1: pdm0m1-clk1 { +- rockchip,pins = +- /* pdm0m1_clk1 */ +- <0 RK_PC4 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m1_sdi0: pdm0m1-sdi0 { +- rockchip,pins = +- /* pdm0m1_sdi0 */ +- <0 RK_PC7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m1_sdi1: pdm0m1-sdi1 { +- rockchip,pins = +- /* pdm0m1_sdi1 */ +- <0 RK_PD0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m1_sdi2: pdm0m1-sdi2 { +- rockchip,pins = +- /* pdm0m1_sdi2 */ +- <0 RK_PD4 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm0m1_sdi3: pdm0m1-sdi3 { +- rockchip,pins = +- /* pdm0m1_sdi3 */ +- <0 RK_PD6 2 &pcfg_pull_none>; +- }; +- }; +- +- pdm1 { +- /omit-if-no-ref/ +- pdm1m0_clk: pdm1m0-clk { +- rockchip,pins = +- /* pdm1_clk0_m0 */ +- <4 RK_PD5 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m0_clk1: pdm1m0-clk1 { +- rockchip,pins = +- /* pdm1m0_clk1 */ +- <4 RK_PD4 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m0_sdi0: pdm1m0-sdi0 { +- rockchip,pins = +- /* pdm1m0_sdi0 */ +- <4 RK_PD3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m0_sdi1: pdm1m0-sdi1 { +- rockchip,pins = +- /* pdm1m0_sdi1 */ +- <4 RK_PD2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m0_sdi2: pdm1m0-sdi2 { +- rockchip,pins = +- /* pdm1m0_sdi2 */ +- <4 RK_PD1 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m0_sdi3: pdm1m0-sdi3 { +- rockchip,pins = +- /* pdm1m0_sdi3 */ +- <4 RK_PD0 2 &pcfg_pull_none>; +- }; +- /omit-if-no-ref/ +- pdm1m1_clk: pdm1m1-clk { +- rockchip,pins = +- /* pdm1_clk0_m1 */ +- <1 RK_PB4 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m1_clk1: pdm1m1-clk1 { +- rockchip,pins = +- /* pdm1m1_clk1 */ +- <1 RK_PB3 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m1_sdi0: pdm1m1-sdi0 { +- rockchip,pins = +- /* pdm1m1_sdi0 */ +- <1 RK_PA7 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m1_sdi1: pdm1m1-sdi1 { +- rockchip,pins = +- /* pdm1m1_sdi1 */ +- <1 RK_PB0 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m1_sdi2: pdm1m1-sdi2 { +- rockchip,pins = +- /* pdm1m1_sdi2 */ +- <1 RK_PB1 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pdm1m1_sdi3: pdm1m1-sdi3 { +- rockchip,pins = +- /* pdm1m1_sdi3 */ +- <1 RK_PB2 2 &pcfg_pull_none>; +- }; +- }; +- +- pmic { +- /omit-if-no-ref/ +- pmic_pins: pmic-pins { +- rockchip,pins = +- /* pmic_int_l */ +- <0 RK_PA7 0 &pcfg_pull_up>, +- /* pmic_sleep1 */ +- <0 RK_PA2 1 &pcfg_pull_none>, +- /* pmic_sleep2 */ +- <0 RK_PA3 1 &pcfg_pull_none>, +- /* pmic_sleep3 */ +- <0 RK_PC1 1 &pcfg_pull_none>, +- /* pmic_sleep4 */ +- <0 RK_PC2 1 &pcfg_pull_none>, +- /* pmic_sleep5 */ +- <0 RK_PC3 1 &pcfg_pull_none>, +- /* pmic_sleep6 */ +- <0 RK_PD6 1 &pcfg_pull_none>; +- }; +- }; +- +- pmu { +- /omit-if-no-ref/ +- pmu_pins: pmu-pins { +- rockchip,pins = +- /* pmu_debug */ +- <0 RK_PA5 3 &pcfg_pull_none>; +- }; +- }; +- +- pwm0 { +- /omit-if-no-ref/ +- pwm0m0_pins: pwm0m0-pins { +- rockchip,pins = +- /* pwm0_m0 */ +- <0 RK_PB7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm0m1_pins: pwm0m1-pins { +- rockchip,pins = +- /* pwm0_m1 */ +- <1 RK_PD2 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm0m2_pins: pwm0m2-pins { +- rockchip,pins = +- /* pwm0_m2 */ +- <1 RK_PA2 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm1 { +- /omit-if-no-ref/ +- pwm1m0_pins: pwm1m0-pins { +- rockchip,pins = +- /* pwm1_m0 */ +- <0 RK_PC0 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm1m1_pins: pwm1m1-pins { +- rockchip,pins = +- /* pwm1_m1 */ +- <1 RK_PD3 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm1m2_pins: pwm1m2-pins { +- rockchip,pins = +- /* pwm1_m2 */ +- <1 RK_PA3 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm2 { +- /omit-if-no-ref/ +- pwm2m0_pins: pwm2m0-pins { +- rockchip,pins = +- /* pwm2_m0 */ +- <0 RK_PC4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm2m1_pins: pwm2m1-pins { +- rockchip,pins = +- /* pwm2_m1 */ +- <3 RK_PB1 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm3 { +- /omit-if-no-ref/ +- pwm3m0_pins: pwm3m0-pins { +- rockchip,pins = +- /* pwm3_ir_m0 */ +- <0 RK_PD4 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm3m1_pins: pwm3m1-pins { +- rockchip,pins = +- /* pwm3_ir_m1 */ +- <3 RK_PB2 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm3m2_pins: pwm3m2-pins { +- rockchip,pins = +- /* pwm3_ir_m2 */ +- <1 RK_PC2 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm3m3_pins: pwm3m3-pins { +- rockchip,pins = +- /* pwm3_ir_m3 */ +- <1 RK_PA7 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm4 { +- /omit-if-no-ref/ +- pwm4m0_pins: pwm4m0-pins { +- rockchip,pins = +- /* pwm4_m0 */ +- <0 RK_PC5 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm5 { +- /omit-if-no-ref/ +- pwm5m0_pins: pwm5m0-pins { +- rockchip,pins = +- /* pwm5_m0 */ +- <0 RK_PB1 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm5m1_pins: pwm5m1-pins { +- rockchip,pins = +- /* pwm5_m1 */ +- <0 RK_PC6 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm6 { +- /omit-if-no-ref/ +- pwm6m0_pins: pwm6m0-pins { +- rockchip,pins = +- /* pwm6_m0 */ +- <0 RK_PC7 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm6m1_pins: pwm6m1-pins { +- rockchip,pins = +- /* pwm6_m1 */ +- <4 RK_PC1 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm7 { +- /omit-if-no-ref/ +- pwm7m0_pins: pwm7m0-pins { +- rockchip,pins = +- /* pwm7_ir_m0 */ +- <0 RK_PD0 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm7m1_pins: pwm7m1-pins { +- rockchip,pins = +- /* pwm7_ir_m1 */ +- <4 RK_PD4 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm7m2_pins: pwm7m2-pins { +- rockchip,pins = +- /* pwm7_ir_m2 */ +- <1 RK_PC3 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm8 { +- /omit-if-no-ref/ +- pwm8m0_pins: pwm8m0-pins { +- rockchip,pins = +- /* pwm8_m0 */ +- <3 RK_PA7 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm8m1_pins: pwm8m1-pins { +- rockchip,pins = +- /* pwm8_m1 */ +- <4 RK_PD0 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm8m2_pins: pwm8m2-pins { +- rockchip,pins = +- /* pwm8_m2 */ +- <3 RK_PD0 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm9 { +- /omit-if-no-ref/ +- pwm9m0_pins: pwm9m0-pins { +- rockchip,pins = +- /* pwm9_m0 */ +- <3 RK_PB0 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm9m1_pins: pwm9m1-pins { +- rockchip,pins = +- /* pwm9_m1 */ +- <4 RK_PD1 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm9m2_pins: pwm9m2-pins { +- rockchip,pins = +- /* pwm9_m2 */ +- <3 RK_PD1 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm10 { +- /omit-if-no-ref/ +- pwm10m0_pins: pwm10m0-pins { +- rockchip,pins = +- /* pwm10_m0 */ +- <3 RK_PA0 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm10m1_pins: pwm10m1-pins { +- rockchip,pins = +- /* pwm10_m1 */ +- <4 RK_PD3 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm10m2_pins: pwm10m2-pins { +- rockchip,pins = +- /* pwm10_m2 */ +- <3 RK_PD3 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm11 { +- /omit-if-no-ref/ +- pwm11m0_pins: pwm11m0-pins { +- rockchip,pins = +- /* pwm11_ir_m0 */ +- <3 RK_PA1 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm11m1_pins: pwm11m1-pins { +- rockchip,pins = +- /* pwm11_ir_m1 */ +- <4 RK_PB4 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm11m2_pins: pwm11m2-pins { +- rockchip,pins = +- /* pwm11_ir_m2 */ +- <1 RK_PC4 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm11m3_pins: pwm11m3-pins { +- rockchip,pins = +- /* pwm11_ir_m3 */ +- <3 RK_PD5 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm12 { +- /omit-if-no-ref/ +- pwm12m0_pins: pwm12m0-pins { +- rockchip,pins = +- /* pwm12_m0 */ +- <3 RK_PB5 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm12m1_pins: pwm12m1-pins { +- rockchip,pins = +- /* pwm12_m1 */ +- <4 RK_PB5 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm13 { +- /omit-if-no-ref/ +- pwm13m0_pins: pwm13m0-pins { +- rockchip,pins = +- /* pwm13_m0 */ +- <3 RK_PB6 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm13m1_pins: pwm13m1-pins { +- rockchip,pins = +- /* pwm13_m1 */ +- <4 RK_PB6 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm13m2_pins: pwm13m2-pins { +- rockchip,pins = +- /* pwm13_m2 */ +- <1 RK_PB7 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm14 { +- /omit-if-no-ref/ +- pwm14m0_pins: pwm14m0-pins { +- rockchip,pins = +- /* pwm14_m0 */ +- <3 RK_PC2 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm14m1_pins: pwm14m1-pins { +- rockchip,pins = +- /* pwm14_m1 */ +- <4 RK_PB2 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm14m2_pins: pwm14m2-pins { +- rockchip,pins = +- /* pwm14_m2 */ +- <1 RK_PD6 11 &pcfg_pull_none>; +- }; +- }; +- +- pwm15 { +- /omit-if-no-ref/ +- pwm15m0_pins: pwm15m0-pins { +- rockchip,pins = +- /* pwm15_ir_m0 */ +- <3 RK_PC3 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm15m1_pins: pwm15m1-pins { +- rockchip,pins = +- /* pwm15_ir_m1 */ +- <4 RK_PB3 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm15m2_pins: pwm15m2-pins { +- rockchip,pins = +- /* pwm15_ir_m2 */ +- <1 RK_PC6 11 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- pwm15m3_pins: pwm15m3-pins { +- rockchip,pins = +- /* pwm15_ir_m3 */ +- <1 RK_PD7 11 &pcfg_pull_none>; +- }; +- }; +- +- refclk { +- /omit-if-no-ref/ +- refclk_pins: refclk-pins { +- rockchip,pins = +- /* refclk_out */ +- <0 RK_PA0 1 &pcfg_pull_none>; +- }; +- }; +- +- sata { +- /omit-if-no-ref/ +- sata_pins: sata-pins { +- rockchip,pins = +- /* sata_cp_pod */ +- <0 RK_PC6 13 &pcfg_pull_none>, +- /* sata_cpdet */ +- <0 RK_PD4 13 &pcfg_pull_none>, +- /* sata_mp_switch */ +- <0 RK_PD5 13 &pcfg_pull_none>; +- }; +- }; +- +- sata0 { +- /omit-if-no-ref/ +- sata0m0_pins: sata0m0-pins { +- rockchip,pins = +- /* sata0_act_led_m0 */ +- <4 RK_PB6 6 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- sata0m1_pins: sata0m1-pins { +- rockchip,pins = +- /* sata0_act_led_m1 */ +- <1 RK_PB3 6 &pcfg_pull_none>; +- }; +- }; +- +- sata1 { +- /omit-if-no-ref/ +- sata1m0_pins: sata1m0-pins { +- rockchip,pins = +- /* sata1_act_led_m0 */ +- <4 RK_PB5 6 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- sata1m1_pins: sata1m1-pins { +- rockchip,pins = +- /* sata1_act_led_m1 */ +- <1 RK_PA1 6 &pcfg_pull_none>; +- }; +- }; +- +- sata2 { +- /omit-if-no-ref/ +- sata2m0_pins: sata2m0-pins { +- rockchip,pins = +- /* sata2_act_led_m0 */ +- <4 RK_PB1 6 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- sata2m1_pins: sata2m1-pins { +- rockchip,pins = +- /* sata2_act_led_m1 */ +- <1 RK_PB7 6 &pcfg_pull_none>; +- }; +- }; +- +- sdio { +- /omit-if-no-ref/ +- sdiom1_pins: sdiom1-pins { +- rockchip,pins = +- /* sdio_clk_m1 */ +- <3 RK_PA5 2 &pcfg_pull_none>, +- /* sdio_cmd_m1 */ +- <3 RK_PA4 2 &pcfg_pull_none>, +- /* sdio_d0_m1 */ +- <3 RK_PA0 2 &pcfg_pull_none>, +- /* sdio_d1_m1 */ +- <3 RK_PA1 2 &pcfg_pull_none>, +- /* sdio_d2_m1 */ +- <3 RK_PA2 2 &pcfg_pull_none>, +- /* sdio_d3_m1 */ +- <3 RK_PA3 2 &pcfg_pull_none>; +- }; +- }; +- +- sdmmc { +- /omit-if-no-ref/ +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = +- /* sdmmc_d0 */ +- <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc_d1 */ +- <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc_d2 */ +- <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, +- /* sdmmc_d3 */ +- <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = +- /* sdmmc_clk */ +- <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = +- /* sdmmc_cmd */ +- <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; +- }; +- +- /omit-if-no-ref/ +- sdmmc_det: sdmmc-det { +- rockchip,pins = +- /* sdmmc_det */ +- <0 RK_PA4 1 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- sdmmc_pwren: sdmmc-pwren { +- rockchip,pins = +- /* sdmmc_pwren */ +- <0 RK_PA5 2 &pcfg_pull_none>; +- }; +- }; +- +- spdif0 { +- /omit-if-no-ref/ +- spdif0m0_tx: spdif0m0-tx { +- rockchip,pins = +- /* spdif0m0_tx */ +- <1 RK_PB6 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spdif0m1_tx: spdif0m1-tx { +- rockchip,pins = +- /* spdif0m1_tx */ +- <4 RK_PB4 6 &pcfg_pull_none>; +- }; +- }; +- +- spdif1 { +- /omit-if-no-ref/ +- spdif1m0_tx: spdif1m0-tx { +- rockchip,pins = +- /* spdif1m0_tx */ +- <1 RK_PB7 3 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spdif1m1_tx: spdif1m1-tx { +- rockchip,pins = +- /* spdif1m1_tx */ +- <4 RK_PB1 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- spdif1m2_tx: spdif1m2-tx { +- rockchip,pins = +- /* spdif1m2_tx */ +- <4 RK_PC1 3 &pcfg_pull_none>; +- }; +- }; +- +- spi0 { +- /omit-if-no-ref/ +- spi0m0_pins: spi0m0-pins { +- rockchip,pins = +- /* spi0_clk_m0 */ +- <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, +- /* spi0_miso_m0 */ +- <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, +- /* spi0_mosi_m0 */ +- <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m0_cs0: spi0m0-cs0 { +- rockchip,pins = +- /* spi0_cs0_m0 */ +- <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m0_cs1: spi0m0-cs1 { +- rockchip,pins = +- /* spi0_cs1_m0 */ +- <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; +- }; +- /omit-if-no-ref/ +- spi0m1_pins: spi0m1-pins { +- rockchip,pins = +- /* spi0_clk_m1 */ +- <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, +- /* spi0_miso_m1 */ +- <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, +- /* spi0_mosi_m1 */ +- <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m1_cs0: spi0m1-cs0 { +- rockchip,pins = +- /* spi0_cs0_m1 */ +- <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m1_cs1: spi0m1-cs1 { +- rockchip,pins = +- /* spi0_cs1_m1 */ +- <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; +- }; +- /omit-if-no-ref/ +- spi0m2_pins: spi0m2-pins { +- rockchip,pins = +- /* spi0_clk_m2 */ +- <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, +- /* spi0_miso_m2 */ +- <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, +- /* spi0_mosi_m2 */ +- <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m2_cs0: spi0m2-cs0 { +- rockchip,pins = +- /* spi0_cs0_m2 */ +- <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m2_cs1: spi0m2-cs1 { +- rockchip,pins = +- /* spi0_cs1_m2 */ +- <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; +- }; +- /omit-if-no-ref/ +- spi0m3_pins: spi0m3-pins { +- rockchip,pins = +- /* spi0_clk_m3 */ +- <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, +- /* spi0_miso_m3 */ +- <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, +- /* spi0_mosi_m3 */ +- <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m3_cs0: spi0m3-cs0 { +- rockchip,pins = +- /* spi0_cs0_m3 */ +- <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi0m3_cs1: spi0m3-cs1 { +- rockchip,pins = +- /* spi0_cs1_m3 */ +- <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- spi1 { +- /omit-if-no-ref/ +- spi1m1_pins: spi1m1-pins { +- rockchip,pins = +- /* spi1_clk_m1 */ +- <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, +- /* spi1_miso_m1 */ +- <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, +- /* spi1_mosi_m1 */ +- <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m1_cs0: spi1m1-cs0 { +- rockchip,pins = +- /* spi1_cs0_m1 */ +- <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m1_cs1: spi1m1-cs1 { +- rockchip,pins = +- /* spi1_cs1_m1 */ +- <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m2_pins: spi1m2-pins { +- rockchip,pins = +- /* spi1_clk_m2 */ +- <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, +- /* spi1_miso_m2 */ +- <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, +- /* spi1_mosi_m2 */ +- <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m2_cs0: spi1m2-cs0 { +- rockchip,pins = +- /* spi1_cs0_m2 */ +- <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi1m2_cs1: spi1m2-cs1 { +- rockchip,pins = +- /* spi1_cs1_m2 */ +- <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- spi2 { +- /omit-if-no-ref/ +- spi2m0_pins: spi2m0-pins { +- rockchip,pins = +- /* spi2_clk_m0 */ +- <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, +- /* spi2_miso_m0 */ +- <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, +- /* spi2_mosi_m0 */ +- <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m0_cs0: spi2m0-cs0 { +- rockchip,pins = +- /* spi2_cs0_m0 */ +- <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m0_cs1: spi2m0-cs1 { +- rockchip,pins = +- /* spi2_cs1_m0 */ +- <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_pins: spi2m1-pins { +- rockchip,pins = +- /* spi2_clk_m1 */ +- <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, +- /* spi2_miso_m1 */ +- <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, +- /* spi2_mosi_m1 */ +- <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_cs0: spi2m1-cs0 { +- rockchip,pins = +- /* spi2_cs0_m1 */ +- <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m1_cs1: spi2m1-cs1 { +- rockchip,pins = +- /* spi2_cs1_m1 */ +- <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m2_pins: spi2m2-pins { +- rockchip,pins = +- /* spi2_clk_m2 */ +- <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, +- /* spi2_miso_m2 */ +- <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, +- /* spi2_mosi_m2 */ +- <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m2_cs0: spi2m2-cs0 { +- rockchip,pins = +- /* spi2_cs0_m2 */ +- <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi2m2_cs1: spi2m2-cs1 { +- rockchip,pins = +- /* spi2_cs1_m2 */ +- <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- spi3 { +- /omit-if-no-ref/ +- spi3m1_pins: spi3m1-pins { +- rockchip,pins = +- /* spi3_clk_m1 */ +- <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, +- /* spi3_miso_m1 */ +- <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, +- /* spi3_mosi_m1 */ +- <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m1_cs0: spi3m1-cs0 { +- rockchip,pins = +- /* spi3_cs0_m1 */ +- <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m1_cs1: spi3m1-cs1 { +- rockchip,pins = +- /* spi3_cs1_m1 */ +- <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m2_pins: spi3m2-pins { +- rockchip,pins = +- /* spi3_clk_m2 */ +- <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, +- /* spi3_miso_m2 */ +- <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, +- /* spi3_mosi_m2 */ +- <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m2_cs0: spi3m2-cs0 { +- rockchip,pins = +- /* spi3_cs0_m2 */ +- <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m2_cs1: spi3m2-cs1 { +- rockchip,pins = +- /* spi3_cs1_m2 */ +- <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m3_pins: spi3m3-pins { +- rockchip,pins = +- /* spi3_clk_m3 */ +- <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, +- /* spi3_miso_m3 */ +- <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, +- /* spi3_mosi_m3 */ +- <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m3_cs0: spi3m3-cs0 { +- rockchip,pins = +- /* spi3_cs0_m3 */ +- <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi3m3_cs1: spi3m3-cs1 { +- rockchip,pins = +- /* spi3_cs1_m3 */ +- <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- spi4 { +- /omit-if-no-ref/ +- spi4m0_pins: spi4m0-pins { +- rockchip,pins = +- /* spi4_clk_m0 */ +- <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, +- /* spi4_miso_m0 */ +- <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, +- /* spi4_mosi_m0 */ +- <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi4m0_cs0: spi4m0-cs0 { +- rockchip,pins = +- /* spi4_cs0_m0 */ +- <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi4m0_cs1: spi4m0-cs1 { +- rockchip,pins = +- /* spi4_cs1_m0 */ +- <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi4m1_pins: spi4m1-pins { +- rockchip,pins = +- /* spi4_clk_m1 */ +- <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, +- /* spi4_miso_m1 */ +- <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, +- /* spi4_mosi_m1 */ +- <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi4m1_cs0: spi4m1-cs0 { +- rockchip,pins = +- /* spi4_cs0_m1 */ +- <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi4m1_cs1: spi4m1-cs1 { +- rockchip,pins = +- /* spi4_cs1_m1 */ +- <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi4m2_pins: spi4m2-pins { +- rockchip,pins = +- /* spi4_clk_m2 */ +- <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, +- /* spi4_miso_m2 */ +- <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, +- /* spi4_mosi_m2 */ +- <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; +- }; +- +- /omit-if-no-ref/ +- spi4m2_cs0: spi4m2-cs0 { +- rockchip,pins = +- /* spi4_cs0_m2 */ +- <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; +- }; +- }; +- +- tsadc { +- /omit-if-no-ref/ +- tsadcm1_shut: tsadcm1-shut { +- rockchip,pins = +- /* tsadcm1_shut */ +- <0 RK_PA2 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- tsadc_shut: tsadc-shut { +- rockchip,pins = +- /* tsadc_shut */ +- <0 RK_PA1 2 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- tsadc_shut_org: tsadc-shut-org { +- rockchip,pins = +- /* tsadc_shut_org */ +- <0 RK_PA1 1 &pcfg_pull_none>; +- }; +- }; +- +- uart0 { +- /omit-if-no-ref/ +- uart0m0_xfer: uart0m0-xfer { +- rockchip,pins = +- /* uart0_rx_m0 */ +- <0 RK_PC4 4 &pcfg_pull_up>, +- /* uart0_tx_m0 */ +- <0 RK_PC5 4 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart0m1_xfer: uart0m1-xfer { +- rockchip,pins = +- /* uart0_rx_m1 */ +- <0 RK_PB0 4 &pcfg_pull_up>, +- /* uart0_tx_m1 */ +- <0 RK_PB1 4 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart0m2_xfer: uart0m2-xfer { +- rockchip,pins = +- /* uart0_rx_m2 */ +- <4 RK_PA4 10 &pcfg_pull_up>, +- /* uart0_tx_m2 */ +- <4 RK_PA3 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart0_ctsn: uart0-ctsn { +- rockchip,pins = +- /* uart0_ctsn */ +- <0 RK_PD1 4 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart0_rtsn: uart0-rtsn { +- rockchip,pins = +- /* uart0_rtsn */ +- <0 RK_PC6 4 &pcfg_pull_none>; +- }; +- }; +- +- uart1 { +- /omit-if-no-ref/ +- uart1m1_xfer: uart1m1-xfer { +- rockchip,pins = +- /* uart1_rx_m1 */ +- <1 RK_PB7 10 &pcfg_pull_up>, +- /* uart1_tx_m1 */ +- <1 RK_PB6 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart1m1_ctsn: uart1m1-ctsn { +- rockchip,pins = +- /* uart1m1_ctsn */ +- <1 RK_PD7 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart1m1_rtsn: uart1m1-rtsn { +- rockchip,pins = +- /* uart1m1_rtsn */ +- <1 RK_PD6 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart1m2_xfer: uart1m2-xfer { +- rockchip,pins = +- /* uart1_rx_m2 */ +- <0 RK_PD2 10 &pcfg_pull_up>, +- /* uart1_tx_m2 */ +- <0 RK_PD1 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart1m2_ctsn: uart1m2-ctsn { +- rockchip,pins = +- /* uart1m2_ctsn */ +- <0 RK_PD0 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart1m2_rtsn: uart1m2-rtsn { +- rockchip,pins = +- /* uart1m2_rtsn */ +- <0 RK_PC7 10 &pcfg_pull_none>; +- }; +- }; +- +- uart2 { +- /omit-if-no-ref/ +- uart2m0_xfer: uart2m0-xfer { +- rockchip,pins = +- /* uart2_rx_m0 */ +- <0 RK_PB6 10 &pcfg_pull_up>, +- /* uart2_tx_m0 */ +- <0 RK_PB5 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart2m1_xfer: uart2m1-xfer { +- rockchip,pins = +- /* uart2_rx_m1 */ +- <4 RK_PD1 10 &pcfg_pull_up>, +- /* uart2_tx_m1 */ +- <4 RK_PD0 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart2m2_xfer: uart2m2-xfer { +- rockchip,pins = +- /* uart2_rx_m2 */ +- <3 RK_PB2 10 &pcfg_pull_up>, +- /* uart2_tx_m2 */ +- <3 RK_PB1 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart2_ctsn: uart2-ctsn { +- rockchip,pins = +- /* uart2_ctsn */ +- <3 RK_PB4 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart2_rtsn: uart2-rtsn { +- rockchip,pins = +- /* uart2_rtsn */ +- <3 RK_PB3 10 &pcfg_pull_none>; +- }; +- }; +- +- uart3 { +- /omit-if-no-ref/ +- uart3m0_xfer: uart3m0-xfer { +- rockchip,pins = +- /* uart3_rx_m0 */ +- <1 RK_PC0 10 &pcfg_pull_up>, +- /* uart3_tx_m0 */ +- <1 RK_PC1 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart3m1_xfer: uart3m1-xfer { +- rockchip,pins = +- /* uart3_rx_m1 */ +- <3 RK_PB6 10 &pcfg_pull_up>, +- /* uart3_tx_m1 */ +- <3 RK_PB5 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart3m2_xfer: uart3m2-xfer { +- rockchip,pins = +- /* uart3_rx_m2 */ +- <4 RK_PA6 10 &pcfg_pull_up>, +- /* uart3_tx_m2 */ +- <4 RK_PA5 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart3_ctsn: uart3-ctsn { +- rockchip,pins = +- /* uart3_ctsn */ +- <1 RK_PC3 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart3_rtsn: uart3-rtsn { +- rockchip,pins = +- /* uart3_rtsn */ +- <1 RK_PC2 10 &pcfg_pull_none>; +- }; +- }; +- +- uart4 { +- /omit-if-no-ref/ +- uart4m0_xfer: uart4m0-xfer { +- rockchip,pins = +- /* uart4_rx_m0 */ +- <1 RK_PD3 10 &pcfg_pull_up>, +- /* uart4_tx_m0 */ +- <1 RK_PD2 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart4m1_xfer: uart4m1-xfer { +- rockchip,pins = +- /* uart4_rx_m1 */ +- <3 RK_PD0 10 &pcfg_pull_up>, +- /* uart4_tx_m1 */ +- <3 RK_PD1 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart4m2_xfer: uart4m2-xfer { +- rockchip,pins = +- /* uart4_rx_m2 */ +- <1 RK_PB2 10 &pcfg_pull_up>, +- /* uart4_tx_m2 */ +- <1 RK_PB3 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart4_ctsn: uart4-ctsn { +- rockchip,pins = +- /* uart4_ctsn */ +- <1 RK_PC7 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart4_rtsn: uart4-rtsn { +- rockchip,pins = +- /* uart4_rtsn */ +- <1 RK_PC5 10 &pcfg_pull_none>; +- }; +- }; +- +- uart5 { +- /omit-if-no-ref/ +- uart5m0_xfer: uart5m0-xfer { +- rockchip,pins = +- /* uart5_rx_m0 */ +- <4 RK_PD4 10 &pcfg_pull_up>, +- /* uart5_tx_m0 */ +- <4 RK_PD5 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart5m0_ctsn: uart5m0-ctsn { +- rockchip,pins = +- /* uart5m0_ctsn */ +- <4 RK_PD2 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart5m0_rtsn: uart5m0-rtsn { +- rockchip,pins = +- /* uart5m0_rtsn */ +- <4 RK_PD3 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart5m1_xfer: uart5m1-xfer { +- rockchip,pins = +- /* uart5_rx_m1 */ +- <3 RK_PC5 10 &pcfg_pull_up>, +- /* uart5_tx_m1 */ +- <3 RK_PC4 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart5m1_ctsn: uart5m1-ctsn { +- rockchip,pins = +- /* uart5m1_ctsn */ +- <2 RK_PA2 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart5m1_rtsn: uart5m1-rtsn { +- rockchip,pins = +- /* uart5m1_rtsn */ +- <2 RK_PA3 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart5m2_xfer: uart5m2-xfer { +- rockchip,pins = +- /* uart5_rx_m2 */ +- <2 RK_PD4 10 &pcfg_pull_up>, +- /* uart5_tx_m2 */ +- <2 RK_PD5 10 &pcfg_pull_up>; +- }; +- }; +- +- uart6 { +- /omit-if-no-ref/ +- uart6m1_xfer: uart6m1-xfer { +- rockchip,pins = +- /* uart6_rx_m1 */ +- <1 RK_PA0 10 &pcfg_pull_up>, +- /* uart6_tx_m1 */ +- <1 RK_PA1 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart6m1_ctsn: uart6m1-ctsn { +- rockchip,pins = +- /* uart6m1_ctsn */ +- <1 RK_PA3 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart6m1_rtsn: uart6m1-rtsn { +- rockchip,pins = +- /* uart6m1_rtsn */ +- <1 RK_PA2 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart6m2_xfer: uart6m2-xfer { +- rockchip,pins = +- /* uart6_rx_m2 */ +- <1 RK_PD1 10 &pcfg_pull_up>, +- /* uart6_tx_m2 */ +- <1 RK_PD0 10 &pcfg_pull_up>; +- }; +- }; +- +- uart7 { +- /omit-if-no-ref/ +- uart7m1_xfer: uart7m1-xfer { +- rockchip,pins = +- /* uart7_rx_m1 */ +- <3 RK_PC1 10 &pcfg_pull_up>, +- /* uart7_tx_m1 */ +- <3 RK_PC0 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart7m1_ctsn: uart7m1-ctsn { +- rockchip,pins = +- /* uart7m1_ctsn */ +- <3 RK_PC3 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart7m1_rtsn: uart7m1-rtsn { +- rockchip,pins = +- /* uart7m1_rtsn */ +- <3 RK_PC2 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart7m2_xfer: uart7m2-xfer { +- rockchip,pins = +- /* uart7_rx_m2 */ +- <1 RK_PB4 10 &pcfg_pull_up>, +- /* uart7_tx_m2 */ +- <1 RK_PB5 10 &pcfg_pull_up>; +- }; +- }; +- +- uart8 { +- /omit-if-no-ref/ +- uart8m0_xfer: uart8m0-xfer { +- rockchip,pins = +- /* uart8_rx_m0 */ +- <4 RK_PB1 10 &pcfg_pull_up>, +- /* uart8_tx_m0 */ +- <4 RK_PB0 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart8m0_ctsn: uart8m0-ctsn { +- rockchip,pins = +- /* uart8m0_ctsn */ +- <4 RK_PB3 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart8m0_rtsn: uart8m0-rtsn { +- rockchip,pins = +- /* uart8m0_rtsn */ +- <4 RK_PB2 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart8m1_xfer: uart8m1-xfer { +- rockchip,pins = +- /* uart8_rx_m1 */ +- <3 RK_PA3 10 &pcfg_pull_up>, +- /* uart8_tx_m1 */ +- <3 RK_PA2 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart8m1_ctsn: uart8m1-ctsn { +- rockchip,pins = +- /* uart8m1_ctsn */ +- <3 RK_PA5 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart8m1_rtsn: uart8m1-rtsn { +- rockchip,pins = +- /* uart8m1_rtsn */ +- <3 RK_PA4 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart8_xfer: uart8-xfer { +- rockchip,pins = +- /* uart8_rx_ */ +- <4 RK_PB1 10 &pcfg_pull_up>; +- }; +- }; +- +- uart9 { +- /omit-if-no-ref/ +- uart9m0_xfer: uart9m0-xfer { +- rockchip,pins = +- /* uart9_rx_m0 */ +- <2 RK_PC4 10 &pcfg_pull_up>, +- /* uart9_tx_m0 */ +- <2 RK_PC2 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart9m1_xfer: uart9m1-xfer { +- rockchip,pins = +- /* uart9_rx_m1 */ +- <4 RK_PB5 10 &pcfg_pull_up>, +- /* uart9_tx_m1 */ +- <4 RK_PB4 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart9m1_ctsn: uart9m1-ctsn { +- rockchip,pins = +- /* uart9m1_ctsn */ +- <4 RK_PA1 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart9m1_rtsn: uart9m1-rtsn { +- rockchip,pins = +- /* uart9m1_rtsn */ +- <4 RK_PA0 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart9m2_xfer: uart9m2-xfer { +- rockchip,pins = +- /* uart9_rx_m2 */ +- <3 RK_PD4 10 &pcfg_pull_up>, +- /* uart9_tx_m2 */ +- <3 RK_PD5 10 &pcfg_pull_up>; +- }; +- +- /omit-if-no-ref/ +- uart9m2_ctsn: uart9m2-ctsn { +- rockchip,pins = +- /* uart9m2_ctsn */ +- <3 RK_PD3 10 &pcfg_pull_none>; +- }; +- +- /omit-if-no-ref/ +- uart9m2_rtsn: uart9m2-rtsn { +- rockchip,pins = +- /* uart9m2_rtsn */ +- <3 RK_PD2 10 &pcfg_pull_none>; +- }; +- }; +- +- vop { +- /omit-if-no-ref/ +- vop_pins: vop-pins { +- rockchip,pins = +- /* vop_post_empty */ +- <1 RK_PA2 1 &pcfg_pull_none>; +- }; +- }; +-}; +- +-/* +- * This part is edited handly. +- */ +-&pinctrl { +- bt656 { +- /omit-if-no-ref/ +- bt656_pins: bt656-pins { +- rockchip,pins = +- /* bt1120_clkout */ +- <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, +- /* bt1120_d0 */ +- <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, +- /* bt1120_d1 */ +- <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, +- /* bt1120_d2 */ +- <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, +- /* bt1120_d3 */ +- <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, +- /* bt1120_d4 */ +- <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, +- /* bt1120_d5 */ +- <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, +- /* bt1120_d6 */ +- <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, +- /* bt1120_d7 */ +- <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; +- }; +- }; +- +- gpio-func { +- /omit-if-no-ref/ +- tsadc_gpio_func: tsadc-gpio-func { +- rockchip,pins = +- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; diff --git a/target/linux/rockchip/patches-6.6/050-23-v6.11-arm64-dts-rockchip-add-thermal-zones-information-on-RK358.patch b/target/linux/rockchip/patches-6.6/050-23-v6.11-arm64-dts-rockchip-add-thermal-zones-information-on-RK358.patch new file mode 100644 index 00000000000000..1a18eb9358fd7e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-23-v6.11-arm64-dts-rockchip-add-thermal-zones-information-on-RK358.patch @@ -0,0 +1,193 @@ +From 510cd9e688453166b2bff3999ed21cac97385bb5 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 17 Jun 2024 22:28:51 +0400 +Subject: [PATCH] arm64: dts: rockchip: add thermal zones information on RK3588 + +This includes the necessary device tree data to allow thermal +monitoring on RK3588(s) using the on-chip TSADC device, along with +trip points for automatic thermal management. + +Each of the CPU clusters (one for the little cores and two for +the big cores) get a passive cooling trip point at 85C, which +will trigger DVFS throttling of the respective cluster upon +reaching a high temperature condition. + +All zones also have a critical trip point at 115C, which will +trigger a reset. + +Signed-off-by: Alexey Charkov +Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 153 ++++++++++++++++++ + 1 file changed, 153 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + / { + compatible = "rockchip,rk3588"; +@@ -2368,6 +2369,158 @@ + status = "disabled"; + }; + ++ thermal_zones: thermal-zones { ++ /* sensor near the center of the SoC */ ++ package_thermal: package-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 0>; ++ ++ trips { ++ package_crit: package-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ /* sensor between A76 cores 0 and 1 */ ++ bigcore0_thermal: bigcore0-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 1>; ++ ++ trips { ++ bigcore0_alert: bigcore0-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ bigcore0_crit: bigcore0-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&bigcore0_alert>; ++ cooling-device = ++ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ /* sensor between A76 cores 2 and 3 */ ++ bigcore2_thermal: bigcore2-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 2>; ++ ++ trips { ++ bigcore2_alert: bigcore2-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ bigcore2_crit: bigcore2-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&bigcore2_alert>; ++ cooling-device = ++ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ /* sensor between the four A55 cores */ ++ little_core_thermal: littlecore-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 3>; ++ ++ trips { ++ littlecore_alert: littlecore-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ littlecore_crit: littlecore-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&littlecore_alert>; ++ cooling-device = ++ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ /* sensor near the PD_CENTER power domain */ ++ center_thermal: center-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 4>; ++ ++ trips { ++ center_crit: center-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu_thermal: gpu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 5>; ++ ++ trips { ++ gpu_crit: gpu-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ npu_thermal: npu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 6>; ++ ++ trips { ++ npu_crit: npu-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; diff --git a/target/linux/rockchip/patches-6.6/050-24-v6.11-arm64-dts-rockchip-add-passive-GPU-cooling-on-RK3588.patch b/target/linux/rockchip/patches-6.6/050-24-v6.11-arm64-dts-rockchip-add-passive-GPU-cooling-on-RK3588.patch new file mode 100644 index 00000000000000..c7a8bb8aa97a44 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-24-v6.11-arm64-dts-rockchip-add-passive-GPU-cooling-on-RK3588.patch @@ -0,0 +1,50 @@ +From b78f87940a79321a444083aca46ac3e8e53d1a90 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 17 Jun 2024 22:28:53 +0400 +Subject: [PATCH] arm64: dts: rockchip: add passive GPU cooling on RK3588 + +As the GPU support on RK3588 has been merged upstream, along with OPP +values, add a corresponding cooling map for passive cooling using the GPU. + +Signed-off-by: Alexey Charkov +Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-3-c1f5f3267f1e@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -2493,17 +2493,31 @@ + }; + + gpu_thermal: gpu-thermal { +- polling-delay-passive = <0>; ++ polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { ++ gpu_alert: gpu-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&gpu_alert>; ++ cooling-device = ++ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + + npu_thermal: npu-thermal { diff --git a/target/linux/rockchip/patches-6.6/050-25-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588.patch b/target/linux/rockchip/patches-6.6/050-25-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588.patch new file mode 100644 index 00000000000000..cb5c254ffb4a36 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-25-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588.patch @@ -0,0 +1,205 @@ +From 276856db91b46eaa7a4c19226c096a9dc899a3e9 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 17 Jun 2024 22:28:56 +0400 +Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 + +By default the CPUs on RK3588 start up in a conservative performance +mode. Add frequency and voltage mappings to the device tree to enable +dynamic scaling via cpufreq. + +OPP values are adapted from Radxa's downstream kernel for Rock 5B [1], +stripping them down to the minimum frequency and voltage combinations +as expected by the generic upstream cpufreq-dt driver, and also dropping +those OPPs that don't differ in voltage but only in frequency (keeping +the top frequency OPP in each case). + +Note that this patch ignores voltage scaling for the CPU memory +interface which the downstream kernel does through a custom cpufreq +driver, and which is why the downstream version has two sets of voltage +values for each OPP (the second one being meant for the memory +interface supply regulator). This is done instead via regulator +coupling between CPU and memory interface supplies on affected boards. + +This has been tested on Rock 5B with u-boot 2023.11 compiled from +Collabora's integration tree [2] with binary bl31 and appears to be +stable both under active cooling and passive cooling (with throttling) + +[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot + +Signed-off-by: Alexey Charkov +Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 149 +++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 + + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + + 3 files changed, 151 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi +@@ -0,0 +1,149 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/ { ++ cluster0_opp_table: opp-table-cluster0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <675000 675000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <712500 712500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <762500 762500 950000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <850000 850000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <950000 950000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster1_opp_table: opp-table-cluster1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <725000 725000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <762500 762500 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <850000 850000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <925000 925000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <987500 987500 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2400000000 { ++ opp-hz = /bits/ 64 <2400000000>; ++ opp-microvolt = <1000000 1000000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster2_opp_table: opp-table-cluster2 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <725000 725000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <762500 762500 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <850000 850000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <925000 925000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <987500 987500 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2400000000 { ++ opp-hz = /bits/ 64 <2400000000>; ++ opp-microvolt = <1000000 1000000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++}; ++ ++&cpu_b0 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_b1 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_b2 { ++ operating-points-v2 = <&cluster2_opp_table>; ++}; ++ ++&cpu_b3 { ++ operating-points-v2 = <&cluster2_opp_table>; ++}; ++ ++&cpu_l0 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_l1 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_l2 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_l3 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -5,3 +5,4 @@ + */ + + #include "rk3588-extra.dtsi" ++#include "rk3588-opp.dtsi" +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -5,3 +5,4 @@ + */ + + #include "rk3588-base.dtsi" ++#include "rk3588-opp.dtsi" diff --git a/target/linux/rockchip/patches-6.6/050-26-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588j.patch b/target/linux/rockchip/patches-6.6/050-26-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588j.patch new file mode 100644 index 00000000000000..3b39a60ade6b45 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-26-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588j.patch @@ -0,0 +1,140 @@ +From 667885a6865832eb0678c7e02e47a3392f177ecb Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 17 Jun 2024 22:28:57 +0400 +Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j + +RK3588j is the 'industrial' variant of RK3588, and it uses a different +set of OPPs both in terms of allowed frequencies and in terms of +applicable voltages at each frequency setpoint. + +Add the OPPs that apply to RK3588j (and apparently RK3588m too) to +enable dynamic CPU frequency scaling. + +OPP values are derived from Rockchip downstream sources [1] by taking +only those OPPs which have the highest frequency for a given voltage +level and dropping the rest (if they are included, the kernel complains +at boot time about them being inefficient) + +[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi + +Signed-off-by: Alexey Charkov +Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++ + 1 file changed, 108 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +@@ -5,3 +5,111 @@ + */ + + #include "rk3588-extra.dtsi" ++ ++/ { ++ cluster0_opp_table: opp-table-cluster0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <887500 887500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1704000000 { ++ opp-hz = /bits/ 64 <1704000000>; ++ opp-microvolt = <937500 937500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster1_opp_table: opp-table-cluster1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <787500 787500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <875000 875000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <950000 950000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster2_opp_table: opp-table-cluster2 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <787500 787500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <875000 875000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <950000 950000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++}; ++ ++&cpu_b0 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_b1 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_b2 { ++ operating-points-v2 = <&cluster2_opp_table>; ++}; ++ ++&cpu_b3 { ++ operating-points-v2 = <&cluster2_opp_table>; ++}; ++ ++&cpu_l0 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_l1 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_l2 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_l3 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; diff --git a/target/linux/rockchip/patches-6.6/050-27-v6.11-arm64-dts-rockchip-Split-GPU-OPPs-of-RK3588-and-RK3588j.patch b/target/linux/rockchip/patches-6.6/050-27-v6.11-arm64-dts-rockchip-Split-GPU-OPPs-of-RK3588-and-RK3588j.patch new file mode 100644 index 00000000000000..06befc8af9c58c --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-27-v6.11-arm64-dts-rockchip-Split-GPU-OPPs-of-RK3588-and-RK3588j.patch @@ -0,0 +1,177 @@ +From a7b2070505a2a09ea65fa0c8c480c97f62d1978d Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 17 Jun 2024 22:28:58 +0400 +Subject: [PATCH] arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j + +RK3588j uses a different set of OPPs for its GPU, both in terms of +allowed frequencies and in terms of voltages. + +Move the GPU OPPs table into per-variant .dtsi files to accommodate +for this difference. + +The table for RK3588j is adapted from Rockchip downstream sources [1], +while RK3588 one is moved verbatim into the per-variant .dtsi file. +The values provided for RK3588 in the downstream sources match those +in the original commit. + +[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi + +Fixes: 6fca4edb93d3 ("arm64: dts: rockchip: Add rk3588 GPU node") +Signed-off-by: Alexey Charkov +Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-8-c1f5f3267f1e@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 38 ----------------- + arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 41 +++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 33 +++++++++++++++ + 3 files changed, 74 insertions(+), 38 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -451,46 +451,8 @@ + , + ; + interrupt-names = "job", "mmu", "gpu"; +- operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; +- +- gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; +- +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-400000000 { +- opp-hz = /bits/ 64 <400000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-600000000 { +- opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <675000 675000 850000>; +- }; +- opp-700000000 { +- opp-hz = /bits/ 64 <700000000>; +- opp-microvolt = <700000 700000 850000>; +- }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <750000 750000 850000>; +- }; +- opp-900000000 { +- opp-hz = /bits/ 64 <900000000>; +- opp-microvolt = <800000 800000 850000>; +- }; +- opp-1000000000 { +- opp-hz = /bits/ 64 <1000000000>; +- opp-microvolt = <850000 850000 850000>; +- }; +- }; + }; + + usb_host0_xhci: usb@fc000000 { +--- a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi +@@ -114,6 +114,43 @@ + clock-latency-ns = <40000>; + }; + }; ++ ++ gpu_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <675000 675000 850000>; ++ }; ++ opp-700000000 { ++ opp-hz = /bits/ 64 <700000000>; ++ opp-microvolt = <700000 700000 850000>; ++ }; ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-900000000 { ++ opp-hz = /bits/ 64 <900000000>; ++ opp-microvolt = <800000 800000 850000>; ++ }; ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <850000 850000 850000>; ++ }; ++ }; + }; + + &cpu_b0 { +@@ -147,3 +184,7 @@ + &cpu_l3 { + operating-points-v2 = <&cluster0_opp_table>; + }; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +@@ -80,6 +80,35 @@ + clock-latency-ns = <40000>; + }; + }; ++ ++ gpu_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-700000000 { ++ opp-hz = /bits/ 64 <700000000>; ++ opp-microvolt = <750000 750000 850000>; ++ }; ++ opp-850000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <787500 787500 850000>; ++ }; ++ }; + }; + + &cpu_b0 { +@@ -113,3 +142,7 @@ + &cpu_l3 { + operating-points-v2 = <&cluster0_opp_table>; + }; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; From a5d881f3a3db7f05c636391bb337319679317f85 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Thu, 15 Aug 2024 16:04:30 +0800 Subject: [PATCH 3/4] package: busybox: disable mips16 on hard-float The busybox built with mips16 enabled has broken seq command. Disassembling shows that the call to hard-float strtod in mips16 code is generated without the __call_stub_fp. As a result, strtod returns the result in float point registers while the calling mips16 code expect the result in v0/v1. Disable mips16 on hard-float targets for now. The built .ipk goes from 213316 bytes to 251419 bytes. Signed-off-by: Chuanhong Guo --- package/utils/busybox/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/package/utils/busybox/Makefile b/package/utils/busybox/Makefile index 95732789451334..63da28be88f473 100644 --- a/package/utils/busybox/Makefile +++ b/package/utils/busybox/Makefile @@ -6,7 +6,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=busybox PKG_VERSION:=1.36.0 -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_FLAGS:=essential PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 @@ -16,6 +16,10 @@ PKG_HASH:=542750c8af7cb2630e201780b4f99f3dcceeb06f505b479ec68241c1e6af61a5 PKG_BUILD_DEPENDS:=BUSYBOX_CONFIG_PAM:libpam PKG_BUILD_PARALLEL:=1 +ifeq ($(CONFIG_SOFT_FLOAT),) + PKG_BUILD_FLAGS+=no-mips16 +endif + PKG_CHECK_FORMAT_SECURITY:=0 PKG_LICENSE:=GPL-2.0 From 0dc62d9d8bc29307d2001cf04b6a66851433d9e3 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Thu, 8 Aug 2024 12:56:03 +0800 Subject: [PATCH 4/4] siflower: new target for Siflower SF19A2890 Siflower SF19A2890 is an SoC with: Dual-core MIPS InterAptiv at 800MHz DDR3 controller One Gigabit Ethernet MAC with RGMII and IPv4 HNAT engine Built-in 2x2 11N + 2x2 11AC WiFi radio USB 2.0 OTG I2C/SPI/GPIO and various other peripherals This adds support for SF19A2890 EVB with ethernet support. EVB spec: Memory: DDR3 128M Ethernet: RTL8367RB 5-port gigabit switch Flash: 16M NOR Others: MicroUSB OTG, LED x 1, Reset button x1 The built image can be flashed using u-boot recovery. This target is marked as source-only until support for a commercial router board comes. Signed-off-by: Chuanhong Guo --- target/linux/siflower/Makefile | 18 + target/linux/siflower/dts/sf19a2890.dtsi | 651 ++++++++++++++++++ target/linux/siflower/dts/sf19a2890_evb.dts | 140 ++++ .../mips/include/asm/mach-siflower/kmalloc.h | 9 + .../files-6.6/drivers/clk/siflower/Kconfig | 27 + .../files-6.6/drivers/clk/siflower/Makefile | 2 + .../clk/siflower/clk-sf19a2890-periph.c | 170 +++++ .../drivers/clk/siflower/clk-sf19a2890.c | 414 +++++++++++ .../files-6.6/drivers/gpio/gpio-siflower.c | 346 ++++++++++ .../ethernet/stmicro/stmmac/dwmac-sf19a2890.c | 193 ++++++ .../files-6.6/drivers/phy/siflower/Kconfig | 6 + .../files-6.6/drivers/phy/siflower/Makefile | 2 + .../drivers/phy/siflower/phy-sf19a2890-usb.c | 145 ++++ .../drivers/pinctrl/pinctrl-sf19a2890.c | 515 ++++++++++++++ .../drivers/reset/reset-sf19a2890-periph.c | 131 ++++ .../clock/siflower,sf19a2890-clk.h | 27 + target/linux/siflower/image/Makefile | 28 + target/linux/siflower/modules.mk | 15 + ...s-add-support-for-Siflower-SF19A2890.patch | 59 ++ .../002-clk-add-drivers-for-sf19a2890.patch | 31 + .../003-reset-add-support-for-sf19a2890.patch | 38 + ...4-gpio-add-support-for-siflower-socs.patch | 37 + ...rl-add-driver-for-siflower-sf19a2890.patch | 39 ++ ...006-stmmac-add-support-for-sf19a2890.patch | 38 + ...hy-add-support-for-SF19A2890-USB-PHY.patch | 31 + ...2-add-support-for-Siflower-SF19A2890.patch | 36 + ...-OTG-interrupt-regardless-of-GINTSTS.patch | 67 ++ .../base-files/etc/board.d/02_network | 42 ++ .../base-files/lib/upgrade/platform.sh | 22 + target/linux/siflower/sf19a2890/config-6.6 | 266 +++++++ target/linux/siflower/sf19a2890/target.mk | 12 + 31 files changed, 3557 insertions(+) create mode 100644 target/linux/siflower/Makefile create mode 100644 target/linux/siflower/dts/sf19a2890.dtsi create mode 100644 target/linux/siflower/dts/sf19a2890_evb.dts create mode 100644 target/linux/siflower/files-6.6/arch/mips/include/asm/mach-siflower/kmalloc.h create mode 100644 target/linux/siflower/files-6.6/drivers/clk/siflower/Kconfig create mode 100644 target/linux/siflower/files-6.6/drivers/clk/siflower/Makefile create mode 100644 target/linux/siflower/files-6.6/drivers/clk/siflower/clk-sf19a2890-periph.c create mode 100644 target/linux/siflower/files-6.6/drivers/clk/siflower/clk-sf19a2890.c create mode 100644 target/linux/siflower/files-6.6/drivers/gpio/gpio-siflower.c create mode 100644 target/linux/siflower/files-6.6/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c create mode 100644 target/linux/siflower/files-6.6/drivers/phy/siflower/Kconfig create mode 100644 target/linux/siflower/files-6.6/drivers/phy/siflower/Makefile create mode 100644 target/linux/siflower/files-6.6/drivers/phy/siflower/phy-sf19a2890-usb.c create mode 100644 target/linux/siflower/files-6.6/drivers/pinctrl/pinctrl-sf19a2890.c create mode 100644 target/linux/siflower/files-6.6/drivers/reset/reset-sf19a2890-periph.c create mode 100644 target/linux/siflower/files-6.6/include/dt-bindings/clock/siflower,sf19a2890-clk.h create mode 100644 target/linux/siflower/image/Makefile create mode 100644 target/linux/siflower/modules.mk create mode 100644 target/linux/siflower/patches-6.6/001-mips-add-support-for-Siflower-SF19A2890.patch create mode 100644 target/linux/siflower/patches-6.6/002-clk-add-drivers-for-sf19a2890.patch create mode 100644 target/linux/siflower/patches-6.6/003-reset-add-support-for-sf19a2890.patch create mode 100644 target/linux/siflower/patches-6.6/004-gpio-add-support-for-siflower-socs.patch create mode 100644 target/linux/siflower/patches-6.6/005-pinctrl-add-driver-for-siflower-sf19a2890.patch create mode 100644 target/linux/siflower/patches-6.6/006-stmmac-add-support-for-sf19a2890.patch create mode 100644 target/linux/siflower/patches-6.6/007-phy-add-support-for-SF19A2890-USB-PHY.patch create mode 100644 target/linux/siflower/patches-6.6/008-usb-dwc2-add-support-for-Siflower-SF19A2890.patch create mode 100644 target/linux/siflower/patches-6.6/009-usb-dwc2-handle-OTG-interrupt-regardless-of-GINTSTS.patch create mode 100644 target/linux/siflower/sf19a2890/base-files/etc/board.d/02_network create mode 100644 target/linux/siflower/sf19a2890/base-files/lib/upgrade/platform.sh create mode 100644 target/linux/siflower/sf19a2890/config-6.6 create mode 100644 target/linux/siflower/sf19a2890/target.mk diff --git a/target/linux/siflower/Makefile b/target/linux/siflower/Makefile new file mode 100644 index 00000000000000..d6cded021a699f --- /dev/null +++ b/target/linux/siflower/Makefile @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +include $(TOPDIR)/rules.mk + +ARCH:=mipsel +BOARD:=siflower +BOARDNAME:=Siflower SoCs +FEATURES:=squashfs usb usbgadget source-only +SUBTARGETS:=sf19a2890 + +KERNEL_PATCHVER:=6.6 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += \ + kmod-gpio-button-hotplug \ + uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/target/linux/siflower/dts/sf19a2890.dtsi b/target/linux/siflower/dts/sf19a2890.dtsi new file mode 100644 index 00000000000000..b8f1cec83ebd2f --- /dev/null +++ b/target/linux/siflower/dts/sf19a2890.dtsi @@ -0,0 +1,651 @@ +#include +#include +#include +#include + +/ { + compatible = "siflower,sf19a2890"; + #address-cells = <1>; + #size-cells = <1>; + + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + chosen { + bootargs = "earlycon"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + wlan24_dsp: wlandsp@1f00000 { + reg = <0x01f00000 0x200000>; + }; + + wlan5_dsp: wlandsp@2100000 { + reg = <0x02100000 0x200000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mti,interaptiv"; + reg = <0>; + clocks = <&clk CLK_MUXDIV_CPU>; + clock-names = "cpu"; + clock-latency = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "mti,interaptiv"; + reg = <1>; + clocks = <&clk CLK_MUXDIV_CPU>; + clock-names = "cpu"; + clock-latency = <0>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "mti,interaptiv"; + reg = <2>; + clocks = <&clk CLK_MUXDIV_CPU>; + clock-names = "cpu"; + clock-latency = <0>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "mti,interaptiv"; + reg = <3>; + clocks = <&clk CLK_MUXDIV_CPU>; + clock-names = "cpu"; + clock-latency = <0>; + }; + }; + + osc32k: oscillator-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + clock-output-names = "osc32k"; + }; + + osc12m: oscillator-12m { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + #clock-cells = <0>; + clock-output-names = "osc12m"; + }; + + osc40m: oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "osc40m"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&gic>; + + gmac: ethernet@10800000 { + compatible = "siflower,sf19a2890-gmac", "snps,dwmac"; + reg = <0x10800000 0x200000>, + <0x19e04440 0x10>; + interrupts = , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&gmacclk 0>, <&gmacclk 1>, <&gmacclk 3>, <&gmacclk 2>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "gmac_byp_ref"; + resets = <&gmacrst 0>; + reset-names = "stmmaceth"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&mdio_pins>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + wlan_rf: phy@11c00000{ + compatible = "siflower,sf19a2890-rf"; + reg = <0x11c00000 0x600000>; + interrupts = ; + clocks = <&rfclk 1>, <&rfclk 2>, <&rfclk 3>; + clock-names = "axi", "boot", "lp"; + resets = <&rfrst 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pins>; + status = "disabled"; + }; + + usb: usb@17000000 { + compatible = "siflower,sf19a2890-usb"; + reg = <0x17000000 0x40000>; + interrupts = ; + clocks = <&usbclk 0>; + clock-names = "otg"; + resets = <&usbrst 0>; + reset-names = "dwc2"; + dr_mode = "otg"; + phys = <&usb_phy>; + phy-names = "usb2-phy"; + g-np-tx-fifo-size = <768>; + status = "disabled"; + }; + + i2c: i2c@18100000 { + compatible = "snps,designware-i2c"; + reg = <0x18100000 0x1000>; + interrupts = ; + clocks = <&i2cclk 0>; + clock-names = "ref"; + resets = <&i2crst 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + }; + + spi: spi@18202000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x18202000 0x1000>; + cs-gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + clocks = <&spiclk 1>, <&spiclk 0>; + clock-names = "sspclk", "apb_pclk"; + interrupts = ; + resets = <&spirst 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + status = "disabled"; + }; + + uart0: serial@18300000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x18300000 0x1000>; + interrupts = ; + clocks = <&uartclk 3>, <&uartclk 0>; + clock-names = "uartclk", "apb_pclk"; + resets = <&uartrst 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "disabled"; + }; + + uart1: serial@18301000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x18301000 0x1000>; + interrupts = ; + clocks = <&uartclk 4>, <&uartclk 1>; + clock-names = "uartclk", "apb_pclk"; + resets = <&uartrst 1>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; + }; + + uart2: serial@18302000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x18302000 0x1000>; + interrupts = ; + clocks = <&uartclk 5>, <&uartclk 2>; + clock-names = "uartclk", "apb_pclk"; + resets = <&uartrst 2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; + }; + + watchdog: watchdog@18700000 { + compatible = "snps,dw-wdt"; + reg = <0x18700000 0x1000>; + interrupts = ; + clocks = <&wdtclk 0>; + resets = <&wdtrst 0>; + }; + + gpio: gpio@19d00000 { + compatible = "siflower,sf19a2890-gpio"; + reg=<0x19d00000 0x100000>; + interrupts = , + , + , + ; + clocks = <&gpioclk 0>; + resets = <&gpiorst 0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 49>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + clk: clock-controller@19e01000 { + compatible = "siflower,sf19a2890-clk"; + reg = <0x19e01000 0x800>; + clocks = <&osc12m>, <&osc40m>; + clock-names = "osc12m", "osc40m"; + #clock-cells = <1>; + }; + + brom_sysm: syscon@19e02000 { + compatible = "syscon", "simple-mfd"; + reg = <0x19e02000 0x100>; + + reboot { + compatible = "syscon-reboot"; + offset = <0x30>; + value = <0x1>; + }; + }; + + gmacrst: reset-controller@19e04400 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e04400 0x4>; + #reset-cells = <1>; + siflower,reset-masks = <0x3>; + }; + + gmacclk: clock-controller@19e04404 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e04404 0xc>; + clocks = <&clk CLK_MUXDIV_BUS1>, <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_GMAC_BYP_REF>, <&clk CLK_MUXDIV_ETH_TSU>; + clock-output-names = "gmac", "gmac_pclk", "gmac_byp_ref", "ethtsu"; + #clock-cells = <1>; + }; + + wlan24rst: reset-controller@19e08000 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e08000 0x4>; + #reset-cells = <1>; + siflower,reset-masks = <0x7>; + }; + + wlan24clk: clock-controller@19e08004 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e08004 0xc>; + clocks = <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_WLAN24_PLF>; + clock-output-names = "wlan24_axis", "wlan24_axim", "wlan24_plf"; + #clock-cells = <1>; + }; + + rfrst: reset-controller@19e08800 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e08800 0x4>; + #reset-cells = <1>; + siflower,reset-masks = <0x7>; + }; + + rfclk: clock-controller@19e08804 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e08804 0xc>; + clocks = <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_CPU>, <&osc12m>, <&osc32k>; + clock-output-names = "rf_dft", "rf_axis", "rf_boot", "rf_lp"; + #clock-cells = <1>; + }; + + usbrst: reset-controller@19e0c000 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e0c000 0x4>; + #reset-cells = <1>; + siflower,reset-masks = <0x7 0x8 0x10>; + }; + + usbclk: clock-controller@19e0c004 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e0c004 0xc>; + clocks = <&clk CLK_MUXDIV_BUS3>, <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_USBPHY_REF>; + clock-output-names = "usb", "usb_axim", "usbphy_ref"; + siflower,valid-gates = <0xd>; + siflower,critical-gates = <0x4>; + #clock-cells = <1>; + }; + + usb_phy: usb-phy@19e0c040 { + compatible = "siflower,sf19a2890-usb-phy"; + reg = <0x19e0C040 0x60>; + clocks = <&usbclk 2>; + resets = <&usbrst 1>, <&usbrst 2>; + reset-names = "power_on_rst", "usb_phy_rst"; + #phy-cells = <0>; + status = "disabled"; + }; + + wlan5rst: reset-controller@19e0c400 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e0c400 0x4>; + #reset-cells = <1>; + siflower,reset-masks = <0x7>; + }; + + wlan5clk: clock-controller@19e0c404 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e0c404 0xc>; + clocks = <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_WLAN5_PLF>; + clock-output-names = "wlan5_axis", "wlan5_axim", "wlan5_plf"; + #clock-cells = <1>; + }; + + i2crst: reset-controller@19e24400 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e24400 0x4>; + #reset-cells = <1>; + siflower,num-resets = <1>; + }; + + i2cclk: clock-controller@19e24404 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e24404 0xc>; + clocks = <&clk CLK_MUXDIV_PBUS>; + clock-output-names = "i2c0"; + #clock-cells = <1>; + }; + + spirst: reset-controller@19e24800 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e24800 0x4>; + #reset-cells = <1>; + siflower,reset-masks = <0x30>; + }; + + spiclk: clock-controller@19e24804 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e24804 0xc>; + clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>; + clock-output-names = "spi_apb", "spi_ssp"; + siflower,valid-gates = <0x30>; + #clock-cells = <1>; + }; + + uartrst: reset-controller@19e24c00 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e24c00 0x4>; + #reset-cells = <1>; + siflower,reset-masks = <0x11 0x22 0x44>; + }; + + uartclk: clock-controller@19e24c04 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e24c04 0xc>; + clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>, + <&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>; + clock-output-names = "uart0_apb", "uart1_apb", "uart2_apb", + "uart0", "uart1","uart2"; + siflower,valid-gates = <0x77>; + siflower,critical-gates = <0x11>; + #clock-cells = <1>; + }; + + pwmrst: reset-controller@19e25400 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e25400 0x4>; + #reset-cells = <1>; + siflower,num-resets = <1>; + }; + + pwmclk: clock-controller@19e25404 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e25404 0xc>; + clocks = <&clk CLK_MUXDIV_PBUS>; + clock-output-names = "pwm"; + #clock-cells = <1>; + }; + + timerrst: reset-controller@19e25800 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e25800 0x4>; + #reset-cells = <1>; + siflower,num-resets = <1>; + }; + + timerclk: clock-controller@19e25804 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e25804 0xc>; + clocks = <&clk CLK_MUXDIV_PBUS>; + clock-output-names = "timer"; + #clock-cells = <1>; + }; + + wdtrst: reset-controller@19e25c00 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e25c00 0x4>; + #reset-cells = <1>; + siflower,num-resets = <1>; + }; + + wdtclk: clock-controller@19e25c04 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e25c04 0xc>; + clocks = <&clk CLK_MUXDIV_PBUS>; + clock-output-names = "wdt"; + #clock-cells = <1>; + }; + + gpiorst: reset-controller@19e2b400 { + compatible = "siflower,sf19a2890-periph-reset"; + reg = <0x19e2b400 0x4>; + #reset-cells = <1>; + siflower,num-resets = <1>; + }; + + gpioclk: clock-controller@19e2b404 { + compatible = "siflower,sf19a2890-periph-clk"; + reg = <0x19e2b404 0xc>; + clocks = <&clk CLK_MUXDIV_PBUS>; + clock-output-names = "gpio"; + #clock-cells = <1>; + }; + + pinctrl: pinctrl@19e3fc00 { + compatible = "siflower,sf19a2890-pinctrl"; + reg = <0x19e3fc00 0x400>; + + jtag_pins: jtag-pins { + tdo { + pins = "JTAG_TDO"; + function = "func0"; + bias-disable; + }; + + input-pins { + pins = "JTAG_TDI", "JTAG_TMS", "JTAG_TCK"; + function = "func0"; + input-enable; + bias-disable; + }; + + trst { + pins = "JTAG_RST"; + function = "func0"; + input-enable; + bias-pull-down; + }; + }; + + spi_pins: spi-pins { + sck { + pins = "SPI_CLK"; + function = "func0"; + bias-disable; + }; + + mosi { + pins = "SPI_TXD"; + function = "func0"; + bias-pull-down; + }; + + miso { + pins = "SPI_RXD"; + function = "func0"; + input-enable; + bias-pull-down; + }; + + cs { + pins = "SPI_CSN"; + bias-pull-up; + }; + }; + + uart0_pins: uart0-pins { + tx { + pins = "UART_TX"; + function = "func0"; + bias-pull-up; + }; + + rx { + pins = "UART_RX"; + function = "func0"; + input-enable; + bias-pull-up; + }; + }; + + uart0_rtscts: uart0-rtscts-pins { + cts { + pins = "I2C_DAT"; + function = "func0"; + input-enable; + bias-pull-up; + }; + + rts { + pins = "I2C_CLK"; + function = "func0"; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + tx { + pins = "JATG_TDO"; + function = "func1"; + bias-pull-up; + }; + + rx { + pins = "JATG_TDI"; + function = "func1"; + input-enable; + bias-pull-up; + }; + }; + + uart1_rtscts: uart1-rtscts-pins { + cts { + pins = "JTAG_TMS"; + function = "func1"; + input-enable; + bias-pull-up; + }; + + rts { + pins = "JTAG_TCK"; + function = "func1"; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + tx { + pins = "I2C_DAT"; + function = "func1"; + bias-pull-up; + }; + + rx { + pins = "I2C_CLK"; + function = "func1"; + input-enable; + bias-pull-up; + }; + }; + + rgmii_pins: rgmii-pins { + tx-pins { + pins = "RGMII_TXCLK", "RGMII_TXD0", + "RGMII_TXD1", "RGMII_TXD2", + "RGMII_TXD3", "RGMII_TXCTL"; + function = "func0"; + bias-disable; + }; + + rx-pins { + pins = "RGMII_RXCLK", "RGMII_RXD0", + "RGMII_RXD1", "RGMII_RXD2", + "RGMII_RXD3", "RGMII_RXCTL"; + function = "func0"; + input-enable; + bias-disable; + }; + }; + + mdio_pins: mdio-pins { + pins { + pins = "RGMII_MDC", "RGMII_MDIO"; + function = "func0"; + input-enable; + bias-pull-up; + }; + }; + + wlan_pins: wlan-pins { + pins { + pins = "HB0_PA_EN", "HB0_LNA_EN", + "HB0_SW_CTRL0", "HB0_SW_CTRL1", + "HB1_PA_EN", "HB1_LNA_EN", + "HB1_SW_CTRL0", "HB1_SW_CTRL1", + "LB0_PA_EN", "LB0_LNA_EN", + "LB0_SW_CTRL0", "LB0_SW_CTRL1", + "LB1_PA_EN", "LB1_LNA_EN", + "LB1_SW_CTRL0", "LB1_SW_CTRL1"; + function = "func0"; + }; + }; + + + i2c0_pins: i2c0-pins { + pins { + pins = "I2C_CLK", "I2C_DAT"; + function = "func2"; + input-enable; + bias-pull-up; + }; + }; + }; + + gic: interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + mti,reserved-ipi-vectors = <0 8>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&clk CLK_MUXDIV_CPU>; + }; + }; + }; +}; diff --git a/target/linux/siflower/dts/sf19a2890_evb.dts b/target/linux/siflower/dts/sf19a2890_evb.dts new file mode 100644 index 00000000000000..fa71703a318612 --- /dev/null +++ b/target/linux/siflower/dts/sf19a2890_evb.dts @@ -0,0 +1,140 @@ +/dts-v1/; +#include +#include +#include "sf19a2890.dtsi" + +/ { + model = "Siflower SF19A2890 Evaluation Board"; + compatible = "siflower,sf19a2890-evb", "siflower,sf19a2890"; + + aliases { + led-boot = &led_wlan; + led-failsafe = &led_wlan; + led-running = &led_wlan; + led-upgrade = &led_wlan; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + leds { + compatible = "gpio-leds"; + + led_wlan: wlan { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + rtl8367rb { + compatible = "realtek,rtl8367b"; + realtek,extif = <6 0 0 1 1 1 1 1 1 2>; + mii-bus = <&mdio>; + phy-id = <0>; + }; +}; + +&gmac { + status = "okay"; + phy-mode = "rgmii-id"; + snps,ps-speed = <1000>; + nvmem-cells = <&macaddr_factory_0>, <&rgmii_delay_factory_b2>; + nvmem-cell-names = "mac-address", "rgmii-delay"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&wlan_rf { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spl-loader"; + reg = <0x0 0x20000>; /* 128k */ + read-only; + }; + + partition@20000 { + label = "u-boot"; + reg = <0x20000 0x60000>; /* 384k */ + }; + + partition@80000 { + label = "u-boot-env"; + reg = <0x80000 0x10000>; /* 64k */ + }; + + factory: partition@90000 { + label = "factory"; + reg = <0x90000 0x10000>; /* 64k */ + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + rgmii_delay_factory_b2: rgmii-delay@b2 { + reg = <0xb2 0x4>; + }; + }; + }; + + partition@a0000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0xa0000 0x0>; /* 640k- */ + }; + }; + }; +}; diff --git a/target/linux/siflower/files-6.6/arch/mips/include/asm/mach-siflower/kmalloc.h b/target/linux/siflower/files-6.6/arch/mips/include/asm/mach-siflower/kmalloc.h new file mode 100644 index 00000000000000..d0b270e2ec6484 --- /dev/null +++ b/target/linux/siflower/files-6.6/arch/mips/include/asm/mach-siflower/kmalloc.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_SIFLOWER_KMALLOC_H +#define __ASM_MACH_SIFLOWER_KMALLOC_H + +#ifdef CONFIG_DMA_NONCOHERENT +#define ARCH_DMA_MINALIGN 32 +#endif + +#endif /* __ASM_MACH_SIFLOWER_KMALLOC_H */ diff --git a/target/linux/siflower/files-6.6/drivers/clk/siflower/Kconfig b/target/linux/siflower/files-6.6/drivers/clk/siflower/Kconfig new file mode 100644 index 00000000000000..8e1c5a8f269dfb --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/clk/siflower/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 + +menuconfig CLK_SIFLOWER + bool "Siflower SoC driver support" + depends on MIPS || COMPILE_TEST + help + SoC drivers for Siflower Linux-capable SoCs. + +if CLK_SIFLOWER + +config CLK_SF19A2890 + bool "Clock driver for Siflower CLK_SF19A2890" + depends on MIPS || COMPILE_TEST + help + Supports the Top Clock Module found in SF19A2890. If this + kernel is meant to run on a Siflower SF19A2890 SoC, + enable this driver. + +config CLK_SF19A2890_PERIPH + bool "Clock driver for Siflower SF19A2890 peripheral clock gates" + depends on MIPS || COMPILE_TEST + help + Supports the clock gates for various peripherals in SF19A2890. + If this kernel is meant to run on a Siflower SF19A2890 SoC, + enable this driver. + +endif diff --git a/target/linux/siflower/files-6.6/drivers/clk/siflower/Makefile b/target/linux/siflower/files-6.6/drivers/clk/siflower/Makefile new file mode 100644 index 00000000000000..d03a72ee25642e --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/clk/siflower/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_CLK_SF19A2890) += clk-sf19a2890.o +obj-$(CONFIG_CLK_SF19A2890_PERIPH) += clk-sf19a2890-periph.o diff --git a/target/linux/siflower/files-6.6/drivers/clk/siflower/clk-sf19a2890-periph.c b/target/linux/siflower/files-6.6/drivers/clk/siflower/clk-sf19a2890-periph.c new file mode 100644 index 00000000000000..4679c714bd478a --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/clk/siflower/clk-sf19a2890-periph.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include + +#define REG_GATE 0x0 +/* + * A shared 'Bus Output Enable' signal for all APB peripherals. The peripheral + * only responds to bus requests if its dedicated clock is enabled and this + * shared BOE is set. + */ +#define REG_BOE 0x8 +#define BOE_EN GENMASK(1, 0) + +struct sf19a2890_periphclk { + void __iomem *base; + struct clk_hw hw; + u32 idx; +}; + +struct sf19a2890_periphclk_priv { + struct sf19a2890_periphclk *gates; + struct clk_hw_onecell_data clk_data; +}; + +static inline struct sf19a2890_periphclk *hw_to_periphclk(struct clk_hw *hw) +{ + return container_of(hw, struct sf19a2890_periphclk, hw); +} + +static int sf19a2890_periphclk_enable(struct clk_hw *hw) +{ + struct sf19a2890_periphclk *priv = hw_to_periphclk(hw); + u32 reg = readl(priv->base + REG_GATE); + + writel(reg | BIT(priv->idx), priv->base + REG_GATE); + writel(BOE_EN, priv->base + REG_BOE); + return 0; +} + +static void sf19a2890_periphclk_disable(struct clk_hw *hw) +{ + struct sf19a2890_periphclk *priv = hw_to_periphclk(hw); + u32 reg = readl(priv->base + REG_GATE); + + reg &= ~BIT(priv->idx); + writel(reg, priv->base + REG_GATE); + if (reg == 0) + writel(0, priv->base + REG_BOE); +} + +static int sf19a2890_periphclk_is_enabled(struct clk_hw *hw) +{ + struct sf19a2890_periphclk *priv = hw_to_periphclk(hw); + + return !!(readl(priv->base + REG_GATE) & BIT(priv->idx)); +} + +static const struct clk_ops sf19a28_periphclk_ops = { + .enable = sf19a2890_periphclk_enable, + .disable = sf19a2890_periphclk_disable, + .is_enabled = sf19a2890_periphclk_is_enabled, +}; + +static void __init sf19a2890_periphclk_init(struct device_node *node) +{ + struct clk_init_data init = {}; + struct sf19a2890_periphclk_priv *priv; + u32 reg, valid_gates, critical_gates; + int num_clks, i, ret, idx; + const char *name, *parent; + void __iomem *base; + + num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells"); + if (num_clks < 1 || num_clks > 32) + return; + + ret = of_property_read_u32(node, "siflower,valid-gates", &valid_gates); + if (ret < 0) + valid_gates = BIT(num_clks) - 1; + + ret = of_property_read_u32(node, "siflower,critical-gates", &critical_gates); + if (ret < 0) + critical_gates = 0; + + priv = kzalloc(struct_size(priv, clk_data.hws, num_clks), GFP_KERNEL); + if (!priv) + return; + + priv->clk_data.num = num_clks; + + priv->gates = kcalloc(num_clks, sizeof(struct sf19a2890_periphclk), + GFP_KERNEL); + if (!priv->gates) + goto err1; + + base = of_iomap(node, 0); + if (!base) { + pr_err("failed to map resources.\n"); + goto err2; + } + + /* clear unused higher bits for BOE check in disable call. */ + reg = readl(base + REG_GATE); + reg &= valid_gates; + writel(reg, base + REG_GATE); + + for (i = 0, idx = 0; i < num_clks && idx < 32; i++, idx++) { + ret = of_property_read_string_index(node, "clock-output-names", + i, &name); + if (ret != 0) { + pr_err("failed to read output name for the %dth gate.\n", + i); + goto err3; + } + parent = of_clk_get_parent_name(node, i); + if (!parent) { + pr_err("failed to get parent clock for the %dth gate.\n", + i); + goto err3; + } + + while (!(valid_gates & BIT(idx))) { + idx++; + if (idx >= 32) { + pr_err("too few valid gates."); + goto err3; + } + } + + priv->gates[i].base = base; + priv->gates[i].idx = idx; + init.name = name; + init.ops = &sf19a28_periphclk_ops; + init.parent_names = &parent; + init.num_parents = 1; + init.flags = (critical_gates & BIT(idx)) ? CLK_IS_CRITICAL : 0; + priv->gates[i].hw.init = &init; + + ret = clk_hw_register(NULL, &priv->gates[i].hw); + if (ret) { + pr_err("failed to register the %dth gate: %d.\n", i, + ret); + goto err3; + } + priv->clk_data.hws[i] = &priv->gates[i].hw; + } + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, + &priv->clk_data); + if (ret) { + pr_err("failed to add hw provider.\n"); + goto err3; + } + return; +err3: + for (i--; i >= 0; i--) + clk_hw_unregister_gate(priv->clk_data.hws[i]); +err2: + kfree(priv->gates); +err1: + kfree(priv); +} + +CLK_OF_DECLARE(sf19a2890_periphclk, "siflower,sf19a2890-periph-clk", + sf19a2890_periphclk_init); diff --git a/target/linux/siflower/files-6.6/drivers/clk/siflower/clk-sf19a2890.c b/target/linux/siflower/files-6.6/drivers/clk/siflower/clk-sf19a2890.c new file mode 100644 index 00000000000000..626fbe7b8e24ae --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/clk/siflower/clk-sf19a2890.c @@ -0,0 +1,414 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_PLL_BASE 0x0 +#define REG_PLL_PD 0x0 +#define PLL_PD BIT(0) +#define PLL_PD_VCO BIT(1) +#define PLL_PD_POSTDIV BIT(2) +#define PLL_PD_4PHASE BIT(3) +#define PLL_PD_DAC BIT(4) +#define PLL_PD_DSM BIT(5) + +/* + * PLL_PARAM is a 48-bit value put into 6 registers, 8-bit per register: + * REFDIV = PLL_PARAM[47:42] + * POSTDIV2 = PLL_PARAM[41:39] + * POSTDIV1 = PLL_PARAM[38:36] + * FRAC = PLL_PARAM[35:12] + * FBDIV = PLL_PARAM[11:0] + */ + +#define REG_PLL_PARAM(_x) (0x4 + (_x) * 4) +#define PLL_REFDIV_HI 47 +#define PLL_REFDIV_LO 42 +#define PLL_POSTDIV2_HI 41 +#define PLL_POSTDIV2_LO 39 +#define PLL_POSTDIV1_HI 38 +#define PLL_POSTDIV1_LO 36 +#define PLL_FRAC_HI 35 +#define PLL_FRAC_LO 12 +#define PLL_FRAC_BITS (PLL_FRAC_HI - PLL_FRAC_LO + 1) +#define PLL_FBDIV_HI 11 +#define PLL_FBDIV_LO 0 + +#define REG_PLL_CFG 0x1c +#define PLL_CFG_BYPASS BIT(0) +#define PLL_CFG_SRC GENMASK(2, 1) +#define PLL_CFG_OCLK_SEL BIT(3) +#define PLL_CFG_OCLK_GATE BIT(4) +#define PLL_CFG_LOAD_DIVS BIT(5) + +#define REG_PLL_LOCK 0x20 + +/* + * Read-only register indicating the value of the hardware clock source + * override pin. When the first bit of this register is set, PLL clock + * source is forced to the 40M oscillator regardless of PLL_CFG_SRC + * value. + */ +#define REG_PLL_SRC_OVERRIDE 0x24 + +struct sf_clk_common { + void __iomem *base; + spinlock_t *lock; + struct clk_hw hw; +}; + +struct sf19a2890_clk { + struct sf_clk_common common; + ulong offset; +}; + +#define SF_CLK_COMMON(_name, _parents, _op, _flags) \ + { \ + .hw.init = CLK_HW_INIT_PARENTS(_name, _parents, _op, _flags), \ + } + +static inline struct sf_clk_common *hw_to_sf_clk_common(struct clk_hw *hw) +{ + return container_of(hw, struct sf_clk_common, hw); +} + +static inline struct sf19a2890_clk *cmn_to_clk(struct sf_clk_common *cmn_priv) +{ + return container_of(cmn_priv, struct sf19a2890_clk, common); +} + +static inline u32 sf_readl(struct sf_clk_common *priv, u32 reg) +{ + return readl(priv->base + reg); +} + +static inline void sf_writel(struct sf_clk_common *priv, u32 reg, u32 val) +{ + return writel(val, priv->base + reg); +} + +static inline void sf_rmw(struct sf_clk_common *priv, u32 reg, u32 clr, u32 set) +{ + u32 val = sf_readl(priv, reg); + + val &= ~clr; + val |= set; + sf_writel(priv, reg, val); +} + +static u32 sf_pll_param_get(struct sf19a2890_clk *priv, u32 hi, u32 lo) +{ + struct sf_clk_common *cmn = &priv->common; + u32 ret = 0; + int reg_hi = hi / 8; + int reg_lo = lo / 8; + u32 reg_hi_pos = hi % 8; + u32 reg_lo_pos = lo % 8; + int i; + + if (reg_hi == reg_lo) { + u32 mask = (BIT(reg_hi_pos - reg_lo_pos + 1)) - 1; + u32 reg_val = + sf_readl(cmn, priv->offset + REG_PLL_PARAM(reg_hi)); + return (reg_val >> reg_lo_pos) & mask; + } + + ret = sf_readl(cmn, priv->offset + REG_PLL_PARAM(reg_hi)) & + (BIT(reg_hi_pos + 1) - 1); + for (i = reg_hi - 1; i > reg_lo; i--) + ret = (ret << 8) | + sf_readl(cmn, priv->offset + REG_PLL_PARAM(i)); + ret = (ret << (8 - reg_lo_pos)) | + (sf_readl(cmn, priv->offset + REG_PLL_PARAM(reg_lo)) >> + reg_lo_pos); + + return ret; +} + +static unsigned long sf19a28_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + u32 refdiv = sf_pll_param_get(priv, PLL_REFDIV_HI, PLL_REFDIV_LO); + u32 fbdiv = sf_pll_param_get(priv, PLL_FBDIV_HI, PLL_FBDIV_LO); + u32 postdiv1 = sf_pll_param_get(priv, PLL_POSTDIV1_HI, PLL_POSTDIV1_LO); + u32 postdiv2 = sf_pll_param_get(priv, PLL_POSTDIV2_HI, PLL_POSTDIV2_LO); + u32 pll_pd = sf_readl(cmn_priv, PLL_PD); + u32 ref = parent_rate / refdiv; + u32 rate = ref * fbdiv; + u32 frac; + u64 frac_rate; + + if (!(pll_pd & PLL_PD_DSM)) { + frac = sf_pll_param_get(priv, PLL_FRAC_HI, PLL_FRAC_LO); + frac_rate = ((u64)rate * frac) >> PLL_FRAC_BITS; + rate += frac_rate; + } + rate = rate / postdiv1 / postdiv2; + return rate; +} + +static u8 sf19a28_pll_get_parent(struct clk_hw *hw) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + u32 cfg; + + if (sf_readl(cmn_priv, priv->offset + REG_PLL_SRC_OVERRIDE)) + return 1; + cfg = sf_readl(cmn_priv, priv->offset + REG_PLL_CFG); + return (FIELD_GET(PLL_CFG_SRC, cfg) == 1); +} + +static const struct clk_ops sf19a28_pll_ops = { + .recalc_rate = sf19a28_pll_recalc_rate, + .get_parent = sf19a28_pll_get_parent, +}; + +static const char * const clk_pll_parents[] = { "osc12m", "osc40m" }; + +#define SF19A28_PLL(_name, _offset, _flags) \ + struct sf19a2890_clk _name = { \ + .common = SF_CLK_COMMON(#_name, clk_pll_parents, \ + &sf19a28_pll_ops, _flags), \ + .offset = REG_PLL_BASE + _offset, \ + } + +static SF19A28_PLL(pll_cpu, 0x0, 0); +static SF19A28_PLL(pll_ddr, 0x40, 0); +static SF19A28_PLL(pll_cmn, 0x80, 0); + +#define REG_MUXDIV_BASE 0x400 +#define REG_MUXDIV_CFG 0x0 +#define MUXDIV_USE_NCO BIT(3) +#define MUXDIV_SRC_SEL GENMASK(2, 0) +#define REG_MUXDIV_RATIO 0x4 +#define MUXDIV_RATIO_MAX 0xff +#define REG_MUXDIV_NCO_V 0x8 +#define REG_MUXDIV_EN 0xc +#define REG_MUXDIV_XN_DIV_RATIO 0x10 +#define MUXDIV_XN_DIV_MAX 3 + +static unsigned long sf19a28_muxdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + u32 div; + + div = sf_readl(cmn_priv, priv->offset + REG_MUXDIV_RATIO) + 1; + return parent_rate / div; +} + +int sf19a28_muxdiv_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) +{ + unsigned int div; + + div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate); + if (!div) + div = 1; + else if (div > MUXDIV_RATIO_MAX + 1) + div = MUXDIV_RATIO_MAX + 1; + + req->rate = req->best_parent_rate / div; + return 0; +} + +static int sf19a28_muxdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + unsigned int div; + + div = DIV_ROUND_CLOSEST(parent_rate, rate); + if (div < 1) + div = 1; + else if (div > MUXDIV_RATIO_MAX + 1) + div = MUXDIV_RATIO_MAX + 1; + div -= 1; + + sf_writel(cmn_priv, priv->offset + REG_MUXDIV_RATIO, div); + + return 0; +} + +static int sf19a28_muxdiv_enable(struct clk_hw *hw) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + + sf_writel(cmn_priv, priv->offset + REG_MUXDIV_EN, 1); + return 0; +} + +static void sf19a28_muxdiv_disable(struct clk_hw *hw) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + + sf_writel(cmn_priv, priv->offset + REG_MUXDIV_EN, 0); +} + +static int sf19a28_muxdiv_is_enabled(struct clk_hw *hw) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + + return !!sf_readl(cmn_priv, priv->offset + REG_MUXDIV_EN); +} + +static u8 sf19a28_muxdiv_get_parent(struct clk_hw *hw) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + u32 cfg = sf_readl(cmn_priv, priv->offset + REG_MUXDIV_CFG); + u32 src = FIELD_GET(MUXDIV_SRC_SEL, cfg); + + if (src <= 2) + return src; + if (src == 4) + return 3; + return 4; +} + +static int sf19a28_muxdiv_set_parent(struct clk_hw *hw, u8 index) +{ + struct sf_clk_common *cmn_priv = hw_to_sf_clk_common(hw); + struct sf19a2890_clk *priv = cmn_to_clk(cmn_priv); + u32 src; + + if (index <= 2) + src = index; + else if (index == 3) + src = 4; + else + src = 6; + sf_writel(cmn_priv, priv->offset + REG_MUXDIV_CFG, src); + return 0; +} + +static const char * const clk_muxdiv_parents[] = { "pll_cpu", "pll_ddr", "pll_cmn", + "osc12m", "osc40m" }; + +static const struct clk_ops sf19a28_muxdiv_ops = { + .recalc_rate = sf19a28_muxdiv_recalc_rate, + .determine_rate = sf19a28_muxdiv_determine_rate, + .set_rate = sf19a28_muxdiv_set_rate, + .enable = sf19a28_muxdiv_enable, + .disable = sf19a28_muxdiv_disable, + .is_enabled = sf19a28_muxdiv_is_enabled, + .get_parent = sf19a28_muxdiv_get_parent, + .set_parent = sf19a28_muxdiv_set_parent, +}; + +#define SF19A28_MUXDIV(_name, _offset, _flags) \ + struct sf19a2890_clk _name = { \ + .common = SF_CLK_COMMON(#_name, clk_muxdiv_parents, \ + &sf19a28_muxdiv_ops, _flags), \ + .offset = REG_MUXDIV_BASE + _offset, \ + } + +static SF19A28_MUXDIV(muxdiv_bus1, 0x0, CLK_IS_CRITICAL); +static SF19A28_MUXDIV(muxdiv_bus2, 0x20, CLK_IS_CRITICAL); +static SF19A28_MUXDIV(muxdiv_bus3, 0x40, CLK_IS_CRITICAL); +static SF19A28_MUXDIV(muxdiv_cpu, 0x100, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); +static SF19A28_MUXDIV(muxdiv_pbus, 0x120, CLK_IS_CRITICAL); +static SF19A28_MUXDIV(muxdiv_mem_phy, 0x140, CLK_IS_CRITICAL); +static SF19A28_MUXDIV(muxdiv_uart, 0x180, 0); +static SF19A28_MUXDIV(muxdiv_eth_ref, 0x200, 0); +static SF19A28_MUXDIV(muxdiv_eth_byp_ref, 0x220, 0); +static SF19A28_MUXDIV(muxdiv_eth_tsu, 0x240, 0); +static SF19A28_MUXDIV(muxdiv_gmac_byp_ref, 0x260, 0); +static SF19A28_MUXDIV(muxdiv_m6250_0, 0x280, 0); +static SF19A28_MUXDIV(muxdiv_m6250_1, 0x2a0, 0); +static SF19A28_MUXDIV(muxdiv_wlan24_plf, 0x2c0, 0); +static SF19A28_MUXDIV(muxdiv_wlan5_plf, 0x2e0, 0); +static SF19A28_MUXDIV(muxdiv_usbphy_ref, 0x300, 0); +static SF19A28_MUXDIV(muxdiv_tclk, 0x320, 0); +static SF19A28_MUXDIV(muxdiv_npu_pe, 0x340, 0); + +static struct clk_hw_onecell_data sf19a2890_hw_clks = { + .num = CLK_SF19A2890_MAX, + .hws = { + [CLK_PLL_CPU] = &pll_cpu.common.hw, + [CLK_PLL_DDR] = &pll_ddr.common.hw, + [CLK_PLL_CMN] = &pll_cmn.common.hw, + [CLK_MUXDIV_BUS1] = &muxdiv_bus1.common.hw, + [CLK_MUXDIV_BUS2] = &muxdiv_bus2.common.hw, + [CLK_MUXDIV_BUS3] = &muxdiv_bus3.common.hw, + [CLK_MUXDIV_CPU] = &muxdiv_cpu.common.hw, + [CLK_MUXDIV_PBUS] = &muxdiv_pbus.common.hw, + [CLK_MUXDIV_MEM_PHY] = &muxdiv_mem_phy.common.hw, + [CLK_MUXDIV_UART] = &muxdiv_uart.common.hw, + [CLK_MUXDIV_ETH_REF] = &muxdiv_eth_ref.common.hw, + [CLK_MUXDIV_ETH_BYP_REF] = &muxdiv_eth_byp_ref.common.hw, + [CLK_MUXDIV_ETH_TSU] = &muxdiv_eth_tsu.common.hw, + [CLK_MUXDIV_GMAC_BYP_REF] = &muxdiv_gmac_byp_ref.common.hw, + [CLK_MUXDIV_M6250_0] = &muxdiv_m6250_0.common.hw, + [CLK_MUXDIV_M6250_1] = &muxdiv_m6250_1.common.hw, + [CLK_MUXDIV_WLAN24_PLF] = &muxdiv_wlan24_plf.common.hw, + [CLK_MUXDIV_WLAN5_PLF] = &muxdiv_wlan5_plf.common.hw, + [CLK_MUXDIV_USBPHY_REF] = &muxdiv_usbphy_ref.common.hw, + [CLK_MUXDIV_TCLK] = &muxdiv_tclk.common.hw, + [CLK_MUXDIV_NPU_PE_CLK] = &muxdiv_npu_pe.common.hw, + }, +}; + + +struct sf19a2890_clk_ctrl { + void __iomem *base; + spinlock_t lock; +}; + +static void __init sf19a2890_clk_init(struct device_node *node) +{ + struct sf19a2890_clk_ctrl *ctrl; + int i, ret; + + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return; + + ctrl->base = of_iomap(node, 0); + if (!ctrl->base) { + pr_err("failed to map resources.\n"); + return; + } + + spin_lock_init(&ctrl->lock); + + for (i = 0; i < sf19a2890_hw_clks.num; i++) { + struct clk_hw *hw = sf19a2890_hw_clks.hws[i]; + struct sf_clk_common *common; + + if (!hw) + continue; + common = hw_to_sf_clk_common(hw); + common->base = ctrl->base; + common->lock = &ctrl->lock; + ret = clk_hw_register(NULL, hw); + if (ret) { + pr_err("Couldn't register clock %d: %d\n", i, ret); + goto err; + } + } + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &sf19a2890_hw_clks); + if (ret) { + pr_err("failed to add hw provider.\n"); + goto err; + } + return; +err: + iounmap(ctrl->base); +} + +CLK_OF_DECLARE(sf19a2890_clk, "siflower,sf19a2890-clk", sf19a2890_clk_init); diff --git a/target/linux/siflower/files-6.6/drivers/gpio/gpio-siflower.c b/target/linux/siflower/files-6.6/drivers/gpio/gpio-siflower.c new file mode 100644 index 00000000000000..b28ecafec87ff2 --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/gpio/gpio-siflower.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_IR(n) (0x40 * (n) + 0x00) +#define GPIO_OR(n) (0x40 * (n) + 0x04) +#define GPIO_OEN(n) (0x40 * (n) + 0x08) +#define GPIO_IMR(n) (0x40 * (n) + 0x0c) +#define GPIO_GPIMR(n) (0x40 * (n) + 0x10) +#define GPIO_PIR(n) (0x40 * (n) + 0x14) +#define GPIO_ITR(n) (0x40 * (n) + 0x18) +#define GPIO_IFR(n) (0x40 * (n) + 0x1c) +#define GPIO_ICR(n) (0x40 * (n) + 0x20) +#define GPIO_GPxIR(n) (0x4 * (n) + 0x4000) + +#define GPIOS_PER_GROUP 16 + +struct sf_gpio_priv { + struct gpio_chip gc; + void __iomem *base; + struct clk *clk; + struct reset_control *rstc; + unsigned int irq[]; +}; + +#define to_sf_gpio(x) container_of(x, struct sf_gpio_priv, gc) + +static u32 sf_gpio_rd(struct sf_gpio_priv *priv, unsigned long reg) +{ + return readl_relaxed(priv->base + reg); +} + +static void sf_gpio_wr(struct sf_gpio_priv *priv, unsigned long reg, + u32 val) +{ + writel_relaxed(val, priv->base + reg); +} + +static int sf_gpio_get_value(struct gpio_chip *gc, unsigned int offset) +{ + struct sf_gpio_priv *priv = to_sf_gpio(gc); + + return sf_gpio_rd(priv, GPIO_IR(offset)); +} + +static void sf_gpio_set_value(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct sf_gpio_priv *priv = to_sf_gpio(gc); + + sf_gpio_wr(priv, GPIO_OR(offset), value); +} + +static int sf_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + struct sf_gpio_priv *priv = to_sf_gpio(gc); + + if (sf_gpio_rd(priv, GPIO_OEN(offset))) + return GPIO_LINE_DIRECTION_IN; + else + return GPIO_LINE_DIRECTION_OUT; +} + +static int sf_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) +{ + struct sf_gpio_priv *priv = to_sf_gpio(gc); + + sf_gpio_wr(priv, GPIO_OEN(offset), 1); + return 0; +} + +static int sf_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct sf_gpio_priv *priv = to_sf_gpio(gc); + + sf_gpio_wr(priv, GPIO_OR(offset), value); + sf_gpio_wr(priv, GPIO_OEN(offset), 0); + return 0; +} + +static int sf_gpio_set_debounce(struct gpio_chip *gc, unsigned int offset, + u32 debounce) +{ + struct sf_gpio_priv *priv = to_sf_gpio(gc); + unsigned long freq = clk_get_rate(priv->clk); + u64 mul; + + /* (ICR + 1) * IFR = debounce_us * clkfreq_mhz / 4 */ + mul = (u64)debounce * freq; + do_div(mul, 1000000 * 4); + if (mul > 0xff00) + return -EINVAL; + + sf_gpio_wr(priv, GPIO_ICR(offset), 0xff); + sf_gpio_wr(priv, GPIO_IFR(offset), DIV_ROUND_UP(mul, 0x100)); + + return 0; +} + +static int sf_gpio_set_config(struct gpio_chip *gc, unsigned int offset, + unsigned long config) +{ + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_INPUT_DEBOUNCE: + return sf_gpio_set_debounce(gc, offset, + pinconf_to_config_argument(config)); + default: + return gpiochip_generic_config(gc, offset, config); + } +} + +static void sf_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct sf_gpio_priv *priv = to_sf_gpio(gc); + unsigned long offset = irqd_to_hwirq(data); + + sf_gpio_wr(priv, GPIO_PIR(offset), 0); +} + +static void sf_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct sf_gpio_priv *priv = to_sf_gpio(gc); + unsigned long offset = irqd_to_hwirq(data); + + sf_gpio_wr(priv, GPIO_IMR(offset), 1); + sf_gpio_wr(priv, GPIO_GPIMR(offset), 1); +} + +static void sf_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct sf_gpio_priv *priv = to_sf_gpio(gc); + unsigned long offset = irqd_to_hwirq(data); + + sf_gpio_wr(priv, GPIO_IMR(offset), 0); + sf_gpio_wr(priv, GPIO_GPIMR(offset), 0); +} + +/* We are actually setting the parents' affinity. */ +static int sf_gpio_irq_set_affinity(struct irq_data *data, + const struct cpumask *dest, bool force) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + unsigned long offset = irqd_to_hwirq(data); + const struct cpumask *pdest; + struct irq_desc *pdesc; + struct irq_data *pdata; + unsigned int group; + int ret; + + /* Find the parent IRQ and call its irq_set_affinity */ + group = offset / GPIOS_PER_GROUP; + if (group >= gc->irq.num_parents) + return -EINVAL; + + pdesc = irq_to_desc(gc->irq.parents[group]); + if (!pdesc) + return -EINVAL; + + pdata = irq_desc_get_irq_data(pdesc); + if (!pdata->chip->irq_set_affinity) + return -EINVAL; + + ret = pdata->chip->irq_set_affinity(pdata, dest, force); + if (ret < 0) + return ret; + + /* Copy its effective_affinity back */ + pdest = irq_data_get_effective_affinity_mask(pdata); + irq_data_update_effective_affinity(data, pdest); + return ret; +} + +static int sf_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct sf_gpio_priv *priv = to_sf_gpio(gc); + unsigned long offset = irqd_to_hwirq(data); + u32 val; + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + val = 4; + break; + case IRQ_TYPE_EDGE_FALLING: + val = 2; + break; + case IRQ_TYPE_EDGE_BOTH: + val = 6; + break; + case IRQ_TYPE_LEVEL_HIGH: + val = 1; + break; + case IRQ_TYPE_LEVEL_LOW: + val = 0; + break; + default: + return -EINVAL; + } + sf_gpio_wr(priv, GPIO_ITR(offset), val); + + if (flow_type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(data, handle_level_irq); + else + irq_set_handler_locked(data, handle_edge_irq); + + return 0; +} + +static const struct irq_chip sf_gpio_irqchip = { + .name = KBUILD_MODNAME, + .irq_ack = sf_gpio_irq_ack, + .irq_mask = sf_gpio_irq_mask, + .irq_unmask = sf_gpio_irq_unmask, + .irq_set_affinity = sf_gpio_irq_set_affinity, + .irq_set_type = sf_gpio_irq_set_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void sf_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct irq_chip *ic = irq_desc_get_chip(desc); + struct sf_gpio_priv *priv = to_sf_gpio(gc); + unsigned int irq = irq_desc_get_irq(desc); + unsigned int group = irq - priv->irq[0]; + unsigned long pending; + unsigned int n; + + chained_irq_enter(ic, desc); + + pending = sf_gpio_rd(priv, GPIO_GPxIR(group)); + for_each_set_bit(n, &pending, GPIOS_PER_GROUP) { + generic_handle_domain_irq(gc->irq.domain, + n + group * GPIOS_PER_GROUP); + } + + chained_irq_exit(ic, desc); +} + +static int sf_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sf_gpio_priv *priv; + struct gpio_irq_chip *girq; + struct gpio_chip *gc; + u32 ngpios, ngroups; + int ret, i; + + ngpios = (unsigned int) device_get_match_data(dev); + ngroups = DIV_ROUND_UP(ngpios, GPIOS_PER_GROUP); + priv = devm_kzalloc(dev, struct_size(priv, irq, ngroups), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + priv->rstc = devm_reset_control_get_optional(&pdev->dev, NULL); + if (IS_ERR(priv->rstc)) + return PTR_ERR(priv->rstc); + + ret = reset_control_deassert(priv->rstc); + if (ret) + return ret; + + for (i = 0; i < ngroups; i++) { + ret = platform_get_irq(pdev, i); + if (ret < 0) + return ret; + + priv->irq[i] = ret; + } + + gc = &priv->gc; + gc->label = KBUILD_MODNAME; + gc->parent = dev; + gc->owner = THIS_MODULE; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->get_direction = sf_gpio_get_direction; + gc->direction_input = sf_gpio_direction_input; + gc->direction_output = sf_gpio_direction_output; + gc->get = sf_gpio_get_value; + gc->set = sf_gpio_set_value; + gc->set_config = sf_gpio_set_config; + gc->base = -1; + gc->ngpio = ngpios; + + girq = &gc->irq; + gpio_irq_chip_set_chip(girq, &sf_gpio_irqchip); + girq->num_parents = ngroups; + girq->parents = priv->irq; + girq->parent_handler = sf_gpio_irq_handler; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + platform_set_drvdata(pdev, priv); + return devm_gpiochip_add_data(dev, gc, priv); +} + +static int sf_gpio_remove(struct platform_device *pdev) +{ + struct sf_gpio_priv *priv = platform_get_drvdata(pdev); + + reset_control_assert(priv->rstc); + return 0; +} + +static const struct of_device_id sf_gpio_ids[] = { + { .compatible = "siflower,sf19a2890-gpio", .data = (void *)49 }, + {}, +}; +MODULE_DEVICE_TABLE(of, sf_gpio_ids); + +static struct platform_driver sf_gpio_driver = { + .probe = sf_gpio_probe, + .remove = sf_gpio_remove, + .driver = { + .name = "siflower_gpio", + .owner = THIS_MODULE, + .of_match_table = sf_gpio_ids, + }, +}; +module_platform_driver(sf_gpio_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Qingfang Deng "); +MODULE_DESCRIPTION("GPIO driver for SiFlower SoCs"); diff --git a/target/linux/siflower/files-6.6/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c b/target/linux/siflower/files-6.6/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c new file mode 100644 index 00000000000000..05067e9a438169 --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Siflower SF19A2890 GMAC glue layer + * SF19A2890 GMAC is a DWMAC 3.73a with a custom HNAT engine + * between its MAC and DMA engine. + * + * Copyright (C) 2024 Chuanhong Guo + */ + +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +struct sf19a2890_gmac_priv { + struct device *dev; + void __iomem *gmac_cfg; + struct clk *gmac_byp_ref_clk; +}; + +#define REG_MISC 0x0 +#define MISC_PHY_INTF_SEL GENMASK(2, 0) +#define PHY_IF_GMII_MII 0 +#define PHY_IF_RGMII 1 +#define PHY_IF_RMII 4 +#define MISC_PTP_AUX_TS_TRIG BIT(3) +#define MISC_SBD_FLOWCTRL BIT(4) +#define CLK_RMII_OEN BIT(5) + +#define REG_CLK_TX_DELAY 0x4 +#define REG_CLK_RX_PHY_DELAY 0x8 +#define REG_CLK_RX_PHY_DELAY_EN 0xc + +/* Siflower stores RGMII delay as a 4-byte hex string in MTD. */ +#define SFGMAC_DELAY_STR_LEN 4 +static int sfgmac_set_delay_from_nvmem(struct sf19a2890_gmac_priv *priv) +{ + struct device_node *np = priv->dev->of_node; + int ret = 0; + struct nvmem_cell *cell; + const void *data; + size_t retlen; + u16 gmac_delay; + u8 delay_tx, delay_rx; + + cell = of_nvmem_cell_get(np, "rgmii-delay"); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + data = nvmem_cell_read(cell, &retlen); + nvmem_cell_put(cell); + + if (IS_ERR(data)) + return PTR_ERR(data); + + if (retlen < SFGMAC_DELAY_STR_LEN) { + ret = -EINVAL; + goto exit; + } + + ret = kstrtou16(data, 16, &gmac_delay); + if (ret == 0) { + delay_tx = (gmac_delay >> 8) & 0xff; + delay_rx = gmac_delay & 0xff; + writel(delay_tx, priv->gmac_cfg + REG_CLK_TX_DELAY); + writel(delay_rx, priv->gmac_cfg + REG_CLK_RX_PHY_DELAY); + if (delay_rx) + writel(1, priv->gmac_cfg + REG_CLK_RX_PHY_DELAY_EN); + } + +exit: + kfree(data); + + return ret; +} + +static int sfgmac_setup_phy_interface(struct sf19a2890_gmac_priv *priv) +{ + phy_interface_t phy_iface; + int mode; + u32 reg; + + of_get_phy_mode(priv->dev->of_node, &phy_iface); + switch (phy_iface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + mode = PHY_IF_GMII_MII; + break; + case PHY_INTERFACE_MODE_RMII: + mode = PHY_IF_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + mode = PHY_IF_RGMII; + break; + default: + return -EOPNOTSUPP; + } + reg = readl(priv->gmac_cfg + REG_MISC); + reg &= ~MISC_PHY_INTF_SEL; + reg |= FIELD_PREP(MISC_PHY_INTF_SEL, mode); + writel(reg, priv->gmac_cfg + REG_MISC); + return 0; +} + +static int sf19a2890_gmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct sf19a2890_gmac_priv *priv; + struct stmmac_resources stmmac_res; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + + priv->gmac_byp_ref_clk = devm_clk_get_enabled(&pdev->dev, "gmac_byp_ref"); + if (IS_ERR(priv->gmac_byp_ref_clk)) + return PTR_ERR(priv->gmac_byp_ref_clk); + + priv->gmac_cfg = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(priv->gmac_cfg)) { + dev_err(&pdev->dev, "failed to map regs for gmac config.\n"); + return PTR_ERR(priv->gmac_cfg); + } + + ret = sfgmac_set_delay_from_nvmem(priv); + if (ret == -EPROBE_DEFER) + return -EPROBE_DEFER; + + ret = sfgmac_setup_phy_interface(priv); + if (ret) + return ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) { + dev_err(&pdev->dev, "dt configuration failed\n"); + return PTR_ERR(plat_dat); + } + + plat_dat->bsp_priv = priv; + /* This DWMAC has PCSSEL set, but it's not SGMII capable, and doesn't + * return anything in PCS registers under RGMII mode. + * Set this flag to bypass reading pcs regs stmmac_ethtool_get_link_ksettings. + * No idea if it's correct or not. + */ + plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS; + + ret = stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); + if (ret) + goto err_remove_config_dt; + + return 0; + +err_remove_config_dt: + if (pdev->dev.of_node) + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; +} + +static const struct of_device_id dwmac_sf19a2890_match[] = { + { .compatible = "siflower,sf19a2890-gmac"}, + { } +}; +MODULE_DEVICE_TABLE(of, dwmac_sf19a2890_match); + +static struct platform_driver sf19a2890_gmac_driver = { + .probe = sf19a2890_gmac_probe, + .remove_new = stmmac_pltfr_remove, + .driver = { + .name = "sf19a2890-gmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = dwmac_sf19a2890_match, + }, +}; +module_platform_driver(sf19a2890_gmac_driver); + +MODULE_DESCRIPTION("SF19A2890 GMAC driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/siflower/files-6.6/drivers/phy/siflower/Kconfig b/target/linux/siflower/files-6.6/drivers/phy/siflower/Kconfig new file mode 100644 index 00000000000000..000d1864e99b2d --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/phy/siflower/Kconfig @@ -0,0 +1,6 @@ +config PHY_SF19A2890_USB + tristate "SIFLOWER sf19a2890 USB2.0 PHY driver" + default n + select GENERIC_PHY + help + Enable this to support the USB2.0 PHY on the SIFLOWER SF19A2890. diff --git a/target/linux/siflower/files-6.6/drivers/phy/siflower/Makefile b/target/linux/siflower/files-6.6/drivers/phy/siflower/Makefile new file mode 100644 index 00000000000000..0c65e8c8663226 --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/phy/siflower/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_PHY_SF19A2890_USB) += phy-sf19a2890-usb.o + diff --git a/target/linux/siflower/files-6.6/drivers/phy/siflower/phy-sf19a2890-usb.c b/target/linux/siflower/files-6.6/drivers/phy/siflower/phy-sf19a2890-usb.c new file mode 100644 index 00000000000000..21f65957bec025 --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/phy/siflower/phy-sf19a2890-usb.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USB_SLEEPM 0x4 + +struct sf19a2890_usb_phy { + struct device *dev; + struct clk *phy_clk; + struct reset_control *usb_phy_rst; + struct reset_control *power_on_rst; + void __iomem *base; +}; + +static int sf19a2890_usb_phy_power_on(struct phy *phy) +{ + struct sf19a2890_usb_phy *p_phy = phy_get_drvdata(phy); + int ret; + + ret = clk_prepare_enable(p_phy->phy_clk); + if (ret < 0) { + dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret); + return ret; + } + + ret = reset_control_deassert(p_phy->usb_phy_rst); + if (ret) + goto err1; + + ret = reset_control_deassert(p_phy->power_on_rst); + if (ret) + goto err2; + + writel(1, p_phy->base + USB_SLEEPM); + return 0; +err2: + reset_control_assert(p_phy->usb_phy_rst); +err1: + clk_disable_unprepare(p_phy->phy_clk); + return ret; +} + +static int sf19a2890_usb_phy_power_off(struct phy *phy) +{ + struct sf19a2890_usb_phy *p_phy = phy_get_drvdata(phy); + + writel(0, p_phy->base + USB_SLEEPM); + reset_control_assert(p_phy->power_on_rst); + reset_control_assert(p_phy->usb_phy_rst); + clk_disable_unprepare(p_phy->phy_clk); + return 0; +} + +static const struct phy_ops sf19a2890_usb_phy_ops = { + .power_on = sf19a2890_usb_phy_power_on, + .power_off = sf19a2890_usb_phy_power_off, + .owner = THIS_MODULE, +}; + +static int sf19a2890_usb_phy_probe(struct platform_device *pdev) +{ + struct sf19a2890_usb_phy *p_phy; + struct phy_provider *provider; + struct phy *phy; + int ret; + + p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL); + if (!p_phy) + return -ENOMEM; + + p_phy->dev = &pdev->dev; + + p_phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(p_phy->base)) + return PTR_ERR(p_phy->base); + + p_phy->phy_clk = devm_clk_get(p_phy->dev, NULL); + if (IS_ERR(p_phy->phy_clk)) + return dev_err_probe(p_phy->dev, PTR_ERR(p_phy->phy_clk), + "failed to get usb phy clock\n"); + + p_phy->power_on_rst = + devm_reset_control_get_exclusive(&pdev->dev, "power_on_rst"); + if (IS_ERR(p_phy->power_on_rst)) + return PTR_ERR(p_phy->power_on_rst); + + ret = reset_control_assert(p_phy->power_on_rst); + if (ret) + return ret; + + p_phy->usb_phy_rst = + devm_reset_control_get_exclusive(&pdev->dev, "usb_phy_rst"); + if (IS_ERR(p_phy->usb_phy_rst)) + return PTR_ERR(p_phy->usb_phy_rst); + + ret = reset_control_assert(p_phy->usb_phy_rst); + if (ret) + return ret; + + phy = devm_phy_create(p_phy->dev, NULL, &sf19a2890_usb_phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(p_phy->dev, PTR_ERR(phy), + "Failed to create PHY\n"); + + phy_set_drvdata(phy, p_phy); + + provider = + devm_of_phy_provider_register(p_phy->dev, of_phy_simple_xlate); + if (IS_ERR(provider)) + return dev_err_probe(p_phy->dev, PTR_ERR(provider), + "Failed to register PHY provider\n"); + + platform_set_drvdata(pdev, p_phy); + return 0; +} + +static const struct of_device_id sf19a2890_usb_phy_of_match[] = { + { + .compatible = "siflower,sf19a2890-usb-phy", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, sf19a2890_usb_phy_of_match); + +static struct platform_driver sf19a2890_usb_phy_driver = { + .probe = sf19a2890_usb_phy_probe, + .driver = { + .name = "sf19a2890-usb-phy", + .of_match_table = sf19a2890_usb_phy_of_match, + }, +}; +module_platform_driver(sf19a2890_usb_phy_driver); + +MODULE_AUTHOR("Ziying Wu "); +MODULE_DESCRIPTION("Siflower SF19A2890 USB2.0 PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/siflower/files-6.6/drivers/pinctrl/pinctrl-sf19a2890.c b/target/linux/siflower/files-6.6/drivers/pinctrl/pinctrl-sf19a2890.c new file mode 100644 index 00000000000000..42f8cb9668f4b5 --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/pinctrl/pinctrl-sf19a2890.c @@ -0,0 +1,515 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Siflower SF19A2890 pinctrl. + * + * Based on: + * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) + * + * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MODULE_NAME "sf19a2890-pinctrl" + +struct sf_pinctrl { + struct device *dev; + void __iomem *base; + + struct pinctrl_dev *pctl_dev; + struct pinctrl_desc pctl_desc; + struct pinctrl_gpio_range gpio_range; +}; + +#define SF19A28_NUM_GPIOS 49 + +#define SF19A28_REG_PC(pin) ((pin) * 0x8) +#define PC_OEN BIT(7) +#define PC_ST BIT(6) +#define PC_IE BIT(5) +#define PC_PD BIT(4) +#define PC_PU BIT(3) +#define PC_DS GENMASK(2, 0) + +#define DRIVE_MIN 6 +#define DRIVE_STEP 3 +#define DRIVE_MAX (7 * DRIVE_STEP) + +#define SF19A28_REG_PMX(pin) ((pin) * 0x8 + 0x4) +/* + * FUNC_SW: + * 0: Override pad output enable with PC_OEN + * 1: take OEN from GPIO or alternative function + * FMUX_SEL: + * 0: Alternative function mode + * 1: GPIO mode + */ +#define PMX_FUNC_SW BIT(3) +#define PMX_FMUX_SEL BIT(2) +#define PMX_MODE GENMASK(1, 0) + +static struct pinctrl_pin_desc sf19a2890_gpio_pins[] = { + PINCTRL_PIN(0, "JTAG_TDO"), + PINCTRL_PIN(1, "JTAG_TDI"), + PINCTRL_PIN(2, "JTAG_TMS"), + PINCTRL_PIN(3, "JTAG_TCK"), + PINCTRL_PIN(4, "JTAG_RST"), + PINCTRL_PIN(5, "SPI_TXD"), + PINCTRL_PIN(6, "SPI_RXD"), + PINCTRL_PIN(7, "SPI_CLK"), + PINCTRL_PIN(8, "SPI_CSN"), + PINCTRL_PIN(9, "UART_TX"), + PINCTRL_PIN(10, "UART_RX"), + PINCTRL_PIN(11, "I2C_DAT"), + PINCTRL_PIN(12, "I2C_CLK"), + PINCTRL_PIN(13, "RGMII_GTX_CLK"), + PINCTRL_PIN(14, "RGMII_TXCLK"), + PINCTRL_PIN(15, "RGMII_TXD0"), + PINCTRL_PIN(16, "RGMII_TXD1"), + PINCTRL_PIN(17, "RGMII_TXD2"), + PINCTRL_PIN(18, "RGMII_TXD3"), + PINCTRL_PIN(19, "RGMII_TXCTL"), + PINCTRL_PIN(20, "RGMII_RXCLK"), + PINCTRL_PIN(21, "RGMII_RXD0"), + PINCTRL_PIN(22, "RGMII_RXD1"), + PINCTRL_PIN(23, "RGMII_RXD2"), + PINCTRL_PIN(24, "RGMII_RXD3"), + PINCTRL_PIN(25, "RGMII_RXCTL"), + PINCTRL_PIN(26, "RGMII_COL"), + PINCTRL_PIN(27, "RGMII_CRS"), + PINCTRL_PIN(28, "RGMII_MDC"), + PINCTRL_PIN(29, "RGMII_MDIO"), + PINCTRL_PIN(30, "HB0_PA_EN"), + PINCTRL_PIN(31, "HB0_LNA_EN"), + PINCTRL_PIN(32, "HB0_SW_CTRL0"), + PINCTRL_PIN(33, "HB0_SW_CTRL1"), + PINCTRL_PIN(34, "HB1_PA_EN"), + PINCTRL_PIN(35, "HB1_LNA_EN"), + PINCTRL_PIN(36, "HB1_SW_CTRL0"), + PINCTRL_PIN(37, "HB1_SW_CTRL1"), + PINCTRL_PIN(38, "LB0_PA_EN"), + PINCTRL_PIN(39, "LB0_LNA_EN"), + PINCTRL_PIN(40, "LB0_SW_CTRL0"), + PINCTRL_PIN(41, "LB0_SW_CTRL1"), + PINCTRL_PIN(42, "LB1_PA_EN"), + PINCTRL_PIN(43, "LB1_LNA_EN"), + PINCTRL_PIN(44, "LB1_SW_CTRL0"), + PINCTRL_PIN(45, "LB1_SW_CTRL1"), + PINCTRL_PIN(46, "CLK_OUT"), + PINCTRL_PIN(47, "EXT_CLK_IN"), + PINCTRL_PIN(48, "DRVVBUS0"), +}; + +static const char * const sf19a2890_gpio_groups[] = { + "JTAG_TDO", + "JTAG_TDI", + "JTAG_TMS", + "JTAG_TCK", + "JTAG_RST", + "SPI_TXD", + "SPI_RXD", + "SPI_CLK", + "SPI_CSN", + "UART_TX", + "UART_RX", + "I2C_DAT", + "I2C_CLK", + "RGMII_GTX_CLK", + "RGMII_TXCLK", + "RGMII_TXD0", + "RGMII_TXD1", + "RGMII_TXD2", + "RGMII_TXD3", + "RGMII_TXCTL", + "RGMII_RXCLK", + "RGMII_RXD0", + "RGMII_RXD1", + "RGMII_RXD2", + "RGMII_RXD3", + "RGMII_RXCTL", + "RGMII_COL", + "RGMII_CRS", + "RGMII_MDC", + "RGMII_MDIO", + "HB0_PA_EN", + "HB0_LNA_EN", + "HB0_SW_CTRL0", + "HB0_SW_CTRL1", + "HB1_PA_EN", + "HB1_LNA_EN", + "HB1_SW_CTRL0", + "HB1_SW_CTRL1", + "LB0_PA_EN", + "LB0_LNA_EN", + "LB0_SW_CTRL0", + "LB0_SW_CTRL1", + "LB1_PA_EN", + "LB1_LNA_EN", + "LB1_SW_CTRL0", + "LB1_SW_CTRL1", + "CLK_OUT", + "EXT_CLK_IN", + "DRVVBUS0", +}; + +#define SF19A28_FUNC0 0 +#define SF19A28_FUNC1 1 +#define SF19A28_FUNC2 2 +#define SF19A28_FUNC3 3 +#define SF19A28_NUM_FUNCS 4 + +static const char * const sf19a2890_functions[] = { + "func0", "func1", "func2", "func3" +}; + +static inline u32 sf_pinctrl_rd(struct sf_pinctrl *pc, ulong reg) +{ + return readl(pc->base + reg); +} + +static inline void sf_pinctrl_wr(struct sf_pinctrl *pc, ulong reg, u32 val) +{ + writel(val, pc->base + reg); +} + +static inline void sf_pinctrl_rmw(struct sf_pinctrl *pc, ulong reg, u32 clr, + u32 set) +{ + u32 val; + + val = sf_pinctrl_rd(pc, reg); + val &= ~clr; + val |= set; + sf_pinctrl_wr(pc, reg, val); +} + +static int sf19a2890_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return SF19A28_NUM_GPIOS; +} + +static const char *sf19a2890_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return sf19a2890_gpio_groups[selector]; +} + +static int sf19a2890_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + *pins = &sf19a2890_gpio_pins[selector].number; + *num_pins = 1; + + return 0; +} + +static void sf19a2890_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned offset) +{ + struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + u32 conf = sf_pinctrl_rd(pc, SF19A28_REG_PC(offset)); + u32 mux = sf_pinctrl_rd(pc, SF19A28_REG_PMX(offset)); + + if (!(mux & PMX_FUNC_SW)) + seq_puts(s, "Forced OE"); + else if (mux & PMX_FMUX_SEL) + seq_puts(s, "GPIO"); + else + seq_printf(s, "Func%lu", mux & PMX_MODE); + seq_puts(s, " |"); + + if (!(conf & PC_OEN) && !(mux & PMX_FUNC_SW)) + seq_puts(s, " Output"); + if ((conf & PC_ST)) + seq_puts(s, " Schmitt_Trigger"); + if ((conf & PC_IE)) + seq_puts(s, " Input"); + if ((conf & PC_PD)) + seq_puts(s, " Pull_Down"); + if ((conf & PC_PU)) + seq_puts(s, " Pull_Up"); + + seq_printf(s, " Drive: %lu mA", + DRIVE_MIN + (conf & PC_DS) * DRIVE_STEP); +} + +static const struct pinctrl_ops sf19a2890_pctl_ops = { + .get_groups_count = sf19a2890_pctl_get_groups_count, + .get_group_name = sf19a2890_pctl_get_group_name, + .get_group_pins = sf19a2890_pctl_get_group_pins, + .pin_dbg_show = sf19a2890_pctl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static int sf19a2890_pmx_free(struct pinctrl_dev *pctldev, unsigned offset) +{ + struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + sf_pinctrl_rmw(pc, SF19A28_REG_PC(offset), PC_IE, PC_OEN); + sf_pinctrl_rmw(pc, SF19A28_REG_PMX(offset), PMX_FUNC_SW, 0); + return 0; +} + +static int sf19a2890_pmx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return SF19A28_NUM_FUNCS; +} + +static const char *sf19a2890_pmx_get_function_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return sf19a2890_functions[selector]; +} + +static int sf19a2890_pmx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char *const **groups, + unsigned *const num_groups) +{ + /* every pin can do every function */ + *groups = sf19a2890_gpio_groups; + *num_groups = SF19A28_NUM_GPIOS; + + return 0; +} + +static int sf19a2890_pmx_set(struct pinctrl_dev *pctldev, + unsigned func_selector, unsigned group_selector) +{ + struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + unsigned pin = group_selector; + + sf_pinctrl_wr(pc, SF19A28_REG_PMX(pin), + PMX_FUNC_SW | FIELD_PREP(PMX_MODE, func_selector)); + return 0; +} + +static int sf19a2890_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + /* Set to GPIO mode & Let peripheral control OEN */ + sf_pinctrl_wr(pc, SF19A28_REG_PMX(offset), PMX_FUNC_SW | PMX_FMUX_SEL); + /* + * Set PC_IE regardless of whether GPIO is in input mode. + * Otherwise GPIO driver can't read back its status in output mode. + */ + sf_pinctrl_rmw(pc, SF19A28_REG_PC(offset), 0, PC_IE); + return 0; +} + +static void sf19a2890_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + sf19a2890_pmx_free(pctldev, offset); +} + +static const struct pinmux_ops sf19a2890_pmx_ops = { + .free = sf19a2890_pmx_free, + .get_functions_count = sf19a2890_pmx_get_functions_count, + .get_function_name = sf19a2890_pmx_get_function_name, + .get_function_groups = sf19a2890_pmx_get_function_groups, + .set_mux = sf19a2890_pmx_set, + .gpio_request_enable = sf19a2890_pmx_gpio_request_enable, + .gpio_disable_free = sf19a2890_pmx_gpio_disable_free, +}; + +static int sf19a2890_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 arg = 0; + u32 val = 0; + + if (pin >= SF19A28_NUM_GPIOS) + return -EINVAL; + + val = sf_pinctrl_rd(pc, SF19A28_REG_PC(pin)); + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT: + val &= PC_ST; + if (val) + arg = 1; + break; + + case PIN_CONFIG_INPUT_ENABLE: + val &= PC_IE; + if (val) + arg = 1; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + val &= PC_PD; + if (val) + arg = 1; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + val &= PC_PU; + if (val) + arg = 1; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + arg = DRIVE_MIN + (val & PC_DS) * DRIVE_STEP; + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int sf19a2890_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u32 arg, val; + int i; + + val = sf_pinctrl_rd(pc, SF19A28_REG_PC(pin)); + + if (pin >= SF19A28_NUM_GPIOS) + return -EINVAL; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg) + val |= PC_ST; + else + val &= ~PC_ST; + break; + + case PIN_CONFIG_INPUT_ENABLE: + if (arg) + val |= PC_IE; + else + val &= ~PC_IE; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg) { + val |= PC_PD; + val &= ~PC_PU; + } else { + val &= ~PC_PD; + } + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (arg) { + val |= PC_PU; + val &= ~PC_PD; + } else { + val &= ~PC_PU; + } + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + val &= ~PC_DS; + if (arg > DRIVE_MAX) + val |= PC_DS; + else if (arg > DRIVE_MIN) + val |= FIELD_PREP(PC_DS, (arg - DRIVE_MIN) / + DRIVE_STEP); + break; + default: + break; + } + sf_pinctrl_wr(pc, SF19A28_REG_PC(pin), val); + } + return 0; +} + +static const struct pinconf_ops sf19a2890_pinconf_ops = { + .is_generic = true, + .pin_config_get = sf19a2890_pinconf_get, + .pin_config_set = sf19a2890_pinconf_set, +}; + +static const struct pinctrl_desc sf19a2890_pinctrl_desc = { + .name = MODULE_NAME, + .pins = sf19a2890_gpio_pins, + .npins = SF19A28_NUM_GPIOS, + .pctlops = &sf19a2890_pctl_ops, + .pmxops = &sf19a2890_pmx_ops, + .confops = &sf19a2890_pinconf_ops, + .owner = THIS_MODULE, +}; + +static const struct pinctrl_gpio_range sf_pinctrl_gpio_range = { + .name = MODULE_NAME, + .npins = SF19A28_NUM_GPIOS, +}; + +static const struct of_device_id sf_pinctrl_match[] = { + { .compatible = "siflower,sf19a2890-pinctrl" }, + {} +}; + +static int sf_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sf_pinctrl *pc; + + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + platform_set_drvdata(pdev, pc); + pc->dev = dev; + + pc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pc->base)) + return PTR_ERR(pc->base); + + pc->pctl_desc = sf19a2890_pinctrl_desc; + pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); + if (IS_ERR(pc->pctl_dev)) + return PTR_ERR(pc->pctl_dev); + + return 0; +} + +static struct platform_driver sf_pinctrl_driver = { + .probe = sf_pinctrl_probe, + .driver = { + .name = MODULE_NAME, + .of_match_table = sf_pinctrl_match, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(sf_pinctrl_driver); + +MODULE_AUTHOR("Chuanhong Guo "); +MODULE_DESCRIPTION("Siflower SF19A2890 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/siflower/files-6.6/drivers/reset/reset-sf19a2890-periph.c b/target/linux/siflower/files-6.6/drivers/reset/reset-sf19a2890-periph.c new file mode 100644 index 00000000000000..21874da51716fc --- /dev/null +++ b/target/linux/siflower/files-6.6/drivers/reset/reset-sf19a2890-periph.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include +#include +#include + +struct reset_sf19a28_periph_data { + struct reset_controller_dev rcdev; + void __iomem *base; + spinlock_t lock; + u32 reset_masks[]; +}; + +static inline struct reset_sf19a28_periph_data * +to_reset_sf19a28_periph_data(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct reset_sf19a28_periph_data, rcdev); +} + +static int reset_sf19a28_periph_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct reset_sf19a28_periph_data *data = to_reset_sf19a28_periph_data(rcdev); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + reg = readl(data->base); + if (assert) + reg |= data->reset_masks[id]; + else + reg &= ~data->reset_masks[id]; + writel(reg, data->base); + spin_unlock_irqrestore(&data->lock, flags); + return 0; +} + +static int reset_sf19a28_periph_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return reset_sf19a28_periph_update(rcdev, id, true); +} + +static int reset_sf19a28_periph_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return reset_sf19a28_periph_update(rcdev, id, false); +} + +static int reset_sf19a28_periph_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct reset_sf19a28_periph_data *data = to_reset_sf19a28_periph_data(rcdev); + u32 reg; + + reg = readl(data->base); + return !!(reg & data->reset_masks[id]); +} + +const struct reset_control_ops reset_sf19a28_periph_ops = { + .assert = reset_sf19a28_periph_assert, + .deassert = reset_sf19a28_periph_deassert, + .status = reset_sf19a28_periph_status, +}; + +static const struct of_device_id reset_sf19a28_periph_dt_ids[] = { + { .compatible = "siflower,sf19a2890-periph-reset", }, + { /* sentinel */ }, +}; + +static int reset_sf19a28_periph_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct reset_sf19a28_periph_data *data; + void __iomem *base; + int nr_resets; + int ret, i; + u32 tmp; + + nr_resets = of_property_count_u32_elems(node, "siflower,reset-masks"); + + if (nr_resets < 1) { + ret = of_property_read_u32(node, "siflower,num-resets", &tmp); + if (ret < 0 || tmp < 1) + return -EINVAL; + nr_resets = tmp; + } + + if (nr_resets >= 32) { + dev_err(dev, "too many resets."); + return -EINVAL; + } + + data = devm_kzalloc(dev, struct_size(data, reset_masks, nr_resets), GFP_KERNEL); + if (!data) + return -ENOMEM; + + ret = of_property_read_u32_array(node, "siflower,reset-masks", + data->reset_masks, nr_resets); + if (ret) + for (i = 0; i < nr_resets; i++) + data->reset_masks[i] = BIT(i); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + spin_lock_init(&data->lock); + data->base = base; + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = nr_resets; + data->rcdev.ops = &reset_sf19a28_periph_ops; + data->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static struct platform_driver reset_sf19a28_periph_driver = { + .probe = reset_sf19a28_periph_probe, + .driver = { + .name = "reset-sf19a2890-periph", + .of_match_table = reset_sf19a28_periph_dt_ids, + }, +}; +builtin_platform_driver(reset_sf19a28_periph_driver); diff --git a/target/linux/siflower/files-6.6/include/dt-bindings/clock/siflower,sf19a2890-clk.h b/target/linux/siflower/files-6.6/include/dt-bindings/clock/siflower,sf19a2890-clk.h new file mode 100644 index 00000000000000..06bf0b007e1e0f --- /dev/null +++ b/target/linux/siflower/files-6.6/include/dt-bindings/clock/siflower,sf19a2890-clk.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +#ifndef __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_CLK_H +#define __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_CLK_H +#define CLK_PLL_CPU 0 +#define CLK_PLL_DDR 1 +#define CLK_PLL_CMN 2 +#define CLK_MUXDIV_BUS1 3 +#define CLK_MUXDIV_BUS2 4 +#define CLK_MUXDIV_BUS3 5 +#define CLK_MUXDIV_CPU 6 +#define CLK_MUXDIV_PBUS 7 +#define CLK_MUXDIV_MEM_PHY 8 +#define CLK_MUXDIV_UART 9 +#define CLK_MUXDIV_ETH_REF 10 +#define CLK_MUXDIV_ETH_BYP_REF 11 +#define CLK_MUXDIV_ETH_TSU 12 +#define CLK_MUXDIV_GMAC_BYP_REF 13 +#define CLK_MUXDIV_M6250_0 14 +#define CLK_MUXDIV_M6250_1 15 +#define CLK_MUXDIV_WLAN24_PLF 16 +#define CLK_MUXDIV_WLAN5_PLF 17 +#define CLK_MUXDIV_USBPHY_REF 18 +#define CLK_MUXDIV_TCLK 19 +#define CLK_MUXDIV_NPU_PE_CLK 20 + +#define CLK_SF19A2890_MAX 21 +#endif /* __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_CLK_H */ diff --git a/target/linux/siflower/image/Makefile b/target/linux/siflower/image/Makefile new file mode 100644 index 00000000000000..e86927dd78fd44 --- /dev/null +++ b/target/linux/siflower/image/Makefile @@ -0,0 +1,28 @@ + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +KERNEL_LOADADDR := 0x80100000 + +define Device/Default + PROFILES := Default + BLOCKSIZE := 64k + FILESYSTEMS := squashfs + DEVICE_DTS_DIR := ../dts + KERNEL := kernel-bin | append-dtb | lzma | uImage lzma + KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin = append-kernel | pad-to $$$$(BLOCKSIZE) | \ + append-rootfs | pad-rootfs | append-metadata +endef + +define Device/siflower_sf19a2890-evb + DEVICE_VENDOR := Siflower + DEVICE_MODEL := SF19A2890 EVB + BOARD_NAME := siflower,sf19a2890-evb + DEVICE_DTS := sf19a2890_evb + DEVICE_PACKAGES := kmod-switch-rtl8367b swconfig +endef +TARGET_DEVICES += siflower_sf19a2890-evb + +$(eval $(call BuildImage)) diff --git a/target/linux/siflower/modules.mk b/target/linux/siflower/modules.mk new file mode 100644 index 00000000000000..e8aaf768e4325c --- /dev/null +++ b/target/linux/siflower/modules.mk @@ -0,0 +1,15 @@ +define KernelPackage/phy-sf19a2890-usb + TITLE:=Siflower SF19A2890 USB 2.0 PHY Driver + KCONFIG:=CONFIG_PHY_SF19A2890_USB + DEPENDS:=@TARGET_siflower_sf19a2890 + SUBMENU:=$(USB_MENU) + FILES:=$(LINUX_DIR)/drivers/phy/siflower/phy-sf19a2890-usb.ko + AUTOLOAD:=$(call AutoLoad,45,phy-sf19a2890-usb,1) +endef + +define KernelPackage/phy-sf19a2890-usb/description + Support for Siflower SF19A2890 USB 2.0 PHY connected to the USB + controller. +endef + +$(eval $(call KernelPackage,phy-sf19a2890-usb)) diff --git a/target/linux/siflower/patches-6.6/001-mips-add-support-for-Siflower-SF19A2890.patch b/target/linux/siflower/patches-6.6/001-mips-add-support-for-Siflower-SF19A2890.patch new file mode 100644 index 00000000000000..69bd0b83d73f02 --- /dev/null +++ b/target/linux/siflower/patches-6.6/001-mips-add-support-for-Siflower-SF19A2890.patch @@ -0,0 +1,59 @@ +From c2ec4604afb39904c01dfe38ca8289c446b898bb Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 20 Aug 2024 08:32:17 +0800 +Subject: [PATCH 1/9] mips: add support for Siflower SF19A2890 + +Signed-off-by: Chuanhong Guo +--- + arch/mips/Kconfig | 29 +++++++++++++++++++++++++++++ + arch/mips/generic/Platform | 1 + + 2 files changed, 30 insertions(+) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -861,6 +861,35 @@ config SIBYTE_BIGSUR + select ZONE_DMA32 if 64BIT + select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI + ++config MACH_SIFLOWER_MIPS ++ bool "Siflower MIPS SoCs" ++ select MIPS_GENERIC ++ select ARM_AMBA ++ select BOOT_RAW ++ select CEVT_R4K ++ select CLKSRC_MIPS_GIC ++ select COMMON_CLK ++ select CPU_MIPSR2_IRQ_EI ++ select CPU_MIPSR2_IRQ_VI ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select IRQ_MIPS_CPU ++ select MIPS_CPU_SCACHE ++ select MIPS_GIC ++ select MIPS_L1_CACHE_SHIFT_5 ++ select NO_EXCEPT_FILL ++ select SMP_UP if SMP ++ select SYS_HAS_CPU_MIPS32_R2 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ select SYS_SUPPORTS_MIPS16 ++ select SYS_SUPPORTS_MIPS_CPS ++ select SYS_SUPPORTS_MULTITHREADING ++ select USE_OF ++ help ++ Select this to build a kernel which supports SoCs from Siflower ++ with MIPS InterAptiv cores, like Siflower SF19A2890. ++ + config SNI_RM + bool "SNI RM200/300/400" + select ARC_MEMORY +--- a/arch/mips/generic/Platform ++++ b/arch/mips/generic/Platform +@@ -10,6 +10,7 @@ + + # Note: order matters, keep the asm/mach-generic include last. + cflags-$(CONFIG_MACH_INGENIC_SOC) += -I$(srctree)/arch/mips/include/asm/mach-ingenic ++cflags-$(CONFIG_MACH_SIFLOWER_MIPS) += -I$(srctree)/arch/mips/include/asm/mach-siflower + cflags-$(CONFIG_MIPS_GENERIC) += -I$(srctree)/arch/mips/include/asm/mach-generic + + load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000 diff --git a/target/linux/siflower/patches-6.6/002-clk-add-drivers-for-sf19a2890.patch b/target/linux/siflower/patches-6.6/002-clk-add-drivers-for-sf19a2890.patch new file mode 100644 index 00000000000000..620e432a4979b0 --- /dev/null +++ b/target/linux/siflower/patches-6.6/002-clk-add-drivers-for-sf19a2890.patch @@ -0,0 +1,31 @@ +From fcb96cb774abf14375326c41cedd237d6c8f6e94 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 20 Aug 2024 08:33:01 +0800 +Subject: [PATCH 2/9] clk: add drivers for sf19a2890 + +Signed-off-by: Chuanhong Guo +--- + drivers/clk/Kconfig | 1 + + drivers/clk/Makefile | 1 + + 2 files changed, 2 insertions(+) + +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -489,6 +489,7 @@ source "drivers/clk/renesas/Kconfig" + source "drivers/clk/rockchip/Kconfig" + source "drivers/clk/samsung/Kconfig" + source "drivers/clk/sifive/Kconfig" ++source "drivers/clk/siflower/Kconfig" + source "drivers/clk/socfpga/Kconfig" + source "drivers/clk/sprd/Kconfig" + source "drivers/clk/starfive/Kconfig" +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -116,6 +116,7 @@ obj-y += renesas/ + obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ + obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ + obj-$(CONFIG_CLK_SIFIVE) += sifive/ ++obj-$(CONFIG_CLK_SIFLOWER) += siflower/ + obj-y += socfpga/ + obj-$(CONFIG_PLAT_SPEAR) += spear/ + obj-y += sprd/ diff --git a/target/linux/siflower/patches-6.6/003-reset-add-support-for-sf19a2890.patch b/target/linux/siflower/patches-6.6/003-reset-add-support-for-sf19a2890.patch new file mode 100644 index 00000000000000..52992ac5dda489 --- /dev/null +++ b/target/linux/siflower/patches-6.6/003-reset-add-support-for-sf19a2890.patch @@ -0,0 +1,38 @@ +From 819d2a48d45f3734c876186e651917bae69be9ba Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 20 Aug 2024 08:33:43 +0800 +Subject: [PATCH 3/9] reset: add support for sf19a2890 + +Signed-off-by: Chuanhong Guo +--- + drivers/reset/Kconfig | 8 ++++++++ + drivers/reset/Makefile | 1 + + 2 files changed, 9 insertions(+) + +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -211,6 +211,14 @@ config RESET_SCMI + This driver uses SCMI Message Protocol to interact with the + firmware controlling all the reset signals. + ++config RESET_SF19A2890_PERIPH ++ bool "Siflower SF19A2890 Peripheral Reset Controller Driver" ++ default MACH_SIFLOWER_MIPS ++ depends on HAS_IOMEM ++ help ++ This enables reset controller driver for peripheral reset blocks ++ found on Siflower SF19A2890 SoC. ++ + config RESET_SIMPLE + bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT + default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_QCOM_PDC) += reset-qc + obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o + obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o + obj-$(CONFIG_RESET_SCMI) += reset-scmi.o ++obj-$(CONFIG_RESET_SF19A2890_PERIPH) += reset-sf19a2890-periph.o + obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o + obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o + obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o diff --git a/target/linux/siflower/patches-6.6/004-gpio-add-support-for-siflower-socs.patch b/target/linux/siflower/patches-6.6/004-gpio-add-support-for-siflower-socs.patch new file mode 100644 index 00000000000000..c381b86e14734e --- /dev/null +++ b/target/linux/siflower/patches-6.6/004-gpio-add-support-for-siflower-socs.patch @@ -0,0 +1,37 @@ +From 1d37455eacb1d0c262ae6aaecadf27964cbf97d8 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 20 Aug 2024 08:33:57 +0800 +Subject: [PATCH 4/9] gpio: add support for siflower socs + +--- + drivers/gpio/Kconfig | 8 ++++++++ + drivers/gpio/Makefile | 1 + + 2 files changed, 9 insertions(+) + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -576,6 +576,14 @@ config GPIO_SIFIVE + help + Say yes here to support the GPIO device on SiFive SoCs. + ++config GPIO_SIFLOWER ++ tristate "SiFlower GPIO support" ++ depends on OF_GPIO ++ depends on MACH_SIFLOWER_MIPS || COMPILE_TEST ++ select GPIOLIB_IRQCHIP ++ help ++ GPIO controller driver for SiFlower SoCs. ++ + config GPIO_SIOX + tristate "SIOX GPIO support" + depends on SIOX +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -143,6 +143,7 @@ obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio + obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o + obj-$(CONFIG_GPIO_SCH) += gpio-sch.o + obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o ++obj-$(CONFIG_GPIO_SIFLOWER) += gpio-siflower.o + obj-$(CONFIG_GPIO_SIM) += gpio-sim.o + obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o + obj-$(CONFIG_GPIO_SL28CPLD) += gpio-sl28cpld.o diff --git a/target/linux/siflower/patches-6.6/005-pinctrl-add-driver-for-siflower-sf19a2890.patch b/target/linux/siflower/patches-6.6/005-pinctrl-add-driver-for-siflower-sf19a2890.patch new file mode 100644 index 00000000000000..e9026476d3669c --- /dev/null +++ b/target/linux/siflower/patches-6.6/005-pinctrl-add-driver-for-siflower-sf19a2890.patch @@ -0,0 +1,39 @@ +From 59c6a4972b584d986f72fe8d7c55930fdf799bc8 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 20 Aug 2024 08:34:20 +0800 +Subject: [PATCH 5/9] pinctrl: add driver for siflower sf19a2890 + +--- + drivers/pinctrl/Kconfig | 10 ++++++++++ + drivers/pinctrl/Makefile | 1 + + 2 files changed, 11 insertions(+) + +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -417,6 +417,16 @@ config PINCTRL_ROCKCHIP + help + This support pinctrl and GPIO driver for Rockchip SoCs. + ++config PINCTRL_SF19A2890 ++ tristate "Siflower SF19A2890 pinctrl driver" ++ depends on OF && (MACH_SIFLOWER_MIPS || COMPILE_TEST) ++ select PINMUX ++ select PINCONF ++ select GENERIC_PINCONF ++ default MACH_SIFLOWER_MIPS ++ help ++ Say Y here to enable the Siflower SF19A2890 pinctrl driver. ++ + config PINCTRL_SINGLE + tristate "One-register-per-pin type device tree based pinctrl driver" + depends on OF +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-p + obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o + obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o + obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o ++obj-$(CONFIG_PINCTRL_SF19A2890) += pinctrl-sf19a2890.o + obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o + obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o + obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o diff --git a/target/linux/siflower/patches-6.6/006-stmmac-add-support-for-sf19a2890.patch b/target/linux/siflower/patches-6.6/006-stmmac-add-support-for-sf19a2890.patch new file mode 100644 index 00000000000000..b65cd3ed0488ab --- /dev/null +++ b/target/linux/siflower/patches-6.6/006-stmmac-add-support-for-sf19a2890.patch @@ -0,0 +1,38 @@ +From baa6c00f7a88b28f6838a9743f66c9f7f4716e25 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 20 Aug 2024 08:34:42 +0800 +Subject: [PATCH 6/9] stmmac: add support for sf19a2890 + +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 9 +++++++++ + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + + 2 files changed, 10 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -142,6 +142,15 @@ config DWMAC_ROCKCHIP + This selects the Rockchip RK3288 SoC glue layer support for + the stmmac device driver. + ++config DWMAC_SF19A2890 ++ tristate "Siflower SF19A2890 GMAC support" ++ default MACH_SIFLOWER_MIPS ++ help ++ Support for GMAC on Siflower SF19A2890 SoC. ++ ++ This selects the Siflower SF19A2890 SoC glue layer support for ++ the stmmac device driver. ++ + config DWMAC_SOCFPGA + tristate "SOCFPGA dwmac support" + default ARCH_INTEL_SOCFPGA +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -21,6 +21,7 @@ obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-me + obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o + obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o + obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o ++obj-$(CONFIG_DWMAC_SF19A2890) += dwmac-sf19a2890.o + obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o + obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o + obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o diff --git a/target/linux/siflower/patches-6.6/007-phy-add-support-for-SF19A2890-USB-PHY.patch b/target/linux/siflower/patches-6.6/007-phy-add-support-for-SF19A2890-USB-PHY.patch new file mode 100644 index 00000000000000..97b7126e02de32 --- /dev/null +++ b/target/linux/siflower/patches-6.6/007-phy-add-support-for-SF19A2890-USB-PHY.patch @@ -0,0 +1,31 @@ +From 68817a14ae9dff587cee8515e68c67cba89b39ab Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Mon, 9 Sep 2024 10:18:33 +0800 +Subject: [PATCH 7/9] phy: add support for SF19A2890 USB PHY + +Signed-off-by: Chuanhong Guo +--- + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + 2 files changed, 2 insertions(+) + +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -90,6 +90,7 @@ source "drivers/phy/ralink/Kconfig" + source "drivers/phy/renesas/Kconfig" + source "drivers/phy/rockchip/Kconfig" + source "drivers/phy/samsung/Kconfig" ++source "drivers/phy/siflower/Kconfig" + source "drivers/phy/socionext/Kconfig" + source "drivers/phy/st/Kconfig" + source "drivers/phy/starfive/Kconfig" +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -29,6 +29,7 @@ obj-y += allwinner/ \ + renesas/ \ + rockchip/ \ + samsung/ \ ++ siflower/ \ + socionext/ \ + st/ \ + starfive/ \ diff --git a/target/linux/siflower/patches-6.6/008-usb-dwc2-add-support-for-Siflower-SF19A2890.patch b/target/linux/siflower/patches-6.6/008-usb-dwc2-add-support-for-Siflower-SF19A2890.patch new file mode 100644 index 00000000000000..b551e4f2cae27f --- /dev/null +++ b/target/linux/siflower/patches-6.6/008-usb-dwc2-add-support-for-Siflower-SF19A2890.patch @@ -0,0 +1,36 @@ +From 29282086f215ae723e6d2c139d23094e699ba5bb Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Mon, 9 Sep 2024 16:46:53 +0800 +Subject: [PATCH 8/9] usb: dwc2: add support for Siflower SF19A2890 + +Signed-off-by: Chuanhong Guo +--- + drivers/usb/dwc2/params.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -200,6 +200,14 @@ static void dwc2_set_amcc_params(struct + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; + } + ++static void dwc2_set_sf19a2890_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->max_transfer_size = 65535; ++ p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; ++} ++ + static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; +@@ -294,6 +302,8 @@ const struct of_device_id dwc2_of_match_ + .data = dwc2_set_amlogic_a1_params }, + { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, + { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, ++ { .compatible = "siflower,sf19a2890-usb", ++ .data = dwc2_set_sf19a2890_params }, + { .compatible = "st,stm32f4x9-fsotg", + .data = dwc2_set_stm32f4x9_fsotg_params }, + { .compatible = "st,stm32f4x9-hsotg" }, diff --git a/target/linux/siflower/patches-6.6/009-usb-dwc2-handle-OTG-interrupt-regardless-of-GINTSTS.patch b/target/linux/siflower/patches-6.6/009-usb-dwc2-handle-OTG-interrupt-regardless-of-GINTSTS.patch new file mode 100644 index 00000000000000..03fb16879cdf83 --- /dev/null +++ b/target/linux/siflower/patches-6.6/009-usb-dwc2-handle-OTG-interrupt-regardless-of-GINTSTS.patch @@ -0,0 +1,67 @@ +From 0b04c37a1aae523025195c29a6477cf26234d26c Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 10 Sep 2024 09:10:27 +0800 +Subject: [PATCH 9/9] usb: dwc2: handle OTG interrupt regardless of GINTSTS + +The DWC OTG 3.30a found on Siflower SF19A2890 has battery charger +support enabled. It triggers MultVallpChng interrupt (bit 20 of +GOTGINT) but doesn't set OTGInt in GINTSTS. As a result, this +interrupt is never handled, and linux disables USB interrupt +because "nobody cares". + +Handle OTG interrupt in IRQ handler regardless of whether the +OTGInt bit in GINTSTS is set or not. + +Signed-off-by: Chuanhong Guo +--- + drivers/usb/dwc2/core_intr.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +--- a/drivers/usb/dwc2/core_intr.c ++++ b/drivers/usb/dwc2/core_intr.c +@@ -79,7 +79,7 @@ static void dwc2_handle_mode_mismatch_in + * + * @hsotg: Programming view of DWC_otg controller + */ +-static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ++static irqreturn_t dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) + { + u32 gotgint; + u32 gotgctl; +@@ -87,6 +87,10 @@ static void dwc2_handle_otg_intr(struct + + gotgint = dwc2_readl(hsotg, GOTGINT); + gotgctl = dwc2_readl(hsotg, GOTGCTL); ++ ++ if (!gotgint) ++ return IRQ_NONE; ++ + dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, + dwc2_op_state_str(hsotg)); + +@@ -229,6 +233,7 @@ static void dwc2_handle_otg_intr(struct + + /* Clear GOTGINT */ + dwc2_writel(hsotg, gotgint, GOTGINT); ++ return IRQ_HANDLED; + } + + /** +@@ -842,6 +847,8 @@ irqreturn_t dwc2_handle_common_intr(int + hsotg->frame_number = (dwc2_readl(hsotg, HFNUM) + & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; + ++ retval = dwc2_handle_otg_intr(hsotg); ++ + gintsts = dwc2_read_common_intr(hsotg); + if (gintsts & ~GINTSTS_PRTINT) + retval = IRQ_HANDLED; +@@ -855,8 +862,6 @@ irqreturn_t dwc2_handle_common_intr(int + + if (gintsts & GINTSTS_MODEMIS) + dwc2_handle_mode_mismatch_intr(hsotg); +- if (gintsts & GINTSTS_OTGINT) +- dwc2_handle_otg_intr(hsotg); + if (gintsts & GINTSTS_CONIDSTSCHNG) + dwc2_handle_conn_id_status_change_intr(hsotg); + if (gintsts & GINTSTS_DISCONNINT) diff --git a/target/linux/siflower/sf19a2890/base-files/etc/board.d/02_network b/target/linux/siflower/sf19a2890/base-files/etc/board.d/02_network new file mode 100644 index 00000000000000..f3da21444bb276 --- /dev/null +++ b/target/linux/siflower/sf19a2890/base-files/etc/board.d/02_network @@ -0,0 +1,42 @@ + +. /lib/functions.sh +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh + +siflower_setup_interfaces() +{ + local board="$1" + + case $board in + siflower,sf19a2890-evb) + ucidef_add_switch "switch0" \ + "0:wan" "1:lan" "2:lan" "3:lan" "4:lan" "6@eth0" + ;; + esac +} + +siflower_setup_macs() +{ + local board="$1" + local lan_mac="" + local wan_mac="" + local label_mac="" + + case $board in + siflower,sf19a2890-evb) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary factory 0x0)" 1) + ;; + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac + [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac +} + +board_config_update +board=$(board_name) +siflower_setup_interfaces $board +siflower_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/siflower/sf19a2890/base-files/lib/upgrade/platform.sh b/target/linux/siflower/sf19a2890/base-files/lib/upgrade/platform.sh new file mode 100644 index 00000000000000..80cf1cdcf09027 --- /dev/null +++ b/target/linux/siflower/sf19a2890/base-files/lib/upgrade/platform.sh @@ -0,0 +1,22 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +platform_check_image() { + local board=$(board_name) + + case "$board" in + *) + return 0 + ;; + esac +} + +platform_do_upgrade() { + local board=$(board_name) + + case "$board" in + *) + default_do_upgrade "$1" + ;; + esac +} diff --git a/target/linux/siflower/sf19a2890/config-6.6 b/target/linux/siflower/sf19a2890/config-6.6 new file mode 100644 index 00000000000000..bec75436e00458 --- /dev/null +++ b/target/linux/siflower/sf19a2890/config-6.6 @@ -0,0 +1,266 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_AMBA=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BOARD_SCACHE=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CEVT_R4K=y +CONFIG_CLKSRC_MIPS_GIC=y +CONFIG_CLK_SF19A2890=y +CONFIG_CLK_SF19A2890_PERIPH=y +CONFIG_CLK_SIFLOWER=y +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_COREDUMP=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRC16=y +CONFIG_CRC_CCITT=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CSRC_R4K=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +# CONFIG_DWMAC_GENERIC is not set +CONFIG_DWMAC_SF19A2890=y +CONFIG_DW_WATCHDOG=y +CONFIG_ELF_CORE=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FANOTIFY=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_SIFLOWER=y +CONFIG_GRO_CELLS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MACH_SIFLOWER_MIPS=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CLOCK_VSYSCALL=y +CONFIG_MIPS_CM=y +CONFIG_MIPS_CMDLINE_DTB_EXTEND=y +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CPC=y +CONFIG_MIPS_CPS=y +# CONFIG_MIPS_CPS_NS16550_BOOL is not set +CONFIG_MIPS_CPS_PM=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_FP_SUPPORT=y +CONFIG_MIPS_GENERIC=y +CONFIG_MIPS_GIC=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_L1_CACHE_SHIFT_5=y +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_NR_CPU_NR_MAP=4 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_TAG_NONE=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCS_XPCS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +# CONFIG_PHY_SF19A2890_USB is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SF19A2890=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_EVENTS=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SF19A2890_PERIPH=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_INFO=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_PL022=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SRAM=y +CONFIG_STACKPROTECTOR=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_SWPHY=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WEAK_ORDERING=y +CONFIG_WERROR=y +CONFIG_XPS=y diff --git a/target/linux/siflower/sf19a2890/target.mk b/target/linux/siflower/sf19a2890/target.mk new file mode 100644 index 00000000000000..6c477098955e24 --- /dev/null +++ b/target/linux/siflower/sf19a2890/target.mk @@ -0,0 +1,12 @@ +ARCH:=mipsel +SUBTARGET:=sf19a2890 +BOARDNAME:=Siflower SF19A2890 based boards +FEATURES+=fpu +CPU_TYPE:=24kc +CPU_SUBTYPE:=24kf + +KERNELNAME:=vmlinux + +define Target/Description + Build firmware images for Siflower SF19A2890 based boards. +endef