From d6c6378869d13b5a6a9bb2a2f1319daf1332da6e Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Sat, 14 Dec 2024 23:15:16 +0800 Subject: [PATCH 1/2] rockchip: add 6.12 testing kernel support --- target/linux/rockchip/Makefile | 2 +- target/linux/rockchip/armv8/config-6.12 | 778 ++++++++++++++++++ .../files/drivers/devfreq/rk3328_dmc.c | 10 + .../pci/controller/dwc/pcie-dw-rkvendor.c | 1 + ...-rockchip-use-system-LED-for-OpenWrt.patch | 77 ++ ...-r8169-add-LED-configuration-from-OF.patch | 58 ++ ...TL8211-add-LED-configuration-from-OF.patch | 44 + ...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 24 + .../105-nanopi-r4s-sd-signalling.patch | 36 + .../patches-6.12/106-r4s-openwrt-leds.patch | 16 + ...-initial-signal-voltage-on-power-off.patch | 35 + ...568-update-gicv3-its-and-pci-msi-map.patch | 77 ++ ...gic-v3-add-hackaround-for-rk3568-its.patch | 161 ++++ ...dts-rockchip-rk3568-Add-xpcs-support.patch | 33 + ...icro-stmmac-Add-SGMII-QSGMII-support.patch | 320 +++++++ ...chip-naneng-combo-add-rk3576-support.patch | 375 +++++++++ ...8-add-i2c0-controller-for-nanopi-r2s.patch | 22 + ...-support-for-FriendlyARM-NanoPi-Neo3.patch | 442 ++++++++++ ...chip-rk3399-add-support-more-devices.patch | 11 + ...ockchip-naneng-combphy-fix-phy-reset.patch | 39 + ...-pinctrl-rockchip-add-rk3528-support.patch | 269 ++++++ ...rmal-rockchip-add-support-for-rk3528.patch | 191 +++++ ...-rockchip-power-domain-Add-always-on.patch | 61 ++ ...chip-power-domain-add-rk3528-support.patch | 103 +++ ...-add-clock-controller-for-the-RK3528.patch | 179 ++++ ...stmmac-dwmac-rk3528-add-GMAC-support.patch | 227 +++++ ...inno-usb2-add-phy-support-for-rk3528.patch | 67 ++ ...ip-naneng-combphy-add-support-rk3528.patch | 170 ++++ ...i-of-dwcmshc-pcie-support-for-rk3528.patch | 103 +++ ...w_mmc-rockchip-add-v2-tuning-support.patch | 118 +++ ...-for-rockchip-hardware-random-number.patch | 45 + ...ip-add-hardware-random-number-genera.patch | 26 + ...ip-add-devfreq-driver-for-rk3328-dmc.patch | 44 + ...setting-ddr-clock-via-SIP-Version-2-.patch | 210 +++++ ...eq-rockchip-dfi-add-more-soc-support.patch | 53 ++ ...m64-dts-rockchip-rk3328-add-dfi-node.patch | 25 + ...-dts-rockchip-rk3328-devices-add-dmc.patch | 58 ++ ...ip-add-more-cpu-operating-points-for.patch | 44 + 38 files changed, 4553 insertions(+), 1 deletion(-) create mode 100644 target/linux/rockchip/armv8/config-6.12 create mode 100644 target/linux/rockchip/patches-6.12/100-rockchip-use-system-LED-for-OpenWrt.patch create mode 100644 target/linux/rockchip/patches-6.12/101-net-realtek-r8169-add-LED-configuration-from-OF.patch create mode 100644 target/linux/rockchip/patches-6.12/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch create mode 100644 target/linux/rockchip/patches-6.12/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch create mode 100644 target/linux/rockchip/patches-6.12/105-nanopi-r4s-sd-signalling.patch create mode 100644 target/linux/rockchip/patches-6.12/106-r4s-openwrt-leds.patch create mode 100644 target/linux/rockchip/patches-6.12/107-mmc-core-set-initial-signal-voltage-on-power-off.patch create mode 100644 target/linux/rockchip/patches-6.12/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch create mode 100644 target/linux/rockchip/patches-6.12/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch create mode 100644 target/linux/rockchip/patches-6.12/112-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch create mode 100644 target/linux/rockchip/patches-6.12/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch create mode 100644 target/linux/rockchip/patches-6.12/120-phy-rockchip-naneng-combo-add-rk3576-support.patch create mode 100644 target/linux/rockchip/patches-6.12/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch create mode 100644 target/linux/rockchip/patches-6.12/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch create mode 100644 target/linux/rockchip/patches-6.12/210-rockchip-rk3399-add-support-more-devices.patch create mode 100644 target/linux/rockchip/patches-6.12/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch create mode 100644 target/linux/rockchip/patches-6.12/301-pinctrl-rockchip-add-rk3528-support.patch create mode 100644 target/linux/rockchip/patches-6.12/302-thermal-rockchip-add-support-for-rk3528.patch create mode 100644 target/linux/rockchip/patches-6.12/303-soc-rockchip-power-domain-Add-always-on.patch create mode 100644 target/linux/rockchip/patches-6.12/304-soc-rockchip-power-domain-add-rk3528-support.patch create mode 100644 target/linux/rockchip/patches-6.12/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch create mode 100644 target/linux/rockchip/patches-6.12/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch create mode 100644 target/linux/rockchip/patches-6.12/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch create mode 100644 target/linux/rockchip/patches-6.12/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch create mode 100644 target/linux/rockchip/patches-6.12/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch create mode 100644 target/linux/rockchip/patches-6.12/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch create mode 100644 target/linux/rockchip/patches-6.12/801-char-add-support-for-rockchip-hardware-random-number.patch create mode 100644 target/linux/rockchip/patches-6.12/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch create mode 100644 target/linux/rockchip/patches-6.12/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch create mode 100644 target/linux/rockchip/patches-6.12/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch create mode 100644 target/linux/rockchip/patches-6.12/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch create mode 100644 target/linux/rockchip/patches-6.12/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch create mode 100644 target/linux/rockchip/patches-6.12/807-arm64-dts-rockchip-rk3328-devices-add-dmc.patch create mode 100644 target/linux/rockchip/patches-6.12/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index c3d46c278e2845..a2b3f947f3b155 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -8,7 +8,7 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa SUBTARGETS:=armv8 KERNEL_PATCHVER:=6.6 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=6.12 define Target/Description Build firmware image for Rockchip SoC devices. diff --git a/target/linux/rockchip/armv8/config-6.12 b/target/linux/rockchip/armv8/config-6.12 new file mode 100644 index 00000000000000..ff4d654ac3d771 --- /dev/null +++ b/target/linux/rockchip/armv8/config-6.12 @@ -0,0 +1,778 @@ +CONFIG_64BIT=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=33 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PKEY_BITS=3 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_EXECMEM_LATE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARC_EMAC_CORE=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_ERRATUM_1742098=y +CONFIG_ARM64_ERRATUM_2051678=y +CONFIG_ARM64_ERRATUM_2054223=y +CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2077057=y +CONFIG_ARM64_ERRATUM_2441007=y +CONFIG_ARM64_ERRATUM_2441009=y +CONFIG_ARM64_ERRATUM_2658417=y +CONFIG_ARM64_ERRATUM_3117295=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_ERRATUM_858921=y +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_PTR_AUTH_KERNEL=y +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_SVE=y +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=48 +# CONFIG_ARM64_VA_BITS_39 is not set +CONFIG_ARM64_VA_BITS_48=y +# CONFIG_ARM64_VA_BITS_52 is not set +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y +CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y +# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_MHU=y +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_MHU_V3 is not set +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_RK3328_DMC_DEVFREQ=y +# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +# CONFIG_ARM_SCMI_CPUFREQ is not set +# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set +CONFIG_ARM_SCMI_HAVE_SHMEM=y +CONFIG_ARM_SCMI_HAVE_TRANSPORT=y +# CONFIG_ARM_SCMI_PERF_DOMAIN is not set +CONFIG_ARM_SCMI_POWER_CONTROL=y +CONFIG_ARM_SCMI_POWER_DOMAIN=y +CONFIG_ARM_SCMI_PROTOCOL=y +# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set +CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y +CONFIG_ARM_SCMI_TRANSPORT_SMC=y +# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +CONFIG_ARM_SMMU_V3=y +# CONFIG_ARM_SMMU_V3_SVA is not set +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CHARGER_GPIO=y +# CONFIG_CHARGER_RK817 is not set +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_PX30=y +CONFIG_CLK_RK3308=y +CONFIG_CLK_RK3328=y +CONFIG_CLK_RK3368=y +CONFIG_CLK_RK3399=y +CONFIG_CLK_RK3528=y +CONFIG_CLK_RK3568=y +CONFIG_CLK_RK3576=y +CONFIG_CLK_RK3588=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=64 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_ROCKCHIP=y +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT=y +CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_CPUSETS_V1 is not set +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_RESERVE=y +CONFIG_CRC16=y +CONFIG_CRC64=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC_T10DIF=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SIG2=y +CONFIG_CRYPTO_SM4=y +CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y +CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y +CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVMEM=y +# CONFIG_DEVPORT is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DIMLIB=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_CMA=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS_HELPERS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DT_IDLE_GENPD=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_ROCKCHIP=y +CONFIG_DW_WATCHDOG=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_EMAC_ROCKCHIP=y +CONFIG_ENERGY_MODEL=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXECMEM=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_FANOTIFY=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FS_STACK=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_ROCKCHIP=y +# CONFIG_GPIO_VIRTUSER is not set +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HID=y +CONFIG_HID_SUPPORT=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_PCIE is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y +CONFIG_HWMON=y +CONFIG_HWSPINLOCK=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_RK3X=y +# CONFIG_IDPF is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INDIRECT_PIO=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_MATRIXKMAP=y +# CONFIG_INPUT_MISC is not set +# CONFIG_IOMMUFD is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_IO_PGTABLE=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_DART is not set +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IO_STRICT_DEVMEM is not set +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_FILE=y +CONFIG_KSM=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_LIBCRC32C=y +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_BUS_MUX_GPIO=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MEMCG_V1 is not set +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_KHADAS_MCU is not set +CONFIG_MFD_RK8XX=y +CONFIG_MFD_RK8XX_I2C=y +CONFIG_MFD_RK8XX_SPI=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_CQHCI=y +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_HI3798MV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_DW_PCI is not set +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MOTORCOMM_PHY=y +CONFIG_MQ_IOSCHED_DEADLINE=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_FLAGS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_TASKS_RCU=y +CONFIG_NET_DEVMEM=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=256 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_ROCKCHIP_EFUSE=y +CONFIG_NVMEM_ROCKCHIP_OTP=y +CONFIG_NVMEM_SYSFS=y +CONFIG_NVME_CORE=y +# CONFIG_NVME_HOST_AUTH is not set +# CONFIG_NVME_HWMON is not set +# CONFIG_NVME_MULTIPATH is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_OLD_SIGSUSPEND3=y +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SHIFT=12 +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_ROCKCHIP=y +CONFIG_PCIE_ROCKCHIP_DW=y +CONFIG_PCIE_ROCKCHIP_DW_HOST=y +CONFIG_PCIE_ROCKCHIP_HOST=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_STUB=y +CONFIG_PCS_XPCS=y +CONFIG_PER_VMA_LOCK=y +# CONFIG_PFCP is not set +CONFIG_PGTABLE_HAS_HUGE_LEAVES=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_ROCKCHIP_DP=y +# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set +CONFIG_PHY_ROCKCHIP_EMMC=y +# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y +CONFIG_PHY_ROCKCHIP_PCIE=y +# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PHY_ROCKCHIP_USB=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_RK805=y +CONFIG_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_SCMI is not set +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PL330_DMA=y +CONFIG_PLATFORM_MHU=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_VMCORE=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_ROCKCHIP=y +# CONFIG_QFMT_V2 is not set +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +CONFIG_RAID_ATTRS=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_MODULE_REGION_FULL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_RCU_TRACE=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_ARM_SCMI is not set +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK808=y +CONFIG_RELOCATABLE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y +CONFIG_RESET_SCMI=y +CONFIG_RFS_ACCEL=y +CONFIG_ROCKCHIP_ERRATUM_3588001=y +CONFIG_ROCKCHIP_GRF=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_ROCKCHIP_MBOX=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +CONFIG_ROCKCHIP_THERMAL=y +CONFIG_ROCKCHIP_TIMER=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +# CONFIG_RPMB is not set +CONFIG_RPS=y +CONFIG_RSEQ=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_RK808=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_NVMEM=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_PROC_FS is not set +CONFIG_SCSI_SAS_ATTRS=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SENSORS_ARM_SCMI is not set +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_AMBAKMI=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_ROCKCHIP=y +CONFIG_SPI_ROCKCHIP_SFC=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SRAM=y +CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_STRICT_DEVMEM=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_SWAP is not set +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYSVIPC_COMPAT=y +# CONFIG_TEXTSEARCH is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_CLOCK=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TRANS_TABLE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TYPEC=y +# CONFIG_TYPEC_ANX7411 is not set +CONFIG_TYPEC_FUSB302=y +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set +# CONFIG_TYPEC_MUX_IT5205 is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_PTN36502 is not set +# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set +# CONFIG_TYPEC_RT1719 is not set +# CONFIG_TYPEC_STUSB160X is not set +# CONFIG_TYPEC_TCPCI is not set +CONFIG_TYPEC_TCPM=y +# CONFIG_TYPEC_TPS6598X is not set +# CONFIG_TYPEC_WUSB3801 is not set +# CONFIG_UCLAMP_TASK is not set +# CONFIG_UEVENT_HELPER is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_HOST=y +CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_HID=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_PHY=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_BUS=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_VDSO_GETRANDOM=y +# CONFIG_VIRTIO_MENU is not set +CONFIG_VMAP_STACK=y +CONFIG_VMCORE_INFO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XARRAY_MULTI=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARM64=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c b/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c index 72601a0904fa2a..322314a8b80745 100644 --- a/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c +++ b/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c @@ -817,7 +817,11 @@ static int rk3328_dmcfreq_probe(struct platform_device *pdev) return ret; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) static int rk3328_dmcfreq_remove(struct platform_device *pdev) +#else +static void rk3328_dmcfreq_remove(struct platform_device *pdev) +#endif { struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev); @@ -827,7 +831,9 @@ static int rk3328_dmcfreq_remove(struct platform_device *pdev) devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq); dev_pm_opp_of_remove_table(dmcfreq->dev); +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) return 0; +#endif } static const struct of_device_id rk3328dmc_devfreq_of_match[] = { @@ -838,7 +844,11 @@ MODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match); static struct platform_driver rk3328_dmcfreq_driver = { .probe = rk3328_dmcfreq_probe, +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) .remove = rk3328_dmcfreq_remove, +#else + .remove_new = rk3328_dmcfreq_remove, +#endif .driver = { .name = "rk3328-dmc-freq", .pm = &rk3328_dmcfreq_pm, diff --git a/target/linux/rockchip/files/drivers/pci/controller/dwc/pcie-dw-rkvendor.c b/target/linux/rockchip/files/drivers/pci/controller/dwc/pcie-dw-rkvendor.c index 228525cb5d9384..a3ebd12d831a74 100644 --- a/target/linux/rockchip/files/drivers/pci/controller/dwc/pcie-dw-rkvendor.c +++ b/target/linux/rockchip/files/drivers/pci/controller/dwc/pcie-dw-rkvendor.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/target/linux/rockchip/patches-6.12/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.12/100-rockchip-use-system-LED-for-OpenWrt.patch new file mode 100644 index 00000000000000..9a7827978aed3c --- /dev/null +++ b/target/linux/rockchip/patches-6.12/100-rockchip-use-system-LED-for-OpenWrt.patch @@ -0,0 +1,77 @@ +From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 21:38:20 +0200 +Subject: [PATCH] rockchip: use system LED for OpenWrt + +Use the SYS LED on the casing for showing system status. + +This patch is kept separate from the NanoPi R2S support patch, as i plan +on submitting the device support upstream. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -6,6 +6,7 @@ + /dts-v1/; + + #include ++#include + #include + #include "rk3328.dtsi" + +@@ -17,6 +18,11 @@ + ethernet0 = &gmac2io; + ethernet1 = &rtl8153; + mmc0 = &sdmmc; ++ ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; + }; + + chosen { +@@ -49,19 +55,22 @@ + pinctrl-names = "default"; + + lan_led: led-0 { ++ color = ; ++ function = LED_FUNCTION_LAN; + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:lan"; + }; + + sys_led: led-1 { ++ color = ; ++ function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:red:sys"; + default-state = "on"; + }; + + wan_led: led-2 { ++ color = ; ++ function = LED_FUNCTION_WAN; + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:wan"; + }; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -14,6 +14,11 @@ + ethernet0 = &gmac2io; + mmc0 = &sdmmc; + mmc1 = &emmc; ++ ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen { diff --git a/target/linux/rockchip/patches-6.12/101-net-realtek-r8169-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-6.12/101-net-realtek-r8169-add-LED-configuration-from-OF.patch new file mode 100644 index 00000000000000..20ceaea9d02bfc --- /dev/null +++ b/target/linux/rockchip/patches-6.12/101-net-realtek-r8169-add-LED-configuration-from-OF.patch @@ -0,0 +1,58 @@ +From edcc2833819f6750bf003b95a6ac856aced26274 Mon Sep 17 00:00:00 2001 +From: AnYun +Date: Sat, 18 Mar 2023 23:05:16 +0800 +Subject: [PATCH] r8169: add LED configuration from OF + +--- + drivers/net/ethernet/realtek/r8169_main.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -175,6 +176,7 @@ enum rtl_registers { + MAR0 = 8, /* Multicast filter. */ + CounterAddrLow = 0x10, + CounterAddrHigh = 0x14, ++ CustomLED = 0x18, + TxDescStartAddrLow = 0x20, + TxDescStartAddrHigh = 0x24, + TxHDescStartAddrLow = 0x28, +@@ -5371,6 +5373,22 @@ static bool rtl_aspm_is_safe(struct rtl8 + return false; + } + ++static int rtl_led_configuration(struct rtl8169_private *tp) ++{ ++ u32 led_data; ++ int ret; ++ ++ ret = of_property_read_u32(tp->pci_dev->dev.of_node, ++ "realtek,led-data", &led_data); ++ ++ if (ret) ++ return ret; ++ ++ RTL_W16(tp, CustomLED, led_data); ++ ++ return 0; ++} ++ + static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) + { + struct rtl8169_private *tp; +@@ -5539,6 +5557,7 @@ static int rtl_init_one(struct pci_dev * + if (!tp->counters) + return -ENOMEM; + ++ rtl_led_configuration(tp); + pci_set_drvdata(pdev, tp); + + rc = r8169_mdio_register(tp); diff --git a/target/linux/rockchip/patches-6.12/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-6.12/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch new file mode 100644 index 00000000000000..46010e3f7ce270 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch @@ -0,0 +1,44 @@ +From edcc2833819f6750bf003b95a6ac856aced26276 Mon Sep 17 00:00:00 2001 +From: AnYun +Date: Mon, 3 Apr 2023 23:26:04 +0800 +Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f + +--- + drivers/net/phy/realtek.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -28,6 +28,8 @@ + #define RTL821x_EXT_PAGE_SELECT 0x1e + #define RTL821x_PAGE_SELECT 0x1f + ++#define RTL8211F_LCR 0x10 ++#define RTL8211F_EEELCR 0x11 + #define RTL8211F_PHYCR1 0x18 + #define RTL8211F_PHYCR2 0x19 + #define RTL8211F_INSR 0x1d +@@ -372,6 +374,7 @@ static int rtl8211f_config_init(struct p + struct rtl821x_priv *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; + u16 val_txdly, val_rxdly; ++ u32 led_data; + int ret; + + ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, +@@ -438,6 +441,15 @@ static int rtl8211f_config_init(struct p + val_rxdly ? "enabled" : "disabled"); + } + ++ ret = of_property_read_u32(dev->of_node, ++ "realtek,led-data", &led_data); ++ if (!ret) { ++ phy_write(phydev, RTL821x_PAGE_SELECT, 0xd04); ++ phy_write(phydev, RTL8211F_LCR, led_data); ++ phy_write(phydev, RTL8211F_EEELCR, 0x0); ++ phy_write(phydev, RTL821x_PAGE_SELECT, 0x0); ++ } ++ + if (priv->has_phycr2) { + ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2, + RTL8211F_CLKOUT_EN, priv->phycr2); diff --git a/target/linux/rockchip/patches-6.12/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-6.12/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch new file mode 100644 index 00000000000000..9f154e17daa101 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch @@ -0,0 +1,24 @@ +From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 26 Jul 2020 13:32:59 +0200 +Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S + +This adds the OF node for the USB3 ethernet adapter on the FriendlyARM +NanoPi R2S. Add the correct value for the RTL8153 LED configuration +register to match the blink behavior of the other port on the device. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ + 1 file changed, 1 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -407,6 +407,7 @@ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; ++ realtek,led-data = <0x87>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.12/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-6.12/105-nanopi-r4s-sd-signalling.patch new file mode 100644 index 00000000000000..c8ffc026e8e782 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/105-nanopi-r4s-sd-signalling.patch @@ -0,0 +1,36 @@ +From: David Bauer +Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S + +The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting +while U-Boot requires the card to be in 3.3V mode. + +Remove UHS support from the SD controller so the card remains in 3.3V +mode. This reduces transfer speeds but ensures a reboot whether from +userspace or following a kernel panic is always working. + +Signed-off-by: David Bauer + +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -336,7 +336,6 @@ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; +- sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -121,6 +121,11 @@ + status = "disabled"; + }; + ++&sdmmc { ++ /delete-property/ sd-uhs-sdr104; ++ cap-sd-highspeed; ++}; ++ + &u2phy0_host { + phy-supply = <&vdd_5v>; + }; diff --git a/target/linux/rockchip/patches-6.12/106-r4s-openwrt-leds.patch b/target/linux/rockchip/patches-6.12/106-r4s-openwrt-leds.patch new file mode 100644 index 00000000000000..d7579d61e90ce3 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/106-r4s-openwrt-leds.patch @@ -0,0 +1,16 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -19,6 +19,13 @@ + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + ++ aliases { ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; ++ }; ++ + /delete-node/ display-subsystem; + + gpio-leds { diff --git a/target/linux/rockchip/patches-6.12/107-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-6.12/107-mmc-core-set-initial-signal-voltage-on-power-off.patch new file mode 100644 index 00000000000000..0a58265be22a23 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/107-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -0,0 +1,35 @@ +From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Wed, 20 Feb 2019 07:38:34 +0000 +Subject: [PATCH] mmc: core: set initial signal voltage on power off + +Some boards have SD card connectors where the power rail cannot be switched +off by the driver. If the card has not been power cycled, it may still be +using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling +will fail to boot from a UHS card that continue to use 1.8V signaling. + +Set initial signal voltage in mmc_power_off() to allow re-boot to function. + +This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), +same issue have been seen on some Rockchip RK3399 boards. + +I am sending this as a RFC because I have no insights into SD/MMC subsystem, +this change fix a re-boot issue on my boards and does not break emmc/sdio. +Is this an acceptable workaround? Any advice is appreciated. + +Signed-off-by: Jonas Karlman +--- + drivers/mmc/core/core.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/mmc/core/core.c ++++ b/drivers/mmc/core/core.c +@@ -1370,6 +1370,8 @@ void mmc_power_off(struct mmc_host *host + + mmc_pwrseq_power_off(host); + ++ mmc_set_initial_signal_voltage(host); ++ + host->ios.clock = 0; + host->ios.vdd = 0; + diff --git a/target/linux/rockchip/patches-6.12/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch b/target/linux/rockchip/patches-6.12/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch new file mode 100644 index 00000000000000..1e0883e523385c --- /dev/null +++ b/target/linux/rockchip/patches-6.12/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch @@ -0,0 +1,77 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -64,7 +64,7 @@ + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; +- bus-range = <0x0 0xf>; ++ bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; +@@ -87,7 +87,7 @@ + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; +- msi-map = <0x0 &gic 0x1000 0x1000>; ++ msi-map = <0x1000 &its 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; +@@ -117,7 +117,7 @@ + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; +- bus-range = <0x0 0xf>; ++ bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; +@@ -140,7 +140,7 @@ + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; +- msi-map = <0x0 &gic 0x2000 0x1000>; ++ msi-map = <0x2000 &its 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -356,14 +356,21 @@ + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; ++ #interrupt-cells = <3>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ interrupt-controller; ++ + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ +- <0x0 0xfd460000 0 0x80000>; /* GICR */ ++ <0x0 0xfd460000 0 0xc0000>; /* GICR */ + interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- mbi-alias = <0x0 0xfd410000>; +- mbi-ranges = <296 24>; +- msi-controller; ++ its: interrupt-controller@fd440000 { ++ compatible = "arm,gic-v3-its"; ++ msi-controller; ++ #msi-cells = <1>; ++ reg = <0x0 0xfd440000 0x0 0x20000>; ++ }; + }; + + usb_host0_ehci: usb@fd800000 { +@@ -1038,7 +1045,7 @@ + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; +- msi-map = <0x0 &gic 0x0 0x1000>; ++ msi-map = <0x0 &its 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; diff --git a/target/linux/rockchip/patches-6.12/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch b/target/linux/rockchip/patches-6.12/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch new file mode 100644 index 00000000000000..2a633c894562db --- /dev/null +++ b/target/linux/rockchip/patches-6.12/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch @@ -0,0 +1,161 @@ +From 536378a084c6a4148141e132efee2fa9a464e007 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Thu, 3 Jun 2021 11:36:35 -0400 +Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its + +--- + drivers/irqchip/irq-gic-v3-its.c | 70 +++++++++++++++++++++++++++++--- + 1 file changed, 65 insertions(+), 5 deletions(-) + +--- a/drivers/irqchip/irq-gic-common.h ++++ b/drivers/irqchip/irq-gic-common.h +@@ -34,5 +34,6 @@ extern const struct msi_parent_ops gic_v + #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) + #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1) + #define RDIST_FLAGS_FORCE_NON_SHAREABLE (1 << 2) ++#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE (1 << 3) + + #endif /* _IRQ_GIC_COMMON_H */ +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -2183,6 +2183,11 @@ static struct page *its_allocate_prop_ta + { + struct page *prop_page; + ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) { ++ pr_debug("ITS ALLOCATE PROP WORKAROUND\n"); ++ gfp_flags |= GFP_DMA; ++ } ++ + prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); + if (!prop_page) + return NULL; +@@ -2305,6 +2310,7 @@ static int its_setup_baser(struct its_no + u64 baser_phys, tmp; + u32 alloc_pages, psz; + struct page *page; ++ gfp_t gfp_flags; + void *base; + + psz = baser->psz; +@@ -2317,7 +2323,10 @@ static int its_setup_baser(struct its_no + order = get_order(GITS_BASER_PAGES_MAX * psz); + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); ++ gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) ++ gfp_flags |= GFP_DMA; ++ page = alloc_pages_node(its->numa_node, gfp_flags, order); + if (!page) + return -ENOMEM; + +@@ -2957,6 +2966,10 @@ static struct page *its_allocate_pending + { + struct page *pend_page; + ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) { ++ gfp_flags |= GFP_DMA; ++ } ++ + pend_page = alloc_pages(gfp_flags | __GFP_ZERO, + get_order(LPI_PENDBASE_SZ)); + if (!pend_page) +@@ -3305,7 +3318,12 @@ static bool its_alloc_table_entry(struct + + /* Allocate memory for 2nd level table */ + if (!table[idx]) { +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) { ++ gfp_flags |= GFP_DMA; ++ } ++ ++ page = alloc_pages_node(its->numa_node, gfp_flags, + get_order(baser->psz)); + if (!page) + return false; +@@ -3389,6 +3407,7 @@ static struct its_device *its_create_dev + unsigned long *lpi_map = NULL; + unsigned long flags; + u16 *col_map = NULL; ++ gfp_t gfp_flags; + void *itt; + int lpi_base; + int nr_lpis; +@@ -3401,7 +3420,11 @@ static struct its_device *its_create_dev + if (WARN_ON(!is_power_of_2(nvecs))) + nvecs = roundup_pow_of_two(nvecs); + +- dev = kzalloc(sizeof(*dev), GFP_KERNEL); ++ gfp_flags = GFP_KERNEL; ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) ++ gfp_flags |= GFP_DMA; ++ ++ dev = kzalloc(sizeof(*dev), gfp_flags); + /* + * Even if the device wants a single LPI, the ITT must be + * sized as a power of two (and you need at least one bit...). +@@ -3409,7 +3432,7 @@ static struct its_device *its_create_dev + nr_ites = max(2, nvecs); + sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); + sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; +- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); ++ itt = kzalloc_node(sz, gfp_flags, its->numa_node); + if (alloc_lpis) { + lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); + if (lpi_map) +@@ -4771,6 +4794,21 @@ static bool __maybe_unused its_enable_qu + return true; + } + ++static bool __maybe_unused its_enable_rk3568001(void *data) ++{ ++ struct its_node *its = data; ++ ++ if (!of_machine_is_compatible("rockchip,rk3566") && ++ !of_machine_is_compatible("rockchip,rk3568")) ++ return false; ++ ++ its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; ++ gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE | ++ RDIST_FLAGS_FORCE_NO_LOCAL_CACHE; ++ ++ return true; ++} ++ + static bool __maybe_unused its_enable_rk3588001(void *data) + { + struct its_node *its = data; +@@ -4857,6 +4895,12 @@ static const struct gic_quirk its_quirks + #endif + #ifdef CONFIG_ROCKCHIP_ERRATUM_3588001 + { ++ .desc = "ITS: Rockchip erratum RK3568001", ++ .iidr = 0x0201743b, ++ .mask = 0xffffffff, ++ .init = its_enable_rk3568001, ++ }, ++ { + .desc = "ITS: Rockchip erratum RK3588001", + .iidr = 0x0201743b, + .mask = 0xffffffff, +@@ -5125,6 +5169,7 @@ static int __init its_probe_one(struct i + { + u64 baser, tmp; + struct page *page; ++ gfp_t gfp_flags; + u32 ctlr; + int err; + +@@ -5160,7 +5205,9 @@ static int __init its_probe_one(struct i + } + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA; ++ ++ page = alloc_pages_node(its->numa_node, gfp_flags, + get_order(ITS_CMD_QUEUE_SZ)); + if (!page) { + err = -ENOMEM; diff --git a/target/linux/rockchip/patches-6.12/112-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch b/target/linux/rockchip/patches-6.12/112-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch new file mode 100644 index 00000000000000..8589b5911e15b4 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/112-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch @@ -0,0 +1,33 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -175,11 +175,13 @@ + clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, + <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, +- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; ++ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, ++ <&cru PCLK_XPCS>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", +- "clk_mac_speed", "ptp_ref"; ++ "clk_mac_speed", "ptp_ref", ++ "pclk_xpcs"; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -417,6 +417,12 @@ + status = "disabled"; + }; + ++ xpcs: syscon@fda00000 { ++ compatible = "rockchip,rk3568-xpcs", "syscon"; ++ reg = <0x0 0xfda00000 0x0 0x200000>; ++ status = "disabled"; ++ }; ++ + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.12/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch b/target/linux/rockchip/patches-6.12/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch new file mode 100644 index 00000000000000..2609b67343ebfb --- /dev/null +++ b/target/linux/rockchip/patches-6.12/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch @@ -0,0 +1,320 @@ +From ca89ea7e0760c096c6fd807d321ecb8416f8cd9d Mon Sep 17 00:00:00 2001 +From: David Wu +Date: Thu, 31 Dec 2020 18:32:03 +0800 +Subject: [PATCH] ethernet: stmicro: stmmac: Add SGMII/QSGMII support for + RK3568 + +After the completion of Clause 37 auto-negotiation, xpcs automatically +switches to the negotiated speed for 10/100/1000M. + +Change-Id: Iab9dd6ee61a35bf89fd3a0721f5d398de501a7ec +Signed-off-by: David Wu +--- + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 228 +++++++++++++++++- + 1 file changed, 217 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -28,6 +29,8 @@ struct rk_gmac_ops { + void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay); + void (*set_to_rmii)(struct rk_priv_data *bsp_priv); ++ void (*set_to_sgmii)(struct rk_priv_data *bsp_priv); ++ void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv); + void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); + void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); + void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, +@@ -38,7 +41,7 @@ struct rk_gmac_ops { + }; + + static const char * const rk_clocks[] = { +- "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", ++ "aclk_mac", "pclk_mac", "pclk_xpcs", "mac_clk_tx", "clk_mac_speed", + }; + + static const char * const rk_rmii_clocks[] = { +@@ -48,6 +51,7 @@ static const char * const rk_rmii_clocks + enum rk_clocks_index { + RK_ACLK_MAC = 0, + RK_PCLK_MAC, ++ RK_PCLK_XPCS, + RK_MAC_CLK_TX, + RK_CLK_MAC_SPEED, + RK_MAC_CLK_RX, +@@ -79,6 +83,7 @@ struct rk_priv_data { + + struct regmap *grf; + struct regmap *php_grf; ++ struct regmap *xpcs; + }; + + #define HIWORD_UPDATE(val, mask, shift) \ +@@ -91,6 +96,128 @@ struct rk_priv_data { + (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ + ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) + ++/* XPCS */ ++#define XPCS_APB_INCREMENT (0x4) ++#define XPCS_APB_MASK GENMASK_ULL(20, 0) ++ ++#define SR_MII_BASE (0x1F0000) ++#define SR_MII1_BASE (0x1A0000) ++ ++#define VR_MII_DIG_CTRL1 (0x8000) ++#define VR_MII_AN_CTRL (0x8001) ++#define VR_MII_AN_INTR_STS (0x8002) ++#define VR_MII_LINK_TIMER_CTRL (0x800A) ++ ++#define SR_MII_CTRL_AN_ENABLE \ ++ (BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000) ++#define MII_MAC_AUTO_SW (0x0200) ++#define PCS_MODE_OFFSET (0x1) ++#define MII_AN_INTR_EN (0x1) ++#define PCS_SGMII_MODE (0x2 << PCS_MODE_OFFSET) ++#define PCS_QSGMII_MODE (0X3 << PCS_MODE_OFFSET) ++#define VR_MII_CTRL_SGMII_AN_EN (PCS_SGMII_MODE | MII_AN_INTR_EN) ++#define VR_MII_CTRL_QSGMII_AN_EN (PCS_QSGMII_MODE | MII_AN_INTR_EN) ++ ++#define SR_MII_OFFSET(_x) ({ \ ++ typeof(_x) (x) = (_x); \ ++ (((x) == 0) ? SR_MII_BASE : (SR_MII1_BASE + ((x) - 1) * 0x10000)); \ ++}) \ ++ ++static int xpcs_read(void *priv, int reg) ++{ ++ struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv; ++ int ret, val; ++ ++ ret = regmap_read(bsp_priv->xpcs, ++ (u32)(reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK, ++ &val); ++ if (ret) ++ return ret; ++ ++ return val; ++} ++ ++static int xpcs_write(void *priv, int reg, u16 value) ++{ ++ struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv; ++ ++ return regmap_write(bsp_priv->xpcs, ++ (reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK, value); ++} ++ ++static int xpcs_poll_reset(struct rk_priv_data *bsp_priv, int dev) ++{ ++ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */ ++ unsigned int retries = 12; ++ int ret; ++ ++ do { ++ msleep(50); ++ ret = xpcs_read(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1); ++ if (ret < 0) ++ return ret; ++ } while (ret & MDIO_CTRL1_RESET && --retries); ++ ++ return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0; ++} ++ ++static int xpcs_soft_reset(struct rk_priv_data *bsp_priv, int dev) ++{ ++ int ret; ++ ++ ret = xpcs_write(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1, ++ MDIO_CTRL1_RESET); ++ if (ret < 0) ++ return ret; ++ ++ return xpcs_poll_reset(bsp_priv, dev); ++} ++ ++static int xpcs_setup(struct rk_priv_data *bsp_priv, int mode) ++{ ++ int ret, i, idx = bsp_priv->id; ++ u32 val; ++ ++ if (mode == PHY_INTERFACE_MODE_QSGMII && idx > 0) ++ return 0; ++ ++ ret = xpcs_soft_reset(bsp_priv, idx); ++ if (ret) { ++ dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret); ++ return ret; ++ } ++ ++ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_INTR_STS, 0x0); ++ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_LINK_TIMER_CTRL, 0x1); ++ ++ if (mode == PHY_INTERFACE_MODE_SGMII) ++ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL, ++ VR_MII_CTRL_SGMII_AN_EN); ++ else ++ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL, ++ VR_MII_CTRL_QSGMII_AN_EN); ++ ++ if (mode == PHY_INTERFACE_MODE_QSGMII) { ++ for (i = 0; i < 4; i++) { ++ val = xpcs_read(bsp_priv, ++ SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1); ++ xpcs_write(bsp_priv, ++ SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1, ++ val | MII_MAC_AUTO_SW); ++ xpcs_write(bsp_priv, SR_MII_OFFSET(i) + MII_BMCR, ++ SR_MII_CTRL_AN_ENABLE); ++ } ++ } else { ++ val = xpcs_read(bsp_priv, SR_MII_OFFSET(idx) + VR_MII_DIG_CTRL1); ++ xpcs_write(bsp_priv, SR_MII_OFFSET(idx) + VR_MII_DIG_CTRL1, ++ val | MII_MAC_AUTO_SW); ++ xpcs_write(bsp_priv, SR_MII_OFFSET(idx) + MII_BMCR, ++ SR_MII_CTRL_AN_ENABLE); ++ } ++ ++ return ret; ++} ++ + #define PX30_GRF_GMAC_CON1 0x0904 + + /* PX30_GRF_GMAC_CON1 */ +@@ -1019,6 +1146,7 @@ static const struct rk_gmac_ops rk3399_o + #define RK3568_GRF_GMAC1_CON1 0x038c + + /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ ++#define RK3568_GMAC_GMII_MODE GRF_BIT(7) + #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ + (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) + #define RK3568_GMAC_PHY_INTF_SEL_RMII \ +@@ -1034,6 +1162,46 @@ static const struct rk_gmac_ops rk3399_o + #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) + #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) + ++#define RK3568_PIPE_GRF_XPCS_CON0 0X0040 ++ ++#define RK3568_PIPE_GRF_XPCS_QGMII_MAC_SEL GRF_BIT(0) ++#define RK3568_PIPE_GRF_XPCS_SGMII_MAC_SEL GRF_BIT(1) ++#define RK3568_PIPE_GRF_XPCS_PHY_READY GRF_BIT(2) ++ ++static void rk3568_set_to_sgmii(struct rk_priv_data *bsp_priv) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ u32 con1; ++ ++ if (IS_ERR(bsp_priv->grf)) { ++ dev_err(dev, "Missing rockchip,grf property\n"); ++ return; ++ } ++ ++ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : ++ RK3568_GRF_GMAC0_CON1; ++ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_GMII_MODE); ++ ++ xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_SGMII); ++} ++ ++static void rk3568_set_to_qsgmii(struct rk_priv_data *bsp_priv) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ u32 con1; ++ ++ if (IS_ERR(bsp_priv->grf)) { ++ dev_err(dev, "Missing rockchip,grf property\n"); ++ return; ++ } ++ ++ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : ++ RK3568_GRF_GMAC0_CON1; ++ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_GMII_MODE); ++ ++ xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_QSGMII); ++} ++ + static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +@@ -1106,6 +1274,8 @@ static void rk3568_set_gmac_speed(struct + static const struct rk_gmac_ops rk3568_ops = { + .set_to_rgmii = rk3568_set_to_rgmii, + .set_to_rmii = rk3568_set_to_rmii, ++ .set_to_sgmii = rk3568_set_to_sgmii, ++ .set_to_qsgmii = rk3568_set_to_qsgmii, + .set_rgmii_speed = rk3568_set_gmac_speed, + .set_rmii_speed = rk3568_set_gmac_speed, + .regs_valid = true, +@@ -1733,7 +1903,7 @@ static int gmac_clk_enable(struct rk_pri + return 0; + } + +-static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) ++static int rk_gmac_phy_power_on(struct rk_priv_data *bsp_priv, bool enable) + { + struct regulator *ldo = bsp_priv->regulator; + int ret; +@@ -1832,6 +2002,18 @@ static struct rk_priv_data *rk_gmac_setu + "rockchip,grf"); + bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,php-grf"); ++ bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node, ++ "rockchip,xpcs"); ++ if (!IS_ERR(bsp_priv->xpcs)) { ++ struct phy *comphy; ++ ++ comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL); ++ if (IS_ERR(comphy)) ++ dev_err(dev, "devm_of_phy_get error\n"); ++ ret = phy_init(comphy); ++ if (ret) ++ dev_err(dev, "phy_init error\n"); ++ } + + if (plat->phy_node) { + bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, +@@ -1909,11 +2091,19 @@ static int rk_gmac_powerup(struct rk_pri + dev_info(dev, "init for RMII\n"); + bsp_priv->ops->set_to_rmii(bsp_priv); + break; ++ case PHY_INTERFACE_MODE_SGMII: ++ dev_info(dev, "init for SGMII\n"); ++ bsp_priv->ops->set_to_sgmii(bsp_priv); ++ break; ++ case PHY_INTERFACE_MODE_QSGMII: ++ dev_info(dev, "init for QSGMII\n"); ++ bsp_priv->ops->set_to_qsgmii(bsp_priv); ++ break; + default: + dev_err(dev, "NO interface defined!\n"); + } + +- ret = phy_power_on(bsp_priv, true); ++ ret = rk_gmac_phy_power_on(bsp_priv, true); + if (ret) { + gmac_clk_enable(bsp_priv, false); + return ret; +@@ -1934,7 +2124,7 @@ static void rk_gmac_powerdown(struct rk_ + + pm_runtime_put_sync(&gmac->pdev->dev); + +- phy_power_on(gmac, false); ++ rk_gmac_phy_power_on(gmac, false); + gmac_clk_enable(gmac, false); + } + +@@ -1955,6 +2145,9 @@ static void rk_fix_speed(void *priv, uns + if (bsp_priv->ops->set_rmii_speed) + bsp_priv->ops->set_rmii_speed(bsp_priv, speed); + break; ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ break; + default: + dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); + } diff --git a/target/linux/rockchip/patches-6.12/120-phy-rockchip-naneng-combo-add-rk3576-support.patch b/target/linux/rockchip/patches-6.12/120-phy-rockchip-naneng-combo-add-rk3576-support.patch new file mode 100644 index 00000000000000..943584dbac3fa4 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/120-phy-rockchip-naneng-combo-add-rk3576-support.patch @@ -0,0 +1,375 @@ +From: Frank Wang +To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, + krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de +Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, + william.wu@rock-chips.com, tim.chen@rock-chips.com, + Kever Yang , + Frank Wang +Subject: [PATCH v3 2/2] phy: rockchip-naneng-combo: add rk3576 support +Date: Fri, 18 Oct 2024 14:25:26 +0800 [thread overview] +Message-ID: <20241018062526.33994-2-frawang.cn@gmail.com> (raw) +In-Reply-To: <20241018062526.33994-1-frawang.cn@gmail.com> + +From: Kever Yang + +Rockchip RK3576 integrates two naneng-combo PHY, PHY0 is used for +PCIE and SATA, PHY1 is used for PCIE, SATA and USB3. + +This adds device specific data support. + +Signed-off-by: Kever Yang +Signed-off-by: William Wu +Signed-off-by: Frank Wang +--- +Changelog: +v3: + - add detail commit contents. + - using FIELD_PREP() instead of bit shift. + - leave a blank line after each switch break case. + +v2: + - using constants macro instead of magic values. + - add more comments for PHY tuning operations. + +v1: + - https://patchwork.kernel.org/project/linux-phy/patch/20241015013351.4884-2-frawang.cn@gmail.com/ + + .../rockchip/phy-rockchip-naneng-combphy.c | 279 ++++++++++++++++++ + 1 file changed, 279 insertions(+) + +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -37,6 +37,10 @@ + #define PHYREG8 0x1C + #define PHYREG8_SSC_EN BIT(4) + ++#define PHYREG10 0x24 ++#define PHYREG10_SSC_PCM_MASK GENMASK(3, 0) ++#define PHYREG10_SSC_PCM_3500PPM 7 ++ + #define PHYREG11 0x28 + #define PHYREG11_SU_TRIM_0_7 0xF0 + +@@ -61,17 +65,26 @@ + #define PHYREG16 0x3C + #define PHYREG16_SSC_CNT_VALUE 0x5f + ++#define PHYREG17 0x40 ++ + #define PHYREG18 0x44 + #define PHYREG18_PLL_LOOP 0x32 + ++#define PHYREG21 0x50 ++#define PHYREG21_RX_SQUELCH_VAL 0x0D ++ + #define PHYREG27 0x6C + #define PHYREG27_RX_TRIM_RK3588 0x4C + ++#define PHYREG30 0x74 ++ + #define PHYREG32 0x7C + #define PHYREG32_SSC_MASK GENMASK(7, 4) ++#define PHYREG32_SSC_DIR_MASK GENMASK(5, 4) + #define PHYREG32_SSC_DIR_SHIFT 4 + #define PHYREG32_SSC_UPWARD 0 + #define PHYREG32_SSC_DOWNWARD 1 ++#define PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6) + #define PHYREG32_SSC_OFFSET_SHIFT 6 + #define PHYREG32_SSC_OFFSET_500PPM 1 + +@@ -79,6 +92,7 @@ + #define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) + #define PHYREG33_PLL_KVCO_SHIFT 2 + #define PHYREG33_PLL_KVCO_VALUE 2 ++#define PHYREG33_PLL_KVCO_VALUE_RK3576 4 + + struct rockchip_combphy_priv; + +@@ -98,6 +112,7 @@ struct rockchip_combphy_grfcfg { + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; ++ struct combphy_reg pipe_clk_24m; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; +@@ -584,6 +599,266 @@ static const struct rockchip_combphy_cfg + .combphy_cfg = rk3568_combphy_cfg, + }; + ++static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) ++{ ++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; ++ unsigned long rate; ++ u32 val; ++ ++ switch (priv->type) { ++ case PHY_TYPE_PCIE: ++ /* Set SSC downward spread spectrum */ ++ val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD); ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); ++ break; ++ ++ case PHY_TYPE_USB3: ++ /* Set SSC downward spread spectrum */ ++ val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD); ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ ++ /* Enable adaptive CTLE for USB3.0 Rx */ ++ val = readl(priv->mmio + PHYREG15); ++ val |= PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + PHYREG15); ++ ++ /* Set PLL KVCO fine tuning signals */ ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33); ++ ++ /* Set PLL LPF R1 to su_trim[10:7]=1001 */ ++ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ ++ /* Set PLL input clock divider 1/2 */ ++ val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2); ++ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6); ++ ++ /* Set PLL loop divider */ ++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ ++ /* Set PLL KVCO to min and set PLL charge pump current to max */ ++ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ ++ /* Set Rx squelch input filler bandwidth */ ++ writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); ++ break; ++ ++ case PHY_TYPE_SATA: ++ /* Enable adaptive CTLE for SATA Rx */ ++ val = readl(priv->mmio + PHYREG15); ++ val |= PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + PHYREG15); ++ ++ /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ ++ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; ++ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; ++ writel(val, priv->mmio + PHYREG7); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); ++ break; ++ ++ default: ++ dev_err(priv->dev, "incompatible PHY type\n"); ++ return -EINVAL; ++ } ++ ++ rate = clk_get_rate(priv->refclk); ++ ++ switch (rate) { ++ case REF_CLOCK_24MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); ++ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { ++ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ ++ val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE); ++ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, ++ val, PHYREG15); ++ ++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ } else if (priv->type == PHY_TYPE_PCIE) { ++ /* PLL KVCO tuning fine */ ++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ val, PHYREG33); ++ ++ /* Set up rx_pck invert and rx msb to disable */ ++ writel(0x00, priv->mmio + PHYREG27); ++ ++ /* ++ * Set up SU adjust signal: ++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min ++ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011 ++ * su_trim[31:24], CKDRV adjust ++ */ ++ writel(0x90, priv->mmio + PHYREG11); ++ writel(0x02, priv->mmio + PHYREG12); ++ writel(0x57, priv->mmio + PHYREG14); ++ ++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ } ++ break; ++ ++ case REF_CLOCK_25MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); ++ break; ++ ++ case REF_CLOCK_100MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); ++ if (priv->type == PHY_TYPE_PCIE) { ++ /* gate_tx_pck_sel length select work for L1SS */ ++ writel(0xc0, priv->mmio + PHYREG30); ++ ++ /* PLL KVCO tuning fine */ ++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ val, PHYREG33); ++ ++ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ ++ writel(0x4c, priv->mmio + PHYREG27); ++ ++ /* ++ * Set up SU adjust signal: ++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min ++ * su_trim[15:8], bypass PLL loop divider code, and ++ * PLL LPF R1 adujst bits[9:7]=3'b101 ++ * su_trim[23:16], CKRCV adjust ++ * su_trim[31:24], CKDRV adjust ++ */ ++ writel(0x90, priv->mmio + PHYREG11); ++ writel(0x43, priv->mmio + PHYREG12); ++ writel(0x88, priv->mmio + PHYREG13); ++ writel(0x56, priv->mmio + PHYREG14); ++ } else if (priv->type == PHY_TYPE_SATA) { ++ /* downward spread spectrum +500ppm */ ++ val = FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD); ++ val |= FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PPM); ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ ++ /* ssc ppm adjust to 3500ppm */ ++ rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK, ++ PHYREG10_SSC_PCM_3500PPM, ++ PHYREG10); ++ } ++ break; ++ ++ default: ++ dev_err(priv->dev, "Unsupported rate: %lu\n", rate); ++ return -EINVAL; ++ } ++ ++ if (priv->ext_refclk) { ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); ++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { ++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ val, PHYREG33); ++ ++ /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */ ++ writel(0x0c, priv->mmio + PHYREG27); ++ ++ /* ++ * Set up SU adjust signal: ++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min ++ * su_trim[15:8], bypass PLL loop divider code, and ++ * PLL LPF R1 adujst bits[9:7]=3'b101. ++ * su_trim[23:16], CKRCV adjust ++ * su_trim[31:24], CKDRV adjust ++ */ ++ writel(0x90, priv->mmio + PHYREG11); ++ writel(0x43, priv->mmio + PHYREG12); ++ writel(0x88, priv->mmio + PHYREG13); ++ writel(0x56, priv->mmio + PHYREG14); ++ } ++ } ++ ++ if (priv->enable_ssc) { ++ val = readl(priv->mmio + PHYREG8); ++ val |= PHYREG8_SSC_EN; ++ writel(val, priv->mmio + PHYREG8); ++ ++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { ++ /* Set PLL loop divider */ ++ writel(0x00, priv->mmio + PHYREG17); ++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ ++ /* Set up rx_pck invert and rx msb to disable */ ++ writel(0x00, priv->mmio + PHYREG27); ++ ++ /* ++ * Set up SU adjust signal: ++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min ++ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101 ++ * su_trim[23:16], CKRCV adjust ++ * su_trim[31:24], CKDRV adjust ++ */ ++ writel(0x90, priv->mmio + PHYREG11); ++ writel(0x02, priv->mmio + PHYREG12); ++ writel(0x08, priv->mmio + PHYREG13); ++ writel(0x57, priv->mmio + PHYREG14); ++ writel(0x40, priv->mmio + PHYREG15); ++ ++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ ++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); ++ writel(val, priv->mmio + PHYREG33); ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { ++ /* pipe-phy-grf */ ++ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, ++ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, ++ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, ++ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, ++ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, ++ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, ++ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, ++ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, ++ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, ++ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, ++ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, ++ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, ++ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, ++ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, ++ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, ++ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, ++ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, ++ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, ++ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, ++ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, ++ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, ++ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, ++ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, ++ /* php-grf */ ++ .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, ++ .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, ++}; ++ ++static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { ++ .num_phys = 2, ++ .phy_ids = { ++ 0x2b050000, ++ 0x2b060000 ++ }, ++ .grfcfg = &rk3576_combphy_grfcfgs, ++ .combphy_cfg = rk3576_combphy_cfg, ++}; ++ + static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) + { + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; +@@ -776,6 +1051,10 @@ static const struct of_device_id rockchi + .data = &rk3568_combphy_cfgs, + }, + { ++ .compatible = "rockchip,rk3576-naneng-combphy", ++ .data = &rk3576_combphy_cfgs, ++ }, ++ { + .compatible = "rockchip,rk3588-naneng-combphy", + .data = &rk3588_combphy_cfgs, + }, diff --git a/target/linux/rockchip/patches-6.12/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch b/target/linux/rockchip/patches-6.12/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch new file mode 100644 index 00000000000000..4516341a0c8a11 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch @@ -0,0 +1,22 @@ +From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001 +From: QiuSimons <45143996+QiuSimons@users.noreply.github.com> +Date: Tue, 4 Aug 2020 20:17:53 +0800 +Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s + +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++ + 1 files changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -176,6 +176,10 @@ + }; + }; + ++&i2c0 { ++ status = "okay"; ++}; ++ + &i2c1 { + status = "okay"; + diff --git a/target/linux/rockchip/patches-6.12/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch b/target/linux/rockchip/patches-6.12/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch new file mode 100644 index 00000000000000..36247a840589aa --- /dev/null +++ b/target/linux/rockchip/patches-6.12/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch @@ -0,0 +1,442 @@ +From 0f989817a4c1d2c3d196d550ff05cda98bc91324 Mon Sep 17 00:00:00 2001 +From: Julian Pidancet +Date: Sun, 23 Jan 2022 16:34:08 +0100 +Subject: [PATCH v2] rockchip: rk3328: add support for FriendlyARM NanoPi NEO3 + +This patch adds support for FriendlyARM NanoPi NEO3 + +Soc: RockChip RK3328 +RAM: 1GB/2GB DDR4 +LAN: 10/100/1000M Ethernet with unique MAC +USB Host: 1x USB3.0 Type A and 2x USB2.0 on 2.54mm pin header +MicroSD: x 1 for system boot and storage +LED: Power LED x 1, System LED x 1 +Key: User Button x 1 +Fan: 2 Pin JST ZH 1.5mm Connector for 5V Fan +GPIO: 26 pin-header, include I2C, UART, SPI, I2S, GPIO +Power: 5V/1A, via Type-C or GPIO + +Signed-off-by: Julian Pidancet +--- + +This is another shot at previous work submitted by Marty Jones + (https://lore.kernel.org/linux-arm-kernel/20201228152836.02795e09.mj8263788@gmail.com/), +which is now a year old. + +v2: Following up on Robin Murphy's comments, the NEO3 DTS is now +standalone and no longer includes the nanopi R2S one. The lan_led and +wan_len nodes have been removed, and the sys_led node has been renamed +to status_led in accordance with the board schematics. + + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3328-nanopi-neo3.dts | 396 ++++++++++++++++++ + 2 files changed, 397 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-na + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts +@@ -0,0 +1,394 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 David Bauer ++ * Copyright (c) 2022 Julian Pidancet ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3328.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi NEO3"; ++ compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328"; ++ ++ aliases { ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clk: gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&reset_button_pin>; ++ pinctrl-names = "default"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&status_led_pin>; ++ pinctrl-names = "default"; ++ ++ status_led: led-0 { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-neo3:green:status"; ++ }; ++ }; ++ ++ vcc_io_sdio: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&sdio_vcc_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_io_sdio"; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-settling-time-us = <5000>; ++ regulator-type = "voltage"; ++ startup-delay-us = <2000>; ++ states = <1800000 0x1>, ++ <3300000 0x0>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_rtl8153: vcc-rtl8153-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8153_en_drv>; ++ regulator-always-on; ++ regulator-name = "vcc_rtl8153"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&display_subsystem { ++ status = "disabled"; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; ++ clock_in_out = "input"; ++ phy-handle = <&rtl8211e>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc_io_33>; ++ pinctrl-0 = <&rgmiim1_pins>; ++ pinctrl-names = "default"; ++ rx_delay = <0x18>; ++ snps,aal; ++ tx_delay = <0x24>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211e: ethernet-phy@1 { ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: pmic@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vdd_5v>; ++ vcc2-supply = <&vdd_5v>; ++ vcc3-supply = <&vdd_5v>; ++ vcc4-supply = <&vdd_5v>; ++ vcc5-supply = <&vcc_io_33>; ++ vcc6-supply = <&vdd_5v>; ++ ++ regulators { ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io_33: DCDC_REG4 { ++ regulator-name = "vcc_io_33"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ pmuio-supply = <&vcc_io_33>; ++ vccio1-supply = <&vcc_io_33>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io_sdio>; ++ vccio4-supply = <&vcc_18>; ++ vccio5-supply = <&vcc_io_33>; ++ vccio6-supply = <&vcc_io_33>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ button { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ ethernet-phy { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ status_led_pin: status-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sd { ++ sdio_vcc_pin: sdio-vcc-pin { ++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ rtl8153_en_drv: rtl8153-en-drv { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_sd>; ++ vqmmc-supply = <&vcc_io_sdio>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb20_otg { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usb-eth@2 { ++ compatible = "realtek,rtl8153"; ++ reg = <2>; ++ ++ realtek,led-data = <0x87>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.12/210-rockchip-rk3399-add-support-more-devices.patch b/target/linux/rockchip/patches-6.12/210-rockchip-rk3399-add-support-more-devices.patch new file mode 100644 index 00000000000000..2b014d80f9b2a1 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/210-rockchip-rk3399-add-support-more-devices.patch @@ -0,0 +1,11 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -45,6 +45,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gr + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-guangmiao-g4c.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb diff --git a/target/linux/rockchip/patches-6.12/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch b/target/linux/rockchip/patches-6.12/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch new file mode 100644 index 00000000000000..8c82c95c7eb701 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch @@ -0,0 +1,39 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -264,6 +264,7 @@ + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1775,6 +1775,7 @@ + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; +@@ -1791,6 +1792,7 @@ + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -324,7 +324,7 @@ static int rockchip_combphy_parse_dt(str + + priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); + +- priv->phy_rst = devm_reset_control_array_get_exclusive(dev); ++ priv->phy_rst = devm_reset_control_get(dev, "phy"); + if (IS_ERR(priv->phy_rst)) + return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); + diff --git a/target/linux/rockchip/patches-6.12/301-pinctrl-rockchip-add-rk3528-support.patch b/target/linux/rockchip/patches-6.12/301-pinctrl-rockchip-add-rk3528-support.patch new file mode 100644 index 00000000000000..d05e75cfe6c9f4 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/301-pinctrl-rockchip-add-rk3528-support.patch @@ -0,0 +1,269 @@ +From ee5af82a6f88fd28849ea6d98cf43fbe9cbbbb19 Mon Sep 17 00:00:00 2001 +From: Steven Liu +Date: Thu, 11 Aug 2022 15:15:28 +0800 +Subject: [PATCH] pinctrl: rockchip: add rk3528 support + +Signed-off-by: Steven Liu +Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 +--- + drivers/pinctrl/pinctrl-rockchip.c | 196 ++++++++++++++++++++++++++++- + drivers/pinctrl/pinctrl-rockchip.h | 1 + + 2 files changed, 196 insertions(+), 1 deletion(-) + +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -2036,6 +2036,150 @@ static int rk3568_calc_pull_reg_and_bit( + return 0; + } + ++#define RK3528_DRV_BITS_PER_PIN 8 ++#define RK3528_DRV_PINS_PER_REG 2 ++#define RK3528_DRV_GPIO0_OFFSET 0x100 ++#define RK3528_DRV_GPIO1_OFFSET 0x20120 ++#define RK3528_DRV_GPIO2_OFFSET 0x30160 ++#define RK3528_DRV_GPIO3_OFFSET 0x20190 ++#define RK3528_DRV_GPIO4_OFFSET 0x101C0 ++ ++static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ switch (bank->bank_num) { ++ case 0: ++ *reg = RK3528_DRV_GPIO0_OFFSET; ++ break; ++ ++ case 1: ++ *reg = RK3528_DRV_GPIO1_OFFSET; ++ break; ++ ++ case 2: ++ *reg = RK3528_DRV_GPIO2_OFFSET; ++ break; ++ ++ case 3: ++ *reg = RK3528_DRV_GPIO3_OFFSET; ++ break; ++ ++ case 4: ++ *reg = RK3528_DRV_GPIO4_OFFSET; ++ break; ++ ++ default: ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ break; ++ } ++ ++ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3528_DRV_PINS_PER_REG; ++ *bit *= RK3528_DRV_BITS_PER_PIN; ++ ++ return 0; ++} ++ ++#define RK3528_PULL_BITS_PER_PIN 2 ++#define RK3528_PULL_PINS_PER_REG 8 ++#define RK3528_PULL_GPIO0_OFFSET 0x200 ++#define RK3528_PULL_GPIO1_OFFSET 0x20210 ++#define RK3528_PULL_GPIO2_OFFSET 0x30220 ++#define RK3528_PULL_GPIO3_OFFSET 0x20230 ++#define RK3528_PULL_GPIO4_OFFSET 0x10240 ++ ++static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ switch (bank->bank_num) { ++ case 0: ++ *reg = RK3528_PULL_GPIO0_OFFSET; ++ break; ++ ++ case 1: ++ *reg = RK3528_PULL_GPIO1_OFFSET; ++ break; ++ ++ case 2: ++ *reg = RK3528_PULL_GPIO2_OFFSET; ++ break; ++ ++ case 3: ++ *reg = RK3528_PULL_GPIO3_OFFSET; ++ break; ++ ++ case 4: ++ *reg = RK3528_PULL_GPIO4_OFFSET; ++ break; ++ ++ default: ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ break; ++ } ++ ++ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3528_PULL_PINS_PER_REG; ++ *bit *= RK3528_PULL_BITS_PER_PIN; ++ ++ return 0; ++} ++ ++#define RK3528_SMT_BITS_PER_PIN 1 ++#define RK3528_SMT_PINS_PER_REG 8 ++#define RK3528_SMT_GPIO0_OFFSET 0x400 ++#define RK3528_SMT_GPIO1_OFFSET 0x20410 ++#define RK3528_SMT_GPIO2_OFFSET 0x30420 ++#define RK3528_SMT_GPIO3_OFFSET 0x20430 ++#define RK3528_SMT_GPIO4_OFFSET 0x10440 ++ ++static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, ++ struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ switch (bank->bank_num) { ++ case 0: ++ *reg = RK3528_SMT_GPIO0_OFFSET; ++ break; ++ ++ case 1: ++ *reg = RK3528_SMT_GPIO1_OFFSET; ++ break; ++ ++ case 2: ++ *reg = RK3528_SMT_GPIO2_OFFSET; ++ break; ++ ++ case 3: ++ *reg = RK3528_SMT_GPIO3_OFFSET; ++ break; ++ ++ case 4: ++ *reg = RK3528_SMT_GPIO4_OFFSET; ++ break; ++ ++ default: ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ break; ++ } ++ ++ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3528_SMT_PINS_PER_REG; ++ *bit *= RK3528_SMT_BITS_PER_PIN; ++ return 0; ++} ++ + #define RK3568_DRV_PMU_OFFSET 0x70 + #define RK3568_DRV_GRF_OFFSET 0x200 + #define RK3568_DRV_BITS_PER_PIN 8 +@@ -2495,6 +2639,10 @@ static int rockchip_set_drive_perpin(str + rmask_bits = RK3588_DRV_BITS_PER_PIN; + ret = strength; + goto config; ++ } else if (ctrl->type == RK3528) { ++ rmask_bits = RK3528_DRV_BITS_PER_PIN; ++ ret = (1 << (strength + 1)) - 1; ++ goto config; + } else if (ctrl->type == RK3568) { + rmask_bits = RK3568_DRV_BITS_PER_PIN; + ret = (1 << (strength + 1)) - 1; +@@ -2639,6 +2787,7 @@ static int rockchip_get_pull(struct rock + case RK3328: + case RK3368: + case RK3399: ++ case RK3528: + case RK3568: + case RK3576: + case RK3588: +@@ -2699,6 +2848,7 @@ static int rockchip_set_pull(struct rock + case RK3328: + case RK3368: + case RK3399: ++ case RK3528: + case RK3568: + case RK3576: + case RK3588: +@@ -2965,6 +3115,7 @@ static bool rockchip_pinconf_pull_valid( + case RK3328: + case RK3368: + case RK3399: ++ case RK3528: + case RK3568: + case RK3576: + case RK3588: +@@ -4084,6 +4235,49 @@ static struct rockchip_pin_ctrl rk3399_p + .drv_calc_reg = rk3399_calc_drv_reg_and_bit, + }; + ++static struct rockchip_pin_bank rk3528_pin_banks[] = { ++ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0, 0, 0, 0), ++ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0x20020, 0x20028, 0x20030, 0x20038), ++ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0x30040, 0, 0, 0), ++ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0x20060, 0x20068, 0x20070, 0), ++ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0x10080, 0x10088, 0x10090, 0x10098), ++}; ++ ++static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = { ++ .pin_banks = rk3528_pin_banks, ++ .nr_banks = ARRAY_SIZE(rk3528_pin_banks), ++ .label = "RK3528-GPIO", ++ .type = RK3528, ++ .pull_calc_reg = rk3528_calc_pull_reg_and_bit, ++ .drv_calc_reg = rk3528_calc_drv_reg_and_bit, ++ .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit, ++}; ++ + static struct rockchip_pin_bank rk3568_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, +@@ -4208,6 +4402,8 @@ static const struct of_device_id rockchi + .data = &rk3368_pin_ctrl }, + { .compatible = "rockchip,rk3399-pinctrl", + .data = &rk3399_pin_ctrl }, ++ { .compatible = "rockchip,rk3528-pinctrl", ++ .data = &rk3528_pin_ctrl }, + { .compatible = "rockchip,rk3568-pinctrl", + .data = &rk3568_pin_ctrl }, + { .compatible = "rockchip,rk3576-pinctrl", +--- a/drivers/pinctrl/pinctrl-rockchip.h ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type { + RK3328, + RK3368, + RK3399, ++ RK3528, + RK3568, + RK3576, + RK3588, diff --git a/target/linux/rockchip/patches-6.12/302-thermal-rockchip-add-support-for-rk3528.patch b/target/linux/rockchip/patches-6.12/302-thermal-rockchip-add-support-for-rk3528.patch new file mode 100644 index 00000000000000..600229e78fbac9 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/302-thermal-rockchip-add-support-for-rk3528.patch @@ -0,0 +1,191 @@ +From 1e244fb37e21ce92a32b203cb030510bc3b42d29 Mon Sep 17 00:00:00 2001 +From: Shaohan Yao +Date: Fri, 9 Sep 2022 14:34:08 +0800 +Subject: [PATCH] thermal: rockchip: Support the rk3528 SoC in thermal driver + +There are one Temperature Sensor on rk3528, channel 0 is for chip. + +Signed-off-by: Shaohan Yao +Change-Id: Ib5bbb81615fe9fab80f26cdd2098cfb56746ca15 +--- + drivers/thermal/rockchip_thermal.c | 107 +++++++++++++++++++++++++++++ + 1 file changed, 107 insertions(+) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -185,6 +185,8 @@ struct rockchip_thermal_data { + #define TSADCV2_AUTO_PERIOD_HT 0x6c + #define TSADCV3_AUTO_PERIOD 0x154 + #define TSADCV3_AUTO_PERIOD_HT 0x158 ++#define TSADCV9_Q_MAX 0x210 ++#define TSADCV9_FLOW_CON 0x218 + + #define TSADCV2_AUTO_EN BIT(0) + #define TSADCV2_AUTO_EN_MASK BIT(16) +@@ -195,6 +197,7 @@ struct rockchip_thermal_data { + #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) + + #define TSADCV3_AUTO_Q_SEL_EN BIT(1) ++#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17) + + #define TSADCV2_INT_SRC_EN(chn) BIT(chn) + #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) +@@ -208,9 +211,12 @@ struct rockchip_thermal_data { + #define TSADCV2_DATA_MASK 0xfff + #define TSADCV3_DATA_MASK 0x3ff + #define TSADCV4_DATA_MASK 0x1ff ++#define TSADCV5_DATA_MASK 0x7ff + + #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 + #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 ++#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c ++#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 + #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ + #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ + #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ +@@ -220,6 +226,9 @@ struct rockchip_thermal_data { + #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ + #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ + #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ ++#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */ ++#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ ++#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ + + #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ + #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ +@@ -230,6 +239,8 @@ struct rockchip_thermal_data { + + #define PX30_GRF_SOC_CON2 0x0408 + ++#define RK3528_GRF_TSADC_CON 0x40030 ++ + #define RK3568_GRF_TSADC_CON 0x0600 + #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) + #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) +@@ -497,6 +508,45 @@ static const struct tsadc_table rk3399_c + {TSADCV3_DATA_MASK, 125000}, + }; + ++static const struct tsadc_table rk3528_code_table[] = { ++ {0, -40000}, ++ {1419, -40000}, ++ {1427, -35000}, ++ {1435, -30000}, ++ {1443, -25000}, ++ {1452, -20000}, ++ {1460, -15000}, ++ {1468, -10000}, ++ {1477, -5000}, ++ {1486, 0}, ++ {1494, 5000}, ++ {1502, 10000}, ++ {1510, 15000}, ++ {1519, 20000}, ++ {1527, 25000}, ++ {1535, 30000}, ++ {1544, 35000}, ++ {1552, 40000}, ++ {1561, 45000}, ++ {1569, 50000}, ++ {1578, 55000}, ++ {1586, 60000}, ++ {1594, 65000}, ++ {1603, 70000}, ++ {1612, 75000}, ++ {1620, 80000}, ++ {1628, 85000}, ++ {1637, 90000}, ++ {1646, 95000}, ++ {1654, 100000}, ++ {1662, 105000}, ++ {1671, 110000}, ++ {1679, 115000}, ++ {1688, 120000}, ++ {1696, 125000}, ++ {TSADCV5_DATA_MASK, 125000}, ++}; ++ + static const struct tsadc_table rk3568_code_table[] = { + {0, -40000}, + {1584, -40000}, +@@ -834,6 +884,37 @@ static void rk_tsadcv8_initialize(struct + regs + TSADCV2_AUTO_CON); + } + ++static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs, ++ enum tshut_polarity tshut_polarity) ++{ ++ writel_relaxed(TSADCV7_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); ++ writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME, ++ regs + TSADCV3_AUTO_PERIOD_HT); ++ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, ++ regs + TSADCV3_HIGHT_INT_DEBOUNCE); ++ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, ++ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); ++ writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV9_Q_MAX); ++ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, ++ regs + TSADCV2_AUTO_CON); ++ if (tshut_polarity == TSHUT_HIGH_ACTIVE) ++ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | ++ TSADCV2_AUTO_TSHUT_POLARITY_MASK, ++ regs + TSADCV2_AUTO_CON); ++ else ++ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, ++ regs + TSADCV2_AUTO_CON); ++ ++ if (!IS_ERR(grf)) { ++ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); ++ udelay(15); ++ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); ++ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); ++ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); ++ usleep_range(100, 200); ++ } ++} ++ + static void rk_tsadcv2_irq_ack(void __iomem *regs) + { + u32 val; +@@ -1258,6 +1339,31 @@ static const struct rockchip_tsadc_chip + }, + }; + ++static const struct rockchip_tsadc_chip rk3528_tsadc_data = { ++ /* cpu, gpu */ ++ .chn_offset = 0, ++ .chn_num = 1, /* one channels for tsadc */ ++ ++ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ ++ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ ++ .tshut_temp = 95000, ++ ++ .initialize = rk_tsadcv11_initialize, ++ .irq_ack = rk_tsadcv4_irq_ack, ++ .control = rk_tsadcv4_control, ++ .get_temp = rk_tsadcv4_get_temp, ++ .set_alarm_temp = rk_tsadcv3_alarm_temp, ++ .set_tshut_temp = rk_tsadcv3_tshut_temp, ++ .set_tshut_mode = rk_tsadcv3_tshut_mode, ++ ++ .table = { ++ .id = rk3528_code_table, ++ .length = ARRAY_SIZE(rk3528_code_table), ++ .data_mask = TSADCV2_DATA_MASK, ++ .mode = ADC_INCREMENT, ++ }, ++}; ++ + static const struct rockchip_tsadc_chip rk3568_tsadc_data = { + /* cpu, gpu */ + .chn_offset = 0, +@@ -1338,6 +1444,10 @@ static const struct of_device_id of_rock + .data = (void *)&rk3399_tsadc_data, + }, + { ++ .compatible = "rockchip,rk3528-tsadc", ++ .data = (void *)&rk3528_tsadc_data, ++ }, ++ { + .compatible = "rockchip,rk3568-tsadc", + .data = (void *)&rk3568_tsadc_data, + }, diff --git a/target/linux/rockchip/patches-6.12/303-soc-rockchip-power-domain-Add-always-on.patch b/target/linux/rockchip/patches-6.12/303-soc-rockchip-power-domain-Add-always-on.patch new file mode 100644 index 00000000000000..6451153900c444 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/303-soc-rockchip-power-domain-Add-always-on.patch @@ -0,0 +1,61 @@ +From 54d4b6b3014f3122a2235533e6511b0d6ca2cd45 Mon Sep 17 00:00:00 2001 +From: Finley Xiao +Date: Wed, 12 Oct 2022 19:25:38 +0800 +Subject: [PATCH] soc: rockchip: power-domain: Add always on configuration for + power domain + +Signed-off-by: Finley Xiao +Change-Id: Ic57f7f3a564f7d71b680e3c435d0460474b5a4a0 +--- + drivers/pmdomain/rockchip/pm-domains.c | 41 +++++++++++++++++++++++-------- + 1 file changed, 31 insertions(+), 10 deletions(-) + +--- a/drivers/pmdomain/rockchip/pm-domains.c ++++ b/drivers/pmdomain/rockchip/pm-domains.c +@@ -49,6 +49,7 @@ struct rockchip_domain_info { + int clk_ungate_mask; + int mem_status_mask; + int repair_status_mask; ++ bool always_on; + u32 pwr_offset; + u32 mem_offset; + u32 req_offset; +@@ -662,6 +663,26 @@ static void rockchip_pd_detach_dev(struc + pm_clk_destroy(dev); + } + ++static int rockchip_pd_add_alwasy_on_flag(struct rockchip_pm_domain *pd) ++{ ++ int error; ++ ++ if (pd->genpd.flags & GENPD_FLAG_ALWAYS_ON) ++ return 0; ++ pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON; ++ if (!rockchip_pmu_domain_is_on(pd)) { ++ error = rockchip_pd_power(pd, true); ++ if (error) { ++ dev_err(pd->pmu->dev, ++ "failed to power on domain '%s': %d\n", ++ pd->genpd.name, error); ++ return error; ++ } ++ } ++ ++ return 0; ++} ++ + static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, + struct device_node *node) + { +@@ -779,6 +800,11 @@ static int rockchip_pm_add_one_domain(st + pd->genpd.flags = GENPD_FLAG_PM_CLK; + if (pd_info->active_wakeup) + pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; ++ if (pd_info->always_on) { ++ error = rockchip_pd_add_alwasy_on_flag(pd); ++ if (error) ++ goto err_unprepare_clocks; ++ } + pm_genpd_init(&pd->genpd, NULL, + !rockchip_pmu_domain_is_on(pd) || + (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); diff --git a/target/linux/rockchip/patches-6.12/304-soc-rockchip-power-domain-add-rk3528-support.patch b/target/linux/rockchip/patches-6.12/304-soc-rockchip-power-domain-add-rk3528-support.patch new file mode 100644 index 00000000000000..568d012784fc35 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/304-soc-rockchip-power-domain-add-rk3528-support.patch @@ -0,0 +1,103 @@ +From 2ed777fcd035089bd7996bfa09c023521ecf0e24 Mon Sep 17 00:00:00 2001 +From: Finley Xiao +Date: Fri, 30 Sep 2022 20:11:50 +0800 +Subject: [PATCH] soc: rockchip: power-domain: add power domain support for + rk3528 + +This driver is modified to support RK3528 SoCs. + +Signed-off-by: Finley Xiao +Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612 +--- + drivers/pmdomain/rockchip/pm-domains.c | 47 +++++++++++++++++++++++++++++++ + 1 file changed, 47 insertions(+) + +--- a/drivers/pmdomain/rockchip/pm-domains.c ++++ b/drivers/pmdomain/rockchip/pm-domains.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -130,6 +131,20 @@ struct rockchip_pmu { + .active_wakeup = wakeup, \ + } + ++#define DOMAIN_M_A(_name, pwr, status, req, idle, ack, always, wakeup) \ ++{ \ ++ .name = _name, \ ++ .pwr_w_mask = (pwr) << 16, \ ++ .pwr_mask = (pwr), \ ++ .status_mask = (status), \ ++ .req_w_mask = (req) << 16, \ ++ .req_mask = (req), \ ++ .idle_mask = (idle), \ ++ .ack_mask = (ack), \ ++ .always_on = always, \ ++ .active_wakeup = wakeup, \ ++} ++ + #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \ + { \ + .name = _name, \ +@@ -195,6 +210,9 @@ struct rockchip_pmu { + #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) + ++#define DOMAIN_RK3528(name, pwr, req, always, wakeup) \ ++ DOMAIN_M_A(name, pwr, pwr, req, req, req, always, wakeup) ++ + #define DOMAIN_RK3568(name, pwr, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) + +@@ -1156,6 +1174,18 @@ static const struct rockchip_domain_info + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), + }; + ++static const struct rockchip_domain_info rk3528_pm_domains[] = { ++ [RK3528_PD_PMU] = DOMAIN_RK3528("pmu", 0, BIT(0), true, false), ++ [RK3528_PD_BUS] = DOMAIN_RK3528("bus", 0, BIT(1), true, false), ++ [RK3528_PD_DDR] = DOMAIN_RK3528("ddr", 0, BIT(2), true, false), ++ [RK3528_PD_MSCH] = DOMAIN_RK3528("msch", 0, BIT(3), true, false), ++ [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4), true, false), ++ [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5), true, false), ++ [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6), true, false), ++ [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7), true, false), ++ [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8), true, false), ++}; ++ + static const struct rockchip_domain_info rk3568_pm_domains[] = { + [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), + [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), +@@ -1357,6 +1387,17 @@ static const struct rockchip_pmu_info rk + .domain_info = rk3399_pm_domains, + }; + ++static const struct rockchip_pmu_info rk3528_pmu = { ++ .pwr_offset = 0x1210, ++ .status_offset = 0x1230, ++ .req_offset = 0x1110, ++ .idle_offset = 0x1128, ++ .ack_offset = 0x1120, ++ ++ .num_domains = ARRAY_SIZE(rk3528_pm_domains), ++ .domain_info = rk3528_pm_domains, ++}; ++ + static const struct rockchip_pmu_info rk3568_pmu = { + .pwr_offset = 0xa0, + .status_offset = 0x98, +@@ -1456,6 +1497,10 @@ static const struct of_device_id rockchi + .data = (void *)&rk3399_pmu, + }, + { ++ .compatible = "rockchip,rk3528-power-controller", ++ .data = (void *)&rk3528_pmu, ++ }, ++ { + .compatible = "rockchip,rk3568-power-controller", + .data = (void *)&rk3568_pmu, + }, diff --git a/target/linux/rockchip/patches-6.12/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch b/target/linux/rockchip/patches-6.12/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch new file mode 100644 index 00000000000000..a61b532b7ceee6 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch @@ -0,0 +1,179 @@ +From 16f512f1e10375dc48aa6c26cedeb7079aba01de Mon Sep 17 00:00:00 2001 +From: Joseph Chen +Date: Sat, 13 Aug 2022 01:15:20 +0000 +Subject: [PATCH] clk: rockchip: Add clock controller for the RK3528 + +Add the clock tree definition for the new RK3528 SoC. + +gmac1 clocks are all controlled by GRF, but CRU helps to abstract +these two clocks for gmac1 since the clock source is from CRU. + +The io-in clocks are module phy output clock, gating child +clocks by disabling phy output but not CRU gate. + +Add gmac0 clocks. +They are all orphans if clk_gmac0_io_i is not registered by +GMAC driver. But it's fine that GMAC driver only get it but +not to set/get rate. + +Add CLK_SET_RATE_PARENT for mclk_sai_i2s0/1. +Allowed to change parent rate. + +Add CLK_SET_RATE_NO_REPARENT for dclk_vop0. +dclk_vop0 is often used for HDMI, it prefers parent clock from +clk_hdmiphy_pixel_io for better clock quality and any rate. +It assigns clk_hdmiphy_pixel_io as parent in dts and hope not to +change parent any more. + +Add CLK_SET_RATE_PARENT for aclk_gpu. +Allow aclk_gpu and aclk_gpu_mali to change parent rate. + +Add CLK_SET_RATE_PARENT for aclk_rkvdec_pvtmux_root. +Allow aclk_rkvdec_pvtmux_root and aclk_rkvdec to change parent rate. + +set aclk_m_core = core_clk/2. +aclk_m_core signoff is 550M, but we set div=2 for better +performance. + +Add CLK_IS_CRITICAL for clk_32k. +Mainly for pvtpll during reboot stage. + +Add CLK_IS_CRITICAL for all IOC clocks. +IOC doesn't share clock with GRF. The iomux can't be changed if they +are disabled. + +Disable aclk_{vpu,vpu_l,vo}_root rate change +They are all shared by multiple modules, disable rate change +by modules. + +Don't register clk_uart_jtag +It's for force jtag uart delay counter. It must be open +for box product without tf card but with uart0. + +Signed-off-by: Joseph Chen +Signed-off-by: Elaine Zhang +Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224 +--- + drivers/clk/rockchip/Kconfig | 7 + + drivers/clk/rockchip/Makefile | 1 + + drivers/clk/rockchip/clk-rk3528.c | 1187 +++++++++++++++++++++++++++++ + drivers/clk/rockchip/clk.h | 28 + + 4 files changed, 1223 insertions(+) + create mode 100644 drivers/clk/rockchip/clk-rk3528.c + +--- a/drivers/clk/rockchip/Kconfig ++++ b/drivers/clk/rockchip/Kconfig +@@ -93,6 +93,13 @@ config CLK_RK3399 + help + Build the driver for RK3399 Clock Driver. + ++config CLK_RK3528 ++ bool "Rockchip RK3528 clock controller support" ++ depends on ARM64 || COMPILE_TEST ++ default y ++ help ++ Build the driver for RK3528 Clock Driver. ++ + config CLK_RK3568 + bool "Rockchip RK3568 clock controller support" + depends on ARM64 || COMPILE_TEST +--- a/drivers/clk/rockchip/Makefile ++++ b/drivers/clk/rockchip/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-r + obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o + obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o + obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o ++obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o + obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o + obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o + obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o +--- a/drivers/clk/rockchip/clk.c ++++ b/drivers/clk/rockchip/clk.c +@@ -527,6 +527,14 @@ void rockchip_clk_register_branches(stru + ctx->reg_base + list->gate_offset, + list->gate_shift, list->gate_flags, &ctx->lock); + break; ++ case branch_gate_no_set_rate: ++ flags &= ~CLK_SET_RATE_PARENT; ++ ++ clk = clk_register_gate(NULL, list->name, ++ list->parent_names[0], flags, ++ ctx->reg_base + list->gate_offset, ++ list->gate_shift, list->gate_flags, &ctx->lock); ++ break; + case branch_composite: + clk = rockchip_clk_register_branch(list->name, + list->parent_names, list->num_parents, +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -207,6 +207,34 @@ struct clk; + #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) + #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) + ++#define RK3528_PMU_CRU_BASE 0x10000 ++#define RK3528_PCIE_CRU_BASE 0x20000 ++#define RK3528_DDRPHY_CRU_BASE 0x28000 ++#define RK3528_VPU_GRF_BASE 0x40000 ++#define RK3528_VO_GRF_BASE 0x60000 ++#define RK3528_SDMMC_CON0 (RK3528_VO_GRF_BASE + 0x24) ++#define RK3528_SDMMC_CON1 (RK3528_VO_GRF_BASE + 0x28) ++#define RK3528_SDIO0_CON0 (RK3528_VPU_GRF_BASE + 0x4) ++#define RK3528_SDIO0_CON1 (RK3528_VPU_GRF_BASE + 0x8) ++#define RK3528_SDIO1_CON0 (RK3528_VPU_GRF_BASE + 0xc) ++#define RK3528_SDIO1_CON1 (RK3528_VPU_GRF_BASE + 0x10) ++#define RK3528_PLL_CON(x) RK2928_PLL_CON(x) ++#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) ++#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) ++#define RK3528_MODE_CON 0x280 ++#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) ++#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) ++#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) ++#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) ++#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) ++#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) ++#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE) ++#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE) ++#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) ++#define RK3528_GLB_CNT_TH 0xc00 ++#define RK3528_GLB_SRST_FST 0xc08 ++#define RK3528_GLB_SRST_SND 0xc0c ++ + #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) + #define RK3568_MODE_CON0 0xc0 + #define RK3568_MISC_CON0 0xc4 +@@ -461,6 +489,7 @@ struct rockchip_pll_clock { + }; + + #define ROCKCHIP_PLL_SYNC_RATE BIT(0) ++#define ROCKCHIP_PLL_FIXED_MODE BIT(1) + + #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ + _lshift, _pflags, _rtable) \ +@@ -569,6 +598,7 @@ enum rockchip_clk_branch_type { + branch_muxgrf, + branch_divider, + branch_fraction_divider, ++ branch_gate_no_set_rate, + branch_gate, + branch_mmc, + branch_inverter, +@@ -889,6 +919,19 @@ struct rockchip_clk_branch { + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ ++ .flags = f, \ ++ .gate_offset = o, \ ++ .gate_shift = b, \ ++ .gate_flags = gf, \ ++ } ++ ++#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf) \ ++ { \ ++ .id = _id, \ ++ .branch_type = branch_gate_no_set_rate, \ ++ .name = cname, \ ++ .parent_names = (const char *[]){ pname }, \ ++ .num_parents = 1, \ + .flags = f, \ + .gate_offset = o, \ + .gate_shift = b, \ diff --git a/target/linux/rockchip/patches-6.12/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch b/target/linux/rockchip/patches-6.12/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch new file mode 100644 index 00000000000000..45aeb54cd42d62 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch @@ -0,0 +1,227 @@ +From 61c0ac431798861b0696ccc549138b2eec8a4766 Mon Sep 17 00:00:00 2001 +From: David Wu +Date: Sat, 24 Sep 2022 18:29:52 +0800 +Subject: [PATCH] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3528 + +Add constants and callback functions for the dwmac on RK3528 Soc. +As can be seen, the base structure is the same. In addition, there +is an internal phy inside with Gmac0. + +Signed-off-by: David Wu +Change-Id: I8a69a1239ed3ae91bfe44c96287210da758f9cf9 +--- + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 179 +++++++++++++++++- + 1 file changed, 173 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -1140,6 +1140,201 @@ static const struct rk_gmac_ops rk3399_o + .set_rmii_speed = rk3399_set_rmii_speed, + }; + ++#define RK3528_VO_GRF_GMAC_CON 0X60018 ++#define RK3528_VPU_GRF_GMAC_CON5 0X40018 ++#define RK3528_VPU_GRF_GMAC_CON6 0X4001c ++ ++#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) ++#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) ++#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) ++#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) ++ ++#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) ++#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) ++ ++#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) ++#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) ++#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) ++ ++#define RK3528_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(12) ++#define RK3528_GMAC1_CLK_SELET_IO GRF_BIT(12) ++ ++#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) ++#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) ++#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) ++#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) ++ ++#define RK3528_GMAC1_CLK_RGMII_DIV1 \ ++ (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) ++#define RK3528_GMAC1_CLK_RGMII_DIV5 \ ++ (GRF_BIT(11) | GRF_BIT(10)) ++#define RK3528_GMAC1_CLK_RGMII_DIV50 \ ++ (GRF_BIT(11) | GRF_CLR_BIT(10)) ++ ++#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) ++#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) ++#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) ++#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) ++ ++#define RK3528_VO_GRF_MACPHY_CON0 0X6001c ++#define RK3528_VO_GRF_MACPHY_CON1 0X60020 ++ ++static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, ++ int tx_delay, int rx_delay) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ ++ if (IS_ERR(bsp_priv->grf)) { ++ dev_err(dev, "Missing rockchip,grf property\n"); ++ return; ++ } ++ ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ RK3528_GMAC1_PHY_INTF_SEL_RGMII); ++ ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | ++ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); ++ ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, ++ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | ++ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); ++} ++ ++static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ unsigned int id = bsp_priv->id; ++ ++ if (IS_ERR(bsp_priv->grf)) { ++ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); ++ return; ++ } ++ ++ if (id == 1) ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ RK3528_GMAC1_PHY_INTF_SEL_RMII); ++ else ++ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, ++ RK3528_GMAC0_PHY_INTF_SEL_RMII); ++} ++ ++static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ unsigned int val = 0; ++ ++ switch (speed) { ++ case 10: ++ val = RK3528_GMAC1_CLK_RGMII_DIV50; ++ break; ++ case 100: ++ val = RK3528_GMAC1_CLK_RGMII_DIV5; ++ break; ++ case 1000: ++ val = RK3528_GMAC1_CLK_RGMII_DIV1; ++ break; ++ default: ++ goto err; ++ } ++ ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); ++ return; ++err: ++ dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed); ++} ++ ++static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ unsigned int val, offset, id = bsp_priv->id; ++ ++ switch (speed) { ++ case 10: ++ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 : ++ RK3528_GMAC0_CLK_RMII_DIV20; ++ break; ++ case 100: ++ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 : ++ RK3528_GMAC0_CLK_RMII_DIV2; ++ break; ++ default: ++ goto err; ++ } ++ ++ offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON; ++ regmap_write(bsp_priv->grf, offset, val); ++ ++ return; ++err: ++ dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed); ++} ++ ++static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, ++ bool input, bool enable) ++{ ++ unsigned int value, id = bsp_priv->id; ++ ++ if (id == 1) { ++ value = input ? RK3528_GMAC1_CLK_SELET_IO : ++ RK3528_GMAC1_CLK_SELET_CRU; ++ value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : ++ RK3528_GMAC1_CLK_RMII_GATE; ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value); ++ } else { ++ value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : ++ RK3528_GMAC0_CLK_RMII_GATE; ++ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value); ++ } ++} ++ ++/* Integrated FEPHY */ ++#define RK_FEPHY_SHUTDOWN GRF_BIT(1) ++#define RK_FEPHY_POWERUP GRF_CLR_BIT(1) ++#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) ++#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) ++#define RK_FEPHY_PHY_ID GRF_BIT(11) ++ ++#define RK_FEPHY_BGS HIWORD_UPDATE(0x0, 0xf, 0) ++ ++static void rk3528_integrated_sphy_power(struct rk_priv_data *priv) ++{ ++ struct device *dev = &priv->pdev->dev; ++ ++ if (IS_ERR(priv->grf) || !priv->phy_reset) { ++ dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n", ++ __func__); ++ return; ++ } ++ ++ unsigned int bgs = RK_FEPHY_BGS; ++ ++ reset_control_assert(priv->phy_reset); ++ udelay(20); ++ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0, ++ RK_FEPHY_POWERUP | ++ RK_FEPHY_INTERNAL_RMII_SEL | ++ RK_FEPHY_24M_CLK_SEL | ++ RK_FEPHY_PHY_ID); ++ ++ /*if (priv->otp_data > 0) ++ bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);*/ ++ ++ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON1, bgs); ++ usleep_range(10 * 1000, 12 * 1000); ++ reset_control_deassert(priv->phy_reset); ++ usleep_range(50 * 1000, 60 * 1000); ++} ++ ++static const struct rk_gmac_ops rk3528_ops = { ++ .set_to_rgmii = rk3528_set_to_rgmii, ++ .set_to_rmii = rk3528_set_to_rmii, ++ .set_rgmii_speed = rk3528_set_rgmii_speed, ++ .set_rmii_speed = rk3528_set_rmii_speed, ++ .set_clock_selection = rk3528_set_clock_selection, ++ .integrated_phy_powerup = rk3528_integrated_sphy_power, ++}; ++ + #define RK3568_GRF_GMAC0_CON0 0x0380 + #define RK3568_GRF_GMAC0_CON1 0x0384 + #define RK3568_GRF_GMAC1_CON0 0x0388 +@@ -2255,6 +2450,7 @@ static const struct of_device_id rk_gmac + { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, + { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, + { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, ++ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, + { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, + { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, + { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, diff --git a/target/linux/rockchip/patches-6.12/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch b/target/linux/rockchip/patches-6.12/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch new file mode 100644 index 00000000000000..9f2d0d25e78fe5 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch @@ -0,0 +1,67 @@ +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -1905,6 +1905,56 @@ static const struct rockchip_usb2phy_cfg + { /* sentinel */ } + }; + ++static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { ++ { ++ .reg = 0xffdf0000, ++ .num_ports = 2, ++ .clkout_ctl = { 0x041c, 7, 2, 0, 0x27 }, ++ .port_cfgs = { ++ [USB2PHY_PORT_OTG] = { ++ .phy_sus = { 0x6004c, 15, 0, 0, 0x1d1 }, ++ .bvalid_det_en = { 0x60074, 3, 2, 0, 3 }, ++ .bvalid_det_st = { 0x60078, 3, 2, 0, 3 }, ++ .bvalid_det_clr = { 0x6007c, 3, 2, 0, 3 }, ++ .idfall_det_en = { 0x60074, 5, 5, 0, 1 }, ++ .idfall_det_st = { 0x60078, 5, 5, 0, 1 }, ++ .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 }, ++ .idrise_det_en = { 0x60074, 4, 4, 0, 1 }, ++ .idrise_det_st = { 0x60078, 4, 4, 0, 1 }, ++ .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 }, ++ .ls_det_en = { 0x60074, 0, 0, 0, 1 }, ++ .ls_det_st = { 0x60078, 0, 0, 0, 1 }, ++ .ls_det_clr = { 0x6007c, 0, 0, 0, 1 }, ++ .utmi_avalid = { 0x6006c, 1, 1, 0, 1 }, ++ .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 }, ++ .utmi_id = { 0x6006c, 6, 6, 0, 1 }, ++ .utmi_ls = { 0x6006c, 5, 4, 0, 1 }, ++ }, ++ [USB2PHY_PORT_HOST] = { ++ .phy_sus = { 0x6005c, 15, 0, 0x1d2, 0x1d1 }, ++ .ls_det_en = { 0x60090, 0, 0, 0, 1 }, ++ .ls_det_st = { 0x60094, 0, 0, 0, 1 }, ++ .ls_det_clr = { 0x60098, 0, 0, 0, 1 }, ++ .utmi_ls = { 0x6006c, 13, 12, 0, 1 }, ++ .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 } ++ } ++ }, ++ .chg_det = { ++ .opmode = { 0x6004c, 3, 0, 5, 1 }, ++ .cp_det = { 0x6006c, 19, 19, 0, 1 }, ++ .dcp_det = { 0x6006c, 18, 18, 0, 1 }, ++ .dp_det = { 0x6006c, 20, 20, 0, 1 }, ++ .idm_sink_en = { 0x60058, 1, 1, 0, 1 }, ++ .idp_sink_en = { 0x60058, 0, 0, 0, 1 }, ++ .idp_src_en = { 0x60058, 2, 2, 0, 1 }, ++ .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 }, ++ .vdm_src_en = { 0x60058, 5, 5, 0, 1 }, ++ .vdp_src_en = { 0x60058, 4, 4, 0, 1 }, ++ }, ++ }, ++ { /* sentinel */ } ++}; ++ + static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { + { + .reg = 0xfe8a0000, +@@ -2223,6 +2273,7 @@ static const struct of_device_id rockchi + { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, + { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, + { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, ++ { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs }, + { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, + { .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs }, + { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs }, diff --git a/target/linux/rockchip/patches-6.12/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch b/target/linux/rockchip/patches-6.12/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch new file mode 100644 index 00000000000000..8aca368f32a997 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch @@ -0,0 +1,170 @@ +From 432666b59bdbef2c386e92dd88be4206203ff8ac Mon Sep 17 00:00:00 2001 +From: Jon Lin +Date: Sat, 8 Oct 2022 15:48:37 +0800 +Subject: [PATCH] phy: rockchip: naneng-combphy: add support rk3528 + +1. The layout of controller registers has changed, remove legacy config; +2. Using the default value for grf register; +3. sync to use rk3568 parameter for phy PLL, signal test pass +4. Add 24MHz refclk for rk3528 PCIe, Enable the counting clock of the +rterm detect by setting tx_trim[14] bit for rx detecting. +5. set SSC modulation frequency to 31.5KHz + +Change-Id: I45742c416d452037e61b7a7b8765269931d56402 +Signed-off-by: Jon Lin +Signed-off-by: Jianwei Zheng +--- + .../rockchip/phy-rockchip-naneng-combphy.c | 139 +++++++++++++++++- + 1 file changed, 138 insertions(+), 1 deletion(-) + +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -97,7 +97,7 @@ + struct rockchip_combphy_priv; + + struct combphy_reg { +- u16 offset; ++ u32 offset; + u16 bitend; + u16 bitstart; + u16 disable; +@@ -107,6 +107,7 @@ struct combphy_reg { + struct rockchip_combphy_grfcfg { + struct combphy_reg pcie_mode_set; + struct combphy_reg usb_mode_set; ++ struct combphy_reg u3otg0_port_en; + struct combphy_reg sgmii_mode_set; + struct combphy_reg qsgmii_mode_set; + struct combphy_reg pipe_rxterm_set; +@@ -393,6 +394,120 @@ static int rockchip_combphy_probe(struct + return PTR_ERR_OR_ZERO(phy_provider); + } + ++static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) ++{ ++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; ++ unsigned long rate; ++ u32 val; ++ ++ switch (priv->type) { ++ case PHY_TYPE_PCIE: ++ /* Set SSC downward spread spectrum. */ ++ val = readl(priv->mmio + 0x18); ++ val &= ~GENMASK(5, 4); ++ val |= 0x01 << 4; ++ writel(val, priv->mmio + 0x18); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); ++ break; ++ ++ case PHY_TYPE_USB3: ++ /* Set SSC downward spread spectrum. */ ++ val = readl(priv->mmio + 0x18); ++ val &= ~GENMASK(5, 4); ++ val |= 0x01 << 4; ++ writel(val, priv->mmio + 0x18); ++ ++ /* Enable adaptive CTLE for USB3.0 Rx. */ ++ val = readl(priv->mmio + 0x200); ++ val &= ~GENMASK(17, 17); ++ val |= 0x01 << 17; ++ writel(val, priv->mmio + 0x200); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); ++ break; ++ ++ default: ++ dev_err(priv->dev, "incompatible PHY type\n"); ++ return -EINVAL; ++ } ++ ++ rate = clk_get_rate(priv->refclk); ++ ++ switch (rate) { ++ case REF_CLOCK_24MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); ++ if (priv->type == PHY_TYPE_USB3) { ++ /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz. */ ++ val = readl(priv->mmio + 0x100); ++ val &= ~GENMASK(10, 0); ++ val |= 0x17d; ++ writel(val, priv->mmio + 0x100); ++ } else if (priv->type == PHY_TYPE_PCIE) { ++ /* tx_trim[14]=1, Enable the counting clock of the rterm detect */ ++ val = readl(priv->mmio + 0x218); ++ val |= (1 << 14); ++ writel(val, priv->mmio + 0x218); ++ } ++ break; ++ ++ case REF_CLOCK_100MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); ++ if (priv->type == PHY_TYPE_PCIE) { ++ /* PLL KVCO tuning fine. */ ++ val = readl(priv->mmio + 0x18); ++ val &= ~(0x7 << 10); ++ val |= 0x2 << 10; ++ writel(val, priv->mmio + 0x18); ++ ++ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ ++ val = readl(priv->mmio + 0x108); ++ val &= ~(0x7f7); ++ val |= 0x4f0; ++ writel(val, priv->mmio + 0x108); ++ } ++ break; ++ ++ default: ++ dev_err(priv->dev, "unsupported rate: %lu\n", rate); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { ++ /* pipe-phy-grf */ ++ .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, ++ .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, ++ .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, ++ .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, ++ .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, ++ .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, ++ .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, ++ .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, ++ .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, ++ .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, ++ .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, ++ .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, ++ .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, ++ .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, ++ .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, ++ .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, ++ /* pipe-grf */ ++ .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, ++}; ++ ++static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { ++ .grfcfg = &rk3528_combphy_grfcfgs, ++ .combphy_cfg = rk3528_combphy_cfg, ++}; ++ + static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) + { + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; +@@ -1047,6 +1162,10 @@ static const struct rockchip_combphy_cfg + + static const struct of_device_id rockchip_combphy_of_match[] = { + { ++ .compatible = "rockchip,rk3528-naneng-combphy", ++ .data = &rk3528_combphy_cfgs, ++ }, ++ { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, diff --git a/target/linux/rockchip/patches-6.12/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch b/target/linux/rockchip/patches-6.12/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch new file mode 100644 index 00000000000000..b6a5ab56839d04 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch @@ -0,0 +1,103 @@ +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -688,19 +688,20 @@ static void dwcmshc_rk3568_set_clock(str + 0x3 << 19; /* post-change delay */ + sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); + +- if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || +- host->mmc->ios.timing == MMC_TIMING_MMC_HS400) ++ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) + txclk_tapnum = priv->txclk_tapnum; + +- if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { ++ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { + txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; + +- extra = DLL_CMDOUT_SRC_CLK_NEG | +- DLL_CMDOUT_EN_SRC_CLK_NEG | +- DWCMSHC_EMMC_DLL_DLYENA | +- DLL_CMDOUT_TAPNUM_90_DEGREES | +- DLL_CMDOUT_TAPNUM_FROM_SW; +- sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); ++ if (priv->devtype != DWCMSHC_RK3568) { ++ extra = DLL_CMDOUT_SRC_CLK_NEG | ++ DLL_CMDOUT_EN_SRC_CLK_NEG | ++ DWCMSHC_EMMC_DLL_DLYENA | ++ DLL_CMDOUT_TAPNUM_90_DEGREES | ++ DLL_CMDOUT_TAPNUM_FROM_SW; ++ sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); ++ } + } + + extra = DWCMSHC_EMMC_DLL_DLYENA | +@@ -741,10 +742,10 @@ static int dwcmshc_rk35xx_init(struct de + if (!priv) + return -ENOMEM; + +- if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc")) +- priv->devtype = DWCMSHC_RK3588; +- else ++ if (of_device_is_compatible(dev->of_node, "rockchip,rk3568-dwcmshc")) + priv->devtype = DWCMSHC_RK3568; ++ else ++ priv->devtype = DWCMSHC_RK3588; + + priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); + if (IS_ERR(priv->reset)) { +@@ -1156,6 +1157,16 @@ static const struct sdhci_ops sdhci_dwcm + .irq = dwcmshc_cqe_irq_handler, + }; + ++static const struct sdhci_ops sdhci_dwcmshc_rk3528_ops = { ++ .set_clock = dwcmshc_rk3568_set_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .set_uhs_signaling = dwcmshc_set_uhs_signaling, ++ .get_max_clock = sdhci_pltfm_clk_get_max_clock, ++ .reset = rk35xx_sdhci_reset, ++ .adma_write_desc = dwcmshc_adma_write_desc, ++ .irq = dwcmshc_cqe_irq_handler, ++}; ++ + static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, +@@ -1218,6 +1229,18 @@ static const struct dwcmshc_pltfm_data s + .postinit = dwcmshc_rk35xx_postinit, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk3528_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_rk3528_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | ++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | ++ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, ++ }, ++ .init = dwcmshc_rk35xx_init, ++ .postinit = dwcmshc_rk35xx_postinit, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_th1520_ops, +@@ -1320,6 +1343,10 @@ static const struct of_device_id sdhci_d + .compatible = "rockchip,rk3568-dwcmshc", + .data = &sdhci_dwcmshc_rk35xx_pdata, + }, ++ { ++ .compatible = "rockchip,rk3528-dwcmshc", ++ .data = &sdhci_dwcmshc_rk3528_pdata, ++ }, + { + .compatible = "snps,dwcmshc-sdhci", + .data = &sdhci_dwcmshc_pdata, +--- a/drivers/pci/controller/dwc/Makefile ++++ b/drivers/pci/controller/dwc/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom- + obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o + obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o + obj-$(CONFIG_PCIE_ROCKCHIP_DW) += pcie-dw-rockchip.o ++obj-$(CONFIG_PCIE_ROCKCHIP_DW) += pcie-dw-rkvendor.o + obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o + obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o + obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o diff --git a/target/linux/rockchip/patches-6.12/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch b/target/linux/rockchip/patches-6.12/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch new file mode 100644 index 00000000000000..428822e457593e --- /dev/null +++ b/target/linux/rockchip/patches-6.12/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch @@ -0,0 +1,118 @@ +From 4ff037c13c1e7ab16362d39a59ebb8fffb929f99 Mon Sep 17 00:00:00 2001 +From: Shawn Lin +Date: Wed, 15 Apr 2020 09:19:09 +0800 +Subject: [PATCH] mmc: dw_mmc-rockchip: add v2 tuning support + +v2 tuning will inherit pre-stage loader's phase +settings for the first time, and do re-tune if +necessary. Re-tune will still try the rough degrees, +for instance, 90, 180, 270, 360 but continue to do the +fine tuning if sample window isn't good enough. + +Change-Id: I593384ee381d09df5b9adfc29a18eb22517b2764 +Signed-off-by: Shawn Lin +--- + drivers/mmc/host/dw_mmc-rockchip.c | 48 ++++++++++++++++++++++++++++++ + 1 file changed, 48 insertions(+) + +--- a/drivers/mmc/host/dw_mmc-rockchip.c ++++ b/drivers/mmc/host/dw_mmc-rockchip.c +@@ -35,6 +35,8 @@ struct dw_mci_rockchip_priv_data { + int default_sample_phase; + int num_phases; + bool internal_phase; ++ int last_degree; ++ bool use_v2_tuning; + }; + + /* +@@ -279,6 +281,58 @@ static void dw_mci_rk3288_set_ios(struct + #define TUNING_ITERATION_TO_PHASE(i, num_phases) \ + (DIV_ROUND_UP((i) * 360, num_phases)) + ++static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode) ++{ ++ struct dw_mci *host = slot->host; ++ struct dw_mci_rockchip_priv_data *priv = host->priv; ++ struct mmc_host *mmc = slot->mmc; ++ u32 degrees[4] = {0, 90, 180, 270}, degree; ++ int i; ++ static bool inherit = true; ++ ++ if (inherit) { ++ inherit = false; ++ i = clk_get_phase(priv->sample_clk) / 90; ++ degree = degrees[i]; ++ goto done; ++ } ++ ++ /* ++ * v2 only support 4 degrees in theory. ++ * First we inherit sample phases from firmware, which should ++ * be able work fine, at least in the first place. ++ * If retune is needed, we search forward to pick the last ++ * one phase from degree list and loop around until we get one. ++ * It's impossible all 4 fixed phase won't be able to work. ++ */ ++ for (i = 0; i < ARRAY_SIZE(degrees); i++) { ++ degree = degrees[i] + priv->last_degree + 90; ++ degree = degree % 360; ++ clk_set_phase(priv->sample_clk, degree); ++ if (mmc_send_tuning(mmc, opcode, NULL)) { ++ /* ++ * Tuning error, the phase is a bad phase, ++ * then try using the calculated best phase. ++ */ ++ dev_info(host->dev, "V2 tuned phase to %d error, try the best phase\n", degree); ++ degree = (degree + 180) % 360; ++ clk_set_phase(priv->sample_clk, degree); ++ if (!mmc_send_tuning(mmc, opcode, NULL)) ++ break; ++ } ++ } ++ ++ if (i == ARRAY_SIZE(degrees)) { ++ dev_warn(host->dev, "V2 All phases bad!"); ++ return -EIO; ++ } ++ ++done: ++ dev_info(host->dev, "V2 Successfully tuned phase to %d\n", degree); ++ priv->last_degree = degree; ++ return 0; ++} ++ + static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) + { + struct dw_mci *host = slot->host; +@@ -303,6 +357,12 @@ static int dw_mci_rk3288_execute_tuning( + return -EIO; + } + ++ if (priv->use_v2_tuning) { ++ if (!dw_mci_v2_execute_tuning(slot, opcode)) ++ return 0; ++ /* Otherwise we continue using fine tuning */ ++ } ++ + ranges = kmalloc_array(priv->num_phases / 2 + 1, + sizeof(*ranges), GFP_KERNEL); + if (!ranges) +@@ -431,6 +491,7 @@ static int dw_mci_common_parse_dt(struct + + static int dw_mci_rk3288_parse_dt(struct dw_mci *host) + { ++ struct device_node *np = host->dev->of_node; + struct dw_mci_rockchip_priv_data *priv; + int err; + +@@ -440,6 +501,9 @@ static int dw_mci_rk3288_parse_dt(struct + + priv = host->priv; + ++ if (of_property_read_bool(np, "rockchip,use-v2-tuning")) ++ priv->use_v2_tuning = true; ++ + priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); + if (IS_ERR(priv->drv_clk)) + dev_dbg(host->dev, "ciu-drive not available\n"); diff --git a/target/linux/rockchip/patches-6.12/801-char-add-support-for-rockchip-hardware-random-number.patch b/target/linux/rockchip/patches-6.12/801-char-add-support-for-rockchip-hardware-random-number.patch new file mode 100644 index 00000000000000..9d35a5925dee52 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/801-char-add-support-for-rockchip-hardware-random-number.patch @@ -0,0 +1,45 @@ +From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001 +From: wevsty +Date: Mon, 24 Aug 2020 02:27:11 +0800 +Subject: [PATCH] char: add support for rockchip hardware random number + generator + +This patch provides hardware random number generator support for all rockchip SOC. + +rockchip-rng.c from https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c + +Signed-off-by: wevsty +--- + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -383,6 +383,19 @@ config HW_RANDOM_STM32 + + If unsure, say N. + ++config HW_RANDOM_ROCKCHIP ++ tristate "Rockchip Random Number Generator support" ++ depends on ARCH_ROCKCHIP ++ default HW_RANDOM ++ help ++ This driver provides kernel-side support for the Random Number ++ Generator hardware found on Rockchip cpus. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called rockchip-rng. ++ ++ If unsure, say Y. ++ + config HW_RANDOM_PIC32 + tristate "Microchip PIC32 Random Number Generator support" + depends on MACH_PIC32 || COMPILE_TEST +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += + obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o + obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o + obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o ++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o + obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o + obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o + obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o diff --git a/target/linux/rockchip/patches-6.12/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-6.12/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch new file mode 100644 index 00000000000000..d91cf97763fc52 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -0,0 +1,26 @@ +From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001 +From: wevsty +Date: Mon, 24 Aug 2020 02:27:11 +0800 +Subject: [PATCH] arm64: dts: rockchip: add hardware random number generator + for RK3328 and RK3399 + +Adding Hardware Random Number Generator Resources to the RK3328 and RK3399. + +Signed-off-by: wevsty +--- + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1127,10 +1127,10 @@ + }; + + rng: rng@fe388000 { +- compatible = "rockchip,rk3568-rng"; ++ compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xfe388000 0x0 0x4000>; + clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; +- clock-names = "core", "ahb"; ++ clock-names = "clk_trng", "hclk_trng"; + resets = <&cru SRST_TRNG_NS>; + status = "disabled"; + }; diff --git a/target/linux/rockchip/patches-6.12/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch b/target/linux/rockchip/patches-6.12/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch new file mode 100644 index 00000000000000..6d19871742edae --- /dev/null +++ b/target/linux/rockchip/patches-6.12/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch @@ -0,0 +1,44 @@ +From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Tue, 19 Nov 2019 13:53:25 +0800 +Subject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc + +Signed-off-by: hmz007 +--- + drivers/devfreq/Kconfig | 18 +- + drivers/devfreq/Makefile | 1 + + drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++ + 3 files changed, 862 insertions(+), 3 deletions(-) + create mode 100644 drivers/devfreq/rk3328_dmc.c + +--- a/drivers/devfreq/Kconfig ++++ b/drivers/devfreq/Kconfig +@@ -129,6 +129,18 @@ config ARM_MEDIATEK_CCI_DEVFREQ + buck voltages and update a proper CCI frequency. Use the notification + to get the regulator status. + ++config ARM_RK3328_DMC_DEVFREQ ++ tristate "ARM RK3328 DMC DEVFREQ Driver" ++ depends on ARCH_ROCKCHIP ++ select DEVFREQ_EVENT_ROCKCHIP_DFI ++ select DEVFREQ_GOV_SIMPLE_ONDEMAND ++ select PM_DEVFREQ_EVENT ++ select PM_OPP ++ help ++ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller). ++ It sets the frequency for the memory controller and reads the usage counts ++ from hardware. ++ + config ARM_RK3399_DMC_DEVFREQ + tristate "ARM RK3399 DMC DEVFREQ Driver" + depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ +--- a/drivers/devfreq/Makefile ++++ b/drivers/devfreq/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += + obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o + obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o + obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o ++obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o + obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o + obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o + obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o diff --git a/target/linux/rockchip/patches-6.12/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch b/target/linux/rockchip/patches-6.12/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch new file mode 100644 index 00000000000000..b4c061019d2571 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch @@ -0,0 +1,210 @@ +From ce6d3614888e6358466f0e84e248177a6bca5258 Mon Sep 17 00:00:00 2001 +From: Tang Yun ping +Date: Thu, 4 May 2017 20:49:58 +0800 +Subject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2 + APIs + +commit 764e893ee82321938fc6f4349e9e7caf06a04410 rockchip. + +Signed-off-by: Tang Yun ping +Signed-off-by: hmz007 +--- + drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++ + drivers/clk/rockchip/clk-rk3328.c | 7 +- + drivers/clk/rockchip/clk.h | 3 +- + include/soc/rockchip/rockchip_sip.h | 11 +++ + 4 files changed, 147 insertions(+), 4 deletions(-) + +--- a/drivers/clk/rockchip/clk-ddr.c ++++ b/drivers/clk/rockchip/clk-ddr.c +@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr + .get_parent = rockchip_ddrclk_get_parent, + }; + ++/* See v4.4/include/dt-bindings/display/rk_fb.h */ ++#define SCREEN_NULL 0 ++#define SCREEN_HDMI 6 ++ ++static inline int rk_drm_get_lcdc_type(void) ++{ ++ return SCREEN_NULL; ++} ++ ++struct share_params { ++ u32 hz; ++ u32 lcdc_type; ++ u32 vop; ++ u32 vop_dclk_mode; ++ u32 sr_idle_en; ++ u32 addr_mcu_el3; ++ /* ++ * 1: need to wait flag1 ++ * 0: never wait flag1 ++ */ ++ u32 wait_flag1; ++ /* ++ * 1: need to wait flag1 ++ * 0: never wait flag1 ++ */ ++ u32 wait_flag0; ++ u32 complt_hwirq; ++ /* if need, add parameter after */ ++}; ++ ++struct rockchip_ddrclk_data { ++ u32 inited_flag; ++ void __iomem *share_memory; ++}; ++ ++static struct rockchip_ddrclk_data ddr_data; ++ ++static void rockchip_ddrclk_data_init(void) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM, ++ 1, SHARE_PAGE_TYPE_DDR, 0, ++ 0, 0, 0, 0, &res); ++ ++ if (!res.a0) { ++ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12); ++ ddr_data.inited_flag = 1; ++ } ++} ++ ++static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw, ++ unsigned long drate, ++ unsigned long prate) ++{ ++ struct share_params *p; ++ struct arm_smccc_res res; ++ ++ if (!ddr_data.inited_flag) ++ rockchip_ddrclk_data_init(); ++ ++ p = (struct share_params *)ddr_data.share_memory; ++ ++ p->hz = drate; ++ p->lcdc_type = rk_drm_get_lcdc_type(); ++ p->wait_flag1 = 1; ++ p->wait_flag0 = 1; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ++ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE, ++ 0, 0, 0, 0, &res); ++ ++ if ((int)res.a1 == -6) { ++ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000); ++ /* TODO: rockchip_dmcfreq_wait_complete(); */ ++ } ++ ++ return res.a0; ++} ++ ++static unsigned long rockchip_ddrclk_sip_recalc_rate_v2 ++ (struct clk_hw *hw, unsigned long parent_rate) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ++ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE, ++ 0, 0, 0, 0, &res); ++ if (!res.a0) ++ return res.a1; ++ else ++ return 0; ++} ++ ++static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long *prate) ++{ ++ struct share_params *p; ++ struct arm_smccc_res res; ++ ++ if (!ddr_data.inited_flag) ++ rockchip_ddrclk_data_init(); ++ ++ p = (struct share_params *)ddr_data.share_memory; ++ ++ p->hz = rate; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ++ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE, ++ 0, 0, 0, 0, &res); ++ if (!res.a0) ++ return res.a1; ++ else ++ return 0; ++} ++ ++static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = { ++ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2, ++ .set_rate = rockchip_ddrclk_sip_set_rate_v2, ++ .round_rate = rockchip_ddrclk_sip_round_rate_v2, ++ .get_parent = rockchip_ddrclk_get_parent, ++}; ++ + struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, + u8 num_parents, int mux_offset, +@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk + case ROCKCHIP_DDRCLK_SIP: + init.ops = &rockchip_ddrclk_sip_ops; + break; ++ case ROCKCHIP_DDRCLK_SIP_V2: ++ init.ops = &rockchip_ddrclk_sip_ops_v2; ++ break; + default: + pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag); + kfree(ddrclk); +--- a/drivers/clk/rockchip/clk-rk3328.c ++++ b/drivers/clk/rockchip/clk-rk3328.c +@@ -315,9 +315,10 @@ static struct rockchip_clk_branch rk3328 + RK3328_CLKGATE_CON(14), 1, GFLAGS), + + /* PD_DDR */ +- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED, +- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, +- RK3328_CLKGATE_CON(0), 4, GFLAGS), ++ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, ++ RK3328_CLKSEL_CON(3), 8, 2, 0, 3, ++ ROCKCHIP_DDRCLK_SIP_V2), ++ + GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED, + RK3328_CLKGATE_CON(18), 6, GFLAGS), + GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -568,7 +568,8 @@ struct clk *rockchip_clk_register_mmc(co + * DDRCLK flags, including method of setting the rate + * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. + */ +-#define ROCKCHIP_DDRCLK_SIP BIT(0) ++#define ROCKCHIP_DDRCLK_SIP 0x01 ++#define ROCKCHIP_DDRCLK_SIP_V2 0x03 + + struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, +--- a/include/soc/rockchip/rockchip_sip.h ++++ b/include/soc/rockchip/rockchip_sip.h +@@ -16,5 +16,16 @@ + #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 + #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 + #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 ++#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08 ++ ++#define ROCKCHIP_SIP_SHARE_MEM 0x82000009 ++ ++/* Share mem page types */ ++typedef enum { ++ SHARE_PAGE_TYPE_INVALID = 0, ++ SHARE_PAGE_TYPE_UARTDBG, ++ SHARE_PAGE_TYPE_DDR, ++ SHARE_PAGE_TYPE_MAX, ++} share_page_type_t; + + #endif diff --git a/target/linux/rockchip/patches-6.12/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch b/target/linux/rockchip/patches-6.12/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch new file mode 100644 index 00000000000000..db8b74887e8ebf --- /dev/null +++ b/target/linux/rockchip/patches-6.12/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch @@ -0,0 +1,53 @@ +From 4db93c6dad0c71750b86163df2fdb21c35f00d9a Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Tue, 19 Nov 2019 12:49:48 +0800 +Subject: [PATCH] PM / devfreq: rockchip-dfi: add more soc support + +Signed-off-by: hmz007 +--- + drivers/devfreq/event/rockchip-dfi.c | 20 ++++++++++++++++++++++++--- + 1 file changed, 20 insertions(+) + +--- a/drivers/devfreq/event/rockchip-dfi.c ++++ b/drivers/devfreq/event/rockchip-dfi.c +@@ -44,6 +44,9 @@ + DDRMON_CTRL_LPDDR4 | \ + DDRMON_CTRL_LPDDR23) + ++#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) ++#define RK3328_GRF_OS_REG2 0x5d0 ++ + #define DDRMON_CH0_WR_NUM 0x20 + #define DDRMON_CH0_RD_NUM 0x24 + #define DDRMON_CH0_COUNT_NUM 0x28 +@@ -669,6 +672,22 @@ static int rockchip_ddr_perf_init(struct + } + #endif + ++static int rk3328_dfi_init(struct rockchip_dfi *dfi) ++{ ++ struct regmap *regmap_pmu = dfi->regmap_pmu; ++ u32 val; ++ ++ regmap_read(regmap_pmu, RK3328_GRF_OS_REG2, &val); ++ dfi->ddr_type = READ_DRAMTYPE_INFO(val); ++ dfi->channel_mask = BIT(0); ++ dfi->max_channels = 1; ++ ++ dfi->ddrmon_stride = 0x0; ++ dfi->ddrmon_ctrl_single = true; ++ ++ return 0; ++} ++ + static int rk3399_dfi_init(struct rockchip_dfi *dfi) + { + struct regmap *regmap_pmu = dfi->regmap_pmu; +@@ -757,6 +776,7 @@ static int rk3588_dfi_init(struct rockch + }; + + static const struct of_device_id rockchip_dfi_id_match[] = { ++ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init }, + { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init }, + { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init }, + { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init }, diff --git a/target/linux/rockchip/patches-6.12/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch b/target/linux/rockchip/patches-6.12/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch new file mode 100644 index 00000000000000..4ec3d8080ac65e --- /dev/null +++ b/target/linux/rockchip/patches-6.12/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch @@ -0,0 +1,25 @@ +From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Tue, 19 Nov 2019 14:21:51 +0800 +Subject: [PATCH] arm64: dts: rockchip: rk3328: add dfi node + +Signed-off-by: hmz007 +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 +++++++ + +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -1074,6 +1074,13 @@ + status = "disabled"; + }; + ++ dfi: dfi@ff790000 { ++ reg = <0x00 0xff790000 0x00 0x400>; ++ compatible = "rockchip,rk3328-dfi"; ++ rockchip,pmu = <&grf>; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@ff811000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; diff --git a/target/linux/rockchip/patches-6.12/807-arm64-dts-rockchip-rk3328-devices-add-dmc.patch b/target/linux/rockchip/patches-6.12/807-arm64-dts-rockchip-rk3328-devices-add-dmc.patch new file mode 100644 index 00000000000000..557c10cb4efb43 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/807-arm64-dts-rockchip-rk3328-devices-add-dmc.patch @@ -0,0 +1,58 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -9,6 +9,7 @@ + #include + #include + #include "rk3328.dtsi" ++#include "rk3328-dram-dmc.dtsi" + + / { + model = "FriendlyElec NanoPi R2S"; +@@ -142,6 +143,10 @@ + cpu-supply = <&vdd_arm>; + }; + ++&dfi { ++ status = "okay"; ++}; ++ + &display_subsystem { + status = "disabled"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -9,6 +9,7 @@ + #include + #include + #include "rk3328.dtsi" ++#include "rk3328-dram-dmc.dtsi" + + / { + model = "Xunlong Orange Pi R1 Plus"; +@@ -108,6 +109,10 @@ + cpu-supply = <&vdd_arm>; + }; + ++&dfi { ++ status = "okay"; ++}; ++ + &display_subsystem { + status = "disabled"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +@@ -14,6 +14,13 @@ + compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; + }; + ++&dmc_opp_table { ++ /delete-node/ opp-798000000; ++ /delete-node/ opp-840000000; ++ /delete-node/ opp-924000000; ++ /delete-node/ opp-1056000000; ++}; ++ + &gmac2io { + phy-handle = <&yt8531c>; + tx_delay = <0x19>; diff --git a/target/linux/rockchip/patches-6.12/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-6.12/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch new file mode 100644 index 00000000000000..35d40024d7be75 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch @@ -0,0 +1,44 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Leonidas P. Papadakos +Date: Fri, 1 Mar 2019 21:55:53 +0200 +Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for + RK3328 + +This allows for greater max frequency on rk3328 boards, +increasing performance. + +It has been included in Armbian (a linux distibution for ARM boards) +for a while now without any reported issues + +https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch +https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch + +Signed-off-by: Leonidas P. Papadakos +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++ + 1 files changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -171,6 +171,21 @@ + opp-microvolt = <1300000>; + clock-latency-ns = <40000>; + }; ++ opp-1392000000 { ++ opp-hz = /bits/ 64 <1392000000>; ++ opp-microvolt = <1350000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1512000000 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1450000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1450000>; ++ clock-latency-ns = <40000>; ++ }; + }; + + analog_sound: analog-sound { From b49e92a28cabea3b9812a7512c67e11c2db3d014 Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Fri, 20 Dec 2024 18:56:19 +0800 Subject: [PATCH 2/2] default-settings: also including english lang po --- package/lean/default-settings/Makefile | 2 +- target/linux/ramips/mt7621/base-files/etc/board.d/02_network | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/package/lean/default-settings/Makefile b/package/lean/default-settings/Makefile index acd35b1bb7d39b..e1afc1cf7152d9 100644 --- a/package/lean/default-settings/Makefile +++ b/package/lean/default-settings/Makefile @@ -18,7 +18,7 @@ define Package/default-settings CATEGORY:=LuCI TITLE:=LuCI support for Default Settings PKGARCH:=all - DEPENDS:=+luci-base +luci +@LUCI_LANG_zh-cn +@LUCI_LANG_zh_Hans + DEPENDS:=+luci-base +luci +@LUCI_LANG_zh-cn +@LUCI_LANG_zh_Hans +@LUCI_LANG_en endef define Package/default-settings/description diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index 3c58566dcadd98..5115e5dde63744 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -197,6 +197,11 @@ ramips_setup_macs() lan_mac=$(macaddr_add "$label_mac" 1) wan_mac=$label_mac ;; + huasifei,mt7621dtu) + label_mac=$(mtd_get_mac_binary factory 0x4) + lan_mac=$label_mac + wan_mac=$(macaddr_add "$label_mac" 1) + ;; hiwifi,hc5962) lan_mac=$(mtd_get_mac_ascii bdinfo "Vfac_mac ") label_mac=$lan_mac