From c1abd6e36d2b2643f4b159266b9361aaf1acb78d Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Thu, 25 Jun 2020 17:30:00 -0700 Subject: [PATCH 01/15] modules: Add Sound Open Firmware module Add the Sound Open Firmware project as a Zephyr module under modules/audio/sof. Signed-off-by: Andy Ross --- modules/Kconfig | 1 + modules/Kconfig.sof | 7 +++++++ west.yml | 6 ++++++ 3 files changed, 14 insertions(+) create mode 100644 modules/Kconfig.sof diff --git a/modules/Kconfig b/modules/Kconfig index 632f2456608bb5..90fcf791358b16 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -22,6 +22,7 @@ source "modules/Kconfig.nuvoton" source "modules/Kconfig.open-amp" source "modules/Kconfig.silabs" source "modules/Kconfig.simplelink" +source "modules/Kconfig.sof" source "modules/Kconfig.st" source "modules/Kconfig.stm32" source "modules/Kconfig.syst" diff --git a/modules/Kconfig.sof b/modules/Kconfig.sof new file mode 100644 index 00000000000000..17e40df34b53b6 --- /dev/null +++ b/modules/Kconfig.sof @@ -0,0 +1,7 @@ +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOF + bool "Sound Open Firmware (SOF)" + help + Build Sound Open Firmware (SOF) support. diff --git a/west.yml b/west.yml index b57877bcf0f378..8867bac93953c7 100644 --- a/west.yml +++ b/west.yml @@ -21,6 +21,8 @@ manifest: remotes: - name: upstream url-base: https://github.com/zephyrproject-rtos + - name: thesofproject + url-base: https://github.com/thesofproject # # Please add items below based on alphabetical order @@ -140,6 +142,10 @@ manifest: - name: trusted-firmware-m path: modules/tee/tfm revision: bb15a511a509c81135af61e02f9f4bfaf86d7fde + - name: sof + remote: thesofproject + revision: stable-v1.6 + path: modules/audio/sof self: path: zephyr From 57df1f3e6d08e613ce6357ed9a90a978c04904f7 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 10 Jul 2020 14:58:32 +0100 Subject: [PATCH 02/15] samples/audio: Add Sound Open Firmware Adds the Sound Open Firmware project, built as a Zephyr application, under samples/subsys/sudio/sof. Signed-off-by: Liam Girdwood --- modules/Kconfig.sof | 4 ++++ samples/audio/sof/CMakeLists.txt | 41 ++++++++++++++++++++++++++++++++ samples/audio/sof/prj.conf | 4 ++++ samples/audio/sof/src/main.c | 36 ++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+) create mode 100644 samples/audio/sof/CMakeLists.txt create mode 100644 samples/audio/sof/prj.conf create mode 100644 samples/audio/sof/src/main.c diff --git a/modules/Kconfig.sof b/modules/Kconfig.sof index 17e40df34b53b6..66d026b8324827 100644 --- a/modules/Kconfig.sof +++ b/modules/Kconfig.sof @@ -5,3 +5,7 @@ config SOF bool "Sound Open Firmware (SOF)" help Build Sound Open Firmware (SOF) support. + +if SOF +rsource "../../modules/audio/sof/Kconfig" +endif \ No newline at end of file diff --git a/samples/audio/sof/CMakeLists.txt b/samples/audio/sof/CMakeLists.txt new file mode 100644 index 00000000000000..4549a8dd4ac959 --- /dev/null +++ b/samples/audio/sof/CMakeLists.txt @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.13.1) + +set(sof_module $ENV{ZEPHYR_BASE}/../modules/audio/sof) + +# This needs to be before find_package, see +# https://github.com/zephyrproject-rtos/zephyr/issues/24512 +set(sof_defconfigs ${sof_module}/src/arch/xtensa/configs) +if (${BOARD} STREQUAL up_squared_adsp) + set(OVERLAY_CONFIG ${sof_defconfigs}/apollolake_defconfig) +endif() +if (${BOARD} STREQUAL intel_adsp_cavs18) + set(OVERLAY_CONFIG ${sof_defconfigs}/cannonlake_defconfig) +endif() +if (${BOARD} STREQUAL intel_adsp_cavs20) + set(OVERLAY_CONFIG ${sof_defconfigs}/icelake_defconfig) +endif() +if (${BOARD} STREQUAL intel_adsp_cavs25) + set(OVERLAY_CONFIG ${sof_defconfigs}/tigerlake_defconfig) +endif() +if (${BOARD} STREQUAL intel_adsp_baytrail) + set(OVERLAY_CONFIG ${sof_defconfigs}/baytrail_defconfig) +endif() +if (${BOARD} STREQUAL intel_adsp_broadwell) + set(OVERLAY_CONFIG ${sof_defconfigs}/broadwell_defconfig) +endif() + +find_package(Zephyr HINTS $ENV{ZEPHYR_BASE}) +project(sample_sof) + +target_sources(app PRIVATE + src/main.c + ) + +zephyr_interface_library_named(sof_lib) + +zephyr_library_include_directories(app PUBLIC + ${sof_module}/src/arch/xtensa/include + ${sof_module}/src/include + ) diff --git a/samples/audio/sof/prj.conf b/samples/audio/sof/prj.conf new file mode 100644 index 00000000000000..e88554f2a72184 --- /dev/null +++ b/samples/audio/sof/prj.conf @@ -0,0 +1,4 @@ +CONFIG_SOF=y +CONFIG_SMP=n +CONFIG_LOG=y +CONFIG_MP_NUM_CPUS=1 diff --git a/samples/audio/sof/src/main.c b/samples/audio/sof/src/main.c new file mode 100644 index 00000000000000..ee3eba34362d68 --- /dev/null +++ b/samples/audio/sof/src/main.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2020 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +LOG_MODULE_REGISTER(main, LOG_LEVEL_DBG); + +/** + * Should be included from sof/schedule/task.h + * but triggers include chain issue + * FIXME + */ +int sof_main(int argc, char *argv[]); + +/** + * TODO: Here comes SOF initialization + */ + +void main(void) +{ + int ret; + + LOG_INF("SOF on %s", CONFIG_BOARD); + + /* sof_main is actually SOF initialization */ + ret = sof_main(0, NULL); + if (ret) { + LOG_ERR("SOF initialization failed"); + } + + LOG_INF("SOF initialized"); +} From 82a635827e15086296d3aa16130d5b096ba57cea Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 27 Oct 2020 12:48:36 +0100 Subject: [PATCH 03/15] rimage: update rimage: add configuration and extended manifest rimage dropped its "-m" parameter and switched over to using "-c" for a configuration file, including a target name. Add support for extended manifest for all cAVS versions. Signed-off-by: Guennadi Liakhovetski --- scripts/west_commands/sign.py | 19 +++++++++++++++++-- .../intel_adsp/cavs_v15/include/soc/memory.h | 2 ++ soc/xtensa/intel_adsp/cavs_v15/linker.ld | 15 +++++++++++++++ .../intel_adsp/cavs_v18/include/soc/memory.h | 2 ++ soc/xtensa/intel_adsp/cavs_v18/linker.ld | 15 +++++++++++++++ .../intel_adsp/cavs_v20/include/soc/memory.h | 2 ++ soc/xtensa/intel_adsp/cavs_v20/linker.ld | 14 ++++++++++++++ .../intel_adsp/cavs_v25/include/soc/memory.h | 2 ++ soc/xtensa/intel_adsp/cavs_v25/linker.ld | 15 +++++++++++++++ 9 files changed, 84 insertions(+), 2 deletions(-) diff --git a/scripts/west_commands/sign.py b/scripts/west_commands/sign.py index d37757c2d4c746..2539b512072d61 100644 --- a/scripts/west_commands/sign.py +++ b/scripts/west_commands/sign.py @@ -420,19 +420,34 @@ def sign(self, command, build_dir, bcfg, formats): board = cache['CACHED_BOARD'] log.inf('Signing for board ' + board) target = self.edt_get_rimage_target(board) - log.inf('Signing for SOC target ' + target) + conf = target + '.toml' + log.inf('Signing for SOC target ' + target + ' using ' + conf) if not args.quiet: log.inf('Signing with tool {}'.format(tool_path)) + s = pathlib.Path(os.environ.get('ZEPHYR_BASE')) + bootloader = str(b / 'zephyr' / 'bootloader.elf.mod') kernel = str(b / 'zephyr' / 'zephyr.elf.mod') out_bin = str(b / 'zephyr' / 'zephyr.ri') + out_xman = str(b / 'zephyr' / 'zephyr.ri.xman') + out_tmp = str(b / 'zephyr' / 'zephyr.rix') + conf_path = str(s / '..' / 'modules' / 'audio' / 'sof' / 'rimage' / 'config' / conf) sign_base = ([tool_path] + args.tool_args + - ['-o', out_bin, '-m', target, '-i', '3'] + + ['-o', out_bin, '-c', conf_path, '-i', '3', '-e'] + [bootloader, kernel]) if not args.quiet: log.inf(quote_sh_list(sign_base)) subprocess.check_call(sign_base) + + filenames = [out_xman, out_bin] + with open(out_tmp, 'wb') as outfile: + for fname in filenames: + with open(fname, 'rb') as infile: + outfile.write(infile.read()) + + os.remove(out_bin) + os.rename(out_tmp, out_bin) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index 616654b588e3d9..d852fb80ad5b4a 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -142,6 +142,8 @@ #define LOG_ENTRY_ELF_BASE 0x20000000 #define LOG_ENTRY_ELF_SIZE 0x2000000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 #define SRAM_ALIAS_BASE 0x9E000000 #define SRAM_ALIAS_MASK 0xFF000000 diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index 08c9d08b7f90c1..29860bd0bacd91 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -132,6 +132,9 @@ MEMORY static_log_entries_seg (!ari) : org = LOG_ENTRY_ELF_BASE, len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE } PHDRS @@ -161,6 +164,7 @@ PHDRS ucram_phdr PT_LOAD; static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; } _rom_store_table = 0; PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); @@ -205,6 +209,11 @@ _memmap_cacheattr_bp_allvalid = 0x22222222; _memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2; PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) +EXTERN(ext_man_cavs_config) + SECTIONS { @@ -567,4 +576,10 @@ SECTIONS { *(*.static_log*) } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr } diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index d496097b4b675f..473814e7d3c4d7 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -139,6 +139,8 @@ #define LOG_ENTRY_ELF_BASE 0x20000000 #define LOG_ENTRY_ELF_SIZE 0x2000000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 #define SRAM_ALIAS_BASE 0x9E000000 #define SRAM_ALIAS_MASK 0xFF000000 diff --git a/soc/xtensa/intel_adsp/cavs_v18/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld index 7ab8a51d5fac80..e0141e203fca70 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v18/linker.ld @@ -112,6 +112,9 @@ MEMORY static_log_entries_seg (!ari) : org = LOG_ENTRY_ELF_BASE, len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE } PHDRS @@ -141,6 +144,7 @@ PHDRS static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; } _rom_store_table = 0; PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); @@ -194,6 +198,11 @@ _memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2; #endif PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) +EXTERN(ext_man_cavs_config) + SECTIONS { @@ -532,4 +541,10 @@ SECTIONS { *(*.static_log*) } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr } diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 1a9983b03dce43..34b4a9d463a7b3 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -139,6 +139,8 @@ #define LOG_ENTRY_ELF_BASE 0x20000000 #define LOG_ENTRY_ELF_SIZE 0x2000000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 #define SRAM_ALIAS_BASE 0x9E000000 #define SRAM_ALIAS_MASK 0xFF000000 diff --git a/soc/xtensa/intel_adsp/cavs_v20/linker.ld b/soc/xtensa/intel_adsp/cavs_v20/linker.ld index c24adfeb7c3e5a..b144b121039b71 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v20/linker.ld @@ -112,8 +112,15 @@ MEMORY static_log_entries_seg (!ari) : org = LOG_ENTRY_ELF_BASE, len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE } +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) +EXTERN(ext_man_cavs_config) + PHDRS { vector_memory_lit_phdr PT_LOAD; @@ -141,6 +148,7 @@ PHDRS static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; } _rom_store_table = 0; PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); @@ -532,4 +540,10 @@ SECTIONS { *(*.static_log*) } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr } diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 6c448a84189fa2..1ad6d443617844 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -139,6 +139,8 @@ #define LOG_ENTRY_ELF_BASE 0x20000000 #define LOG_ENTRY_ELF_SIZE 0x2000000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 #define SRAM_ALIAS_BASE 0x9E000000 #define SRAM_ALIAS_MASK 0xFF000000 diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld index 39a4c99b190644..a5c7cb46ea5b85 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld @@ -112,6 +112,9 @@ MEMORY static_log_entries_seg (!ari) : org = LOG_ENTRY_ELF_BASE, len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE lpsram_alt_reset_vec_seg : org = LP_SRAM_ALT_RESET_VEC_BASE, @@ -154,6 +157,7 @@ PHDRS static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; lpsram_mem_phdr PT_LOAD; sram_alt_fw_reset_vec_phdr PT_LOAD; @@ -214,6 +218,11 @@ _memmap_cacheattr_intel_cavs25_adsp = 0xFF22FFF2; #endif PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) +EXTERN(ext_man_cavs_config) + SECTIONS { @@ -600,4 +609,10 @@ SECTIONS { *(*.static_log*) } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr } From c9938d49d292e8e6f514999340f4aecfecc7452c Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 21 Oct 2020 16:02:14 +0200 Subject: [PATCH 04/15] cavs: restore a missing header soc/xtensa/intel_adsp/common/include/cavs/memory.h wend missing from the SOF update, restore it. Signed-off-by: Guennadi Liakhovetski --- .../intel_adsp/common/include/cavs/memory.h | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 soc/xtensa/intel_adsp/common/include/cavs/memory.h diff --git a/soc/xtensa/intel_adsp/common/include/cavs/memory.h b/soc/xtensa/intel_adsp/common/include/cavs/memory.h new file mode 100644 index 00000000000000..2cf8c80473d96d --- /dev/null +++ b/soc/xtensa/intel_adsp/common/include/cavs/memory.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2019 Intel Corporation. All rights reserved. + * + * Author: Bartosz Kokoszko + */ + +#ifndef __CAVS_MEMORY_H__ +#define __CAVS_MEMORY_H__ + +#include +#if !defined(__ASSEMBLER__) && !defined(LINKER) +#include +#include +#endif + +#define DCACHE_LINE_SIZE XCHAL_DCACHE_LINESIZE + +/* data cache line alignment */ +#define PLATFORM_DCACHE_ALIGN DCACHE_LINE_SIZE + +#define SRAM_BANK_SIZE (64 * 1024) + +#define EBB_BANKS_IN_SEGMENT 32 + +#define EBB_SEGMENT_SIZE EBB_BANKS_IN_SEGMENT + +#if CONFIG_LP_MEMORY_BANKS +#define PLATFORM_LPSRAM_EBB_COUNT CONFIG_LP_MEMORY_BANKS +#else +#define PLATFORM_LPSRAM_EBB_COUNT 0 +#endif + +#define PLATFORM_HPSRAM_EBB_COUNT CONFIG_HP_MEMORY_BANKS + +#define MAX_MEMORY_SEGMENTS PLATFORM_HPSRAM_SEGMENTS + +#if CONFIG_LP_MEMORY_BANKS +#define LP_SRAM_SIZE \ + (CONFIG_LP_MEMORY_BANKS * SRAM_BANK_SIZE) +#else +#define LP_SRAM_SIZE 0 +#endif + +#define HP_SRAM_SIZE \ + (CONFIG_HP_MEMORY_BANKS * SRAM_BANK_SIZE) + +#define PLATFORM_HPSRAM_SEGMENTS ((PLATFORM_HPSRAM_EBB_COUNT \ + + EBB_BANKS_IN_SEGMENT - 1) / EBB_BANKS_IN_SEGMENT) + +#if defined(__ASSEMBLER__) +#define LPSRAM_MASK(ignored) ((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1) + +#define HPSRAM_MASK(seg_idx) ((1 << (PLATFORM_HPSRAM_EBB_COUNT \ + - EBB_BANKS_IN_SEGMENT * seg_idx)) - 1) +#else +#define LPSRAM_MASK(ignored) ((1ULL << PLATFORM_LPSRAM_EBB_COUNT) - 1) + +#define HPSRAM_MASK(seg_idx) ((1ULL << (PLATFORM_HPSRAM_EBB_COUNT \ + - EBB_BANKS_IN_SEGMENT * seg_idx)) - 1) +#endif + +#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * SRAM_BANK_SIZE) + +#define HEAP_BUF_ALIGNMENT PLATFORM_DCACHE_ALIGN + +/** \brief EDF task's default stack size in bytes. */ +#define PLATFORM_TASK_DEFAULT_STACK_SIZE 0x1000 + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +/** + * \brief Data shared between different cores. + * Placed into dedicated section, which should be accessed through + * uncached memory region. SMP platforms without uncache can simply + * align to cache line size instead. + */ +#if PLATFORM_CORE_COUNT > 1 && !defined(UNIT_TEST) +#define SHARED_DATA __section(".shared_data") +#else +#define SHARED_DATA +#endif + +#define SRAM_ALIAS_BASE 0x9E000000 +#define SRAM_ALIAS_MASK 0xFF000000 +#define SRAM_ALIAS_OFFSET 0x20000000 + +#endif + +/** + * FIXME check that correct core count is used + */ +#include +/* SOF Core S configuration */ +#define SRAM_BANK_SIZE (64 * 1024) + +/* low power sequencer */ +#define LPS_RESTORE_VECTOR_OFFSET 0x1000 +#define LPS_RESTORE_VECTOR_SIZE 0x800 +#define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET) + +#endif /* __CAVS_MEMORY_H__ */ From 7f1b03dcb175056e582fb4dd3938846f84bec8db Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 3 Nov 2020 12:32:24 +0100 Subject: [PATCH 05/15] sof: remove superfluous and duplicate code 1. SOF doesn't have to be built in .bin format 2. don't include soc.c and soc_mp.c twice in cmake 3. remove an unused mailbox.h header and unused code in adsp.c Signed-off-by: Guennadi Liakhovetski --- samples/audio/sof/prj.conf | 1 + soc/xtensa/intel_adsp/common/CMakeLists.txt | 2 - soc/xtensa/intel_adsp/common/adsp.c | 41 ------------ .../intel_adsp/common/include/cavs/mailbox.h | 62 ------------------- 4 files changed, 1 insertion(+), 105 deletions(-) delete mode 100644 soc/xtensa/intel_adsp/common/include/cavs/mailbox.h diff --git a/samples/audio/sof/prj.conf b/samples/audio/sof/prj.conf index e88554f2a72184..e1675706f1e774 100644 --- a/samples/audio/sof/prj.conf +++ b/samples/audio/sof/prj.conf @@ -2,3 +2,4 @@ CONFIG_SOF=y CONFIG_SMP=n CONFIG_LOG=y CONFIG_MP_NUM_CPUS=1 +CONFIG_BUILD_OUTPUT_BIN=n diff --git a/soc/xtensa/intel_adsp/common/CMakeLists.txt b/soc/xtensa/intel_adsp/common/CMakeLists.txt index aaf9ad17880c3b..454599990a7935 100644 --- a/soc/xtensa/intel_adsp/common/CMakeLists.txt +++ b/soc/xtensa/intel_adsp/common/CMakeLists.txt @@ -27,7 +27,5 @@ if(CONFIG_SOC_SERIES_INTEL_CAVS_V15 OR CONFIG_SOC_SERIES_INTEL_CAVS_V18 OR CONFIG_SOC_SERIES_INTEL_CAVS_V20 OR CONFIG_SOC_SERIES_INTEL_CAVS_V25) - zephyr_library_sources(soc.c) - zephyr_library_sources(soc_mp.c) include(bootloader.cmake) endif() diff --git a/soc/xtensa/intel_adsp/common/adsp.c b/soc/xtensa/intel_adsp/common/adsp.c index f5bab48fa892d5..ef526a27854a9e 100644 --- a/soc/xtensa/intel_adsp/common/adsp.c +++ b/soc/xtensa/intel_adsp/common/adsp.c @@ -12,44 +12,3 @@ #include LOG_MODULE_REGISTER(sof); - -#include -#include -#include - -#include - -/* - * Sets up the host windows so that the host can see the memory - * content on the DSP SRAM. - */ -static void prepare_host_windows(void) -{ - /* window0, for fw status */ - sys_write32((HP_SRAM_WIN0_SIZE | 0x7), DMWLO(0)); - sys_write32((HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE), - DMWBA(0)); - memset((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), 0, - HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END); - SOC_DCACHE_FLUSH((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), - HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END); - - /* window3, for trace - * zeroed by trace initialization - */ - sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3)); - sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE), - DMWBA(3)); - memset((void *)HP_SRAM_WIN3_BASE, 0, HP_SRAM_WIN3_SIZE); - SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE); -} - -static int adsp_init(const struct device *dev) -{ - prepare_host_windows(); - - return 0; -} - -/* Init after IPM initialization and before logging (uses memory windows) */ -SYS_INIT(adsp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h b/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h deleted file mode 100644 index fe06ab66037990..00000000000000 --- a/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifndef __CAVS_MAILBOX_H__ -#define __CAVS_MAILBOX_H__ - -#include -#include - -/* - * The Window Region on HPSRAM for cAVS platforms is organised like this :- - * +--------------------------------------------------------------------------+ - * | Offset | Region | Size | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE | - * +---------------------+----------------+-----------------------------------+ - * - * Note: For suecreek SRAM_SW_REG window does not exist - MAILBOX_SW_REG_BASE - * and MAILBOX_SW_REG_BASE are equal to 0 - */ - - /* window 3 - trace */ -#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE -#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE - - /* window 2 debug, exception and stream */ -#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE -#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE - -#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE -#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE -#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE - -#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE -#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE -#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE) - - /* window 1 inbox/downlink and FW registers */ -#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE -#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE - - /* window 0 */ -#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE -#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE - -#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE -#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE - -#endif /* __CAVS_MAILBOX_H__ */ From 18da5edcbb210270c67bdff2742584060124b7b5 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 3 Nov 2020 12:35:07 +0100 Subject: [PATCH 06/15] sof: enable compilation on unsupported platforms This allows building SOF for unsupported platforms to enable compilation testing and to simplify porting to new platforms. Signed-off-by: Guennadi Liakhovetski --- samples/audio/sof/CMakeLists.txt | 40 +++++++++++++++++--------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/samples/audio/sof/CMakeLists.txt b/samples/audio/sof/CMakeLists.txt index 4549a8dd4ac959..6f2684a13fc80e 100644 --- a/samples/audio/sof/CMakeLists.txt +++ b/samples/audio/sof/CMakeLists.txt @@ -6,25 +6,27 @@ set(sof_module $ENV{ZEPHYR_BASE}/../modules/audio/sof) # This needs to be before find_package, see # https://github.com/zephyrproject-rtos/zephyr/issues/24512 -set(sof_defconfigs ${sof_module}/src/arch/xtensa/configs) +set(sof_defconfigs ${sof_module}/src/arch) if (${BOARD} STREQUAL up_squared_adsp) - set(OVERLAY_CONFIG ${sof_defconfigs}/apollolake_defconfig) -endif() -if (${BOARD} STREQUAL intel_adsp_cavs18) - set(OVERLAY_CONFIG ${sof_defconfigs}/cannonlake_defconfig) -endif() -if (${BOARD} STREQUAL intel_adsp_cavs20) - set(OVERLAY_CONFIG ${sof_defconfigs}/icelake_defconfig) -endif() -if (${BOARD} STREQUAL intel_adsp_cavs25) - set(OVERLAY_CONFIG ${sof_defconfigs}/tigerlake_defconfig) -endif() -if (${BOARD} STREQUAL intel_adsp_baytrail) - set(OVERLAY_CONFIG ${sof_defconfigs}/baytrail_defconfig) -endif() -if (${BOARD} STREQUAL intel_adsp_broadwell) - set(OVERLAY_CONFIG ${sof_defconfigs}/broadwell_defconfig) -endif() + set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/apollolake_defconfig) +elseif (${BOARD} STREQUAL intel_adsp_cavs18) + set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/cannonlake_defconfig) +elseif (${BOARD} STREQUAL intel_adsp_cavs20) + set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/icelake_defconfig) +elseif (${BOARD} STREQUAL intel_adsp_cavs25) + set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/tigerlake_defconfig) +elseif (${BOARD} STREQUAL intel_adsp_baytrail) + set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/baytrail_defconfig) +elseif (${BOARD} STREQUAL intel_adsp_broadwell) + set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/broadwell_defconfig) +else () + set(OVERLAY_CONFIG ${sof_defconfigs}/host/configs/library_defconfig) + set(ARCH host) +endif () + +if (NOT DEFINED ARCH) + set(ARCH xtensa) +endif () find_package(Zephyr HINTS $ENV{ZEPHYR_BASE}) project(sample_sof) @@ -36,6 +38,6 @@ target_sources(app PRIVATE zephyr_interface_library_named(sof_lib) zephyr_library_include_directories(app PUBLIC - ${sof_module}/src/arch/xtensa/include + ${sof_module}/src/arch/${ARCH}/include ${sof_module}/src/include ) From 5c6040db15bf88f7364850a94bbf4cd1cba17f65 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 08:22:07 +0200 Subject: [PATCH 07/15] cavs: disable all interrupts when configuring interrupt controllers Some interrupts can be enabled by the ROM, e.g. the timer interrupt. When then in Zephyr the interrupt controller is enabled, before individual interrupts are configured, interrupts can arrive and lead to the spurious interrupt handler being invoked. Fix thid by disabling all child interrupts when configuring cAVS interrupt controllers. Signed-off-by: Guennadi Liakhovetski --- drivers/interrupt_controller/intc_cavs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c index 34dc1d1948cf3f..110e48364ce403 100644 --- a/drivers/interrupt_controller/intc_cavs.c +++ b/drivers/interrupt_controller/intc_cavs.c @@ -132,6 +132,11 @@ static const struct irq_next_level_api cavs_apis = { #define CAVS_ICTL_INIT(n) \ static int cavs_ictl_##n##_initialize(const struct device *port) \ { \ + struct cavs_ictl_runtime *context = port->data; \ + volatile struct cavs_registers * const regs = \ + (struct cavs_registers *)context->base_addr; \ + regs->disable_il = ~0; \ + \ return 0; \ } \ \ From c7923e82a19089d78235105ede70d802261c209d Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:21:38 +0200 Subject: [PATCH 08/15] cavs: unify defconfigs for v15, v18, v20 and v25 Unify default configurations to support both SMP and UP: 1. make SMP default, although it's currently disabled in prj.conf 2. use CAVS timer by default in both UP and SMP configurations 3. make MP_NUM_CPUS, IPM and IPM_CAVS_IDC depend on SMP Signed-off-by: Guennadi Liakhovetski --- .../cavs_v15/Kconfig.defconfig.series | 18 +++++++++--------- .../cavs_v18/Kconfig.defconfig.series | 19 +++++++++++-------- .../cavs_v20/Kconfig.defconfig.series | 15 +++++++++------ .../cavs_v25/Kconfig.defconfig.series | 15 +++++++++------ 4 files changed, 38 insertions(+), 29 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series index 457a118b743e9b..1c6e0436e0bbdb 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series @@ -14,9 +14,6 @@ config SOC config SMP default y -config MP_NUM_CPUS - default 2 - config XTENSA_TIMER default n @@ -55,12 +52,6 @@ config TEST_LOGGING_DEFAULTS default n depends on TEST -config IPM_CAVS_IDC - default y - -config IPM - default y - if LOG config LOG_PRINTK @@ -79,6 +70,15 @@ endif # LOG if SMP +config MP_NUM_CPUS + default 2 + +config IPM + default y + +config IPM_CAVS_IDC + default y + config SCHED_IPI_SUPPORTED default y if IPM_CAVS_IDC diff --git a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series index c4179e404d4c03..b0264aeb785efb 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series @@ -11,6 +11,15 @@ config SOC string default "intel_cavs_18" +config SMP + default y + +config XTENSA_TIMER + default n + +config CAVS_TIMER + default y + config SYS_CLOCK_HW_CYCLES_PER_SEC default 400000000 if XTENSA_TIMER default 19200000 if CAVS_TIMER @@ -68,12 +77,6 @@ if SMP config MP_NUM_CPUS default 2 -config XTENSA_TIMER - default n - -config CAVS_TIMER - default y - config IPM default y @@ -83,8 +86,6 @@ config IPM_CAVS_IDC config SCHED_IPI_SUPPORTED default y if IPM_CAVS_IDC -endif # SMP - config IPM_INTEL_ADSP default y depends on IPM @@ -94,4 +95,6 @@ config IPM_CONSOLE depends on CONSOLE depends on IPM +endif # SMP + endif diff --git a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series index 4e51a07000ccd4..ffae452e6455f9 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series @@ -11,6 +11,15 @@ config SOC string default "intel_cavs_20" +config SMP + default y + +config XTENSA_TIMER + default n + +config CAVS_TIMER + default y + config SYS_CLOCK_HW_CYCLES_PER_SEC default 400000000 if XTENSA_TIMER default 19200000 if CAVS_TIMER @@ -67,12 +76,6 @@ if SMP config MP_NUM_CPUS default 2 -config XTENSA_TIMER - default n - -config CAVS_TIMER - default y - config IPM default y diff --git a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series index 3e8a83d2378820..50af7f1cc33ce5 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series @@ -11,6 +11,15 @@ config SOC string default "intel_cavs_25" +config SMP + default y + +config XTENSA_TIMER + default n + +config CAVS_TIMER + default y + config SYS_CLOCK_HW_CYCLES_PER_SEC default 400000000 if XTENSA_TIMER default 19200000 if CAVS_TIMER @@ -67,12 +76,6 @@ if SMP config MP_NUM_CPUS default 2 -config XTENSA_TIMER - default n - -config CAVS_TIMER - default y - config IPM default y From b64d8ee0fb80c28756a43b5facdf71d281853832 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:28:56 +0200 Subject: [PATCH 09/15] cavs: fix manifest base address On cAVS 1.5, 2.0 and 2.5 platforms the correct manifest address is 0xB0032000. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 2 +- soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h | 2 +- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index 473814e7d3c4d7..faa3f876bae55a 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -127,7 +127,7 @@ #define BOOT_LDR_STACK_SIZE (4 * 0x1000) /* Manifest base address in IMR - used by boot loader copy procedure. */ -#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000 +#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 /* Manifest size (seems unused). */ #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 34b4a9d463a7b3..0f96fa22922bd0 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -127,7 +127,7 @@ #define BOOT_LDR_STACK_SIZE (4 * 0x1000) /* Manifest base address in IMR - used by boot loader copy procedure. */ -#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000 +#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 /* Manifest size (seems unused). */ #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 1ad6d443617844..35dd0fbdfc83f7 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -127,7 +127,7 @@ #define BOOT_LDR_STACK_SIZE (4 * 0x1000) /* Manifest base address in IMR - used by boot loader copy procedure. */ -#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000 +#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 /* Manifest size (seems unused). */ #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 From b4ade5aacf2aef544862de061d430f6d67894e5f Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:34:59 +0200 Subject: [PATCH 10/15] xtensa: disable unused memory power down The current unused memory calculation is broken because it doesn't take into account the stack area, allocated at the top of HP SRAM. Until this is fixed disable powering down unused RAM. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/bootloader/boot_loader.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c index a2f88ff9b61929..3319db295eef86 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c @@ -27,6 +27,7 @@ extern void __start(void); #if !defined(CONFIG_SOC_INTEL_S1000) #define MANIFEST_SEGMENT_COUNT 3 +#undef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED static inline void idelay(int n) { @@ -125,6 +126,7 @@ static void parse_module(struct sof_man_fw_header *hdr, #define MAN_SKIP_ENTRIES 1 #endif +#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED static uint32_t get_fw_size_in_use(void) { struct sof_man_fw_desc *desc = @@ -153,6 +155,7 @@ static uint32_t get_fw_size_in_use(void) return fw_size_in_use; } +#endif /* parse FW manifest and copy modules */ static void parse_manifest(void) @@ -256,11 +259,13 @@ static uint32_t hp_sram_power_on_memory(uint32_t memory_size) return hp_sram_pm_banks(ebb_in_use); } +#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size) { /* keep enabled only memory banks used by FW */ return hp_sram_power_on_memory(memory_size); } +#endif static int32_t hp_sram_init(void) { @@ -269,10 +274,12 @@ static int32_t hp_sram_init(void) #else +#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size) { return 0; } +#endif static uint32_t hp_sram_init(void) { @@ -340,7 +347,9 @@ void boot_master_core(void) /* parse manifest and copy modules */ parse_manifest(); +#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED hp_sram_power_off_unused_banks(get_fw_size_in_use()); +#endif #endif /* now call SOF entry */ __start(); From 1bc66ccca2b77e8070db70a63fda89db60d84d92 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:40:33 +0200 Subject: [PATCH 11/15] cavs: fix shim register location on 1.8 and above Shim register location on cAVS 1.5 is different than on 1.8 and up, fix it. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/include/soc.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/soc/xtensa/intel_adsp/common/include/soc.h b/soc/xtensa/intel_adsp/common/include/soc.h index 0cfbf0815c63f7..4fc9b6c7df0d12 100644 --- a/soc/xtensa/intel_adsp/common/include/soc.h +++ b/soc/xtensa/intel_adsp/common/include/soc.h @@ -7,6 +7,8 @@ #include #include +#include + #include #include @@ -61,10 +63,14 @@ #define SSP_MN_DIV_BASE(x) \ (0x00078D00 + ((x) * SSP_MN_DIV_SIZE)) -#define PDM_BASE 0x00010000 +#define PDM_BASE DMIC_BASE /* SOC DSP SHIM Registers */ +#if CAVS_VERSION == CAVS_VERSION_1_5 #define SOC_DSP_SHIM_REG_BASE 0x00001000 +#else +#define SOC_DSP_SHIM_REG_BASE 0x00071f00 +#endif /* SOC DSP SHIM Register - Clock Control */ #define SOC_CLKCTL_REQ_AUDIO_PLL_CLK BIT(31) From 1a81fe7f70f93e71e8166b60fb609cd8a87b4384 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:43:29 +0200 Subject: [PATCH 12/15] xtensa: IPM is only required if SMP is enabled A configuration with CONFIG_MP_NUM_CPUS > 1 and CONFIG_IPM_CAVS_IDC not defined is valid if COMFIG_SMP is disabled. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/soc_mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/xtensa/intel_adsp/common/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c index 5c0b811a7ee48c..f56c05f95d2897 100644 --- a/soc/xtensa/intel_adsp/common/soc_mp.c +++ b/soc/xtensa/intel_adsp/common/soc_mp.c @@ -25,7 +25,7 @@ LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL); #include #include -#if CONFIG_MP_NUM_CPUS > 1 && !defined(CONFIG_IPM_CAVS_IDC) +#if CONFIG_MP_NUM_CPUS > 1 && !defined(CONFIG_IPM_CAVS_IDC) && defined(CONFIG_SMP) #error Need to enable the IPM driver for multiprocessing #endif From c26eb04f22d10088fa4555719587444f647a6550 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 7 Oct 2020 09:47:48 +0200 Subject: [PATCH 13/15] cavs: (cosmetic) clean up and simplification of intc_cavs.c 1. don't use "inline" in .c, let the compiler decide 2. remove superfluous parentheses 3. simplify a function by directly returning the result of a boolean operation Signed-off-by: Guennadi Liakhovetski --- drivers/interrupt_controller/intc_cavs.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c index 110e48364ce403..ecb7669423b441 100644 --- a/drivers/interrupt_controller/intc_cavs.c +++ b/drivers/interrupt_controller/intc_cavs.c @@ -67,7 +67,7 @@ static void cavs_ictl_isr(const struct device *port) config->isr_table_offset); } -static inline void cavs_ictl_irq_enable(const struct device *dev, +static void cavs_ictl_irq_enable(const struct device *dev, unsigned int irq) { struct cavs_ictl_runtime *context = dev->data; @@ -75,10 +75,10 @@ static inline void cavs_ictl_irq_enable(const struct device *dev, volatile struct cavs_registers * const regs = (struct cavs_registers *)context->base_addr; - regs->enable_il = (1 << irq); + regs->enable_il = 1 << irq; } -static inline void cavs_ictl_irq_disable(const struct device *dev, +static void cavs_ictl_irq_disable(const struct device *dev, unsigned int irq) { struct cavs_ictl_runtime *context = dev->data; @@ -86,10 +86,10 @@ static inline void cavs_ictl_irq_disable(const struct device *dev, volatile struct cavs_registers * const regs = (struct cavs_registers *)context->base_addr; - regs->disable_il = (1 << irq); + regs->disable_il = 1 << irq; } -static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev) +static unsigned int cavs_ictl_irq_get_state(const struct device *dev) { struct cavs_ictl_runtime *context = dev->data; @@ -100,11 +100,7 @@ static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev) * corresponding interrupts are disabled. This function * returns 0 only if ALL the interrupts are disabled. */ - if (regs->disable_state_il == 0xFFFFFFFF) { - return 0; - } - - return 1; + return regs->disable_state_il != 0xFFFFFFFF; } static int cavs_ictl_irq_get_line_state(const struct device *dev, From 1522087bd489371176b4c78e7185d984028ecfde Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 8 Oct 2020 15:31:18 +0200 Subject: [PATCH 14/15] intel-adsp: disable SMP support in sync with SOF soc/xtensa/intel_adsp/common/include/cavs/cpu.h redefines PLATFORM_CORE_COUNT and PLATFORM_MASTER_CORE_ID which are already defined in SOF. Be careful to avoid conflicts. Ideally one of the two files should be removed. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 2 -- soc/xtensa/intel_adsp/common/include/cavs/memory.h | 1 - 2 files changed, 3 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index faa3f876bae55a..4ba6ee9b422c72 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -6,8 +6,6 @@ #ifndef __INC_MEMORY_H #define __INC_MEMORY_H -#include - /* L2 HP SRAM */ #define HP_RAM_RESERVE_HEADER_SPACE 0x00010000 diff --git a/soc/xtensa/intel_adsp/common/include/cavs/memory.h b/soc/xtensa/intel_adsp/common/include/cavs/memory.h index 2cf8c80473d96d..438175c0faacb0 100644 --- a/soc/xtensa/intel_adsp/common/include/cavs/memory.h +++ b/soc/xtensa/intel_adsp/common/include/cavs/memory.h @@ -90,7 +90,6 @@ /** * FIXME check that correct core count is used */ -#include /* SOF Core S configuration */ #define SRAM_BANK_SIZE (64 * 1024) From 37359f8885a10c9accbcb20d895ad7dbafb79bb1 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 12 Oct 2020 11:49:49 +0200 Subject: [PATCH 15/15] sof: fix logging on cAVS 1.8, 2.0 and 2.5 The logging base address, provided by the LOG_BACKEND_RB_MEM_BASE Kconfig option has been copied from cAVS 1.5, but it's different on versions 1.8, 2.0 and 2.5. This patch fixes logtool functionality on those platforms. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series | 2 +- soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series | 2 +- soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series index b0264aeb785efb..e4348e2f99d058 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series @@ -65,7 +65,7 @@ config LOG_BACKEND_RB default y config LOG_BACKEND_RB_MEM_BASE - default 0xBE000000 + default 0xBE00A000 config LOG_BACKEND_RB_MEM_SIZE default 8192 diff --git a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series index ffae452e6455f9..eb360b11285992 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series @@ -64,7 +64,7 @@ config LOG_BACKEND_RB default y config LOG_BACKEND_RB_MEM_BASE - default 0xBE000000 + default 0xBE00A000 config LOG_BACKEND_RB_MEM_SIZE default 8192 diff --git a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series index 50af7f1cc33ce5..2ab0c99d0de2ab 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series @@ -64,7 +64,7 @@ config LOG_BACKEND_RB default y config LOG_BACKEND_RB_MEM_BASE - default 0xBE000000 + default 0xBE00A000 config LOG_BACKEND_RB_MEM_SIZE default 8192