diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c
index 34dc1d1948cf3f..ecb7669423b441 100644
--- a/drivers/interrupt_controller/intc_cavs.c
+++ b/drivers/interrupt_controller/intc_cavs.c
@@ -67,7 +67,7 @@ static void cavs_ictl_isr(const struct device *port)
 				      config->isr_table_offset);
 }
 
-static inline void cavs_ictl_irq_enable(const struct device *dev,
+static void cavs_ictl_irq_enable(const struct device *dev,
 					unsigned int irq)
 {
 	struct cavs_ictl_runtime *context = dev->data;
@@ -75,10 +75,10 @@ static inline void cavs_ictl_irq_enable(const struct device *dev,
 	volatile struct cavs_registers * const regs =
 			(struct cavs_registers *)context->base_addr;
 
-	regs->enable_il = (1 << irq);
+	regs->enable_il = 1 << irq;
 }
 
-static inline void cavs_ictl_irq_disable(const struct device *dev,
+static void cavs_ictl_irq_disable(const struct device *dev,
 					 unsigned int irq)
 {
 	struct cavs_ictl_runtime *context = dev->data;
@@ -86,10 +86,10 @@ static inline void cavs_ictl_irq_disable(const struct device *dev,
 	volatile struct cavs_registers * const regs =
 			(struct cavs_registers *)context->base_addr;
 
-	regs->disable_il = (1 << irq);
+	regs->disable_il = 1 << irq;
 }
 
-static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev)
+static unsigned int cavs_ictl_irq_get_state(const struct device *dev)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
@@ -100,11 +100,7 @@ static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev)
 	 * corresponding interrupts are disabled. This function
 	 * returns 0 only if ALL the interrupts are disabled.
 	 */
-	if (regs->disable_state_il == 0xFFFFFFFF) {
-		return 0;
-	}
-
-	return 1;
+	return regs->disable_state_il != 0xFFFFFFFF;
 }
 
 static int cavs_ictl_irq_get_line_state(const struct device *dev,
@@ -132,6 +128,11 @@ static const struct irq_next_level_api cavs_apis = {
 #define CAVS_ICTL_INIT(n)						\
 	static int cavs_ictl_##n##_initialize(const struct device *port) \
 	{								\
+		struct cavs_ictl_runtime *context = port->data;		\
+		volatile struct cavs_registers * const regs =		\
+			(struct cavs_registers *)context->base_addr;	\
+		regs->disable_il = ~0;					\
+									\
 		return 0;						\
 	}								\
 									\
diff --git a/modules/Kconfig b/modules/Kconfig
index 632f2456608bb5..90fcf791358b16 100644
--- a/modules/Kconfig
+++ b/modules/Kconfig
@@ -22,6 +22,7 @@ source "modules/Kconfig.nuvoton"
 source "modules/Kconfig.open-amp"
 source "modules/Kconfig.silabs"
 source "modules/Kconfig.simplelink"
+source "modules/Kconfig.sof"
 source "modules/Kconfig.st"
 source "modules/Kconfig.stm32"
 source "modules/Kconfig.syst"
diff --git a/modules/Kconfig.sof b/modules/Kconfig.sof
new file mode 100644
index 00000000000000..66d026b8324827
--- /dev/null
+++ b/modules/Kconfig.sof
@@ -0,0 +1,11 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOF
+	bool "Sound Open Firmware (SOF)"
+	help
+	  Build Sound Open Firmware (SOF) support.
+
+if SOF
+rsource "../../modules/audio/sof/Kconfig"
+endif
\ No newline at end of file
diff --git a/samples/audio/sof/CMakeLists.txt b/samples/audio/sof/CMakeLists.txt
new file mode 100644
index 00000000000000..6f2684a13fc80e
--- /dev/null
+++ b/samples/audio/sof/CMakeLists.txt
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.13.1)
+
+set(sof_module $ENV{ZEPHYR_BASE}/../modules/audio/sof)
+
+# This needs to be before find_package, see
+# https://github.com/zephyrproject-rtos/zephyr/issues/24512
+set(sof_defconfigs ${sof_module}/src/arch)
+if (${BOARD} STREQUAL up_squared_adsp)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/apollolake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs18)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/cannonlake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs20)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/icelake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs25)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/tigerlake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_baytrail)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/baytrail_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_broadwell)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/broadwell_defconfig)
+else ()
+  set(OVERLAY_CONFIG ${sof_defconfigs}/host/configs/library_defconfig)
+  set(ARCH host)
+endif ()
+
+if (NOT DEFINED ARCH)
+  set(ARCH xtensa)
+endif ()
+
+find_package(Zephyr HINTS $ENV{ZEPHYR_BASE})
+project(sample_sof)
+
+target_sources(app PRIVATE
+    src/main.c
+  )
+
+zephyr_interface_library_named(sof_lib)
+
+zephyr_library_include_directories(app PUBLIC
+    ${sof_module}/src/arch/${ARCH}/include
+    ${sof_module}/src/include
+  )
diff --git a/samples/audio/sof/prj.conf b/samples/audio/sof/prj.conf
new file mode 100644
index 00000000000000..e1675706f1e774
--- /dev/null
+++ b/samples/audio/sof/prj.conf
@@ -0,0 +1,5 @@
+CONFIG_SOF=y
+CONFIG_SMP=n
+CONFIG_LOG=y
+CONFIG_MP_NUM_CPUS=1
+CONFIG_BUILD_OUTPUT_BIN=n
diff --git a/samples/audio/sof/src/main.c b/samples/audio/sof/src/main.c
new file mode 100644
index 00000000000000..ee3eba34362d68
--- /dev/null
+++ b/samples/audio/sof/src/main.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include <logging/log.h>
+LOG_MODULE_REGISTER(main, LOG_LEVEL_DBG);
+
+/**
+ * Should be included from sof/schedule/task.h
+ * but triggers include chain issue
+ * FIXME
+ */
+int sof_main(int argc, char *argv[]);
+
+/**
+ * TODO: Here comes SOF initialization
+ */
+
+void main(void)
+{
+	int ret;
+
+	LOG_INF("SOF on %s", CONFIG_BOARD);
+
+	/* sof_main is actually SOF initialization */
+	ret = sof_main(0, NULL);
+	if (ret) {
+		LOG_ERR("SOF initialization failed");
+	}
+
+	LOG_INF("SOF initialized");
+}
diff --git a/scripts/west_commands/sign.py b/scripts/west_commands/sign.py
index d37757c2d4c746..2539b512072d61 100644
--- a/scripts/west_commands/sign.py
+++ b/scripts/west_commands/sign.py
@@ -420,19 +420,34 @@ def sign(self, command, build_dir, bcfg, formats):
         board = cache['CACHED_BOARD']
         log.inf('Signing for board ' + board)
         target = self.edt_get_rimage_target(board)
-        log.inf('Signing for SOC target ' + target)
+        conf = target + '.toml'
+        log.inf('Signing for SOC target ' + target + ' using ' + conf)
 
         if not args.quiet:
             log.inf('Signing with tool {}'.format(tool_path))
 
+        s = pathlib.Path(os.environ.get('ZEPHYR_BASE'))
+
         bootloader = str(b / 'zephyr' / 'bootloader.elf.mod')
         kernel = str(b / 'zephyr' / 'zephyr.elf.mod')
         out_bin = str(b / 'zephyr' / 'zephyr.ri')
+        out_xman = str(b / 'zephyr' / 'zephyr.ri.xman')
+        out_tmp = str(b / 'zephyr' / 'zephyr.rix')
+        conf_path = str(s / '..' / 'modules' / 'audio' / 'sof' / 'rimage' / 'config' / conf)
 
         sign_base = ([tool_path] + args.tool_args +
-                     ['-o', out_bin, '-m', target, '-i', '3'] +
+                     ['-o', out_bin, '-c', conf_path, '-i', '3', '-e'] +
                      [bootloader, kernel])
 
         if not args.quiet:
             log.inf(quote_sh_list(sign_base))
         subprocess.check_call(sign_base)
+
+        filenames = [out_xman, out_bin]
+        with open(out_tmp, 'wb') as outfile:
+            for fname in filenames:
+                with open(fname, 'rb') as infile:
+                    outfile.write(infile.read())
+
+        os.remove(out_bin)
+        os.rename(out_tmp, out_bin)
diff --git a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
index 457a118b743e9b..1c6e0436e0bbdb 100644
--- a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
+++ b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
@@ -14,9 +14,6 @@ config SOC
 config SMP
 	default y
 
-config MP_NUM_CPUS
-	default 2
-
 config XTENSA_TIMER
 	default n
 
@@ -55,12 +52,6 @@ config TEST_LOGGING_DEFAULTS
 	default n
 	depends on TEST
 
-config IPM_CAVS_IDC
-	default y
-
-config IPM
-	default y
-
 if LOG
 
 config LOG_PRINTK
@@ -79,6 +70,15 @@ endif # LOG
 
 if SMP
 
+config MP_NUM_CPUS
+	default 2
+
+config IPM
+       default y
+
+config IPM_CAVS_IDC
+	default y
+
 config SCHED_IPI_SUPPORTED
 	default y if IPM_CAVS_IDC
 
diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
index 616654b588e3d9..d852fb80ad5b4a 100644
--- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
@@ -142,6 +142,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000
diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld
index 08c9d08b7f90c1..29860bd0bacd91 100644
--- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld
@@ -132,6 +132,9 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 }
 
 PHDRS
@@ -161,6 +164,7 @@ PHDRS
   ucram_phdr PT_LOAD;
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 }
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -205,6 +209,11 @@ _memmap_cacheattr_bp_allvalid = 0x22222222;
 _memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);
+
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 SECTIONS
 {
 
@@ -567,4 +576,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }
diff --git a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series
index c4179e404d4c03..e4348e2f99d058 100644
--- a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series
+++ b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series
@@ -11,6 +11,15 @@ config SOC
 	string
 	default "intel_cavs_18"
 
+config SMP
+       default y
+
+config XTENSA_TIMER
+	default n
+
+config CAVS_TIMER
+	default y
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 400000000 if XTENSA_TIMER
 	default 19200000 if CAVS_TIMER
@@ -56,7 +65,7 @@ config LOG_BACKEND_RB
 	default y
 
 config LOG_BACKEND_RB_MEM_BASE
-	default 0xBE000000
+	default 0xBE00A000
 
 config LOG_BACKEND_RB_MEM_SIZE
 	default 8192
@@ -68,12 +77,6 @@ if SMP
 config MP_NUM_CPUS
 	default 2
 
-config XTENSA_TIMER
-	default n
-
-config CAVS_TIMER
-	default y
-
 config IPM
 	default y
 
@@ -83,8 +86,6 @@ config IPM_CAVS_IDC
 config SCHED_IPI_SUPPORTED
 	default y if IPM_CAVS_IDC
 
-endif # SMP
-
 config IPM_INTEL_ADSP
 	default y
 	depends on IPM
@@ -94,4 +95,6 @@ config IPM_CONSOLE
 	depends on CONSOLE
 	depends on IPM
 
+endif # SMP
+
 endif
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
index d496097b4b675f..4ba6ee9b422c72 100644
--- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
@@ -6,8 +6,6 @@
 #ifndef __INC_MEMORY_H
 #define __INC_MEMORY_H
 
-#include <cavs/cpu.h>
-
 /* L2 HP SRAM */
 #define HP_RAM_RESERVE_HEADER_SPACE		0x00010000
 
@@ -127,7 +125,7 @@
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
 /* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 
 /* Manifest size (seems unused). */
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
@@ -139,6 +137,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000
diff --git a/soc/xtensa/intel_adsp/cavs_v18/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld
index 7ab8a51d5fac80..e0141e203fca70 100644
--- a/soc/xtensa/intel_adsp/cavs_v18/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v18/linker.ld
@@ -112,6 +112,9 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 }
 
 PHDRS
@@ -141,6 +144,7 @@ PHDRS
 
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 }
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -194,6 +198,11 @@ _memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2;
 #endif
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);
+
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 SECTIONS
 {
 
@@ -532,4 +541,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }
diff --git a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series
index 4e51a07000ccd4..eb360b11285992 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series
+++ b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series
@@ -11,6 +11,15 @@ config SOC
 	string
 	default "intel_cavs_20"
 
+config SMP
+       default y
+
+config XTENSA_TIMER
+	default n
+
+config CAVS_TIMER
+	default y
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 400000000 if XTENSA_TIMER
 	default 19200000 if CAVS_TIMER
@@ -55,7 +64,7 @@ config LOG_BACKEND_RB
 	default y
 
 config LOG_BACKEND_RB_MEM_BASE
-	default 0xBE000000
+	default 0xBE00A000
 
 config LOG_BACKEND_RB_MEM_SIZE
 	default 8192
@@ -67,12 +76,6 @@ if SMP
 config MP_NUM_CPUS
 	default 2
 
-config XTENSA_TIMER
-	default n
-
-config CAVS_TIMER
-	default y
-
 config IPM
 	default y
 
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
index 1a9983b03dce43..0f96fa22922bd0 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
@@ -127,7 +127,7 @@
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
 /* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 
 /* Manifest size (seems unused). */
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
@@ -139,6 +139,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000
diff --git a/soc/xtensa/intel_adsp/cavs_v20/linker.ld b/soc/xtensa/intel_adsp/cavs_v20/linker.ld
index c24adfeb7c3e5a..b144b121039b71 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v20/linker.ld
@@ -112,8 +112,15 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 }
 
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 PHDRS
 {
   vector_memory_lit_phdr PT_LOAD;
@@ -141,6 +148,7 @@ PHDRS
 
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 }
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -532,4 +540,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }
diff --git a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series
index 3e8a83d2378820..2ab0c99d0de2ab 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series
+++ b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series
@@ -11,6 +11,15 @@ config SOC
 	string
 	default "intel_cavs_25"
 
+config SMP
+       default y
+
+config XTENSA_TIMER
+	default n
+
+config CAVS_TIMER
+	default y
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 400000000 if XTENSA_TIMER
 	default 19200000 if CAVS_TIMER
@@ -55,7 +64,7 @@ config LOG_BACKEND_RB
 	default y
 
 config LOG_BACKEND_RB_MEM_BASE
-	default 0xBE000000
+	default 0xBE00A000
 
 config LOG_BACKEND_RB_MEM_SIZE
 	default 8192
@@ -67,12 +76,6 @@ if SMP
 config MP_NUM_CPUS
 	default 2
 
-config XTENSA_TIMER
-	default n
-
-config CAVS_TIMER
-	default y
-
 config IPM
 	default y
 
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
index 6c448a84189fa2..35dd0fbdfc83f7 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
@@ -127,7 +127,7 @@
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
 /* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 
 /* Manifest size (seems unused). */
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
@@ -139,6 +139,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000
diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld
index 39a4c99b190644..a5c7cb46ea5b85 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld
@@ -112,6 +112,9 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 
   lpsram_alt_reset_vec_seg :
         org = LP_SRAM_ALT_RESET_VEC_BASE,
@@ -154,6 +157,7 @@ PHDRS
 
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 
   lpsram_mem_phdr PT_LOAD;
   sram_alt_fw_reset_vec_phdr PT_LOAD;
@@ -214,6 +218,11 @@ _memmap_cacheattr_intel_cavs25_adsp = 0xFF22FFF2;
 #endif
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);
+
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 SECTIONS
 {
 
@@ -600,4 +609,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }
diff --git a/soc/xtensa/intel_adsp/common/CMakeLists.txt b/soc/xtensa/intel_adsp/common/CMakeLists.txt
index aaf9ad17880c3b..454599990a7935 100644
--- a/soc/xtensa/intel_adsp/common/CMakeLists.txt
+++ b/soc/xtensa/intel_adsp/common/CMakeLists.txt
@@ -27,7 +27,5 @@ if(CONFIG_SOC_SERIES_INTEL_CAVS_V15 OR
    CONFIG_SOC_SERIES_INTEL_CAVS_V18 OR
    CONFIG_SOC_SERIES_INTEL_CAVS_V20 OR
    CONFIG_SOC_SERIES_INTEL_CAVS_V25)
-	zephyr_library_sources(soc.c)
-	zephyr_library_sources(soc_mp.c)
 	include(bootloader.cmake)
 endif()
diff --git a/soc/xtensa/intel_adsp/common/adsp.c b/soc/xtensa/intel_adsp/common/adsp.c
index f5bab48fa892d5..ef526a27854a9e 100644
--- a/soc/xtensa/intel_adsp/common/adsp.c
+++ b/soc/xtensa/intel_adsp/common/adsp.c
@@ -12,44 +12,3 @@
 
 #include <logging/log.h>
 LOG_MODULE_REGISTER(sof);
-
-#include <ipc.h>
-#include <soc/shim.h>
-#include <adsp/io.h>
-
-#include <cavs/mailbox.h>
-
-/*
- * Sets up the host windows so that the host can see the memory
- * content on the DSP SRAM.
- */
-static void prepare_host_windows(void)
-{
-	/* window0, for fw status */
-	sys_write32((HP_SRAM_WIN0_SIZE | 0x7), DMWLO(0));
-	sys_write32((HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE),
-		    DMWBA(0));
-	memset((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), 0,
-	      HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
-	SOC_DCACHE_FLUSH((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
-			 HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
-
-	/* window3, for trace
-	 * zeroed by trace initialization
-	 */
-	sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3));
-	sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE),
-		    DMWBA(3));
-	memset((void *)HP_SRAM_WIN3_BASE, 0, HP_SRAM_WIN3_SIZE);
-	SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
-}
-
-static int adsp_init(const struct device *dev)
-{
-	prepare_host_windows();
-
-	return 0;
-}
-
-/* Init after IPM initialization and before logging (uses memory windows) */
-SYS_INIT(adsp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
index a2f88ff9b61929..3319db295eef86 100644
--- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
+++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
@@ -27,6 +27,7 @@ extern void __start(void);
 
 #if !defined(CONFIG_SOC_INTEL_S1000)
 #define MANIFEST_SEGMENT_COUNT 3
+#undef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 
 static inline void idelay(int n)
 {
@@ -125,6 +126,7 @@ static void parse_module(struct sof_man_fw_header *hdr,
 #define MAN_SKIP_ENTRIES 1
 #endif
 
+#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 static uint32_t get_fw_size_in_use(void)
 {
 	struct sof_man_fw_desc *desc =
@@ -153,6 +155,7 @@ static uint32_t get_fw_size_in_use(void)
 
 	return fw_size_in_use;
 }
+#endif
 
 /* parse FW manifest and copy modules */
 static void parse_manifest(void)
@@ -256,11 +259,13 @@ static uint32_t hp_sram_power_on_memory(uint32_t memory_size)
 	return hp_sram_pm_banks(ebb_in_use);
 }
 
+#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
 {
 	/* keep enabled only memory banks used by FW */
 	return hp_sram_power_on_memory(memory_size);
 }
+#endif
 
 static int32_t hp_sram_init(void)
 {
@@ -269,10 +274,12 @@ static int32_t hp_sram_init(void)
 
 #else
 
+#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
 {
 	return 0;
 }
+#endif
 
 static uint32_t hp_sram_init(void)
 {
@@ -340,7 +347,9 @@ void boot_master_core(void)
 	/* parse manifest and copy modules */
 	parse_manifest();
 
+#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 	hp_sram_power_off_unused_banks(get_fw_size_in_use());
+#endif
 #endif
 	/* now call SOF entry */
 	__start();
diff --git a/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h b/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h
deleted file mode 100644
index fe06ab66037990..00000000000000
--- a/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: Apache-2.0
- *
- * Copyright(c) 2019 Intel Corporation. All rights reserved.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *         Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __CAVS_MAILBOX_H__
-#define __CAVS_MAILBOX_H__
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The Window Region on HPSRAM for cAVS platforms is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset              | Region         |  Size                             |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE     | Trace Buffer W3|  SRAM_TRACE_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE     | Debug data  W2 |  SRAM_DEBUG_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE     | Inbox  W1      |  SRAM_INBOX_SIZE                  |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE    | Outbox W0      |  SRAM_MAILBOX_SIZE                |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_SW_REG_BASE    | SW Registers W0|  SRAM_SW_REG_SIZE                 |
- * +---------------------+----------------+-----------------------------------+
- *
- * Note: For suecreek SRAM_SW_REG window does not exist - MAILBOX_SW_REG_BASE
- *	 and MAILBOX_SW_REG_BASE are equal to 0
- */
-
- /* window 3 - trace */
-#define MAILBOX_TRACE_SIZE	SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE	SRAM_TRACE_BASE
-
- /* window 2 debug, exception and stream */
-#define MAILBOX_DEBUG_SIZE	SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE	SRAM_DEBUG_BASE
-
-#define MAILBOX_EXCEPTION_SIZE	SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE	SRAM_EXCEPT_BASE
-#define MAILBOX_EXCEPTION_OFFSET  SRAM_DEBUG_SIZE
-
-#define MAILBOX_STREAM_SIZE    SRAM_STREAM_SIZE
-#define MAILBOX_STREAM_BASE    SRAM_STREAM_BASE
-#define MAILBOX_STREAM_OFFSET  (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
-
- /* window 1 inbox/downlink and FW registers */
-#define MAILBOX_HOSTBOX_SIZE	SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE	SRAM_INBOX_BASE
-
- /* window 0 */
-#define MAILBOX_DSPBOX_SIZE	SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE	SRAM_OUTBOX_BASE
-
-#define MAILBOX_SW_REG_SIZE	SRAM_SW_REG_SIZE
-#define MAILBOX_SW_REG_BASE	SRAM_SW_REG_BASE
-
-#endif /* __CAVS_MAILBOX_H__ */
diff --git a/soc/xtensa/intel_adsp/common/include/cavs/memory.h b/soc/xtensa/intel_adsp/common/include/cavs/memory.h
new file mode 100644
index 00000000000000..438175c0faacb0
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/include/cavs/memory.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2019 Intel Corporation. All rights reserved.
+ *
+ * Author: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
+ */
+
+#ifndef __CAVS_MEMORY_H__
+#define __CAVS_MEMORY_H__
+
+#include <adsp/cache.h>
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
+#include <stdint.h>
+#include <cavs/cpu.h>
+#endif
+
+#define DCACHE_LINE_SIZE	XCHAL_DCACHE_LINESIZE
+
+/* data cache line alignment */
+#define PLATFORM_DCACHE_ALIGN	DCACHE_LINE_SIZE
+
+#define SRAM_BANK_SIZE			(64 * 1024)
+
+#define EBB_BANKS_IN_SEGMENT		32
+
+#define EBB_SEGMENT_SIZE		EBB_BANKS_IN_SEGMENT
+
+#if CONFIG_LP_MEMORY_BANKS
+#define PLATFORM_LPSRAM_EBB_COUNT	CONFIG_LP_MEMORY_BANKS
+#else
+#define PLATFORM_LPSRAM_EBB_COUNT	0
+#endif
+
+#define PLATFORM_HPSRAM_EBB_COUNT	CONFIG_HP_MEMORY_BANKS
+
+#define MAX_MEMORY_SEGMENTS		PLATFORM_HPSRAM_SEGMENTS
+
+#if CONFIG_LP_MEMORY_BANKS
+#define LP_SRAM_SIZE \
+	(CONFIG_LP_MEMORY_BANKS * SRAM_BANK_SIZE)
+#else
+#define LP_SRAM_SIZE 0
+#endif
+
+#define HP_SRAM_SIZE \
+	(CONFIG_HP_MEMORY_BANKS * SRAM_BANK_SIZE)
+
+#define PLATFORM_HPSRAM_SEGMENTS	((PLATFORM_HPSRAM_EBB_COUNT \
+	+ EBB_BANKS_IN_SEGMENT - 1) / EBB_BANKS_IN_SEGMENT)
+
+#if defined(__ASSEMBLER__)
+#define LPSRAM_MASK(ignored)	((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1)
+
+#define HPSRAM_MASK(seg_idx)	((1 << (PLATFORM_HPSRAM_EBB_COUNT \
+	- EBB_BANKS_IN_SEGMENT * seg_idx)) - 1)
+#else
+#define LPSRAM_MASK(ignored)	((1ULL << PLATFORM_LPSRAM_EBB_COUNT) - 1)
+
+#define HPSRAM_MASK(seg_idx)	((1ULL << (PLATFORM_HPSRAM_EBB_COUNT \
+	- EBB_BANKS_IN_SEGMENT * seg_idx)) - 1)
+#endif
+
+#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * SRAM_BANK_SIZE)
+
+#define HEAP_BUF_ALIGNMENT		PLATFORM_DCACHE_ALIGN
+
+/** \brief EDF task's default stack size in bytes. */
+#define PLATFORM_TASK_DEFAULT_STACK_SIZE	0x1000
+
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
+
+/**
+ * \brief Data shared between different cores.
+ * Placed into dedicated section, which should be accessed through
+ * uncached memory region. SMP platforms without uncache can simply
+ * align to cache line size instead.
+ */
+#if PLATFORM_CORE_COUNT > 1 && !defined(UNIT_TEST)
+#define SHARED_DATA	__section(".shared_data")
+#else
+#define SHARED_DATA
+#endif
+
+#define SRAM_ALIAS_BASE		0x9E000000
+#define SRAM_ALIAS_MASK		0xFF000000
+#define SRAM_ALIAS_OFFSET	0x20000000
+
+#endif
+
+/**
+ * FIXME check that correct core count is used
+ */
+/* SOF Core S configuration */
+#define SRAM_BANK_SIZE		(64 * 1024)
+
+/* low power sequencer */
+#define LPS_RESTORE_VECTOR_OFFSET 0x1000
+#define LPS_RESTORE_VECTOR_SIZE 0x800
+#define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET)
+
+#endif /* __CAVS_MEMORY_H__ */
diff --git a/soc/xtensa/intel_adsp/common/include/soc.h b/soc/xtensa/intel_adsp/common/include/soc.h
index 0cfbf0815c63f7..4fc9b6c7df0d12 100644
--- a/soc/xtensa/intel_adsp/common/include/soc.h
+++ b/soc/xtensa/intel_adsp/common/include/soc.h
@@ -7,6 +7,8 @@
 #include <string.h>
 #include <errno.h>
 
+#include <cavs/version.h>
+
 #include <sys/sys_io.h>
 
 #include <adsp/cache.h>
@@ -61,10 +63,14 @@
 #define SSP_MN_DIV_BASE(x)			\
 	(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
 
-#define PDM_BASE				0x00010000
+#define PDM_BASE				DMIC_BASE
 
 /* SOC DSP SHIM Registers */
+#if CAVS_VERSION == CAVS_VERSION_1_5
 #define SOC_DSP_SHIM_REG_BASE			0x00001000
+#else
+#define SOC_DSP_SHIM_REG_BASE			0x00071f00
+#endif
 
 /* SOC DSP SHIM Register - Clock Control */
 #define SOC_CLKCTL_REQ_AUDIO_PLL_CLK		BIT(31)
diff --git a/soc/xtensa/intel_adsp/common/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c
index 5c0b811a7ee48c..f56c05f95d2897 100644
--- a/soc/xtensa/intel_adsp/common/soc_mp.c
+++ b/soc/xtensa/intel_adsp/common/soc_mp.c
@@ -25,7 +25,7 @@ LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL);
 #include <drivers/ipm.h>
 #include <ipm/ipm_cavs_idc.h>
 
-#if CONFIG_MP_NUM_CPUS > 1 && !defined(CONFIG_IPM_CAVS_IDC)
+#if CONFIG_MP_NUM_CPUS > 1 && !defined(CONFIG_IPM_CAVS_IDC) && defined(CONFIG_SMP)
 #error Need to enable the IPM driver for multiprocessing
 #endif
 
diff --git a/west.yml b/west.yml
index b57877bcf0f378..8867bac93953c7 100644
--- a/west.yml
+++ b/west.yml
@@ -21,6 +21,8 @@ manifest:
   remotes:
     - name: upstream
       url-base: https://github.com/zephyrproject-rtos
+    - name: thesofproject
+      url-base: https://github.com/thesofproject
 
   #
   # Please add items below based on alphabetical order
@@ -140,6 +142,10 @@ manifest:
     - name: trusted-firmware-m
       path: modules/tee/tfm
       revision: bb15a511a509c81135af61e02f9f4bfaf86d7fde
+    - name: sof
+      remote: thesofproject
+      revision: stable-v1.6
+      path: modules/audio/sof
 
   self:
     path: zephyr