diff --git a/drivers/adc/adc_sam_afec.c b/drivers/adc/adc_sam_afec.c index f993265bd0640e..5e37312ac9999f 100644 --- a/drivers/adc/adc_sam_afec.c +++ b/drivers/adc/adc_sam_afec.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#define DT_DRV_COMPAT atmel_sam_afec + /** @file * @brief Atmel SAM MCU family ADC (AFEC) driver. * @@ -347,60 +349,34 @@ static void adc_sam_isr(void *arg) } } -#ifdef CONFIG_ADC_0 -static void adc0_sam_cfg_func(struct device *dev); - -static const struct adc_sam_cfg adc0_sam_cfg = { - .regs = (Afec *)DT_ADC_0_BASE_ADDRESS, - .cfg_func = adc0_sam_cfg_func, - .periph_id = DT_ADC_0_PERIPHERAL_ID, - .afec_trg_pin = PIN_AFE0_ADTRG, -}; - -static struct adc_sam_data adc0_sam_data = { - ADC_CONTEXT_INIT_TIMER(adc0_sam_data, ctx), - ADC_CONTEXT_INIT_LOCK(adc0_sam_data, ctx), - ADC_CONTEXT_INIT_SYNC(adc0_sam_data, ctx), -}; - -DEVICE_AND_API_INIT(adc0_sam, DT_ADC_0_NAME, adc_sam_init, - &adc0_sam_data, &adc0_sam_cfg, POST_KERNEL, - CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &adc_sam_api); - -static void adc0_sam_cfg_func(struct device *dev) -{ - IRQ_CONNECT(DT_ADC_0_IRQ, DT_ADC_0_IRQ_PRI, adc_sam_isr, - DEVICE_GET(adc0_sam), 0); - irq_enable(DT_ADC_0_IRQ); -} - -#endif /* CONFIG_ADC_0 */ - -#ifdef CONFIG_ADC_1 -static void adc1_sam_cfg_func(struct device *dev); - -static const struct adc_sam_cfg adc1_sam_cfg = { - .regs = (Afec *)DT_ADC_1_BASE_ADDRESS, - .cfg_func = adc1_sam_cfg_func, - .periph_id = DT_ADC_1_PERIPHERAL_ID, - .afec_trg_pin = PIN_AFE1_ADTRG, -}; - -static struct adc_sam_data adc1_sam_data = { - ADC_CONTEXT_INIT_TIMER(adc1_sam_data, ctx), - ADC_CONTEXT_INIT_LOCK(adc1_sam_data, ctx), - ADC_CONTEXT_INIT_SYNC(adc1_sam_data, ctx), -}; - -DEVICE_AND_API_INIT(adc1_sam, DT_ADC_1_NAME, adc_sam_init, - &adc1_sam_data, &adc1_sam_cfg, POST_KERNEL, - CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &adc_sam_api); - -static void adc1_sam_cfg_func(struct device *dev) -{ - IRQ_CONNECT(DT_ADC_1_IRQ, DT_ADC_1_IRQ_PRI, adc_sam_isr, - DEVICE_GET(adc1_sam), 0); - irq_enable(DT_ADC_1_IRQ); -} +#define ADC_SAM_INIT(n) \ + static void adc##n##_sam_cfg_func(struct device *dev); \ + \ + static const struct adc_sam_cfg adc##n##_sam_cfg = { \ + .regs = (Afec *)DT_INST_REG_ADDR(n), \ + .cfg_func = adc##n##_sam_cfg_func, \ + .periph_id = DT_INST_PROP(n, peripheral_id), \ + .afec_trg_pin = ATMEL_SAM_DT_PIN(n, 0), \ + }; \ + \ + static struct adc_sam_data adc##n##_sam_data = { \ + ADC_CONTEXT_INIT_TIMER(adc##n##_sam_data, ctx), \ + ADC_CONTEXT_INIT_LOCK(adc##n##_sam_data, ctx), \ + ADC_CONTEXT_INIT_SYNC(adc##n##_sam_data, ctx), \ + }; \ + \ + DEVICE_AND_API_INIT(adc##n##_sam, DT_INST_LABEL(n), \ + adc_sam_init, &adc##n##_sam_data, \ + &adc##n##_sam_cfg, POST_KERNEL, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ + &adc_sam_api); \ + \ + static void adc##n##_sam_cfg_func(struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ + adc_sam_isr, \ + DEVICE_GET(adc##n##_sam), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } -#endif /* CONFIG_ADC_1 */ +DT_INST_FOREACH(ADC_SAM_INIT) diff --git a/dts/arm/atmel/same70-pinctrl.dtsi b/dts/arm/atmel/same70-pinctrl.dtsi index c547453eb4d516..0ddfc075cd5147 100644 --- a/dts/arm/atmel/same70-pinctrl.dtsi +++ b/dts/arm/atmel/same70-pinctrl.dtsi @@ -10,6 +10,8 @@ soc { pinctrl@400e0e00 { /* instance, signal, pio, pin, peripheral */ + DT_ATMEL_PIN(afec0, adtrg, a, 8, b); + DT_ATMEL_PIN(afec1, adtrg, d, 9, c); DT_ATMEL_PIN(twihs0, twck0, a, 4, a); DT_ATMEL_PIN(twihs0, twd0, a, 3, a); DT_ATMEL_PIN(twihs1, twck1, b, 5, a); diff --git a/dts/arm/atmel/same70.dtsi b/dts/arm/atmel/same70.dtsi index 1e751afd7b3bb9..80c8f09eedc994 100644 --- a/dts/arm/atmel/same70.dtsi +++ b/dts/arm/atmel/same70.dtsi @@ -218,6 +218,7 @@ status = "disabled"; label = "ADC_0"; #io-channel-cells = <1>; + pinctrl-0 = <&pa8b_afec0_adtrg>; }; afec1: adc@40064000 { @@ -228,6 +229,7 @@ status = "disabled"; label = "ADC_1"; #io-channel-cells = <1>; + pinctrl-0 = <&pd9c_afec1_adtrg>; }; pinctrl@400e0e00 { diff --git a/dts/bindings/iio/adc/atmel,sam-afec.yaml b/dts/bindings/iio/adc/atmel,sam-afec.yaml index 45382f97fa1a95..1f468fa820b0f8 100644 --- a/dts/bindings/iio/adc/atmel,sam-afec.yaml +++ b/dts/bindings/iio/adc/atmel,sam-afec.yaml @@ -19,5 +19,17 @@ properties: "#io-channel-cells": const: 1 + pinctrl-0: + type: phandles + required: true + description: | + PIO pin configuration for ADTRG signal. We expect that + the phandles will reference pinctrl nodes. These nodes will + have a nodelabel that matches the Atmel SoC HAL defines and + be of the form p__. + + For example the I2C on SAME7x would be + pinctrl-0 = <&pa8b_afec0_adtrg>; + io-channel-cells: - input diff --git a/soc/arm/atmel_sam/same70/dts_fixup.h b/soc/arm/atmel_sam/same70/dts_fixup.h index 730c4684ccd77b..61af347bc270f6 100644 --- a/soc/arm/atmel_sam/same70/dts_fixup.h +++ b/soc/arm/atmel_sam/same70/dts_fixup.h @@ -48,17 +48,8 @@ #define DT_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY #define DT_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID -#define DT_ADC_0_BASE_ADDRESS DT_ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS -#define DT_ADC_0_IRQ DT_ATMEL_SAM_AFEC_4003C000_IRQ_0 -#define DT_ADC_0_IRQ_PRI DT_ATMEL_SAM_AFEC_4003C000_IRQ_0_PRIORITY #define DT_ADC_0_NAME DT_ATMEL_SAM_AFEC_4003C000_LABEL -#define DT_ADC_0_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_4003C000_PERIPHERAL_ID - -#define DT_ADC_1_BASE_ADDRESS DT_ATMEL_SAM_AFEC_40064000_BASE_ADDRESS -#define DT_ADC_1_IRQ DT_ATMEL_SAM_AFEC_40064000_IRQ_0 -#define DT_ADC_1_IRQ_PRI DT_ATMEL_SAM_AFEC_40064000_IRQ_0_PRIORITY #define DT_ADC_1_NAME DT_ATMEL_SAM_AFEC_40064000_LABEL -#define DT_ADC_1_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_40064000_PERIPHERAL_ID #define DT_USBHS_IRQ DT_ATMEL_SAM_USBHS_40038000_IRQ_0 #define DT_USBHS_IRQ_PRI DT_ATMEL_SAM_USBHS_40038000_IRQ_0_PRIORITY diff --git a/soc/arm/atmel_sam/same70/soc_pinmap.h b/soc/arm/atmel_sam/same70/soc_pinmap.h index 8310d72a3d67bb..c56fbe1ea81bb3 100644 --- a/soc/arm/atmel_sam/same70/soc_pinmap.h +++ b/soc/arm/atmel_sam/same70/soc_pinmap.h @@ -15,11 +15,6 @@ #include -/* Analog to Digital Converter (AFEC) */ - -#define PIN_AFE0_ADTRG {PIO_PA8B_AFEC0_ADTRG, PIOA, ID_PIOA, SOC_GPIO_FUNC_B} -#define PIN_AFE1_ADTRG {PIO_PD9C_AFEC1_ADTRG, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} - /* Ethernet MAC (GMAC) */ #define PINS_GMAC_MASK (PIO_PD0A_GMAC_GTXCK | PIO_PD1A_GMAC_GTXEN \ diff --git a/soc/arm/atmel_sam/samv71/dts_fixup.h b/soc/arm/atmel_sam/samv71/dts_fixup.h index 527d63d815eb3e..d465bdd826ab24 100644 --- a/soc/arm/atmel_sam/samv71/dts_fixup.h +++ b/soc/arm/atmel_sam/samv71/dts_fixup.h @@ -52,17 +52,8 @@ #define DT_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY #define DT_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID -#define DT_ADC_0_BASE_ADDRESS DT_ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS -#define DT_ADC_0_IRQ DT_ATMEL_SAM_AFEC_4003C000_IRQ_0 -#define DT_ADC_0_IRQ_PRI DT_ATMEL_SAM_AFEC_4003C000_IRQ_0_PRIORITY #define DT_ADC_0_NAME DT_ATMEL_SAM_AFEC_4003C000_LABEL -#define DT_ADC_0_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_4003C000_PERIPHERAL_ID - -#define DT_ADC_1_BASE_ADDRESS DT_ATMEL_SAM_AFEC_40064000_BASE_ADDRESS -#define DT_ADC_1_IRQ DT_ATMEL_SAM_AFEC_40064000_IRQ_0 -#define DT_ADC_1_IRQ_PRI DT_ATMEL_SAM_AFEC_40064000_IRQ_0_PRIORITY #define DT_ADC_1_NAME DT_ATMEL_SAM_AFEC_40064000_LABEL -#define DT_ADC_1_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_40064000_PERIPHERAL_ID #define DT_USBHS_IRQ DT_ATMEL_SAM_USBHS_40038000_IRQ_0 #define DT_USBHS_IRQ_PRI DT_ATMEL_SAM_USBHS_40038000_IRQ_0_PRIORITY diff --git a/soc/arm/atmel_sam/samv71/soc_pinmap.h b/soc/arm/atmel_sam/samv71/soc_pinmap.h index 455c3282b261d8..1cb270840f1880 100644 --- a/soc/arm/atmel_sam/samv71/soc_pinmap.h +++ b/soc/arm/atmel_sam/samv71/soc_pinmap.h @@ -16,11 +16,6 @@ #include -/* Analog to Digital Converter (AFEC) */ - -#define PIN_AFE0_ADTRG {PIO_PA8B_AFEC0_ADTRG, PIOA, ID_PIOA, SOC_GPIO_FUNC_B} -#define PIN_AFE1_ADTRG {PIO_PD9C_AFEC1_ADTRG, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} - /* Ethernet MAC (GMAC) */ #define PINS_GMAC_MASK (PIO_PD0A_GMAC_GTXCK | PIO_PD1A_GMAC_GTXEN \