From e89f368ca05fec49264d9c4a1f6ee02736697168 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Thu, 5 Mar 2020 09:48:59 +0900 Subject: [PATCH 1/7] dts: atmel: Add SAM E5x GMAC instance This commit adds a GMAC instance to the SAM E5x device tree, along with the refactoring necessary to specify the SAM E5x-specific components. Signed-off-by: Stephanos Ioannidis --- dts/arm/atmel/same5x.dtsi | 22 ++++++++++++++++++++++ dts/arm/atmel/same5xx18.dtsi | 17 ++++++++++++++++- dts/arm/atmel/same5xx19.dtsi | 17 ++++++++++++++++- dts/arm/atmel/same5xx20.dtsi | 17 ++++++++++++++++- 4 files changed, 70 insertions(+), 3 deletions(-) create mode 100644 dts/arm/atmel/same5x.dtsi diff --git a/dts/arm/atmel/same5x.dtsi b/dts/arm/atmel/same5x.dtsi new file mode 100644 index 00000000000000..578d9dcb6b090b --- /dev/null +++ b/dts/arm/atmel/same5x.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + gmac: ethernet@42000800 { + compatible = "atmel,sam-gmac"; + reg = <0x42000800 0x400>; + interrupts = <84 0>; + interrupt-names = "gmac"; + num-queues = <1>; + local-mac-address = [00 00 00 00 00 00]; + label = "GMAC"; + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/atmel/same5xx18.dtsi b/dts/arm/atmel/same5xx18.dtsi index 03587b55761010..34edf4c7fb114e 100644 --- a/dts/arm/atmel/same5xx18.dtsi +++ b/dts/arm/atmel/same5xx18.dtsi @@ -4,4 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include +#include + +/ { + soc { + nvmctrl@41004000 { + flash0: flash@0 { + reg = <0x0 DT_SIZE_K(256)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(128)>; + }; + }; +}; diff --git a/dts/arm/atmel/same5xx19.dtsi b/dts/arm/atmel/same5xx19.dtsi index 697d2495b9f9bc..4c69e63a400cf7 100644 --- a/dts/arm/atmel/same5xx19.dtsi +++ b/dts/arm/atmel/same5xx19.dtsi @@ -4,4 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include +#include + +/ { + soc { + nvmctrl@41004000 { + flash0: flash@0 { + reg = <0x0 DT_SIZE_K(512)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(192)>; + }; + }; +}; diff --git a/dts/arm/atmel/same5xx20.dtsi b/dts/arm/atmel/same5xx20.dtsi index c76189e742e801..944668f05aa67e 100644 --- a/dts/arm/atmel/same5xx20.dtsi +++ b/dts/arm/atmel/same5xx20.dtsi @@ -4,4 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include +#include + +/ { + soc { + nvmctrl@41004000 { + flash0: flash@0 { + reg = <0x0 DT_SIZE_K(1024)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(256)>; + }; + }; +}; From 73f86eac0d758b6b8f1c9c10fa7216e90fa6b918 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Thu, 5 Mar 2020 09:55:09 +0900 Subject: [PATCH 2/7] boards: atsame54_xpro: Enable GMAC in device tree This commit enables the GMAC (Ethernet) instance in the `atsame54_xpro` device tree. Signed-off-by: Stephanos Ioannidis --- boards/arm/atsame54_xpro/atsame54_xpro.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/boards/arm/atsame54_xpro/atsame54_xpro.dts b/boards/arm/atsame54_xpro/atsame54_xpro.dts index 7db8aae8f4e656..b2118a9b22fc01 100644 --- a/boards/arm/atsame54_xpro/atsame54_xpro.dts +++ b/boards/arm/atsame54_xpro/atsame54_xpro.dts @@ -81,3 +81,7 @@ &usb0 { status = "okay"; }; + +&gmac { + status = "okay"; +}; From 26538e38d69fedebe74b67f923daf6baff9ca397 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Fri, 6 Mar 2020 01:51:44 +0900 Subject: [PATCH 3/7] soc: atmel_sam0: Add GMAC fix-up for SAM D/E5x This commit adds the MCLK clock configuration symbol fix-up for the GMAC peripheral. The APB-agnostic clock configuration fix-up symbols map to the SoC-specific APB, in order to accommodate different SoC variants with the GMAC on different APBs. Signed-off-by: Stephanos Ioannidis --- soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h | 27 +++++++++++++++++++ soc/arm/atmel_sam0/same53/soc.h | 1 + soc/arm/atmel_sam0/same54/soc.h | 1 + 3 files changed, 29 insertions(+) create mode 100644 soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h diff --git a/soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h b/soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h new file mode 100644 index 00000000000000..8a21adfecf7c74 --- /dev/null +++ b/soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * The following GMAC clock configuration fix-up symbols map to the applicable + * APB-specific symbols, in order to accommodate different SoC series with the + * GMAC core connected to different APBs. + */ +#ifdef MCLK_APBAMASK_GMAC +#define MCLK_GMAC (&MCLK->APBAMASK.reg) +#define MCLK_GMAC_MASK (MCLK_APBAMASK_GMAC) +#endif +#ifdef MCLK_APBBMASK_GMAC +#define MCLK_GMAC (&MCLK->APBBMASK.reg) +#define MCLK_GMAC_MASK (MCLK_APBBMASK_GMAC) +#endif +#ifdef MCLK_APBCMASK_GMAC +#define MCLK_GMAC (&MCLK->APBCMASK.reg) +#define MCLK_GMAC_MASK (MCLK_APBCMASK_GMAC) +#endif +#ifdef MCLK_APBDMASK_GMAC +#define MCLK_GMAC (&MCLK->APBDMASK.reg) +#define MCLK_GMAC_MASK (MCLK_APBDMASK_GMAC) +#endif diff --git a/soc/arm/atmel_sam0/same53/soc.h b/soc/arm/atmel_sam0/same53/soc.h index e53f267dd0769b..8eb9ca427e626c 100644 --- a/soc/arm/atmel_sam0/same53/soc.h +++ b/soc/arm/atmel_sam0/same53/soc.h @@ -31,6 +31,7 @@ #include "sercom_fixup_samd5x.h" #include "tc_fixup_samd5x.h" +#include "gmac_fixup_samd5x.h" #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 diff --git a/soc/arm/atmel_sam0/same54/soc.h b/soc/arm/atmel_sam0/same54/soc.h index f8aa4e8b0422e7..6de7230652e738 100644 --- a/soc/arm/atmel_sam0/same54/soc.h +++ b/soc/arm/atmel_sam0/same54/soc.h @@ -29,6 +29,7 @@ #include "sercom_fixup_samd5x.h" #include "tc_fixup_samd5x.h" +#include "gmac_fixup_samd5x.h" #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 From 116338db5bed85b0fab1187ff9e0a910bbcd4197 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Fri, 6 Mar 2020 02:08:44 +0900 Subject: [PATCH 4/7] drivers: ethernet: eth_sam_gmac: Add SAM0 family support This commit adds the GMAC driver support for the Ethernet-capable SAM0 family devices (SAM E53 and E54 at this time). Signed-off-by: Stephanos Ioannidis --- drivers/ethernet/eth_sam0_gmac.h | 134 +++++++++++++++++++++++++++++++ drivers/ethernet/eth_sam_gmac.c | 26 +++++- drivers/ethernet/phy_sam_gmac.c | 4 + 3 files changed, 162 insertions(+), 2 deletions(-) create mode 100644 drivers/ethernet/eth_sam0_gmac.h diff --git a/drivers/ethernet/eth_sam0_gmac.h b/drivers/ethernet/eth_sam0_gmac.h new file mode 100644 index 00000000000000..452ab388ef2b83 --- /dev/null +++ b/drivers/ethernet/eth_sam0_gmac.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_ +#define ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_ + +/* + * Map the SAM-family DFP GMAC register names to the SAM0-family DFP GMAC + * register names. + */ +#define GMAC_NCR NCR.reg +#define GMAC_NCFGR NCFGR.reg +#define GMAC_NSR NSR.reg +#define GMAC_UR UR.reg +#define GMAC_DCFGR DCFGR.reg +#define GMAC_TSR TSR.reg +#define GMAC_RBQB RBQB.reg +#define GMAC_TBQB TBQB.reg +#define GMAC_RSR RSR.reg +#define GMAC_ISR ISR.reg +#define GMAC_IER IER.reg +#define GMAC_IDR IDR.reg +#define GMAC_IMR IMR.reg +#define GMAC_MAN MAN.reg +#define GMAC_RPQ RPQ.reg +#define GMAC_TPQ TPQ.reg +#define GMAC_TPSF TPSF.reg +#define GMAC_RPSF RPSF.reg +#define GMAC_RJFML RJFML.reg +#define GMAC_HRB HRB.reg +#define GMAC_HRT HRT.reg +#define GMAC_SA Sa +#define GMAC_WOL WOL.reg +#define GMAC_IPGS IPGS.reg +#define GMAC_SVLAN SVLAN.reg +#define GMAC_TPFCP TPFCP.reg +#define GMAC_SAMB1 SAMB1.reg +#define GMAC_SAMT1 SAMT1.reg +#define GMAC_NSC NSC.reg +#define GMAC_SCL SCL.reg +#define GMAC_SCH SCH.reg +#define GMAC_EFTSH EFTSH.reg +#define GMAC_EFRSH EFRSH.reg +#define GMAC_PEFTSH PEFTSH.reg +#define GMAC_PEFRSH PEFRSH.reg +#define GMAC_OTLO OTLO.reg +#define GMAC_OTHI OTHI.reg +#define GMAC_FT FT.reg +#define GMAC_BCFT BCFT.reg +#define GMAC_MFT MFT.reg +#define GMAC_PFT PFT.reg +#define GMAC_BFT64 BFT64.reg +#define GMAC_TBFT127 TBFT127.reg +#define GMAC_TBFT255 TBFT255.reg +#define GMAC_TBFT511 TBFT511.reg +#define GMAC_TBFT1023 TBFT1023.reg +#define GMAC_TBFT1518 TBFT1518.reg +#define GMAC_GTBFT1518 GTBFT1518.reg +#define GMAC_TUR TUR.reg +#define GMAC_SCF SCF.reg +#define GMAC_MCF MCF.reg +#define GMAC_EC EC.reg +#define GMAC_LC LC.reg +#define GMAC_DTF DTF.reg +#define GMAC_CSE CSE.reg +#define GMAC_ORLO ORLO.reg +#define GMAC_ORHI ORHI.reg +#define GMAC_FR FR.reg +#define GMAC_BCFR BCFR.reg +#define GMAC_MFR MFR.reg +#define GMAC_PFR PFR.reg +#define GMAC_BFR64 BFR64.reg +#define GMAC_TBFR127 TBFR127.reg +#define GMAC_TBFR255 TBFR255.reg +#define GMAC_TBFR511 TBFR511.reg +#define GMAC_TBFR1023 TBFR1023.reg +#define GMAC_TBFR1518 TBFR1518.reg +#define GMAC_TMXBFR TMXBFR.reg +#define GMAC_UFR UFR.reg +#define GMAC_OFR OFR.reg +#define GMAC_JR JR.reg +#define GMAC_FCSE FCSE.reg +#define GMAC_LFFE LFFE.reg +#define GMAC_RSE RSE.reg +#define GMAC_AE AE.reg +#define GMAC_RRE RRE.reg +#define GMAC_ROE ROE.reg +#define GMAC_IHCE IHCE.reg +#define GMAC_TCE TCE.reg +#define GMAC_UCE UCE.reg +#define GMAC_TISUBN TISUBN.reg +#define GMAC_TSH TSH.reg +#define GMAC_TSSSL TSSSL.reg +#define GMAC_TSSN TSSN.reg +#define GMAC_TSL TSL.reg +#define GMAC_TN TN.reg +#define GMAC_TA TA.reg +#define GMAC_TI TI.reg +#define GMAC_EFTSL EFTSL.reg +#define GMAC_EFTN EFTN.reg +#define GMAC_EFRSL EFRSL.reg +#define GMAC_EFRN EFRN.reg +#define GMAC_PEFTSL PEFTSL.reg +#define GMAC_PEFTN PEFTN.reg +#define GMAC_PEFRSL PEFRSL.reg +#define GMAC_PEFRN PEFRN.reg +#define GMAC_RLPITR RLPITR.reg +#define GMAC_RLPITI RLPITI.reg +#define GMAC_TLPITR TLPITR.reg +#define GMAC_TLPITI TLPITI.reg + +#define GMAC_SAB SAB.reg +#define GMAC_SAT SAT.reg + +/* + * Define the register field value symbols that are missing in the SAM0-family + * DFP GMAC headers. + */ +#define GMAC_NCFGR_CLK_MCK_8 GMAC_NCFGR_CLK(0) +#define GMAC_NCFGR_CLK_MCK_16 GMAC_NCFGR_CLK(1) +#define GMAC_NCFGR_CLK_MCK_32 GMAC_NCFGR_CLK(2) +#define GMAC_NCFGR_CLK_MCK_48 GMAC_NCFGR_CLK(3) +#define GMAC_NCFGR_CLK_MCK_64 GMAC_NCFGR_CLK(4) +#define GMAC_NCFGR_CLK_MCK_96 GMAC_NCFGR_CLK(5) + +#define GMAC_DCFGR_FBLDO_SINGLE GMAC_DCFGR_FBLDO(1) +#define GMAC_DCFGR_FBLDO_INCR4 GMAC_DCFGR_FBLDO(2) +#define GMAC_DCFGR_FBLDO_INCR8 GMAC_DCFGR_FBLDO(3) +#define GMAC_DCFGR_FBLDO_INCR16 GMAC_DCFGR_FBLDO(4) + +#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_ */ diff --git a/drivers/ethernet/eth_sam_gmac.c b/drivers/ethernet/eth_sam_gmac.c index 1e6b01f17bce42..d71b08e2ffbf5f 100644 --- a/drivers/ethernet/eth_sam_gmac.c +++ b/drivers/ethernet/eth_sam_gmac.c @@ -41,6 +41,10 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #include "phy_sam_gmac.h" #include "eth_sam_gmac_priv.h" +#ifdef CONFIG_SOC_FAMILY_SAM0 +#include "eth_sam0_gmac.h" +#endif + #if defined(CONFIG_PTP_CLOCK_SAM_GMAC) #include #include @@ -84,6 +88,14 @@ static inline void dcache_clean(u32_t addr, u32_t size) #define dcache_clean(addr, size) #endif +#ifdef CONFIG_SOC_FAMILY_SAM0 +#define MCK_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#elif CONFIG_SOC_FAMILY_SAM +#define MCK_FREQ_HZ SOC_ATMEL_SAM_MCK_FREQ_HZ +#else +#error Unsupported SoC family +#endif + /* * Verify Kconfig configuration */ @@ -1037,7 +1049,7 @@ static void gmac_setup_ptp_clock_divisors(Gmac *gmac) u8_t cns, acns, nit; - min_cycles = SOC_ATMEL_SAM_MCK_FREQ_HZ; + min_cycles = MCK_FREQ_HZ; min_period = NSEC_PER_SEC; for (i = 0; i < ARRAY_SIZE(mck_divs); ++i) { @@ -1069,7 +1081,7 @@ static int gmac_init(Gmac *gmac, u32_t gmac_ncfgr_val) { int mck_divisor; - mck_divisor = get_mck_clock_divisor(SOC_ATMEL_SAM_MCK_FREQ_HZ); + mck_divisor = get_mck_clock_divisor(MCK_FREQ_HZ); if (mck_divisor < 0) { return mck_divisor; } @@ -1752,11 +1764,17 @@ static int eth_initialize(struct device *dev) cfg->config_func(); +#ifdef CONFIG_SOC_FAMILY_SAM /* Enable GMAC module's clock */ soc_pmc_peripheral_enable(cfg->periph_id); /* Connect pins to the peripheral */ soc_gpio_list_configure(cfg->pin_list, cfg->pin_list_size); +#else + /* Enable MCLK clock on GMAC */ + MCLK->AHBMASK.reg |= MCLK_AHBMASK_GMAC; + *MCLK_GMAC |= MCLK_GMAC_MASK; +#endif return 0; } @@ -2182,13 +2200,17 @@ static void eth0_irq_config(void) #endif } +#ifdef CONFIG_SOC_FAMILY_SAM static const struct soc_gpio_pin pins_eth0[] = PINS_GMAC0; +#endif static const struct eth_sam_dev_cfg eth0_config = { .regs = GMAC, .periph_id = ID_GMAC, +#ifdef CONFIG_SOC_FAMILY_SAM .pin_list = pins_eth0, .pin_list_size = ARRAY_SIZE(pins_eth0), +#endif .config_func = eth0_irq_config, .phy = {GMAC, CONFIG_ETH_SAM_GMAC_PHY_ADDR}, }; diff --git a/drivers/ethernet/phy_sam_gmac.c b/drivers/ethernet/phy_sam_gmac.c index 659e56d4eebb83..da2b1298bfc231 100644 --- a/drivers/ethernet/phy_sam_gmac.c +++ b/drivers/ethernet/phy_sam_gmac.c @@ -12,6 +12,10 @@ #include #include "phy_sam_gmac.h" +#ifdef CONFIG_SOC_FAMILY_SAM0 +#include "eth_sam0_gmac.h" +#endif + #define LOG_MODULE_NAME eth_sam_phy #define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL From 82cb39a674c0e732f2ad131277da62ae068039f0 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Thu, 5 Mar 2020 10:29:14 +0900 Subject: [PATCH 5/7] drivers: pinmux: Add more pin function definitions This commit adds more pin function definitions (PINMUX_FUNC_I through PINMUX_FUNC_P) to the pinmux interface header. The SAM D5x and E5x series devices, for instances, define up to the "function N" and this change is necessary to support such devices. Signed-off-by: Stephanos Ioannidis --- include/drivers/pinmux.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drivers/pinmux.h b/include/drivers/pinmux.h index 4cb85a5e01da69..7fbf5b2271a2ab 100644 --- a/include/drivers/pinmux.h +++ b/include/drivers/pinmux.h @@ -34,6 +34,14 @@ extern "C" { #define PINMUX_FUNC_F 5 #define PINMUX_FUNC_G 6 #define PINMUX_FUNC_H 7 +#define PINMUX_FUNC_I 8 +#define PINMUX_FUNC_J 9 +#define PINMUX_FUNC_K 10 +#define PINMUX_FUNC_L 11 +#define PINMUX_FUNC_M 12 +#define PINMUX_FUNC_N 13 +#define PINMUX_FUNC_O 14 +#define PINMUX_FUNC_P 15 #define PINMUX_PULLUP_ENABLE (0x1) #define PINMUX_PULLUP_DISABLE (0x0) From 5e271a19ea8132a68e61e8aec8c98edfc22ab891 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Sun, 12 Apr 2020 03:00:28 +0900 Subject: [PATCH 6/7] drivers: ethernet: sam_gmac: Add SAM E54 maximum queue count reference This commit adds a reference to the SAM E54 maximum queue count value in the device tree for specifying the range of `ETH_SAM_GMAC_QUEUES` configuration. Signed-off-by: Stephanos Ioannidis --- drivers/ethernet/Kconfig.sam_gmac | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ethernet/Kconfig.sam_gmac b/drivers/ethernet/Kconfig.sam_gmac index 153dade0c65208..23a8cb686f26b5 100644 --- a/drivers/ethernet/Kconfig.sam_gmac +++ b/drivers/ethernet/Kconfig.sam_gmac @@ -18,6 +18,7 @@ config ETH_SAM_GMAC_QUEUES range 1 $(dt_node_int_prop_int,/soc/ethernet@40050088,num-queues) if SOC_SERIES_SAME70 || \ SOC_SERIES_SAMV71 range 1 $(dt_node_int_prop_int,/soc/ethernet@40034000,num-queues) if SOC_SERIES_SAM4E + range 1 $(dt_node_int_prop_int,/soc/ethernet@42000800,num-queues) if SOC_SERIES_SAME54 help Select the number of hardware queues used by the driver. Packets will be routed to appropriate queues based on their priority. From 76196ad2f744e8242170b7c465c2db820e03f64b Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Fri, 6 Mar 2020 02:10:57 +0900 Subject: [PATCH 7/7] boards: arm: atsame54_xpro: Support Ethernet This commit enables the GMAC Ethernet support for the `atsame54_xpro` board which includes an on-board RMII PHY. Signed-off-by: Stephanos Ioannidis --- boards/arm/atsame54_xpro/Kconfig.defconfig | 19 ++++++++++++++++++- boards/arm/atsame54_xpro/atsame54_xpro.yaml | 1 + boards/arm/atsame54_xpro/pinmux.c | 14 ++++++++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/boards/arm/atsame54_xpro/Kconfig.defconfig b/boards/arm/atsame54_xpro/Kconfig.defconfig index 8f8b4d7490ff3d..c3607ee5824879 100644 --- a/boards/arm/atsame54_xpro/Kconfig.defconfig +++ b/boards/arm/atsame54_xpro/Kconfig.defconfig @@ -3,6 +3,23 @@ # Copyright (c) 2019 Benjamin Valentin # SPDX-License-Identifier: Apache-2.0 +if BOARD_ATSAME54_XPRO + config BOARD default "atsame54_xpro" - depends on BOARD_ATSAME54_XPRO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config ETH_SAM_GMAC + default y if NET_L2_ETHERNET + +choice ETH_SAM_GMAC_MAC_SELECT + default ETH_SAM_GMAC_RANDOM_MAC +endchoice + +endif # NETWORKING + +endif # BOARD_ATSAME54_XPRO diff --git a/boards/arm/atsame54_xpro/atsame54_xpro.yaml b/boards/arm/atsame54_xpro/atsame54_xpro.yaml index 9cf0569ee17c32..de741bd14842bb 100644 --- a/boards/arm/atsame54_xpro/atsame54_xpro.yaml +++ b/boards/arm/atsame54_xpro/atsame54_xpro.yaml @@ -15,3 +15,4 @@ supported: - spi - i2c - usb_device + - netif:eth diff --git a/boards/arm/atsame54_xpro/pinmux.c b/boards/arm/atsame54_xpro/pinmux.c index 618673282489a9..45d212019544ef 100644 --- a/boards/arm/atsame54_xpro/pinmux.c +++ b/boards/arm/atsame54_xpro/pinmux.c @@ -106,6 +106,20 @@ static int board_pinmux_init(struct device *dev) pinmux_pin_set(muxa, 25, PINMUX_FUNC_H); pinmux_pin_set(muxa, 24, PINMUX_FUNC_H); #endif + +#if DT_HAS_NODE(DT_NODELABEL(gmac)) + pinmux_pin_set(muxa, 14, PINMUX_FUNC_L); /* PA14 = GTXCK */ + pinmux_pin_set(muxa, 17, PINMUX_FUNC_L); /* PA17 = GTXEN */ + pinmux_pin_set(muxa, 18, PINMUX_FUNC_L); /* PA18 = GTX0 */ + pinmux_pin_set(muxa, 19, PINMUX_FUNC_L); /* PA19 = GTX1 */ + pinmux_pin_set(muxc, 20, PINMUX_FUNC_L); /* PC20 = GRXDV */ + pinmux_pin_set(muxa, 13, PINMUX_FUNC_L); /* PA13 = GRX0 */ + pinmux_pin_set(muxa, 12, PINMUX_FUNC_L); /* PA12 = GRX1 */ + pinmux_pin_set(muxa, 15, PINMUX_FUNC_L); /* PA15 = GRXER */ + pinmux_pin_set(muxc, 11, PINMUX_FUNC_L); /* PC11 = GMDC */ + pinmux_pin_set(muxc, 12, PINMUX_FUNC_L); /* PC12 = GMDIO */ +#endif + return 0; }