From c175847fe209be427cc710d1fe8df3f0c0ef8f7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Tue, 23 Apr 2019 15:08:00 +0200 Subject: [PATCH 01/33] drivers: i2c_bitbang: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some SoCs the frequency of the system clock is obtained at run time as the exact configuration of the hardware is not known at compile time. On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define directly introduces timing errors. This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call to inline function sys_clock_hw_cycles_per_sec() which always returns correct frequency of the system clock. Signed-off-by: Piotr Zięcik --- drivers/i2c/i2c_bitbang.c | 18 +++++------------- drivers/i2c/i2c_bitbang.h | 2 +- 2 files changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/i2c/i2c_bitbang.c b/drivers/i2c/i2c_bitbang.c index 5c074498b4b410..002b6f1c23081e 100644 --- a/drivers/i2c/i2c_bitbang.c +++ b/drivers/i2c/i2c_bitbang.c @@ -37,17 +37,7 @@ #define T_BUF T_LOW #define NS_TO_SYS_CLOCK_HW_CYCLES(ns) \ - ((u64_t)CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC * (ns) / NSEC_PER_SEC + 1) - -static const u32_t delays_fast[] = { - [T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(1300), - [T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(600), -}; - -static const u32_t delays_standard[] = { - [T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(4700), - [T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(4000), -}; + ((u64_t)sys_clock_hw_cycles_per_sec() * (ns) / NSEC_PER_SEC + 1) int i2c_bitbang_configure(struct i2c_bitbang *context, u32_t dev_config) { @@ -59,10 +49,12 @@ int i2c_bitbang_configure(struct i2c_bitbang *context, u32_t dev_config) /* Setup speed to use */ switch (I2C_SPEED_GET(dev_config)) { case I2C_SPEED_STANDARD: - context->delays = delays_standard; + context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(4700); + context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(4000); break; case I2C_SPEED_FAST: - context->delays = delays_fast; + context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(1300); + context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(600); break; default: return -ENOTSUP; diff --git a/drivers/i2c/i2c_bitbang.h b/drivers/i2c/i2c_bitbang.h index 9be690eead34a8..796b49786476f8 100644 --- a/drivers/i2c/i2c_bitbang.h +++ b/drivers/i2c/i2c_bitbang.h @@ -28,7 +28,7 @@ struct i2c_bitbang_io { struct i2c_bitbang { const struct i2c_bitbang_io *io; void *io_context; - const u32_t *delays; + u32_t delays[2]; }; /** From 060b4cb7b75a329aee5f3cb30331152cb56679cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Tue, 23 Apr 2019 15:08:00 +0200 Subject: [PATCH 02/33] drivers: pwm_qmsi: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some SoCs the frequency of the system clock is obtained at run time as the exact configuration of the hardware is not known at compile time. On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define directly introduces timing errors. This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call to inline function sys_clock_hw_cycles_per_sec() which always returns correct frequency of the system clock. Signed-off-by: Piotr Zięcik --- drivers/pwm/pwm_qmsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm_qmsi.c b/drivers/pwm/pwm_qmsi.c index 30c5e1fe83a093..99fcabf4e8a32e 100644 --- a/drivers/pwm/pwm_qmsi.c +++ b/drivers/pwm/pwm_qmsi.c @@ -16,7 +16,7 @@ #include "qm_pwm.h" #include "clk.h" -#define HW_CLOCK_CYCLES_PER_USEC (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / \ +#define HW_CLOCK_CYCLES_PER_USEC (sys_clock_hw_cycles_per_sec() / \ USEC_PER_SEC) /* pwm uses 32 bits counter to control low and high period */ From ab48cfcba1e111a610517094bda55c2de1fae088 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Tue, 23 Apr 2019 15:08:00 +0200 Subject: [PATCH 03/33] drivers: timer: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some SoCs the frequency of the system clock is obtained at run time as the exact configuration of the hardware is not known at compile time. On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define directly introduces timing errors. This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call to inline function sys_clock_hw_cycles_per_sec() which always returns correct frequency of the system clock. Signed-off-by: Piotr Zięcik --- drivers/timer/arcv2_timer0.c | 2 +- drivers/timer/cortex_m_systick.c | 2 +- drivers/timer/nrf_rtc_timer.c | 2 +- drivers/timer/riscv_machine_timer.c | 2 +- drivers/timer/rv32m1_lptmr_timer.c | 5 +++-- drivers/timer/sam0_rtc_timer.c | 2 +- drivers/timer/xtensa_sys_timer.c | 2 +- 7 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/timer/arcv2_timer0.c b/drivers/timer/arcv2_timer0.c index d272bad67cb105..fcd6b630f9746d 100644 --- a/drivers/timer/arcv2_timer0.c +++ b/drivers/timer/arcv2_timer0.c @@ -25,7 +25,7 @@ #define MIN_DELAY 512 #define COUNTER_MAX 0xffffffff #define TIMER_STOPPED 0x0 -#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \ +#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \ / CONFIG_SYS_CLOCK_TICKS_PER_SEC) #define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1) diff --git a/drivers/timer/cortex_m_systick.c b/drivers/timer/cortex_m_systick.c index b58d3ecf4d2d52..5c80c4c2c2038e 100644 --- a/drivers/timer/cortex_m_systick.c +++ b/drivers/timer/cortex_m_systick.c @@ -13,7 +13,7 @@ void z_ExcExit(void); #define COUNTER_MAX 0x00ffffff #define TIMER_STOPPED 0xff000000 -#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \ +#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \ / CONFIG_SYS_CLOCK_TICKS_PER_SEC) #define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1) #define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK) diff --git a/drivers/timer/nrf_rtc_timer.c b/drivers/timer/nrf_rtc_timer.c index cb8a9c915b11d2..a9e8370adb0a0d 100644 --- a/drivers/timer/nrf_rtc_timer.c +++ b/drivers/timer/nrf_rtc_timer.c @@ -16,7 +16,7 @@ #define RTC NRF_RTC1 #define COUNTER_MAX 0x00ffffff -#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \ +#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \ / CONFIG_SYS_CLOCK_TICKS_PER_SEC) #define MAX_TICKS ((COUNTER_MAX - CYC_PER_TICK) / CYC_PER_TICK) diff --git a/drivers/timer/riscv_machine_timer.c b/drivers/timer/riscv_machine_timer.c index 152d2dc6520a87..93a5d2ac34e418 100644 --- a/drivers/timer/riscv_machine_timer.c +++ b/drivers/timer/riscv_machine_timer.c @@ -8,7 +8,7 @@ #include #include -#define CYC_PER_TICK ((u32_t)((u64_t)CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \ +#define CYC_PER_TICK ((u32_t)((u64_t)sys_clock_hw_cycles_per_sec() \ / (u64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC)) #define MAX_TICKS ((0xffffffffu - CYC_PER_TICK) / CYC_PER_TICK) #define MIN_DELAY 1000 diff --git a/drivers/timer/rv32m1_lptmr_timer.c b/drivers/timer/rv32m1_lptmr_timer.c index beb60c38a61010..649839c4a4f41e 100644 --- a/drivers/timer/rv32m1_lptmr_timer.c +++ b/drivers/timer/rv32m1_lptmr_timer.c @@ -19,14 +19,15 @@ * - no tickless */ -#define CYCLES_PER_SEC CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define CYCLES_PER_SEC sys_clock_hw_cycles_per_sec() #define CYCLES_PER_TICK (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) /* * As a simplifying assumption, we only support a clock ticking at the * SIRC reset rate of 8MHz. */ -#if MHZ(8) != CYCLES_PER_SEC +#if defined(CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME) || \ + (MHZ(8) != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) #error "system timer misconfiguration; unsupported clock rate" #endif diff --git a/drivers/timer/sam0_rtc_timer.c b/drivers/timer/sam0_rtc_timer.c index 4fb0ef4c236a2e..c7fc68b7543fd1 100644 --- a/drivers/timer/sam0_rtc_timer.c +++ b/drivers/timer/sam0_rtc_timer.c @@ -23,7 +23,7 @@ #define RTC0 ((RtcMode0 *) DT_INST_0_ATMEL_SAM0_RTC_BASE_ADDRESS) /* Number of sys timer cycles per on tick. */ -#define CYCLES_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \ +#define CYCLES_PER_TICK (SOC_ATMEL_SAM0_GCLK0_FREQ_HZ \ / CONFIG_SYS_CLOCK_TICKS_PER_SEC) /* Maximum number of ticks. */ diff --git a/drivers/timer/xtensa_sys_timer.c b/drivers/timer/xtensa_sys_timer.c index 941321192e6cb4..16d9d1ee1ac270 100644 --- a/drivers/timer/xtensa_sys_timer.c +++ b/drivers/timer/xtensa_sys_timer.c @@ -11,7 +11,7 @@ #define TIMER_IRQ UTIL_CAT(XCHAL_TIMER, \ UTIL_CAT(CONFIG_XTENSA_TIMER_ID, _INTERRUPT)) -#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \ +#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \ / CONFIG_SYS_CLOCK_TICKS_PER_SEC) #define MAX_TICKS ((0xffffffffu - CYC_PER_TICK) / CYC_PER_TICK) #define MIN_DELAY 1000 From 4484bd1e4210f4ea3c0ddbcd1a42448b76d9bcdb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Tue, 23 Apr 2019 15:08:00 +0200 Subject: [PATCH 04/33] debug: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some SoCs the frequency of the system clock is obtained at run time as the exact configuration of the hardware is not known at compile time. On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define directly introduces timing errors. This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call to inline function sys_clock_hw_cycles_per_sec() which always returns correct frequency of the system clock. Signed-off-by: Piotr Zięcik --- subsys/debug/tracing/sysview_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/subsys/debug/tracing/sysview_config.c b/subsys/debug/tracing/sysview_config.c index 61575516e5b2fc..b3b75d4f4e0fb0 100644 --- a/subsys/debug/tracing/sysview_config.c +++ b/subsys/debug/tracing/sysview_config.c @@ -17,8 +17,8 @@ static void cbSendSystemDesc(void) void SEGGER_SYSVIEW_Conf(void) { - SEGGER_SYSVIEW_Init(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + SEGGER_SYSVIEW_Init(sys_clock_hw_cycles_per_sec(), + sys_clock_hw_cycles_per_sec(), &SYSVIEW_X_OS_TraceAPI, cbSendSystemDesc); #if defined(DT_PHYS_RAM_ADDR) /* x86 */ From ffa93694e29e12dcbd414f857afba1c81fef5e44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Tue, 23 Apr 2019 15:08:00 +0200 Subject: [PATCH 05/33] logging: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some SoCs the frequency of the system clock is obtained at run time as the exact configuration of the hardware is not known at compile time. On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define directly introduces timing errors. This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call to inline function sys_clock_hw_cycles_per_sec() which always returns correct frequency of the system clock. Signed-off-by: Piotr Zięcik --- samples/subsys/logging/logger/src/main.c | 2 +- subsys/logging/log_core.c | 24 +++++++++++++++--------- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/samples/subsys/logging/logger/src/main.c b/samples/subsys/logging/logger/src/main.c index eaa6f8ba81b378..97cb41394ba47c 100644 --- a/samples/subsys/logging/logger/src/main.c +++ b/samples/subsys/logging/logger/src/main.c @@ -46,7 +46,7 @@ static u32_t timestamp_freq(void) #ifdef CONFIG_SOC_FAMILY_NRF return 32768 / (NRF_RTC1->PRESCALER + 1); #else - return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; + return sys_clock_hw_cycles_per_sec(); #endif } diff --git a/subsys/logging/log_core.c b/subsys/logging/log_core.c index 694e88ee392ac0..cdb0182eeba048 100644 --- a/subsys/logging/log_core.c +++ b/subsys/logging/log_core.c @@ -432,19 +432,18 @@ void log_hexdump_sync(struct log_msg_ids src_level, const char *metadata, } } -static u32_t timestamp_get(void) +static u32_t k_cycle_get_32_wrapper(void) { - if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 1000000) { - return k_uptime_get_32(); - } else { - return k_cycle_get_32(); - } + /* + * The k_cycle_get_32() is a define which cannot be referenced + * by timestamp_func. Instead, this wrapper is used. + */ + return k_cycle_get_32(); } void log_core_init(void) { - u32_t freq = (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 1000000) ? - 1000 : CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; + u32_t freq; if (!IS_ENABLED(CONFIG_LOG_IMMEDIATE)) { log_msg_pool_init(); @@ -456,7 +455,14 @@ void log_core_init(void) } /* Set default timestamp. */ - timestamp_func = timestamp_get; + if (sys_clock_hw_cycles_per_sec() > 1000000) { + timestamp_func = k_uptime_get_32; + freq = 1000; + } else { + timestamp_func = k_cycle_get_32_wrapper; + freq = sys_clock_hw_cycles_per_sec(); + } + log_output_timestamp_freq_set(freq); /* From 4bbc37be72c32b94b84e3c226c36ff8539b4d7e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Tue, 23 Apr 2019 15:08:00 +0200 Subject: [PATCH 06/33] tests: benchmarks: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some SoCs the frequency of the system clock is obtained at run time as the exact configuration of the hardware is not known at compile time. On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define directly introduces timing errors. This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call to inline function sys_clock_hw_cycles_per_sec() which always returns correct frequency of the system clock. Signed-off-by: Piotr Zięcik --- tests/benchmarks/boot_time/src/main.c | 2 +- tests/benchmarks/timing_info/src/timing_info.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/benchmarks/boot_time/src/main.c b/tests/benchmarks/boot_time/src/main.c index 72049866f9446d..d94e0d48dc7d5b 100644 --- a/tests/benchmarks/boot_time/src/main.c +++ b/tests/benchmarks/boot_time/src/main.c @@ -43,7 +43,7 @@ void main(void) */ k_sleep(1); - int freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000000; + int freq = sys_clock_hw_cycles_per_sec() / 1000000; _start_us = __start_time_stamp / freq; s_main_time_stamp = __main_time_stamp - __start_time_stamp; diff --git a/tests/benchmarks/timing_info/src/timing_info.h b/tests/benchmarks/timing_info/src/timing_info.h index e631b3f23bca7d..ae8266aeb018fa 100644 --- a/tests/benchmarks/timing_info/src/timing_info.h +++ b/tests/benchmarks/timing_info/src/timing_info.h @@ -138,7 +138,7 @@ static inline void benchmark_timer_start(void) { } /* Get Core Frequency in MHz */ static inline u32_t get_core_freq_MHz(void) { - return (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC/1000000); + return (sys_clock_hw_cycles_per_sec() / 1000000); } #define PRINT_STATS(x, y, z) PRINT_F(x, y, z) From 94f0762742317fc866510aadfa638e31adaeea5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 07/33] drivers: i2c_cc32xx: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i2c_cc32xx driver used system clock frequency as a base for I2C clock frequency calculation. This commit corrects that by obtaining the needed value from DTS. Please note, that for I2C devices the clock-frequency property specifies SCK frequency, instead of frequency of the clock driving peripheral. To solve that problem, a new property was added. Signed-off-by: Piotr Zięcik --- drivers/i2c/i2c_cc32xx.c | 2 +- soc/arm/ti_simplelink/cc32xx/dts_fixup.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/i2c_cc32xx.c b/drivers/i2c/i2c_cc32xx.c index f7a17ba2753196..94ee8910e50b13 100644 --- a/drivers/i2c/i2c_cc32xx.c +++ b/drivers/i2c/i2c_cc32xx.c @@ -103,7 +103,7 @@ static int i2c_cc32xx_configure(struct device *dev, u32_t dev_config_raw) return -EINVAL; } - MAP_I2CMasterInitExpClk(base, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + MAP_I2CMasterInitExpClk(base, DT_I2C_0_CLOCK_FREQUENCY, bitrate_id); return 0; diff --git a/soc/arm/ti_simplelink/cc32xx/dts_fixup.h b/soc/arm/ti_simplelink/cc32xx/dts_fixup.h index da618758be7e6e..41a9a624502988 100644 --- a/soc/arm/ti_simplelink/cc32xx/dts_fixup.h +++ b/soc/arm/ti_simplelink/cc32xx/dts_fixup.h @@ -8,6 +8,7 @@ #define DT_I2C_0_LABEL DT_TI_CC32XX_I2C_40020000_LABEL #define DT_I2C_0_BASE_ADDRESS DT_TI_CC32XX_I2C_40020000_BASE_ADDRESS #define DT_I2C_0_BITRATE DT_TI_CC32XX_I2C_40020000_CLOCK_FREQUENCY +#define DT_I2C_0_CLOCK_FREQUENCY DT_TI_CC32XX_I2C_40020000_CLOCKS_CLOCK_FREQUENCY #define DT_I2C_0_IRQ DT_TI_CC32XX_I2C_40020000_IRQ_0 #define DT_I2C_0_IRQ_PRIORITY DT_TI_CC32XX_I2C_40020000_IRQ_0_PRIORITY From 55a832a6ae18f3ff9a432a6f1af42a80cc3a512c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 08/33] soc: snps_arc_iot: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arc/snps_arc_iot/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/arc/snps_arc_iot/soc.c b/soc/arc/snps_arc_iot/soc.c index eb7da7abadeb21..9d7ba6c05e0d7c 100644 --- a/soc/arc/snps_arc_iot/soc.c +++ b/soc/arc/snps_arc_iot/soc.c @@ -19,7 +19,7 @@ static int arc_iot_init(struct device *dev) ARG_UNUSED(dev); if (arc_iot_pll_fout_config( - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000000) < 0) { + DT_SNPS_ARCEM_0_CLOCK_FREQUENCY / 1000000) < 0) { return -1; } From d6d00371e02f18c76ee82ce738bffae4b9bf2760 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 09/33] soc: sam3x: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/atmel_sam/sam3x/soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/arm/atmel_sam/sam3x/soc.h b/soc/arm/atmel_sam/sam3x/soc.h index 591dfcf6003229..51ced5dcebcb01 100644 --- a/soc/arm/atmel_sam/sam3x/soc.h +++ b/soc/arm/atmel_sam/sam3x/soc.h @@ -49,7 +49,7 @@ #endif /* _ASMLANGUAGE */ /** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ DT_ARM_CORTEX_M4_0_CLOCK_FREQUENCY /** Master Clock (MCK) Frequency */ #define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ From 3a727816670100eefd42531933e6d5648f0bfb14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 10/33] soc: sam4s: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/atmel_sam/sam4s/soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/arm/atmel_sam/sam4s/soc.h b/soc/arm/atmel_sam/sam4s/soc.h index f45fbf51ceaffe..1f96509e52f77d 100644 --- a/soc/arm/atmel_sam/sam4s/soc.h +++ b/soc/arm/atmel_sam/sam4s/soc.h @@ -52,7 +52,7 @@ #endif /* !_ASMLANGUAGE */ /** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ DT_ARM_CORTEX_M4_0_CLOCK_FREQUENCY /** Master Clock (MCK) Frequency */ #define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ From caa08fb04c7c35e1bb4c08ad450d9f4a3e0a12be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 11/33] soc: samd2x: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/atmel_sam0/samd20/soc.h | 2 +- soc/arm/atmel_sam0/samd21/soc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/arm/atmel_sam0/samd20/soc.h b/soc/arm/atmel_sam0/samd20/soc.h index 9ce9170abfab1e..102ed13f8e36bd 100644 --- a/soc/arm/atmel_sam0/samd20/soc.h +++ b/soc/arm/atmel_sam0/samd20/soc.h @@ -54,7 +54,7 @@ #endif /* _ASMLANGUAGE */ /** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY /** Master Clock (MCK) Frequency */ #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 diff --git a/soc/arm/atmel_sam0/samd21/soc.h b/soc/arm/atmel_sam0/samd21/soc.h index 4afcc879717e39..94d8dbe46a5d29 100644 --- a/soc/arm/atmel_sam0/samd21/soc.h +++ b/soc/arm/atmel_sam0/samd21/soc.h @@ -48,7 +48,7 @@ #endif /* _ASMLANGUAGE */ /** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY /** Master Clock (MCK) Frequency */ #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 From c81013e32440ccceaee8a99e9318c6bcc2df2125 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Wed, 29 May 2019 14:11:24 +0200 Subject: [PATCH 12/33] soc: samr21: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/atmel_sam0/samr21/soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/arm/atmel_sam0/samr21/soc.h b/soc/arm/atmel_sam0/samr21/soc.h index 14a923564f5d08..fc31adee03e985 100644 --- a/soc/arm/atmel_sam0/samr21/soc.h +++ b/soc/arm/atmel_sam0/samr21/soc.h @@ -34,7 +34,7 @@ #endif /* _ASMLANGUAGE */ /** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY /** Master Clock (MCK) Frequency */ #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 From 02a7d4151621bed3c4fce9947501875c538ceab8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 13/33] soc: same70: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/atmel_sam/same70/dts_fixup.h | 1 + soc/arm/atmel_sam/same70/soc.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/soc/arm/atmel_sam/same70/dts_fixup.h b/soc/arm/atmel_sam/same70/dts_fixup.h index e5138c9519cb0c..dbf4a336c63ec8 100644 --- a/soc/arm/atmel_sam/same70/dts_fixup.h +++ b/soc/arm/atmel_sam/same70/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M7_0_CLOCK_FREQUENCY #define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS diff --git a/soc/arm/atmel_sam/same70/soc.h b/soc/arm/atmel_sam/same70/soc.h index 5efaddc6b973c8..fbeba61ae363a9 100644 --- a/soc/arm/atmel_sam/same70/soc.h +++ b/soc/arm/atmel_sam/same70/soc.h @@ -118,7 +118,7 @@ #define DMA_PERID_TC3_RX 43 /** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ DT_ARM_CORTEX_M7_0_CLOCK_FREQUENCY /** Master Clock (MCK) Frequency */ #define SOC_ATMEL_SAM_MCK_FREQ_HZ \ (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAME70_MDIV) From e9536248f5c1bb9760638c321cf509adad7dd69d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 14/33] soc: k6x: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/nxp_kinetis/k6x/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/arm/nxp_kinetis/k6x/soc.c b/soc/arm/nxp_kinetis/k6x/soc.c index b8b93a47988707..4dc2d90767ce24 100644 --- a/soc/arm/nxp_kinetis/k6x/soc.c +++ b/soc/arm/nxp_kinetis/k6x/soc.c @@ -138,7 +138,7 @@ static ALWAYS_INLINE void clkInit(void) #endif #if CONFIG_USB_KINETIS CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY); #endif } From d7e33168f79c6bf9e2fd3baecb6169a43f6c6055 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 15/33] soc: kl2x: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/nxp_kinetis/kl2x/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/arm/nxp_kinetis/kl2x/soc.c b/soc/arm/nxp_kinetis/kl2x/soc.c index ecb1de8ef7c335..5ee5ca0929b524 100644 --- a/soc/arm/nxp_kinetis/kl2x/soc.c +++ b/soc/arm/nxp_kinetis/kl2x/soc.c @@ -100,7 +100,7 @@ static ALWAYS_INLINE void clkInit(void) #endif #if CONFIG_USB_KINETIS CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY); #endif } From 28a2444ed41701754554809b4cc32b2eb62de518 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 16/33] soc: kwx: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/nxp_kinetis/kwx/soc_kw2xd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c index f989ab3232d5ad..89dcb44c687034 100644 --- a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c +++ b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c @@ -164,7 +164,7 @@ static ALWAYS_INLINE void clkInit(void) CLOCK_SetSimConfig(&simConfig); #if CONFIG_USB_KINETIS CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + DT_ARM_CORTEX_M4_0_CLOCK_FREQUENCY); #endif } From c28c44ba968292f3cb503f17f518e2e3baef79ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 17/33] soc: lpc54xxx: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/nxp_lpc/lpc54xxx/soc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/arm/nxp_lpc/lpc54xxx/soc.c index fe1d123a5c2b70..3b94ce658d74cb 100644 --- a/soc/arm/nxp_lpc/lpc54xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc54xxx/soc.c @@ -49,10 +49,10 @@ static ALWAYS_INLINE void clkInit(void) CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Set FLASH wait states for core */ - CLOCK_SetFLASHAccessCyclesForFreq(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + CLOCK_SetFLASHAccessCyclesForFreq(DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY); /* Set up high frequency FRO output to selected frequency */ - CLOCK_SetupFROClocking(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + CLOCK_SetupFROClocking(DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY); /* Set up dividers */ /* Set AHBCLKDIV divider to value 1 */ From 59812b0e29c90c4aaab8090a20892bec2fb73bdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 18/33] arch: xtensa: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- arch/xtensa/include/xtensa_rtos.h | 6 ++---- arch/xtensa/include/xtensa_timer.h | 2 +- soc/xtensa/esp32/dts_fixup.h | 11 +++++++++++ soc/xtensa/intel_s1000/dts_fixup.h | 2 ++ soc/xtensa/sample_controller/dts_fixup.h | 11 +++++++++++ 5 files changed, 27 insertions(+), 5 deletions(-) create mode 100644 soc/xtensa/esp32/dts_fixup.h create mode 100644 soc/xtensa/sample_controller/dts_fixup.h diff --git a/arch/xtensa/include/xtensa_rtos.h b/arch/xtensa/include/xtensa_rtos.h index 0ebd0f3461008e..16c11ff16e8100 100644 --- a/arch/xtensa/include/xtensa_rtos.h +++ b/arch/xtensa/include/xtensa_rtos.h @@ -46,10 +46,8 @@ #define XT_BOARD 1 #endif -#ifdef CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC - #undef XT_CLOCK_FREQ - #define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -#endif +#undef XT_CLOCK_FREQ +#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY #ifndef XT_TIMER_INDEX #if defined configXT_TIMER_INDEX diff --git a/arch/xtensa/include/xtensa_timer.h b/arch/xtensa/include/xtensa_timer.h index 1fa29f3d3f9cea..089b3e2b962188 100644 --- a/arch/xtensa/include/xtensa_timer.h +++ b/arch/xtensa/include/xtensa_timer.h @@ -115,7 +115,7 @@ * anyway!). */ #if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ) -#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY #endif #if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD) diff --git a/soc/xtensa/esp32/dts_fixup.h b/soc/xtensa/esp32/dts_fixup.h new file mode 100644 index 00000000000000..f17d2865fbaaf9 --- /dev/null +++ b/soc/xtensa/esp32/dts_fixup.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* SoC level DTS fixup file */ + +#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY + +/* End of SoC Level DTS fixup file */ diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h index 66a1f835e97353..3740d771a7f8a3 100644 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ b/soc/xtensa/intel_s1000/dts_fixup.h @@ -2,6 +2,8 @@ /* SoC level DTS fixup file */ +#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY + #define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS #define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED #define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL diff --git a/soc/xtensa/sample_controller/dts_fixup.h b/soc/xtensa/sample_controller/dts_fixup.h new file mode 100644 index 00000000000000..a38b46b4b20249 --- /dev/null +++ b/soc/xtensa/sample_controller/dts_fixup.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* SoC level DTS fixup file */ + +#define DT_CPU_CLOCK_FREQUENCY DT_SAMPLE_CONTROLLER_0_CLOCK_FREQUENCY + +/* End of SoC Level DTS fixup file */ From 788e4e8deb3e8a382566a31617faed941b09e946 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 19/33] soc: msp432p4xx: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- .../msp432p4xx/startup_system_files/system_msp432p401m.c | 3 ++- .../msp432p4xx/startup_system_files/system_msp432p401r.c | 3 ++- .../msp432p4xx/startup_system_files/system_msp432p4111.c | 3 ++- .../msp432p4xx/startup_system_files/system_msp432p411v.c | 3 ++- .../msp432p4xx/startup_system_files/system_msp432p411y.c | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c index 5f947f8780de2f..a3a8c409162022 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c index 8637028496b37c..6b430f357666f4 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c index a745c08bc16073..c9c29c5ae54e01 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c index 9343fdbe109d2d..a212221bd021bc 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c index e45fa1fff6b48a..f5faa778966ae5 100644 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c +++ b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c @@ -44,6 +44,7 @@ #include #include +#include /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: @@ -68,7 +69,7 @@ // <12000000> 12 MHz // <24000000> 24 MHz // <48000000> 48 MHz -#define __SYSTEM_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY /*--------------------- Power Regulator Configuration -----------------------*/ // Power Regulator Mode From bb7b54565aa1a8348f584b25a91cd1fb606db30d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Wed, 29 May 2019 14:05:37 +0200 Subject: [PATCH 20/33] soc: nxp_rt: Get system clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC initialization code used timer clock frequency as a system clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/nxp_imx/rt/soc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/arm/nxp_imx/rt/soc.c b/soc/arm/nxp_imx/rt/soc.c index d0e4dc5f0ef10b..50823e47e7e934 100644 --- a/soc/arm/nxp_imx/rt/soc.c +++ b/soc/arm/nxp_imx/rt/soc.c @@ -179,9 +179,9 @@ static ALWAYS_INLINE void clkInit(void) #if CONFIG_USB_DC_NXP_EHCI CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + DT_NXP_KINETIS_USBD_0_CLOCKS_CLOCK_FREQUENCY); CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + DT_NXP_KINETIS_USBD_0_CLOCKS_CLOCK_FREQUENCY); USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); #endif From c8c9cf3d6f3f368ffa7a1a0cee864607c41fa95d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 21/33] drivers: beetle_clock_control: Get CPU clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The clock control initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/clock_control/beetle_clock_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clock_control/beetle_clock_control.c b/drivers/clock_control/beetle_clock_control.c index 88218747e876d8..d5e87fc592a06b 100644 --- a/drivers/clock_control/beetle_clock_control.c +++ b/drivers/clock_control/beetle_clock_control.c @@ -233,7 +233,7 @@ static int beetle_clock_control_init(struct device *dev) static const struct beetle_clock_control_cfg_t beetle_cc_cfg = { .clock_control_id = 0, - .freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .freq = DT_ARM_CORTEX_M3_0_CLOCK_FREQUENCY, }; /** From 75d1fc79dcbe4a40355ccb4551df9ef16691b2e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 22/33] logging: log_backend_swo: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The log_backend_swo used system clock frequency as a base for SWO clock calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/silabs_exx32/efm32hg/dts_fixup.h | 1 + soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h | 1 + soc/arm/silabs_exx32/efm32wg/dts_fixup.h | 1 + soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h | 1 + soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h | 1 + subsys/logging/log_backend_swo.c | 9 ++++----- 6 files changed, 9 insertions(+), 5 deletions(-) diff --git a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h index c527e9e60bb206..e77f57d837ebed 100644 --- a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL diff --git a/soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h b/soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h index 7e54a999752503..7fea7bed0eb47b 100644 --- a/soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h @@ -7,6 +7,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL diff --git a/soc/arm/silabs_exx32/efm32wg/dts_fixup.h b/soc/arm/silabs_exx32/efm32wg/dts_fixup.h index 83bb2a211ab849..724803b696a4c8 100644 --- a/soc/arm/silabs_exx32/efm32wg/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32wg/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL diff --git a/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h b/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h index b3e22ec1b6f49c..553808e2a963e7 100644 --- a/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL diff --git a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h index e14dfb877c710c..8ff92e043782ce 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL diff --git a/subsys/logging/log_backend_swo.c b/subsys/logging/log_backend_swo.c index 71858ce7d9b7c8..bdc5c68e79f1e2 100644 --- a/subsys/logging/log_backend_swo.c +++ b/subsys/logging/log_backend_swo.c @@ -18,8 +18,8 @@ * this frequency should much the one set by the SWO viewer program. * * The initialization code assumes that SWO core frequency is equal to HCLK - * as defined by SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option. This may require - * additional, vendor specific configuration. + * as defined by DT_CPU_CLOCK_FREQUENCY. This may require additional, + * vendor specific configuration. */ #include @@ -35,13 +35,12 @@ #if CONFIG_LOG_BACKEND_SWO_FREQ_HZ == 0 #define SWO_FREQ_DIV 1 #else -#define SWO_FREQ (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \ - + (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2)) +#define SWO_FREQ (DT_CPU_CLOCK_FREQUENCY + (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2)) #define SWO_FREQ_DIV (SWO_FREQ / CONFIG_LOG_BACKEND_SWO_FREQ_HZ) #if SWO_FREQ_DIV > 0xFFFF #error CONFIG_LOG_BACKEND_SWO_FREQ_HZ is too low. SWO clock divider is 16-bit. \ Minimum supported SWO clock frequency is \ - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC/2^16. + [CPU Clock Frequency]/2^16. #endif #endif From 2b2800db6b7cb84374515e43f68ca80ea97554b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 23/33] drivers: spi_dw: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The spi_dw driver used system clock frequency as a base for SPI bus frequency calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/spi/spi_dw.c | 10 ++++++++-- drivers/spi/spi_dw.h | 12 +++--------- soc/arc/quark_se_c1000_ss/dts_fixup.h | 2 ++ soc/arc/snps_emsk/dts_fixup.h | 5 ++--- soc/arc/snps_emsk/soc.h | 2 -- soc/x86/intel_quark/quark_se/dts_fixup.h | 3 +++ soc/xtensa/intel_s1000/dts_fixup.h | 1 + 7 files changed, 19 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi_dw.c b/drivers/spi/spi_dw.c index a22137a3588c72..0e34d87752db74 100644 --- a/drivers/spi/spi_dw.c +++ b/drivers/spi/spi_dw.c @@ -252,7 +252,8 @@ static int spi_dw_configure(const struct spi_dw_config *info, if (!spi_dw_is_slave(spi)) { /* Baud rate and Slave select, for master only */ - write_baudr(SPI_DW_CLK_DIVIDER(config->frequency), info->regs); + write_baudr(SPI_DW_CLK_DIVIDER(info->clock_frequency, + config->frequency), info->regs); write_ser(1 << config->slave, info->regs); } @@ -273,7 +274,8 @@ static int spi_dw_configure(const struct spi_dw_config *info, LOG_DBG("Installed master config %p: freq %uHz (div = %u)," " ws/dfs %u/%u, mode %u/%u/%u, slave %u", config, config->frequency, - SPI_DW_CLK_DIVIDER(config->frequency), + SPI_DW_CLK_DIVIDER(info->clock_frequency, + config->frequency), SPI_WORD_SIZE_GET(config->operation), spi->dfs, (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) ? 1 : 0, @@ -535,6 +537,7 @@ struct spi_dw_data spi_dw_data_port_0 = { const struct spi_dw_config spi_dw_config_0 = { .regs = DT_SPI_0_BASE_ADDRESS, + .clock_frequency = DT_SPI_0_CLOCK_FREQUENCY, #ifdef CONFIG_SPI_DW_PORT_0_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS), @@ -583,6 +586,7 @@ struct spi_dw_data spi_dw_data_port_1 = { static const struct spi_dw_config spi_dw_config_1 = { .regs = DT_SPI_1_BASE_ADDRESS, + .clock_frequency = DT_SPI_1_CLOCK_FREQUENCY, #ifdef CONFIG_SPI_DW_PORT_1_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS), @@ -631,6 +635,7 @@ struct spi_dw_data spi_dw_data_port_2 = { static const struct spi_dw_config spi_dw_config_2 = { .regs = DT_SPI_2_BASE_ADDRESS, + .clock_frequency = DT_SPI_2_CLOCK_FREQUENCY, #ifdef CONFIG_SPI_DW_PORT_2_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS), @@ -679,6 +684,7 @@ struct spi_dw_data spi_dw_data_port_3 = { static const struct spi_dw_config spi_dw_config_3 = { .regs = DT_SPI_3_BASE_ADDRESS, + .clock_frequency = DT_SPI_3_CLOCK_FREQUENCY, #ifdef CONFIG_SPI_DW_PORT_3_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS), diff --git a/drivers/spi/spi_dw.h b/drivers/spi/spi_dw.h index 51cb44c9b92969..9746c2b6e96086 100644 --- a/drivers/spi/spi_dw.h +++ b/drivers/spi/spi_dw.h @@ -20,6 +20,7 @@ typedef void (*spi_dw_config_t)(void); /* Private structures */ struct spi_dw_config { u32_t regs; + u32_t clock_frequency; #ifdef CONFIG_CLOCK_CONTROL const char *clock_name; void *clock_data; @@ -42,15 +43,8 @@ struct spi_dw_data { /* Helper macros */ -#ifdef DT_SPI_DW_SPI_CLOCK -#define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \ - ((DT_SPI_DW_SPI_CLOCK / ssi_clk_hz) & 0xFFFF) -/* provision for soc.h providing a clock that is different than CPU clock */ -#else -#define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \ - ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / ssi_clk_hz) & 0xFFFF) -#endif - +#define SPI_DW_CLK_DIVIDER(clock_freq, ssi_clk_hz) \ + ((clock_freq / ssi_clk_hz) & 0xFFFF) #ifdef CONFIG_SPI_DW_ARC_AUX_REGS #define Z_REG_READ(__sz) sys_in##__sz diff --git a/soc/arc/quark_se_c1000_ss/dts_fixup.h b/soc/arc/quark_se_c1000_ss/dts_fixup.h index 7bd2d5d3b5b8b6..d1a15ec8fb6f61 100644 --- a/soc/arc/quark_se_c1000_ss/dts_fixup.h +++ b/soc/arc/quark_se_c1000_ss/dts_fixup.h @@ -77,6 +77,7 @@ #define DT_ADC_0_BASE_ADDRESS DT_SNPS_DW_ADC_80015000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010000_BASE_ADDRESS +#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_80010000_CLOCKS_CLOCK_FREQUENCY #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_80010000_LABEL #define DT_SPI_0_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT #define DT_SPI_0_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT_PRIORITY @@ -86,6 +87,7 @@ #define DT_SPI_0_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ_PRIORITY #define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010100_BASE_ADDRESS +#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_80010100_CLOCKS_CLOCK_FREQUENCY #define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_80010100_LABEL #define DT_SPI_1_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT #define DT_SPI_1_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT_PRIORITY diff --git a/soc/arc/snps_emsk/dts_fixup.h b/soc/arc/snps_emsk/dts_fixup.h index dc742f46f4b4a8..99d120735175f4 100644 --- a/soc/arc/snps_emsk/dts_fixup.h +++ b/soc/arc/snps_emsk/dts_fixup.h @@ -69,18 +69,17 @@ */ #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS +#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_F0006000_CLOCKS_CLOCK_FREQUENCY #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL #define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0 #define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY #define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS +#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_F0007000_CLOCKS_CLOCK_FREQUENCY #define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL #define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0 #define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY #define DT_SPI_DW_IRQ_FLAGS 0 -#define DT_SPI_DW_SPI_CLOCK DT_NS16550_F0009000_CLOCK_FREQUENCY - - /* End of SoC Level DTS fixup file */ diff --git a/soc/arc/snps_emsk/soc.h b/soc/arc/snps_emsk/soc.h index 58920ce56f108a..0624919a482f84 100644 --- a/soc/arc/snps_emsk/soc.h +++ b/soc/arc/snps_emsk/soc.h @@ -82,8 +82,6 @@ #define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */ /* SPI */ -#define DT_SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ - #define DT_SPI_DW_IRQ_FLAGS 0 /* diff --git a/soc/x86/intel_quark/quark_se/dts_fixup.h b/soc/x86/intel_quark/quark_se/dts_fixup.h index 27e274ceeb01b5..7114270b8097fe 100644 --- a/soc/x86/intel_quark/quark_se/dts_fixup.h +++ b/soc/x86/intel_quark/quark_se/dts_fixup.h @@ -50,16 +50,19 @@ #define DT_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS +#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001000_CLOCKS_CLOCK_FREQUENCY #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL #define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 #define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY #define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS +#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001400_CLOCKS_CLOCK_FREQUENCY #define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL #define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0 #define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY #define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS +#define DT_SPI_2_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001800_CLOCKS_CLOCK_FREQUENCY #define DT_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL #define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0 #define DT_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h index 3740d771a7f8a3..290a0ccb83a54f 100644 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ b/soc/xtensa/intel_s1000/dts_fixup.h @@ -42,6 +42,7 @@ #define DT_DW_ICTL_IRQ_FLAGS DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS +#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_E000_CLOCKS_CLOCK_FREQUENCY #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_E000_LABEL #define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0 #define DT_SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE From 9000a518b3c580b4deabaa1a821aa2c93c1ef870 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 13:28:31 +0200 Subject: [PATCH 24/33] drivers: uart_cmsdk_apb: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The uart_cmsdk_apb driver used system clock frequency as a base for baudrate calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/serial/uart_cmsdk_apb.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/serial/uart_cmsdk_apb.c b/drivers/serial/uart_cmsdk_apb.c index 944ff3e944099c..6da62db7a7330a 100644 --- a/drivers/serial/uart_cmsdk_apb.c +++ b/drivers/serial/uart_cmsdk_apb.c @@ -464,7 +464,7 @@ static void uart_cmsdk_apb_irq_config_func_0(struct device *dev); static const struct uart_device_config uart_cmsdk_apb_dev_cfg_0 = { .base = (u8_t *)DT_INST_0_ARM_CMSDK_UART_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_INST_0_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_0, #endif @@ -529,7 +529,7 @@ static void uart_cmsdk_apb_irq_config_func_1(struct device *dev); static const struct uart_device_config uart_cmsdk_apb_dev_cfg_1 = { .base = (u8_t *)DT_INST_1_ARM_CMSDK_UART_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_INST_1_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_1, #endif @@ -594,7 +594,7 @@ static void uart_cmsdk_apb_irq_config_func_2(struct device *dev); static const struct uart_device_config uart_cmsdk_apb_dev_cfg_2 = { .base = (u8_t *)DT_INST_2_ARM_CMSDK_UART_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_INST_2_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_2, #endif @@ -659,7 +659,7 @@ static void uart_cmsdk_apb_irq_config_func_3(struct device *dev); static const struct uart_device_config uart_cmsdk_apb_dev_cfg_3 = { .base = (u8_t *)DT_INST_3_ARM_CMSDK_UART_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_INST_3_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_3, #endif @@ -724,7 +724,7 @@ static void uart_cmsdk_apb_irq_config_func_4(struct device *dev); static const struct uart_device_config uart_cmsdk_apb_dev_cfg_4 = { .base = (u8_t *)DT_INST_4_ARM_CMSDK_UART_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_INST_4_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_4, #endif From 0e25db33fd6c2371f140f1527e8805afcf40c9cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 25/33] drivers: uart_pl011: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The uart_pl011 driver used system clock frequency as a base for baudrate calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/serial/uart_pl011.c | 8 ++++---- soc/arm/arm/musca_a/dts_fixup.h | 4 ++++ soc/arm/arm/musca_b1/dts_fixup.h | 4 ++++ 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index 1ead87637caf95..e3b2e6b246f9fe 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -361,8 +361,8 @@ static int pl011_init(struct device *dev) pl011_disable_fifo(dev); /* Set baud rate */ - ret = pl011_set_baudrate(dev, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, - DEV_DATA(dev)->baud_rate); + ret = pl011_set_baudrate(dev, DEV_CFG(dev)->sys_clk_freq, + DEV_DATA(dev)->baud_rate); if (ret != 0) { return ret; } @@ -414,7 +414,7 @@ static void pl011_irq_config_func_0(struct device *dev); static struct uart_device_config pl011_cfg_port_0 = { .base = (u8_t *)DT_PL011_PORT0_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_PL011_PORT0_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = pl011_irq_config_func_0, #endif @@ -468,7 +468,7 @@ static void pl011_irq_config_func_1(struct device *dev); static struct uart_device_config pl011_cfg_port_1 = { .base = (u8_t *)DT_PL011_PORT1_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_PL011_PORT1_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = pl011_irq_config_func_1, #endif diff --git a/soc/arm/arm/musca_a/dts_fixup.h b/soc/arm/arm/musca_a/dts_fixup.h index ecae729d098891..9f243360674d3f 100644 --- a/soc/arm/arm/musca_a/dts_fixup.h +++ b/soc/arm/arm/musca_a/dts_fixup.h @@ -19,6 +19,7 @@ #define DT_PL011_PORT0_IRQ_RXTIM DT_ARM_PL011_40101000_IRQ_RXTIM #define DT_PL011_PORT0_IRQ_ERR DT_ARM_PL011_40101000_IRQ_ERR #define DT_PL011_PORT0_IRQ_PRI DT_ARM_PL011_40101000_IRQ_0_PRIORITY +#define DT_PL011_PORT0_CLOCK_FREQUENCY DT_ARM_PL011_40101000_CLOCKS_CLOCK_FREQUENCY #define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_40101000_CURRENT_SPEED #define DT_PL011_PORT0_NAME DT_ARM_PL011_40101000_LABEL @@ -28,6 +29,7 @@ #define DT_PL011_PORT1_IRQ_RXTIM DT_ARM_PL011_40102000_IRQ_RXTIM #define DT_PL011_PORT1_IRQ_ERR DT_ARM_PL011_40102000_IRQ_ERR #define DT_PL011_PORT1_IRQ_PRI DT_ARM_PL011_40102000_IRQ_0_PRIORITY +#define DT_PL011_PORT1_CLOCK_FREQUENCY DT_ARM_PL011_40102000_CLOCKS_CLOCK_FREQUENCY #define DT_PL011_PORT1_BAUD_RATE DT_ARM_PL011_40102000_CURRENT_SPEED #define DT_PL011_PORT1_NAME DT_ARM_PL011_40102000_LABEL @@ -43,6 +45,7 @@ #define DT_PL011_PORT0_IRQ_RXTIM DT_ARM_PL011_50101000_IRQ_RXTIM #define DT_PL011_PORT0_IRQ_ERR DT_ARM_PL011_50101000_IRQ_ERR #define DT_PL011_PORT0_IRQ_PRI DT_ARM_PL011_50101000_IRQ_0_PRIORITY +#define DT_PL011_PORT0_CLOCK_FREQUENCY DT_ARM_PL011_50101000_CLOCKS_CLOCK_FREQUENCY #define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_50101000_CURRENT_SPEED #define DT_PL011_PORT0_NAME DT_ARM_PL011_50101000_LABEL @@ -52,6 +55,7 @@ #define DT_PL011_PORT1_IRQ_RXTIM DT_ARM_PL011_50102000_IRQ_RXTIM #define DT_PL011_PORT1_IRQ_ERR DT_ARM_PL011_50102000_IRQ_ERR #define DT_PL011_PORT1_IRQ_PRI DT_ARM_PL011_50102000_IRQ_0_PRIORITY +#define DT_PL011_PORT1_CLOCK_FREQUENCY DT_ARM_PL011_50102000_CLOCKS_CLOCK_FREQUENCY #define DT_PL011_PORT1_BAUD_RATE DT_ARM_PL011_50102000_CURRENT_SPEED #define DT_PL011_PORT1_NAME DT_ARM_PL011_50102000_LABEL diff --git a/soc/arm/arm/musca_b1/dts_fixup.h b/soc/arm/arm/musca_b1/dts_fixup.h index 296ecca0cce827..0ee1445269bd08 100644 --- a/soc/arm/arm/musca_b1/dts_fixup.h +++ b/soc/arm/arm/musca_b1/dts_fixup.h @@ -19,6 +19,7 @@ #define DT_PL011_PORT0_IRQ_RXTIM DT_ARM_PL011_40105000_IRQ_RXTIM #define DT_PL011_PORT0_IRQ_ERR DT_ARM_PL011_40105000_IRQ_ERR #define DT_PL011_PORT0_IRQ_PRI DT_ARM_PL011_40105000_IRQ_0_PRIORITY +#define DT_PL011_PORT0_CLOCK_FREQUENCY DT_ARM_PL011_40105000_CLOCKS_CLOCK_FREQUENCY #define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_40105000_CURRENT_SPEED #define DT_PL011_PORT0_NAME DT_ARM_PL011_40105000_LABEL @@ -28,6 +29,7 @@ #define DT_PL011_PORT1_IRQ_RXTIM DT_ARM_PL011_40106000_IRQ_RXTIM #define DT_PL011_PORT1_IRQ_ERR DT_ARM_PL011_40106000_IRQ_ERR #define DT_PL011_PORT1_IRQ_PRI DT_ARM_PL011_40106000_IRQ_0_PRIORITY +#define DT_PL011_PORT1_CLOCK_FREQUENCY DT_ARM_PL011_40106000_CLOCKS_CLOCK_FREQUENCY #define DT_PL011_PORT1_BAUD_RATE DT_ARM_PL011_40106000_CURRENT_SPEED #define DT_PL011_PORT1_NAME DT_ARM_PL011_40106000_LABEL @@ -43,6 +45,7 @@ #define DT_PL011_PORT0_IRQ_RXTIM DT_ARM_PL011_50105000_IRQ_RXTIM #define DT_PL011_PORT0_IRQ_ERR DT_ARM_PL011_50105000_IRQ_ERR #define DT_PL011_PORT0_IRQ_PRI DT_ARM_PL011_50105000_IRQ_0_PRIORITY +#define DT_PL011_PORT0_CLOCK_FREQUENCY DT_ARM_PL011_50105000_CLOCKS_CLOCK_FREQUENCY #define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_50105000_CURRENT_SPEED #define DT_PL011_PORT0_NAME DT_ARM_PL011_50105000_LABEL @@ -52,6 +55,7 @@ #define DT_PL011_PORT1_IRQ_RXTIM DT_ARM_PL011_50106000_IRQ_RXTIM #define DT_PL011_PORT1_IRQ_ERR DT_ARM_PL011_50106000_IRQ_ERR #define DT_PL011_PORT1_IRQ_PRI DT_ARM_PL011_50106000_IRQ_0_PRIORITY +#define DT_PL011_PORT1_CLOCK_FREQUENCY DT_ARM_PL011_50106000_CLOCKS_CLOCK_FREQUENCY #define DT_PL011_PORT1_BAUD_RATE DT_ARM_PL011_50106000_CURRENT_SPEED #define DT_PL011_PORT1_NAME DT_ARM_PL011_50106000_LABEL From 30987585daa98dd2766bed8db19fc5ab27c17a3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 26/33] drivers: uart_cc32xx: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The uart_cc32xx driver used system clock frequency as a base for baudrate calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/serial/uart_cc32xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/uart_cc32xx.c b/drivers/serial/uart_cc32xx.c index 1e0d4fe92f14d8..0b29ed83c4b1d3 100644 --- a/drivers/serial/uart_cc32xx.c +++ b/drivers/serial/uart_cc32xx.c @@ -38,7 +38,7 @@ static void uart_cc32xx_isr(void *arg); static const struct uart_device_config uart_cc32xx_dev_cfg_0 = { .base = (void *)DT_TI_CC32XX_UART_4000C000_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_TI_CC32XX_UART_4000C000_CLOCKS_CLOCK_FREQUENCY, }; static struct uart_cc32xx_dev_data_t uart_cc32xx_dev_data_0 = { From 8219a3a5e3a610f92776eb855e7e5e8320f8a1dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 27/33] drivers: uart_msp432p4xx: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The uart_msp432p4xx driver used system clock frequency as a base for baudrate calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/serial/uart_msp432p4xx.c | 2 +- soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/serial/uart_msp432p4xx.c b/drivers/serial/uart_msp432p4xx.c index daa3a12a8f1662..b749511891b621 100644 --- a/drivers/serial/uart_msp432p4xx.c +++ b/drivers/serial/uart_msp432p4xx.c @@ -39,7 +39,7 @@ static void uart_msp432p4xx_isr(void *arg); static const struct uart_device_config uart_msp432p4xx_dev_cfg_0 = { .base = (void *)DT_UART_MSP432P4XX_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_UART_MSP432P4XX_CLOCK_FREQUENCY, }; static struct uart_msp432p4xx_dev_data_t uart_msp432p4xx_dev_data_0 = { diff --git a/soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h b/soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h index 7854011f95afba..05985f688f5cc2 100644 --- a/soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h +++ b/soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h @@ -12,6 +12,7 @@ #define DT_UART_MSP432P4XX_NAME DT_TI_MSP432P4XX_UART_40001000_LABEL #define DT_UART_MSP432P4XX_BASE_ADDRESS DT_TI_MSP432P4XX_UART_40001000_BASE_ADDRESS +#define DT_UART_MSP432P4XX_CLOCK_FREQUENCY DT_TI_MSP432P4XX_UART_40001000_CLOCKS_CLOCK_FREQUENCY #define DT_UART_MSP432P4XX_BAUD_RATE DT_TI_MSP432P4XX_UART_40001000_CURRENT_SPEED /* End of SoC Level DTS fixup file */ From 7ae312a26427cc3ab5ff89a5b060715a163b5c11 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 28/33] drivers: uart_qmsi: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The uart_qmsi driver used system clock frequency as a base for baudrate calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/serial/uart_qmsi.c | 30 ++++++++++++++++-------- soc/arc/quark_se_c1000_ss/dts_fixup.h | 6 +++-- soc/x86/intel_quark/quark_se/dts_fixup.h | 6 +++-- 3 files changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/serial/uart_qmsi.c b/drivers/serial/uart_qmsi.c index 34e9caf466cd6c..aa6e271b4ba7ba 100644 --- a/drivers/serial/uart_qmsi.c +++ b/drivers/serial/uart_qmsi.c @@ -20,10 +20,10 @@ #define IIR_IID_NO_INTERRUPT_PENDING 0x01 -#define DIVISOR_LOW(baudrate) \ - ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / (16 * baudrate)) & 0xFF) -#define DIVISOR_HIGH(baudrate) \ - (((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / (16 * baudrate)) & 0xFF00) >> 8) +#define DIVISOR_LOW(clock, baudrate) \ + ((clock / (16 * baudrate)) & 0xFF) +#define DIVISOR_HIGH(clock, baudrate) \ + (((clock / (16 * baudrate)) & 0xFF00) >> 8) /* Convenient macro to get the controller instance. */ #define GET_CONTROLLER_INSTANCE(dev) \ @@ -33,6 +33,7 @@ struct uart_qmsi_config_info { qm_uart_t instance; clk_periph_t clock_gate; + u32_t clock_frequency; u32_t baud_divisor; bool hw_fc; @@ -140,9 +141,12 @@ static void irq_config_func_0(struct device *dev); static const struct uart_qmsi_config_info config_info_0 = { .instance = QM_UART_0, .clock_gate = CLK_PERIPH_UARTA_REGISTER | CLK_PERIPH_CLK, + .clock_frequency = DT_UART_QMSI_0_CLOCK_FREQUENCY, .baud_divisor = QM_UART_CFG_BAUD_DL_PACK( - DIVISOR_HIGH(DT_UART_QMSI_0_BAUDRATE), - DIVISOR_LOW(DT_UART_QMSI_0_BAUDRATE), + DIVISOR_HIGH(DT_UART_QMSI_0_CLOCK_FREQUENCY, + DT_UART_QMSI_0_BAUDRATE), + DIVISOR_LOW(DT_UART_QMSI_0_CLOCK_FREQUENCY, + DT_UART_QMSI_0_BAUDRATE), 0), #ifdef CONFIG_UART_QMSI_0_HW_FC .hw_fc = true, @@ -168,9 +172,12 @@ static void irq_config_func_1(struct device *dev); static const struct uart_qmsi_config_info config_info_1 = { .instance = QM_UART_1, .clock_gate = CLK_PERIPH_UARTB_REGISTER | CLK_PERIPH_CLK, + .clock_frequency = DT_UART_QMSI_1_CLOCK_FREQUENCY, .baud_divisor = QM_UART_CFG_BAUD_DL_PACK( - DIVISOR_HIGH(DT_UART_QMSI_1_BAUDRATE), - DIVISOR_LOW(DT_UART_QMSI_1_BAUDRATE), + DIVISOR_HIGH(DT_UART_QMSI_1_CLOCK_FREQUENCY, + DT_UART_QMSI_1_BAUDRATE), + DIVISOR_LOW(DT_UART_QMSI_1_CLOCK_FREQUENCY, + DT_UART_QMSI_1_BAUDRATE), 0), #ifdef CONFIG_UART_QMSI_1_HW_FC .hw_fc = true, @@ -405,13 +412,16 @@ static void irq_config_func_1(struct device *dev) static int uart_qmsi_line_ctrl_set(struct device *dev, u32_t ctrl, u32_t val) { qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev); + const struct uart_qmsi_config_info *config = dev->config->config_info; qm_uart_config_t cfg; switch (ctrl) { case LINE_CTRL_BAUD_RATE: cfg.line_control = QM_UART[instance]->lcr; - cfg.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(DIVISOR_HIGH(val), - DIVISOR_LOW(val), 0); + cfg.baud_divisor = QM_UART_CFG_BAUD_DL_PACK( + DIVISOR_HIGH(config->clock_frequency, val), + DIVISOR_LOW(config->clock_frequency, val), + 0); if (cfg.baud_divisor == 0) { return -EINVAL; } diff --git a/soc/arc/quark_se_c1000_ss/dts_fixup.h b/soc/arc/quark_se_c1000_ss/dts_fixup.h index d1a15ec8fb6f61..3577a02220aa4a 100644 --- a/soc/arc/quark_se_c1000_ss/dts_fixup.h +++ b/soc/arc/quark_se_c1000_ss/dts_fixup.h @@ -2,12 +2,14 @@ /* SoC level DTS fixup file */ -#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED +#define DT_UART_QMSI_0_CLOCK_FREQUENCY DT_INTEL_QMSI_UART_B0002000_CLOCKS_CLOCK_FREQUENCY +#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED #define DT_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL #define DT_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 #define DT_UART_QMSI_0_IRQ_PRI DT_INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY -#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED +#define DT_UART_QMSI_1_CLOCK_FREQUENCY DT_INTEL_QMSI_UART_B0002400_CLOCKS_CLOCK_FREQUENCY +#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED #define DT_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL #define DT_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 #define DT_UART_QMSI_1_IRQ_PRI DT_INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY diff --git a/soc/x86/intel_quark/quark_se/dts_fixup.h b/soc/x86/intel_quark/quark_se/dts_fixup.h index 7114270b8097fe..ce027dce8ff801 100644 --- a/soc/x86/intel_quark/quark_se/dts_fixup.h +++ b/soc/x86/intel_quark/quark_se/dts_fixup.h @@ -2,13 +2,15 @@ /* SoC level DTS fixup file */ -#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED +#define DT_UART_QMSI_0_CLOCK_FREQUENCY DT_INTEL_QMSI_UART_B0002000_CLOCKS_CLOCK_FREQUENCY +#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED #define DT_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL #define DT_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 #define DT_UART_QMSI_0_IRQ_PRI DT_INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY #define DT_UART_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002000_IRQ_0_SENSE -#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED +#define DT_UART_QMSI_1_CLOCK_FREQUENCY DT_INTEL_QMSI_UART_B0002400_CLOCKS_CLOCK_FREQUENCY +#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED #define DT_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL #define DT_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 #define DT_UART_QMSI_1_IRQ_PRI DT_INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY From 1ef851b7e8e1d2c6b2c6a3a769bca91850506fda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 29/33] drivers: uart_stellaris: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The uart_stellaris driver used system clock frequency as a base for baudrate calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/serial/uart_stellaris.c | 6 +++--- soc/arm/ti_lm3s6965/soc.h | 7 ------- soc/arm/ti_simplelink/cc2650/dts_fixup.h | 2 +- 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/serial/uart_stellaris.c b/drivers/serial/uart_stellaris.c index d4d4a2371f8f82..0f96b9ea08e4b6 100644 --- a/drivers/serial/uart_stellaris.c +++ b/drivers/serial/uart_stellaris.c @@ -634,7 +634,7 @@ static void irq_config_func_0(struct device *port); static const struct uart_device_config uart_stellaris_dev_cfg_0 = { .base = (u8_t *)DT_TI_STELLARIS_UART_4000C000_BASE_ADDRESS, - .sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ, + .sys_clk_freq = DT_TI_STELLARIS_UART_4000C000_CLOCKS_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_0, @@ -672,7 +672,7 @@ static void irq_config_func_1(struct device *port); static struct uart_device_config uart_stellaris_dev_cfg_1 = { .base = (u8_t *)DT_TI_STELLARIS_UART_4000D000_BASE_ADDRESS, - .sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ, + .sys_clk_freq = DT_TI_STELLARIS_UART_4000D000_CLOCKS_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_1, @@ -710,7 +710,7 @@ static void irq_config_func_2(struct device *port); static const struct uart_device_config uart_stellaris_dev_cfg_2 = { .base = (u8_t *)DT_TI_STELLARIS_UART_4000E000_BASE_ADDRESS, - .sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ, + .sys_clk_freq = DT_TI_STELLARIS_UART_4000E000_CLOCKS_CLOCK_FREQUENCY, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_2, diff --git a/soc/arm/ti_lm3s6965/soc.h b/soc/arm/ti_lm3s6965/soc.h index 7c99c69dffe89e..fe880535ceb2c4 100644 --- a/soc/arm/ti_lm3s6965/soc.h +++ b/soc/arm/ti_lm3s6965/soc.h @@ -75,13 +75,6 @@ extern "C" { #include #include -/* uart configuration settings */ -#if defined(CONFIG_UART_STELLARIS) - -#define DT_UART_STELLARIS_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ - -#endif /* CONFIG_UART_STELLARIS */ - #endif /* !_ASMLANGUAGE */ #ifdef __cplusplus diff --git a/soc/arm/ti_simplelink/cc2650/dts_fixup.h b/soc/arm/ti_simplelink/cc2650/dts_fixup.h index 4f7fd4793f5e94..9a9a004485c463 100644 --- a/soc/arm/ti_simplelink/cc2650/dts_fixup.h +++ b/soc/arm/ti_simplelink/cc2650/dts_fixup.h @@ -6,7 +6,7 @@ #define DT_TI_STELLARIS_UART_4000C000_BASE_ADDRESS DT_TI_STELLARIS_UART_40001000_BASE_ADDRESS #define DT_TI_STELLARIS_UART_4000C000_CURRENT_SPEED DT_TI_STELLARIS_UART_40001000_CURRENT_SPEED -#define DT_UART_STELLARIS_CLK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define DT_TI_STELLARIS_UART_4000C000_CLOCKS_CLOCK_FREQUENCY DT_TI_STELLARIS_UART_40001000_CLOCKS_CLOCK_FREQUENCY #define DT_TI_STELLARIS_UART_4000C000_IRQ_0 DT_TI_STELLARIS_UART_40001000_IRQ_0 #define DT_TI_STELLARIS_UART_4000C000_IRQ_0_PRIORITY DT_TI_STELLARIS_UART_40001000_IRQ_0_PRIORITY #define DT_TI_STELLARIS_UART_4000C000_LABEL DT_TI_STELLARIS_UART_40001000_LABEL From d5db8cf008a6153b6a893b4ce793f9765206905f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Wed, 29 May 2019 13:15:29 +0200 Subject: [PATCH 30/33] drivers: uart_cc13xx_cc26xx: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The uart_cc13xx_cc26xx driver used system clock frequency as a base for baudrate calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/serial/uart_cc13xx_cc26xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/uart_cc13xx_cc26xx.c b/drivers/serial/uart_cc13xx_cc26xx.c index 2bdcb677113f7e..fd2a41926592cd 100644 --- a/drivers/serial/uart_cc13xx_cc26xx.c +++ b/drivers/serial/uart_cc13xx_cc26xx.c @@ -361,7 +361,7 @@ static int uart_cc13xx_cc26xx_init_0(struct device *dev) static const struct uart_device_config uart_cc13xx_cc26xx_config_0 = { .regs = DT_TI_CC13XX_CC26XX_UART_40001000_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_TI_CC13XX_CC26XX_UART_40001000_CLOCKS_CLOCK_FREQUENCY, }; static struct uart_cc13xx_cc26xx_data uart_cc13xx_cc26xx_data_0 = { @@ -438,7 +438,7 @@ static int uart_cc13xx_cc26xx_init_1(struct device *dev) static const struct uart_device_config uart_cc13xx_cc26xx_config_1 = { .regs = DT_TI_CC13XX_CC26XX_UART_4000B000_BASE_ADDRESS, - .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .sys_clk_freq = DT_TI_CC13XX_CC26XX_UART_4000B000_CLOCKS_CLOCK_FREQUENCY, }; static struct uart_cc13xx_cc26xx_data uart_cc13xx_cc26xx_data_1 = { From bccdf56e4350ec88b8cad8e8126d3b5c893c6659 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH 31/33] drivers: wdog_cmsdk_apb: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The wdog_cmsdk_apb driver used system clock frequency as a base for timeout calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- drivers/watchdog/wdt_cmsdk_apb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/wdt_cmsdk_apb.c b/drivers/watchdog/wdt_cmsdk_apb.c index 10859e347a2cfb..782098214fd9b6 100644 --- a/drivers/watchdog/wdt_cmsdk_apb.c +++ b/drivers/watchdog/wdt_cmsdk_apb.c @@ -110,7 +110,8 @@ static int wdog_cmsdk_apb_install_timeout(struct device *dev, ARG_UNUSED(dev); /* Reload value */ - reload_s = config->window.max * CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; + reload_s = config->window.max * + DT_INST_0_ARM_CMSDK_WATCHDOG_CLOCKS_CLOCK_FREQUENCY; flags = config->flags; wdog->load = reload_s; From efebd07e390d5a105939fa2919e164f4a117d07d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 30 May 2019 12:16:18 +0200 Subject: [PATCH 32/33] drivers: adc_stm32: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The adc_stm32 driver used system timer frequency as a base for busy-wait delay calculation. This commit corrects that by obtaining the needed value from SystemCoreClock variable. Signed-off-by: Piotr Zięcik --- drivers/adc/adc_stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index ab4523833c085d..bbd45b3f39c4ca 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -557,7 +557,7 @@ static int adc_stm32_init(struct device *dev) LOG_ERR("ADC clock rate get error."); } - wait_cycles = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / adc_rate * + wait_cycles = SystemCoreClock / adc_rate * LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES; for (int i = wait_cycles; i >= 0; i--) { From 7850fb5a3633efad3834c4a253b168ba81f4c41a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Wed, 19 Jun 2019 18:38:06 +0200 Subject: [PATCH 33/33] debug: tracing: Fix compilation error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds the kernel.h include in order to provide sys_clock_hw_cycles_per_sec() declaration. Signed-off-by: Piotr Zięcik --- subsys/debug/tracing/sysview_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/debug/tracing/sysview_config.c b/subsys/debug/tracing/sysview_config.c index b3b75d4f4e0fb0..1eddbf66cf5e82 100644 --- a/subsys/debug/tracing/sysview_config.c +++ b/subsys/debug/tracing/sysview_config.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include "SEGGER_SYSVIEW_Zephyr.h"