drivers: serial: uart_sam0: rework devicetree support

Rework the devicetree to utilize new DT_INST macros and extract per instance data for clocks and dma from devicetree. We update the atmel,sam0-uart binding for dma to replace the rxdma and txdma properties with proper 'dmas' property. Signed-off-by: Kumar Gala <[email protected]>
zephyrproject-rtos · Apr 22, 2020 · f56b159 · f56b159
1 parent 079f33a
commit f56b159
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diff --git a/drivers/serial/uart_sam0.c b/drivers/serial/uart_sam0.c
@@ -1045,15 +1045,14 @@ static const struct uart_driver_api uart_sam0_driver_api = {
 };
 
 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
-#define DT_ATMEL_SAM0_UART_SERCOM_IRQ(n, m) DT_ATMEL_SAM0_UART_SERCOM_ ## n ## _IRQ_ ## m
-#define DT_ATMEL_SAM0_UART_SERCOM_IRQ_PRIORITY(n, m) DT_ATMEL_SAM0_UART_SERCOM_ ## n ## _IRQ_ ## m ## _PRIORITY
 
 #define SAM0_UART_IRQ_CONNECT(n, m)					\
 	do {								\
-	IRQ_CONNECT(DT_ATMEL_SAM0_UART_SERCOM_IRQ(n, m),		\
-		    DT_ATMEL_SAM0_UART_SERCOM_IRQ_PRIORITY(n, m),	\
-		    uart_sam0_isr, DEVICE_GET(uart_sam0_##n), 0);	\
-	irq_enable(DT_ATMEL_SAM0_UART_SERCOM_IRQ(n, m));		\
+		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq),		\
+			    DT_INST_IRQ_BY_IDX(n, m, priority),		\
+			    uart_sam0_isr,				\
+			    DEVICE_GET(uart_sam0_##n), 0);		\
+		irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq));		\
 	} while (0)
 
 #define UART_SAM0_IRQ_HANDLER_DECL(n)					\
@@ -1084,120 +1083,53 @@ static void uart_sam0_irq_config_##n(struct device *dev)		\
 #endif
 
 #if CONFIG_UART_ASYNC_API
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_0_TXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_0_TXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_0_RXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_0_RXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_1_TXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_1_TXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_1_RXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_1_RXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_2_TXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_2_TXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_2_RXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_2_RXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_3_TXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_3_TXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_3_RXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_3_RXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_4_TXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_4_TXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_4_RXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_4_RXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_5_TXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_5_TXDMA 0xFFU
-#endif
-#ifndef DT_ATMEL_SAM0_UART_SERCOM_5_RXDMA
-#define DT_ATMEL_SAM0_UART_SERCOM_5_RXDMA 0xFFU
-#endif
-
-#define UART_SAM0_DMA_CHANNELS(n)				 \
-	.tx_dma_request = SERCOM##n##_DMAC_ID_TX,		 \
-	.tx_dma_channel = DT_ATMEL_SAM0_UART_SERCOM_##n##_TXDMA, \
-	.rx_dma_request = SERCOM##n##_DMAC_ID_RX,		 \
-	.rx_dma_channel = DT_ATMEL_SAM0_UART_SERCOM_##n##_RXDMA
+#define UART_SAM0_DMA_CHANNELS(n)					\
+	.tx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, tx),	\
+	.tx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, tx),	\
+	.rx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, rx),	\
+	.rx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
 #else
 #define UART_SAM0_DMA_CHANNELS(n)
 #endif
 
 #define UART_SAM0_SERCOM_PADS(n) \
-	(DT_ATMEL_SAM0_UART_SERCOM_##n##_RXPO << SERCOM_USART_CTRLA_RXPO_Pos) |	\
-	(DT_ATMEL_SAM0_UART_SERCOM_##n##_TXPO << SERCOM_USART_CTRLA_TXPO_Pos)
+	(DT_INST_PROP(n, rxpo) << SERCOM_USART_CTRLA_RXPO_Pos) |	\
+	(DT_INST_PROP(n, txpo) << SERCOM_USART_CTRLA_TXPO_Pos)
 
 #ifdef MCLK
-#define UART_SAM0_CONFIG_DEFN(n)						\
-static const struct uart_sam0_dev_cfg uart_sam0_config_##n = {			\
-	.regs = (SercomUsart *)DT_ATMEL_SAM0_UART_SERCOM_##n##_BASE_ADDRESS,	\
-	.baudrate = DT_ATMEL_SAM0_UART_SERCOM_##n##_CURRENT_SPEED,		\
-	.mclk = MCLK_SERCOM##n,							\
-	.mclk_mask = MCLK_SERCOM##n##_MASK,					\
-	.gclk_core_id = SERCOM##n##_GCLK_ID_CORE,				\
-	.pads = UART_SAM0_SERCOM_PADS(n),					\
-	UART_SAM0_IRQ_HANDLER_FUNC(n)						\
-	UART_SAM0_DMA_CHANNELS(n)						\
+#define UART_SAM0_CONFIG_DEFN(n)					\
+static const struct uart_sam0_dev_cfg uart_sam0_config_##n = {		\
+	.regs = (SercomUsart *)DT_INST_REG_ADDR(n),			\
+	.baudrate = DT_INST_PROP(n, current_speed),			\
+	.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n),	\
+	.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)),	\
+	.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
+	.pads = UART_SAM0_SERCOM_PADS(n),				\
+	UART_SAM0_IRQ_HANDLER_FUNC(n)					\
+	UART_SAM0_DMA_CHANNELS(n)					\
 }
 #else
-#define UART_SAM0_CONFIG_DEFN(n)						\
-static const struct uart_sam0_dev_cfg uart_sam0_config_##n = {			\
-	.regs = (SercomUsart *)DT_ATMEL_SAM0_UART_SERCOM_##n##_BASE_ADDRESS,	\
-	.baudrate = DT_ATMEL_SAM0_UART_SERCOM_##n##_CURRENT_SPEED,		\
-	.pm_apbcmask = PM_APBCMASK_SERCOM##n,					\
-	.gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE,			\
-	.pads = UART_SAM0_SERCOM_PADS(n),					\
-	UART_SAM0_IRQ_HANDLER_FUNC(n)						\
-	UART_SAM0_DMA_CHANNELS(n)						\
+#define UART_SAM0_CONFIG_DEFN(n)					\
+static const struct uart_sam0_dev_cfg uart_sam0_config_##n = {		\
+	.regs = (SercomUsart *)DT_INST_REG_ADDR(n),			\
+	.baudrate = DT_INST_PROP(n, current_speed),			\
+	.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)),	\
+	.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
+	.pads = UART_SAM0_SERCOM_PADS(n),				\
+	UART_SAM0_IRQ_HANDLER_FUNC(n)					\
+	UART_SAM0_DMA_CHANNELS(n)					\
 }
 #endif
 
-#define UART_SAM0_DEVICE_INIT(n)						\
-static struct uart_sam0_dev_data uart_sam0_data_##n;				\
-UART_SAM0_IRQ_HANDLER_DECL(n);							\
-UART_SAM0_CONFIG_DEFN(n);							\
-DEVICE_AND_API_INIT(uart_sam0_##n, DT_ATMEL_SAM0_UART_SERCOM_##n##_LABEL,	\
-		    uart_sam0_init, &uart_sam0_data_##n,			\
-		    &uart_sam0_config_##n, PRE_KERNEL_1,			\
-		    CONFIG_KERNEL_INIT_PRIORITY_DEVICE,				\
-		    &uart_sam0_driver_api);					\
+#define UART_SAM0_DEVICE_INIT(n)					\
+static struct uart_sam0_dev_data uart_sam0_data_##n;			\
+UART_SAM0_IRQ_HANDLER_DECL(n);						\
+UART_SAM0_CONFIG_DEFN(n);						\
+DEVICE_AND_API_INIT(uart_sam0_##n, DT_INST_LABEL(n),			\
+		    uart_sam0_init, &uart_sam0_data_##n,		\
+		    &uart_sam0_config_##n, PRE_KERNEL_1,		\
+		    CONFIG_KERNEL_INIT_PRIORITY_DEVICE,			\
+		    &uart_sam0_driver_api);				\
 UART_SAM0_IRQ_HANDLER(n)
 
-#if DT_ATMEL_SAM0_UART_SERCOM_0_BASE_ADDRESS
-UART_SAM0_DEVICE_INIT(0)
-#endif
-
-#if DT_ATMEL_SAM0_UART_SERCOM_1_BASE_ADDRESS
-UART_SAM0_DEVICE_INIT(1)
-#endif
-
-#if DT_ATMEL_SAM0_UART_SERCOM_2_BASE_ADDRESS
-UART_SAM0_DEVICE_INIT(2)
-#endif
-
-#if DT_ATMEL_SAM0_UART_SERCOM_3_BASE_ADDRESS
-UART_SAM0_DEVICE_INIT(3)
-#endif
-
-#if DT_ATMEL_SAM0_UART_SERCOM_4_BASE_ADDRESS
-UART_SAM0_DEVICE_INIT(4)
-#endif
-
-#if DT_ATMEL_SAM0_UART_SERCOM_5_BASE_ADDRESS
-UART_SAM0_DEVICE_INIT(5)
-#endif
-
-#if DT_ATMEL_SAM0_UART_SERCOM_6_BASE_ADDRESS
-UART_SAM0_DEVICE_INIT(6)
-#endif
-
-#if DT_ATMEL_SAM0_UART_SERCOM7_BASE_ADDRESS
-UART_SAM0_DEVICE_INIT(7)
-#endif
+DT_INST_FOREACH(UART_SAM0_DEVICE_INIT)
diff --git a/dts/bindings/serial/atmel,sam0-uart.yaml b/dts/bindings/serial/atmel,sam0-uart.yaml
@@ -27,12 +27,19 @@ properties:
       required: true
       description: Transmit Data Pinout
 
-    rxdma:
-      type: int
-      required: false
-      description: Receive DMA channel
-
-    txdma:
-      type: int
-      required: false
-      description: Transmit DMA channel
+    dmas:
+      description: |
+        Optional TX & RX dma specifiers.  Each specifier will have a phandle
+        reference to the dmac controller, the channel number, and peripheral
+        trigger source.
+
+        For example dmas for TX, RX on SERCOM3
+           dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
+
+    dma-names:
+      description: |
+        Required if the dmas property exists.  This should be "tx" and "rx"
+        to match the dmas property.
+
+        For example
+           dma-names = "tx", "rx";