diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 6dabc0e8e3e38e0..a39631e9e55410c 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -59,6 +59,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_RA8_SCI_B uart_renesas_ra8_sci_b.c) zephyr_library_sources_ifdef(CONFIG_UART_RCAR uart_rcar.c) zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RA uart_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO_PIO uart_rpi_pico_pio.c) +zephyr_library_sources_ifdef(CONFIG_UART_RTS5912 uart_realtek_rts5912.c) zephyr_library_sources_ifdef(CONFIG_UART_RTT_DRIVER uart_rtt.c) zephyr_library_sources_ifdef(CONFIG_UART_RV32M1_LPUART uart_rv32m1_lpuart.c) zephyr_library_sources_ifdef(CONFIG_UART_RZT2M uart_rzt2m.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a8b20fe2877b4aa..fe09133f0f2006b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -221,4 +221,6 @@ rsource "Kconfig.xmc4xxx" source "drivers/serial/Kconfig.si32" +source "drivers/serial/Kconfig.realtek_rts5912" + endif # SERIAL diff --git a/drivers/serial/Kconfig.realtek_rts5912 b/drivers/serial/Kconfig.realtek_rts5912 new file mode 100644 index 000000000000000..c320d3b512aeeb4 --- /dev/null +++ b/drivers/serial/Kconfig.realtek_rts5912 @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config UART_RTS5912 + bool "UART driver for Realtek RTS5912 EC" + default y + depends on DT_HAS_REALTEK_RTS5912_UART_ENABLED + select SERIAL_HAS_DRIVER + select PINCTRL + select CLOCK_CONTROL + help + This option enables the UART driver for Realtek RTS591x EC. + Say y if you wish to use serial port on Realtek RTS591x EC. diff --git a/drivers/serial/uart_realtek_rts5912.c b/drivers/serial/uart_realtek_rts5912.c new file mode 100644 index 000000000000000..4c0cacce2051543 --- /dev/null +++ b/drivers/serial/uart_realtek_rts5912.c @@ -0,0 +1,383 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#define DT_DRV_COMPAT realtek_rts5912_uart + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +LOG_MODULE_REGISTER(uart_rts5912, CONFIG_UART_LOG_LEVEL); + +#define IIR_MSTAT 0x00 /* modem status interrupt */ +#define IIR_NIP 0x01 /* no interrupt pending */ +#define IIR_THRE 0x02 /* transmit holding register empty interrupt */ +#define IIR_RBRF 0x04 /* receiver buffer register full interrupt */ +#define IIR_LS 0x06 /* receiver line status interrupt */ +#define IIR_MASK 0x07 /* interrupt id bits mask */ +#define IIR_ID 0x06 /* interrupt ID mask without NIP */ + +#define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */ +#define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */ +#define FCR_XMITCLR 0x04 /* clear XMIT FIFO */ + +#define FCR_MODE0 0x00 /* set receiver in mode 0 */ +#define FCR_MODE1 0x08 /* set receiver in mode 1 */ + +/* RCVR FIFO interrupt levels: trigger interrupt with this bytes in FIFO */ +#define FCR_FIFO_1 0x00 /* 1 byte in RCVR FIFO */ +#define FCR_FIFO_4 0x40 /* 4 bytes in RCVR FIFO */ +#define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */ +#define FCR_FIFO_14 0xC0 /* 14 bytes in RCVR FIFO */ + +/* constants for line control register */ +#define LCR_CS5 0x00 /* 5 bits data size */ +#define LCR_CS6 0x01 /* 6 bits data size */ +#define LCR_CS7 0x02 /* 7 bits data size */ +#define LCR_CS8 0x03 /* 8 bits data size */ +#define LCR_2_STB 0x04 /* 2 stop bits */ +#define LCR_1_STB 0x00 /* 1 stop bit */ +#define LCR_PEN 0x08 /* parity enable */ +#define LCR_PDIS 0x00 /* parity disable */ +#define LCR_EPS 0x10 /* even parity select */ +#define LCR_SP 0x20 /* stick parity select */ +#define LCR_SBRK 0x40 /* break control bit */ +#define LCR_DLAB 0x80 /* divisor latch access enable */ + +#define RECEIVER_LINE_STATUS 0x06 + +#define IIRC(dev) (((struct uart_rts5912_dev_data *)(dev)->data)->iir_cache) + +/* device config */ +struct uart_rts5912_device_config { + UART_Type *regs; + const struct pinctrl_dev_config *pcfg; + const struct device *clk_dev; + uint32_t clk_grp; + uint32_t clk_idx; + uint32_t clk_src; + uint32_t clk_div; +}; + +/** Device data structure */ +struct uart_rts5912_dev_data { + struct uart_config uart_config; + struct k_spinlock lock; + uint8_t fcr_cache; + uint8_t iir_cache; +}; + +static int uart_rts5912_set_baud_rate(const struct device *dev, uint32_t baud_rate) +{ + const struct uart_rts5912_device_config *const dev_cfg = dev->config; + struct uart_rts5912_dev_data *dev_data = dev->data; + UART_Type *regs = dev_cfg->regs; + + struct rts5912_sccon_subsys sccon_subsys = { + .clk_grp = dev_cfg->clk_grp, + .clk_idx = dev_cfg->clk_idx, + .clk_src = dev_cfg->clk_src, + .clk_div = dev_cfg->clk_div, + }; + uint32_t uart_clk_freq; + uint32_t divisor; + uint8_t lcr_cache; + int rc; + + rc = clock_control_get_rate(dev_cfg->clk_dev, &sccon_subsys, &uart_clk_freq); + if (rc != 0) { + return rc; + } + + if ((baud_rate != 0U) && (uart_clk_freq != 0U)) { + /* + * calculate baud rate divisor. a variant of + * (uint32_t)(dev_cfg->sys_clk_freq / (16.0 * baud_rate) + 0.5) + */ + divisor = ((uart_clk_freq + (baud_rate << 3)) / baud_rate) >> 4; + + /* set the DLAB to access the baud rate divisor registers */ + lcr_cache = regs->LCR; + regs->LCR = UART_LCR_DLAB_Msk | lcr_cache; + regs->DLL = (uint8_t)(divisor & 0xff); + regs->DLH = (uint8_t)((divisor >> 8) & 0xff); + + /* restore the DLAB to access the baud rate divisor registers */ + regs->LCR = lcr_cache; + + dev_data->uart_config.baudrate = baud_rate; + } + + return 0; +} + +static int uart_rts5912_poll_in(const struct device *dev, unsigned char *c) +{ + const struct uart_rts5912_device_config *const dev_cfg = dev->config; + struct uart_rts5912_dev_data *dev_data = dev->data; + UART_Type *regs = dev_cfg->regs; + + int ret = -1; + + k_spinlock_key_t key = k_spin_lock(&dev_data->lock); + + if ((regs->LSR & UART_LSR_DR_Msk) != 0) { + *c = regs->RBR; + ret = 0; + } + + k_spin_unlock(&dev_data->lock, key); + + return ret; +} + +static void uart_rts5912_poll_out(const struct device *dev, unsigned char c) +{ + const struct uart_rts5912_device_config *const dev_cfg = dev->config; + struct uart_rts5912_dev_data *dev_data = dev->data; + UART_Type *regs = dev_cfg->regs; + + k_spinlock_key_t key = k_spin_lock(&dev_data->lock); + + while ((regs->LSR & UART_LSR_THRE_Msk) == 0) + ; + + regs->THR = c; + + k_spin_unlock(&dev_data->lock, key); +} + +static int uart_rts5912_err_check(const struct device *dev) +{ + const struct uart_rts5912_device_config *const dev_cfg = dev->config; + UART_Type *regs = dev_cfg->regs; + uint32_t lsr, iir; + int err = 0; + + iir = regs->IIR; + if (((iir & UART_IIR_IID_Msk) >> UART_IIR_IID_Pos) == RECEIVER_LINE_STATUS) { + lsr = regs->LSR; + if (lsr & UART_LSR_RFE_Msk) { + if (lsr & UART_LSR_FE_Msk) { + err |= UART_ERROR_FRAMING; + } + if (lsr & UART_LSR_PE_Msk) { + err |= UART_ERROR_PARITY; + } + } + if (lsr & UART_LSR_OE_Msk) { + err |= UART_ERROR_OVERRUN; + } + if (lsr & UART_LSR_BI_Msk) { + err |= UART_BREAK; + } + } + + return err; +} + +static int uart_rts5912_configure(const struct device *dev, const struct uart_config *cfg) +{ + const struct uart_rts5912_device_config *const dev_cfg = dev->config; + struct uart_rts5912_dev_data *dev_data = dev->data; + UART_Type *regs = dev_cfg->regs; + + int ret = 0; + uint32_t lcr_cache; + + k_spinlock_key_t key = k_spin_lock(&dev_data->lock); + + ARG_UNUSED(dev_data); + + dev_data->fcr_cache = 0U; + dev_data->iir_cache = 0U; + + ret = uart_rts5912_set_baud_rate(dev, cfg->baudrate); + if (ret != 0) { + return ret; + } + + /* Local structure to hold temporary values */ + struct uart_config uart_cfg; + + switch (cfg->data_bits) { + case UART_CFG_DATA_BITS_5: + uart_cfg.data_bits = LCR_CS5; + break; + case UART_CFG_DATA_BITS_6: + uart_cfg.data_bits = LCR_CS6; + break; + case UART_CFG_DATA_BITS_7: + uart_cfg.data_bits = LCR_CS7; + break; + case UART_CFG_DATA_BITS_8: + uart_cfg.data_bits = LCR_CS8; + break; + default: + ret = -ENOTSUP; + goto out; + } + + switch (cfg->stop_bits) { + case UART_CFG_STOP_BITS_1: + uart_cfg.stop_bits = LCR_1_STB; + break; + case UART_CFG_STOP_BITS_2: + uart_cfg.stop_bits = LCR_2_STB; + break; + default: + ret = -ENOTSUP; + goto out; + } + + switch (cfg->parity) { + case UART_CFG_PARITY_NONE: + uart_cfg.parity = LCR_PDIS; + break; + case UART_CFG_PARITY_EVEN: + uart_cfg.parity = LCR_EPS; + break; + default: + ret = -ENOTSUP; + goto out; + } + + dev_data->uart_config = *cfg; + + /* data bits, stop bits, parity, clear DLAB */ + regs->LCR = uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity; + + /* + * Program FIFO: enabled, mode 0 + * generate the interrupt at 4th byte + * Clear TX and RX FIFO + */ + dev_data->fcr_cache = FCR_FIFO | FCR_MODE0 | FCR_FIFO_4 | FCR_RCVRCLR | FCR_XMITCLR; + regs->FCR = dev_data->fcr_cache; + + /* clear the port */ + lcr_cache = regs->LCR; + regs->LCR = UART_LCR_DLAB_Msk | lcr_cache; + regs->LCR = lcr_cache; + + /* disable interrupts */ + regs->IER = 0; + +out: + k_spin_unlock(&dev_data->lock, key); + return ret; +} + +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE +static int uart_rts5912_config_get(const struct device *dev, struct uart_config *cfg) +{ + struct uart_rts5912_dev_data *data = dev->data; + + cfg->baudrate = data->uart_config.baudrate; + cfg->parity = data->uart_config.parity; + cfg->stop_bits = data->uart_config.stop_bits; + cfg->data_bits = data->uart_config.data_bits; + cfg->flow_ctrl = data->uart_config.flow_ctrl; + + return 0; +} +#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ + +static const struct uart_driver_api rts5912_uart_driver_api = { + .poll_in = uart_rts5912_poll_in, + .poll_out = uart_rts5912_poll_out, + .err_check = uart_rts5912_err_check, +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + .configure = uart_rts5912_configure, + .config_get = uart_rts5912_config_get, +#endif +}; + +static int rts5912_uart_init(const struct device *dev) +{ + const struct uart_rts5912_device_config *const dev_cfg = dev->config; + struct uart_rts5912_dev_data *dev_data = dev->data; + struct rts5912_sccon_subsys sccon_subsys = { + .clk_grp = dev_cfg->clk_grp, + .clk_idx = dev_cfg->clk_idx, + .clk_src = dev_cfg->clk_src, + .clk_div = dev_cfg->clk_div, + }; + + int rc; + + if (!device_is_ready(dev_cfg->clk_dev)) { + return -ENODEV; + } + + rc = clock_control_on(dev_cfg->clk_dev, (clock_control_subsys_t)&sccon_subsys); + if (rc != 0) { + return rc; + } + + rc = uart_rts5912_configure(dev, &dev_data->uart_config); + if (rc != 0) { + return rc; + } + + rc = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); + + return 0; +} + +#define DEV_CONFIG_REG_INIT(n) .regs = (UART_Type *)(DT_INST_REG_ADDR(n)), + +#define DEV_CONFIG_CLK_DEV_INIT(n) \ + .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(uart##n), uart##n, clk_grp), \ + .clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(uart##n), uart##n, clk_idx), + +#define DEV_CONFIG_IRQ_FUNC_INIT(n) +#define UART_RTS5912_IRQ_FUNC_DECLARE(n) +#define UART_RTS5912_IRQ_FUNC_DEFINE(n) + +#define DEV_DATA_FLOW_CTRL(n) DT_INST_PROP_OR(n, hw_flow_control, UART_CFG_FLOW_CTRL_NONE) + +#define UART_RTS5912_DEVICE_INIT(n) \ + \ + PINCTRL_DT_INST_DEFINE(n); \ + \ + UART_RTS5912_IRQ_FUNC_DECLARE(n); \ + \ + static const struct uart_rts5912_device_config uart_rts5912_dev_cfg_##n = { \ + DEV_CONFIG_REG_INIT(n) DEV_CONFIG_IRQ_FUNC_INIT(n) DEV_CONFIG_CLK_DEV_INIT(n) \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + }; \ + static struct uart_rts5912_dev_data uart_rts5912_dev_data_##n = { \ + .uart_config.baudrate = DT_INST_PROP_OR(n, current_speed, 0), \ + .uart_config.parity = UART_CFG_PARITY_NONE, \ + .uart_config.stop_bits = UART_CFG_STOP_BITS_1, \ + .uart_config.data_bits = UART_CFG_DATA_BITS_8, \ + .uart_config.flow_ctrl = DEV_DATA_FLOW_CTRL(n), \ + }; \ + DEVICE_DT_INST_DEFINE(n, &rts5912_uart_init, NULL, &uart_rts5912_dev_data_##n, \ + &uart_rts5912_dev_cfg_##n, PRE_KERNEL_1, \ + CONFIG_SERIAL_INIT_PRIORITY, &rts5912_uart_driver_api); \ + UART_RTS5912_IRQ_FUNC_DEFINE(n) + +DT_INST_FOREACH_STATUS_OKAY(UART_RTS5912_DEVICE_INIT) diff --git a/dts/arm/realtek/ec/rts5912.dtsi b/dts/arm/realtek/ec/rts5912.dtsi index e8daf5a6f72fcad..f8ba9045e6bad4b 100644 --- a/dts/arm/realtek/ec/rts5912.dtsi +++ b/dts/arm/realtek/ec/rts5912.dtsi @@ -77,6 +77,16 @@ status = "okay"; }; + uart0: uart@40010100 { + compatible = "realtek,rts5912-uart"; + reg = <0x40010100 0x100>; + clocks = <&sccon RTS5912_SCCON_UART UART0_CLKPWR >; + clock-names = "uart0"; + interrupt-parent = <&nvic>; + interrupts = <191 0>; + status = "disabled"; + }; + pinctrl: pin-controller@40090000 { compatible = "realtek,rts5912-pinctrl"; #address-cells = <1>; diff --git a/dts/bindings/serial/realtek,rts5912-uart.yaml b/dts/bindings/serial/realtek,rts5912-uart.yaml new file mode 100644 index 000000000000000..6f57da6aca76626 --- /dev/null +++ b/dts/bindings/serial/realtek,rts5912-uart.yaml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +description: Realtek Rts5912 Uart + +compatible: "realtek,rts5912-uart" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true diff --git a/soc/realtek/ec/rts5912/reg/reg_uart.h b/soc/realtek/ec/rts5912/reg/reg_uart.h new file mode 100644 index 000000000000000..21086f53a4e0606 --- /dev/null +++ b/soc/realtek/ec/rts5912/reg/reg_uart.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2023 Realtek, SIBG-SD7 + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _REALTEK_RTS5912_REG_UART_H +#define _REALTEK_RTS5912_REG_UART_H + +/* + * @brief UART Controller (UART) + */ + +typedef struct { + union { + const volatile uint32_t RBR; + volatile uint32_t THR; + volatile uint32_t DLL; + }; + union { + volatile uint32_t DLH; + volatile uint32_t IER; + }; + union { + const volatile uint32_t IIR; + volatile uint32_t FCR; + }; + volatile uint32_t LCR; + const volatile uint32_t RESERVED; + const volatile uint32_t LSR; + const volatile uint32_t RESERVED1[25]; + const volatile uint32_t USR; + const volatile uint32_t TFL; + const volatile uint32_t RFL; + volatile uint32_t SRR; +} UART_Type; + +/* RBR */ +#define UART_RBR_DATA_Pos (0UL) +#define UART_RBR_DATA_Msk GENMASK(7, 0) +/* THR */ +#define UART_THR_DATA_Pos (0UL) +#define UART_THR_DATA_Msk GENMASK(7, 0) +/* DLL */ +#define UART_DLL_DIVL_Pos (0UL) +#define UART_DLL_DIVL_Msk GENMASK(7, 0) +/* DLH */ +#define UART_DLH_DIVH_Pos (0UL) +#define UART_DLH_DIVH_Msk GENMASK(7, 0) +/* IER */ +#define UART_IER_ERBFI_Pos (0UL) +#define UART_IER_ERBFI_Msk BIT(UART_IER_ERBFI_Pos) +#define UART_IER_ETBEI_Pos (1UL) +#define UART_IER_ETBEI_Msk BIT(UART_IER_ETBEI_Pos) +#define UART_IER_ELSI_Pos (2UL) +#define UART_IER_ELSI_Msk BIT(UART_IER_ELSI_Pos) +#define UART_IER_PTIME_Pos (7UL) +#define UART_IER_PTIME_Msk BIT(UART_IER_PTIME_Pos) +/* IIR */ +#define UART_IIR_IID_Pos (0UL) +#define UART_IIR_IID_Msk GENMASK(3, 0) +#define UART_IIR_FIFOSE_Pos (6UL) +#define UART_IIR_FIFOSE_Msk GENMASK(7, 6) +/* FCR */ +#define UART_FCR_FIFOE_Pos (0UL) +#define UART_FCR_FIFOE_Msk BIT(UART_FCR_FIFOE_Pos) +#define UART_FCR_RFIFOR_Pos (1UL) +#define UART_FCR_RFIFOR_Msk BIT(UART_FCR_RFIFOR_Pos) +#define UART_FCR_XFIFOR_Pos (2UL) +#define UART_FCR_XFIFOR_Msk BIT(UART_FCR_XFIFOR_Pos) +#define UART_FCR_TXTRILEV_Pos (4UL) +#define UART_FCR_TXTRILEV_Msk GENMASK(5, 4) +#define UART_FCR_RXTRILEV_Pos (6UL) +#define UART_FCR_RXTRILEV_Msk GENMASK(7, 6) +/* LCR */ +#define UART_LCR_DLS_Pos (0UL) +#define UART_LCR_DLS_Msk GENMASK(1, 0) +#define UART_LCR_STOP_Pos (2UL) +#define UART_LCR_STOP_Msk BIT(UART_LCR_STOP_Pos) +#define UART_LCR_PEN_Pos (3UL) +#define UART_LCR_PEN_Msk BIT(UART_LCR_PEN_Pos) +#define UART_LCR_EPS_Pos (4UL) +#define UART_LCR_EPS_Msk BIT(UART_LCR_EPS_Pos) +#define UART_LCR_STP_Pos (5UL) +#define UART_LCR_STP_Msk BIT(UART_LCR_STP_Pos) +#define UART_LCR_BC_Pos (6UL) +#define UART_LCR_BC_Msk BIT(UART_LCR_BC_Pos) +#define UART_LCR_DLAB_Pos (7UL) +#define UART_LCR_DLAB_Msk BIT(UART_LCR_DLAB_Pos) +/* LSR */ +#define UART_LSR_DR_Pos (0UL) +#define UART_LSR_DR_Msk BIT(UART_LSR_DR_Pos) +#define UART_LSR_OE_Pos (1UL) +#define UART_LSR_OE_Msk BIT(UART_LSR_OE_Pos) +#define UART_LSR_PE_Pos (2UL) +#define UART_LSR_PE_Msk BIT(UART_LSR_PE_Pos) +#define UART_LSR_FE_Pos (3UL) +#define UART_LSR_FE_Msk BIT(UART_LSR_FE_Pos) +#define UART_LSR_BI_Pos (4UL) +#define UART_LSR_BI_Msk BIT(UART_LSR_BI_Pos) +#define UART_LSR_THRE_Pos (5UL) +#define UART_LSR_THRE_Msk BIT(UART_LSR_THRE_Pos) +#define UART_LSR_TEMT_Pos (6UL) +#define UART_LSR_TEMT_Msk BIT(UART_LSR_TEMT_Pos) +#define UART_LSR_RFE_Pos (7UL) +#define UART_LSR_RFE_Msk BIT(UART_LSR_RFE_Pos) +/* USR */ +#define UART_USR_BUSY_Pos (0UL) +#define UART_USR_BUSY_Msk BIT(UART_USR_BUSY_Pos) +#define UART_USR_TFNF_Pos (1UL) +#define UART_USR_TFNF_Msk BIT(UART_USR_TFNF_Pos) +#define UART_USR_TFE_Pos (2UL) +#define UART_USR_TFE_Msk BIT(UART_USR_TFE_Pos) +#define UART_USR_RFNE_Pos (3UL) +#define UART_USR_RFNE_Msk BIT(UART_USR_RFNE_Pos) +#define UART_USR_RFF_Pos (4UL) +#define UART_USR_RFF_Msk BIT(UART_USR_RFF_Pos) +/* SRR */ +#define UART_SRR_UR_Pos (0UL) +#define UART_SRR_UR_Msk BIT(UART_SRR_UR_Pos) +#define UART_SRR_RFR_Pos (1UL) +#define UART_SRR_RFR_Msk BIT(UART_SRR_RFR_Pos) +#define UART_SRR_XFR_Pos (2UL) +#define UART_SRR_XFR_Msk BIT(UART_SRR_XFR_Pos) + +#endif /* _REALTEK_RTS5912_REG_UART_H */