.gitignore

altera/simulation/modelsim
altera/output_files
*.dpf
PLLJ_PLLSPE_INFO.txt
*.qws
altera/greybox_tmp
xilinx/NaiveMIPS/isim/test_isim_beh.exe.sim/
xilinx/NaiveMIPS/isim/work/
*.debug
*.veo
xilinx/CPLD/top_html/
*.prw
*.ver
*.xdl
*.ppr
*.xsl
*.elf
*.sym
*.blc
xilinx/NaiveMIPS/ipcore_dir/*/simulation/
xilinx/NaiveMIPS/ipcore_dir/*/doc/
planAhead_run_*
xilinx/NaiveMIPS/ipcore_dir/*/example_design/
*.log
*.bak
.DS_Store
.qsys_edit/
*.sopcinfo
altera/naive_mips_soc/simulation/cadence/
altera/naive_mips_soc/simulation/mentor/libraries/Cache_0/@cache/_primary.dat
altera/naive_mips_soc/simulation/mentor/libraries/
altera/naive_mips_soc/simulation/submodules/
altera/naive_mips_soc/synthesis/
altera/naive_mips_soc_cache/synthesis/
altera_de1_soc/software/spl_bsp/uboot-socfpga/
altera/naive_mips_soc/simulation/mentor/work/
altera/sim_cache/simulation/mentor/libraries/
altera/sim_cache/simulation/submodules/
altera_de1_soc/pll_hf_sim/
altera/naive_mips_soc_cache/simulation/mentor/libraries/
._*