From d8adceec0dfe6c7a1664cdf78d334280285a009d Mon Sep 17 00:00:00 2001 From: David Garske Date: Tue, 26 Sep 2023 13:29:48 -0700 Subject: [PATCH] Fix upper real page number from c code. Relocate to upper regions CCSRBAR, Flash and CPLD. Cleanups for readability. --- hal/nxp_p1021.c | 14 ++++---- hal/nxp_ppc.h | 21 ++++++----- hal/nxp_t1024.c | 30 ++++++++-------- hal/nxp_t2080.c | 10 +++--- src/boot_ppc.c | 16 +++++---- src/boot_ppc_mp.S | 12 +++---- src/boot_ppc_start.S | 86 ++++++++++++++++++++++---------------------- 7 files changed, 95 insertions(+), 94 deletions(-) diff --git a/hal/nxp_p1021.c b/hal/nxp_p1021.c index 455d3d1b8..d9fb746b5 100644 --- a/hal/nxp_p1021.c +++ b/hal/nxp_p1021.c @@ -992,18 +992,18 @@ static int hal_pcie_init(void) set_law(3, CONFIG_SYS_PCIE2_IO_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_64KB), /* Map TLB for PCIe */ - set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1); set_tlb(1, 3, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000), - (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000), + (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000), 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1); - set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1); set_tlb(1, 5, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000), - (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), + (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1); - set_tlb(1, 6, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS, + set_tlb(1, 6, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1); return 0; } @@ -1016,7 +1016,7 @@ static int hal_cpld_init(void) /* Setup Local Access Window (LAW) for CPLD/BCSR */ set_law(5, BCSR_BASE, LAW_TRGT_ELBC, LAW_SIZE_256KB); /* Setup TLB MMU (Translation Lookaside Buffer) for CPLD/BCSR */ - set_tlb(1, 8, BCSR_BASE, BCSR_BASE, MAS3_SX | MAS3_SW | MAS3_SR, + set_tlb(1, 8, BCSR_BASE, BCSR_BASE, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1); /* setup eLBC for CPLD (CS1), 8-bit */ @@ -1509,7 +1509,7 @@ static void hal_mp_init(void) /* map reset page to bootpg so we can copy code there */ disable_tlb1(i_tlb); - set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, /* tlb, epn, rpn */ + set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn */ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, /* perms, wimge */ 0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h index 2d4b5c109..656776493 100644 --- a/hal/nxp_ppc.h +++ b/hal/nxp_ppc.h @@ -64,8 +64,8 @@ #define CCSRBAR_SIZE BOOKE_PAGESZ_16M /* relocate to 64-bit 0xF_ */ - //#define CCSRBAR_PHYS_HIGH 0xF - //#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF) + #define CCSRBAR_PHYS_HIGH 0xFULL + #define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF) #define ENABLE_L1_CACHE #define ENABLE_L2_CACHE @@ -80,7 +80,7 @@ #define ENABLE_DDR #define FLASH_BASE_ADDR 0xEC000000 - #define FLASH_BASE_PHYS_HIGH 0x0 + #define FLASH_BASE_PHYS_HIGH 0xFULL #define FLASH_LAW_SIZE LAW_SIZE_64MB #define FLASH_TLB_PAGESZ BOOKE_PAGESZ_64M @@ -96,7 +96,7 @@ #define CCSRBAR_SIZE BOOKE_PAGESZ_16M /* relocate to 64-bit 0xE_ */ - //#define CCSRBAR_PHYS_HIGH 0xE + //#define CCSRBAR_PHYS_HIGH 0xEULL //#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF) #define ENABLE_L1_CACHE @@ -108,7 +108,7 @@ #define ENABLE_DDR #define FLASH_BASE_ADDR 0xE8000000 - #define FLASH_BASE_PHYS_HIGH 0x0 + #define FLASH_BASE_PHYS_HIGH 0x0ULL #define FLASH_LAW_SIZE LAW_SIZE_128MB #define FLASH_TLB_PAGESZ BOOKE_PAGESZ_128M @@ -141,7 +141,7 @@ #define CCSRBAR_PHYS CCSRBAR #endif #ifndef CCSRBAR_PHYS_HIGH -#define CCSRBAR_PHYS_HIGH 0 +#define CCSRBAR_PHYS_HIGH 0ULL #endif /* DDR */ @@ -519,8 +519,7 @@ (((epn) & MAS2_EPN) | (wimge)) #define BOOKE_MAS3(rpn, user, perms) \ (((rpn) & MAS3_RPN) | (user) | (perms)) -#define BOOKE_MAS7(rpn) \ - (((unsigned long long)(rpn) >> 32) & MAS7_RPN) +#define BOOKE_MAS7(urpn) (urpn) /* Stringification */ #ifndef WC_STRINGIFY @@ -536,7 +535,6 @@ }) #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) -#define GET_PHYS_HIGH(addr) (((uint64_t)(addr)) >> 32) #ifndef __ASSEMBLER__ @@ -605,8 +603,9 @@ static inline void set32(volatile unsigned int *addr, unsigned int val) } /* C version in boot_ppc.c */ -extern void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn, - uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize, uint8_t iprot); +extern void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint32_t rpn, + uint32_t urpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize, + uint8_t iprot); extern void disable_tlb1(uint8_t esel); extern void flush_cache(uint32_t start_addr, uint32_t size); diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index e88ede32e..fc488960b 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -27,7 +27,7 @@ /* Tested on T1024E Rev 1.0, e5500 core 2.1, PVR 8024_1021 and SVR 8548_0010 */ /* IFC: CS0 NOR, CS1 MRAM, CS2 CPLD, CS3, MPU CPLD */ -/* DDR4 w/ECC (5 chips MT40A256M16GE-083EIT) - I2C1 SPD Addr 0x51 */ +/* DDR: DDR4 w/ECC (5 chips MT40A256M16GE-083EIT) - SPD on I2C1 at Addr 0x51 */ /* Tests */ #if 1 @@ -261,7 +261,7 @@ static int test_tpm(void); #define IFC_FTIM2(n) ((volatile uint32_t*)(IFC_BASE + 0x01C8 + (n * 0x30))) #define IFC_FTIM3(n) ((volatile uint32_t*)(IFC_BASE + 0x01CC + (n * 0x30))) -#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFF0000) /* Physical base address */ +#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFFFF00) /* Physical base address */ #define IFC_CSPR_PORT_SIZE_8 0x00000080 /* Port Size 8 */ #define IFC_CSPR_PORT_SIZE_16 0x00000100 /* Port Size 16 */ #define IFC_CSPR_WP 0x00000040 /* Write Protect */ @@ -316,8 +316,6 @@ enum ifc_amask_sizes { /* NOR Flash */ -#define FLASH_BASE 0xEC000000 - #define FLASH_BANK_SIZE (64*1024*1024) #define FLASH_PAGE_SIZE (1024) /* program buffer */ #define FLASH_SECTOR_SIZE (128*1024) @@ -361,7 +359,7 @@ enum ifc_amask_sizes { /* CPLD */ #define CPLD_BASE 0xFFDF0000 -#define CPLD_BASE_PHYS (0xF00000000ULL | CPLD_BASE) +#define CPLD_BASE_PHYS_HIGH 0xFULL #define CPLD_VER 0x00 /* CPLD Major Revision Register */ #define CPLD_VER_SUB 0x01 /* CPLD Minor Revision Register */ @@ -754,7 +752,7 @@ void uart_write(const char* buf, uint32_t sz) #if 0 static void* hal_flash_map(uintptr_t sect, uintptr_t offset) { - uint8_t* ptr = FLASH_BASE; + uint8_t* ptr = FLASH_BASE_ADDR; #define FLASH_SECTORS (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE) #define FLASH_CFI_16BIT 0x02 /* word */ @@ -784,7 +782,7 @@ static void hal_flash_init(void) set32(IFC_FTIM3(0), 0); /* NOR IFC Definitions (CS0) */ set32(IFC_CSPR_EXT(0), FLASH_BASE_PHYS_HIGH); - set32(IFC_CSPR(0), (IFC_CSPR_PHYS_ADDR(FLASH_BASE) | \ + set32(IFC_CSPR(0), (IFC_CSPR_PHYS_ADDR(FLASH_BASE_ADDR) | \ IFC_CSPR_PORT_SIZE_16 | \ IFC_CSPR_MSEL_NOR | \ IFC_CSPR_V)); @@ -792,7 +790,7 @@ static void hal_flash_init(void) set32(IFC_CSOR(0), 0x0000000C); /* TRHZ (80 clocks for read enable high) */ /* Get Manufacture ID */ - #define FLASH_IO16(n) *((volatile uint16_t*)(FLASH_BASE + (n))) + #define FLASH_IO16(n) *((volatile uint16_t*)(FLASH_BASE_ADDR + (n))) FLASH_IO16(0) = (((uint16_t)FLASH_CMD_RESET) << 8); udelay(1); @@ -815,7 +813,7 @@ static void hal_ddr_init(void) } /* Map LAW for DDR */ - set_law(15, DDR_ADDRESS, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB); + set_law(15, 0, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB); /* Set early for clock / pin */ set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL); @@ -936,10 +934,10 @@ static void hal_ddr_init(void) #endif /* DDR - TBL=1, Entry 12/13 */ - set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS, + set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, BOOKE_PAGESZ_1G, 1); - set_tlb(1, 13, DDR_ADDRESS + 0x40000000, DDR_ADDRESS + 0x40000000, + set_tlb(1, 13, DDR_ADDRESS + 0x40000000, DDR_ADDRESS + 0x40000000, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, BOOKE_PAGESZ_1G, 1); #endif @@ -990,7 +988,7 @@ static void hal_cpld_init(void) set32(IFC_FTIM3(2), 0); /* CPLD IFC Definitions (CS2) */ - set32(IFC_CSPR_EXT(2), GET_PHYS_HIGH(CPLD_BASE_PHYS)); + set32(IFC_CSPR_EXT(2), CPLD_BASE_PHYS_HIGH); set32(IFC_CSPR(2), (IFC_CSPR_PHYS_ADDR(CPLD_BASE) | IFC_CSPR_PORT_SIZE_8 | IFC_CSPR_MSEL_GPCM | @@ -999,11 +997,11 @@ static void hal_cpld_init(void) set32(IFC_CSOR(2), 0); /* IFC - CPLD */ - set_law(2, GET_PHYS_HIGH(CPLD_BASE_PHYS), CPLD_BASE, + set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE, LAW_TRGT_IFC, LAW_SIZE_4KB); /* CPLD - TBL=1, Entry 11 */ - set_tlb(1, 11, CPLD_BASE, CPLD_BASE_PHYS, + set_tlb(1, 11, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_4K, 1); @@ -1337,7 +1335,7 @@ static void hal_mp_init(void) /* map reset page to bootpg so we can copy code there */ disable_tlb1(i_tlb); - set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, /* tlb, epn, rpn */ + set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn, urpn */ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */ 0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ @@ -1500,7 +1498,7 @@ static int test_flash(void) { int ret; uint32_t i; - uint8_t* pagePtr = (uint8_t*)FLASH_BASE + TEST_ADDRESS; + uint8_t* pagePtr = (uint8_t*)FLASH_BASE_ADDR + TEST_ADDRESS; #ifndef TEST_FLASH_READONLY /* Erase sector */ diff --git a/hal/nxp_t2080.c b/hal/nxp_t2080.c index a1f92b9c0..6a53204af 100644 --- a/hal/nxp_t2080.c +++ b/hal/nxp_t2080.c @@ -144,7 +144,7 @@ enum ifc_amask_sizes { #endif /* CPLD */ #define CPLD_BASE 0xFFDF0000 -#define CPLD_BASE_PHYS (0xF00000000ULL | CPLD_BASE) +#define CPLD_BASE_PHYS_HIGH 0xFULL #define CPLD_SPARE 0x00 #define CPLD_SATA_MUX_SEL 0x02 @@ -458,7 +458,7 @@ static void hal_ddr_init(void) while ((DDR_SDRAM_CFG_2 & DDR_SDRAM_CFG_2_D_INIT)); /* DDR - TBL=1, Entry 19 */ - set_tlb(1, 19, DDR_ADDRESS, DDR_ADDRESS, + set_tlb(1, 19, DDR_ADDRESS, DDR_ADDRESS, 0 MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, BOOKE_PAGESZ_2G, 1); #endif @@ -484,7 +484,7 @@ static void hal_cpld_init(void) IFC_FTIM3(3) = 0; /* CPLD IFC Definitions (CS3) */ - IFC_CSPR_EXT(3) = (0xF); + IFC_CSPR_EXT(3) = CPLD_BASE_PHYS_HIGH; IFC_CSPR(3) = (IFC_CSPR_PHYS_ADDR(CPLD_BASE) | IFC_CSPR_PORT_SIZE_16 | IFC_CSPR_MSEL_GPCM | @@ -493,11 +493,11 @@ static void hal_cpld_init(void) IFC_CSOR(3) = 0; /* IFC - CPLD */ - set_law(2, GET_PHYS_HIGH(CPLD_BASE_PHYS), CPLD_BASE, + set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE, LAW_TRGT_IFC, LAW_SIZE_4KB); /* CPLD - TBL=1, Entry 17 */ - set_tlb(1, 17, CPLD_BASE, CPLD_BASE_PHYS, + set_tlb(1, 17, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_4K, 1); #endif diff --git a/src/boot_ppc.c b/src/boot_ppc.c index c09f7d529..f965a8423 100644 --- a/src/boot_ppc.c +++ b/src/boot_ppc.c @@ -46,9 +46,9 @@ void write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3, asm volatile("isync;msync;tlbwe;isync"); } -void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn, - uint8_t perms, uint8_t wimge, - uint8_t ts, uint8_t tsize, uint8_t iprot) +void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint32_t rpn, + uint32_t urpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize, + uint8_t iprot) { uint32_t _mas0, _mas1, _mas2, _mas3, _mas7; @@ -56,7 +56,7 @@ void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn, _mas1 = BOOKE_MAS1(1, iprot, 0, ts, tsize); _mas2 = BOOKE_MAS2(epn, wimge); _mas3 = BOOKE_MAS3(rpn, 0, perms); - _mas7 = BOOKE_MAS7(rpn); + _mas7 = BOOKE_MAS7(urpn); write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7); } @@ -146,11 +146,11 @@ void do_boot(const uint32_t *app_offset, const uint32_t* dts_offset) void do_boot(const uint32_t *app_offset) #endif { - typedef void (*boot_entry)(uintptr_t r3, uintptr_t r4, uintptr_t r5, uintptr_t r6, - uintptr_t r7, uintptr_t r8, uintptr_t r9); #ifndef BUILD_LOADER_STAGE1 uint32_t msr; #endif + typedef void (*boot_entry)(uintptr_t r3, uintptr_t r4, uintptr_t r5, uintptr_t r6, + uintptr_t r7, uintptr_t r8, uintptr_t r9); boot_entry entry = (boot_entry)app_offset; #ifndef BUILD_LOADER_STAGE1 @@ -167,7 +167,11 @@ void do_boot(const uint32_t *app_offset) * https://elinux.org/images/c/cf/Power_ePAPR_APPROVED_v1.1.pdf */ entry( + #ifdef MMU (uintptr_t)dts_offset, /* r3 = dts address */ + #else + 0, + #endif 0, 0, EPAPR_MAGIC, /* r6 = ePAPR magic */ WOLFBOOT_PARTITION_SIZE, /* r7 = Size of Initial Mapped Area (IMA) */ diff --git a/src/boot_ppc_mp.S b/src/boot_ppc_mp.S index ffb05d97a..2eb099785 100644 --- a/src/boot_ppc_mp.S +++ b/src/boot_ppc_mp.S @@ -40,12 +40,12 @@ .align 12 _mp_page_start: /* Time base, MAS7 and machine check pin enable */ - lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h + lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h ori r0, r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@l mtspr SPRN_HID0, r0 /* enable branch prediction */ - lis r0, (BUCSR_ENABLE)@h + lis r0, (BUCSR_ENABLE)@h ori r0, r0, (BUCSR_ENABLE)@l mtspr SPRN_BUCSR, r0 @@ -55,7 +55,7 @@ _mp_page_start: mttbu r3 /* Enable/invalidate the I-Cache */ - lis r2, (L1CSR_CFI|L1CSR_CLFC)@h + lis r2, (L1CSR_CFI|L1CSR_CLFC)@h ori r2, r2, (L1CSR_CFI|L1CSR_CLFC)@l mtspr L1CSR1, r2 1: @@ -63,7 +63,7 @@ _mp_page_start: and. r1, r3, r2 bne 1b - lis r3, (L1CSR_CPE|L1CSR_CE)@h + lis r3, (L1CSR_CPE|L1CSR_CE)@h ori r3, r3, (L1CSR_CPE|L1CSR_CE)@l mtspr L1CSR1,r3 isync @@ -81,7 +81,7 @@ _mp_page_start: and. r1, r3, r2 bne 1b - lis r3, (L1CSR_CPE|L1CSR_CE)@h + lis r3, (L1CSR_CPE|L1CSR_CE)@h ori r3, r3, (L1CSR_CPE|L1CSR_CE)@l mtspr L1CSR0, r3 isync @@ -91,7 +91,7 @@ _mp_page_start: beq 2b /* Get our PIR to figure out our table entry */ - lis r3, TORESET(_spin_table)@h + lis r3, TORESET(_spin_table)@h ori r3, r3, TORESET(_spin_table)@l /* Determine base address for the core (use r10) */ diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index 560331a7f..5a1fb01e6 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -155,7 +155,7 @@ reset_exceptions: hardware_reg: /* Time base, MAS7 and machine check pin enable */ - lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h + lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h ori r0, r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@l mtspr SPRN_HID0, r0 @@ -174,7 +174,7 @@ hardware_reg: #ifndef BUILD_LOADER_STAGE1 branch_prediction: /* enable branch prediction */ - lis r0, (BUCSR_ENABLE)@h + lis r0, (BUCSR_ENABLE)@h ori r0, r0, (BUCSR_ENABLE)@l mtspr SPRN_BUCSR, r0 #endif @@ -306,9 +306,9 @@ setup_interrupts: #if CCSRBAR_DEF != CCSRBAR_PHYS /* Use R8 = new, R9 = old virtual */ - lis r8, CCSRBAR@h + lis r8, CCSRBAR@h ori r8, r8, CCSRBAR@l - lis r9, (CCSRBAR + 0x1000)@h + lis r9, (CCSRBAR + 0x1000)@h ori r9, r9, (CCSRBAR + 0x1000)@l create_temp_ccsr: @@ -342,13 +342,13 @@ infinite_debug_loop: ccsr_temp_law: /* CCSR - LAW0 (Temp CoreNet 4K) */ #define CCSR_TEMP_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_CORENET) | LAW_SIZE_4KB) - lis r0, CCSRBAR_PHYS_HIGH@h + lis r0, CCSRBAR_PHYS_HIGH@h ori r0, r0, CCSRBAR_PHYS_HIGH@l - lis r1, CCSRBAR_DEF@h + lis r1, CCSRBAR_DEF@h ori r1, r1, CCSRBAR_DEF@l - lis r2, CCSR_TEMP_LAW@h + lis r2, CCSR_TEMP_LAW@h ori r2, r2, CCSR_TEMP_LAW@l - stw r0, LAWBAR_BASE(0)(r9) /* LAWBARH */ + stw r0, LAWBAR_BASE(0)(r9) /* LAWBARH */ stw r1, LAWBAR_BASE(0)+4(r9) /* LAWBARL */ sync stw r2, LAWBAR_BASE(0)+8(r9) /* LAWAR */ @@ -361,12 +361,12 @@ read_old_ccsr: isync write_new_ccsrbar: - lis r0, CCSRBAR_PHYS_HIGH@h + lis r0, CCSRBAR_PHYS_HIGH@h ori r0, r0, CCSRBAR_PHYS_HIGH@l - lis r1, CCSRBAR@h + lis r1, CCSRBAR@h ori r1, r1, CCSRBAR@l #define CCSRAR_C 0x80000000 /* Commit */ - lis r2, CCSRAR_C@h + lis r2, CCSRAR_C@h ori r2, r2, CCSRAR_C@l stw r0, 0(r9) /* CCSRBARH */ sync @@ -383,7 +383,7 @@ write_new_ccsrbar: lwz r0, 0(r9) isync /* write new CCSBAR */ - lis r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@h + lis r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@h ori r0, r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@l stw r0, 0(r9) sync @@ -423,13 +423,13 @@ ccsr_tlb: ccsr_law: /* CCSR - LAW0 (CoreNet 16MB) */ #define CCSR_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_CORENET) | LAW_SIZE_16MB) - lis r9, CCSRBAR + LAWBAR_BASE(0)@h + lis r9, CCSRBAR + LAWBAR_BASE(0)@h ori r9, r9, CCSRBAR + LAWBAR_BASE(0)@l - lis r0, CCSRBAR_PHYS_HIGH@h + lis r0, CCSRBAR_PHYS_HIGH@h ori r0, r0, CCSRBAR_PHYS_HIGH@l - lis r1, CCSRBAR@h + lis r1, CCSRBAR@h ori r1, r1, CCSRBAR@l - lis r2, CCSR_LAW@h + lis r2, CCSR_LAW@h ori r2, r2, CCSR_LAW@l stw r0, 0(r9) /* LAWBARH */ stw r1, 4(r9) /* LAWBARL */ @@ -445,13 +445,13 @@ ccsr_law: flash_law: /* FLASH - LAW1 (IFC 64/128MB) */ #define FLASH_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_IFC) | FLASH_LAW_SIZE) - lis r9, CCSRBAR + LAWBAR_BASE(1)@h + lis r9, CCSRBAR + LAWBAR_BASE(1)@h ori r9, r9, CCSRBAR + LAWBAR_BASE(1)@l - lis r0, FLASH_BASE_PHYS_HIGH@h + lis r0, FLASH_BASE_PHYS_HIGH@h ori r0, r0, FLASH_BASE_PHYS_HIGH@l - lis r1, FLASH_BASE_ADDR@h + lis r1, FLASH_BASE_ADDR@h ori r1, r1, FLASH_BASE_ADDR@l - lis r2, FLASH_LAW@h + lis r2, FLASH_LAW@h ori r2, r2, FLASH_LAW@l stw r0, 0(r9) /* LAWBARH */ stw r1, 4(r9) /* LAWBARL */ @@ -499,18 +499,19 @@ flash_tlb: #endif /* CORE_E500 && ENABLE_DDR */ #ifdef ENABLE_L2_CACHE + #if defined(CORE_E5500) || defined(CORE_E6500) /* --- L2 E5500/E6500 --- */ #ifdef L2SRAM_ADDR l2_sram_law: /* L2 SRAM - LAW2 (DDR 256KB) */ #define L2SRAM_LAW \ (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_DDR_1) | LAW_SIZE_256KB) - lis r9, CCSRBAR + LAWBAR_BASE(2)@h + lis r9, CCSRBAR + LAWBAR_BASE(2)@h ori r9, r9, CCSRBAR + LAWBAR_BASE(2)@l li r0, 0 - lis r1, L2SRAM_ADDR@h + lis r1, L2SRAM_ADDR@h ori r1, r1, L2SRAM_ADDR@l - lis r2, L2SRAM_LAW@h + lis r2, L2SRAM_LAW@h ori r2, r2, L2SRAM_LAW@l stw r0, 0(r9) /* LAWBARH */ stw r1, 4(r9) /* LAWBARL */ @@ -530,7 +531,7 @@ l2_setup_sram: /* T2080RM: 8.4.2.2 or T1024RM 13.4.2.2 * Enabling the CPC after Power-On Reset */ /* R1 = CPC base */ - lis r1, CPC_BASE@h + lis r1, CPC_BASE@h ori r1, r1, CPC_BASE@l /* Set CPC SRAM control register */ @@ -538,7 +539,7 @@ l2_setup_sram: li r0, 0 stw r0, CPCSRCR1(r1) /* SRAM low address */ - lis r0, L2SRAM_ADDR@h + lis r0, L2SRAM_ADDR@h ori r0, r0, L2SRAM_ADDR@l /* Enable SRAM and set size (must match L2SRAM_SIZE) */ ori r0, r0, (CPCSRCR0_SRAMSZ_256 | CPCSRCR0_SRAMEN) @@ -556,7 +557,6 @@ l2_setup_sram: oris r0, r0, CPCHDBCR0_SPEC_DIS@h stw r0, CPCHDBCR0(r1) #endif /* L2SRAM_ADDR */ -#endif /* CORE_E5500 || CORE_E6500 */ #if defined(CORE_E6500) /* --- L2 E6500 --- */ l2_setup_cache: @@ -568,10 +568,10 @@ l2_setup_cache: /* E6500CORERM: 11.7 L2 cache state */ /* R5 = L2 cluster 1 base */ - lis r5, L2_CLUSTER_BASE(0)@h + lis r5, L2_CLUSTER_BASE(0)@h ori r5, r5, L2_CLUSTER_BASE(0)@l /* Invalidate and clear locks */ - lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h + lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h ori r1, r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@l sync stw r1, L2CSR0(r5) @@ -600,7 +600,7 @@ l2_setup_cache: #define L2_BASE (CCSRBAR + 0x20000) /* Invalidate and clear locks */ - lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h + lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h ori r1, r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@l sync isync @@ -627,19 +627,20 @@ l2_poll_invclear: isync mtspr L2CSR0, r4 isync +#endif +#endif /* CORE_E5500 || CORE_E6500 */ -#elif defined(CORE_E500) /* --- L2 E500 --- */ - +#if defined(CORE_E500) /* --- L2 E500 --- */ #ifdef L2SRAM_ADDR l2_sram_law: /* L2 SRAM - LAW2 (eLBC 256KB) */ #define L2SRAM_LAW \ (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_ELBC) | LAW_SIZE_256KB) - lis r9, CCSRBAR + LAWBAR_BASE(2)@h + lis r9, CCSRBAR + LAWBAR_BASE(2)@h ori r9, r9, CCSRBAR + LAWBAR_BASE(2)@l - lis r1, L2SRAM_ADDR@h + lis r1, L2SRAM_ADDR@h ori r1, r1, L2SRAM_ADDR@l - lis r2, L2SRAM_LAW@h + lis r2, L2SRAM_LAW@h ori r2, r2, L2SRAM_LAW@l stw r1, 0(r9) /* LAWBAR */ sync @@ -672,9 +673,9 @@ l2_setup_cache: #define L2CTL_VAL (L2CTL_EN | L2CTL_INV | L2CTL_SIZ(2)) #endif /* Configure the L2 Cache */ - lis r5, L2_BASE@h + lis r5, L2_BASE@h ori r5, r5, L2_BASE@l - lis r1, L2CTL_VAL@h + lis r1, L2CTL_VAL@h ori r1, r1, L2CTL_VAL@l msync isync @@ -688,13 +689,12 @@ l2_setup_sram: /* Set the L2SRAM base address */ mbar isync - lis r1, L2SRAM_ADDR@h + lis r1, L2SRAM_ADDR@h ori r1, r1, L2SRAM_ADDR@l stw r1, L2SRBAR0(r5) mbar #endif /* L2SRAM_ADDR */ - -#endif /* CORE_* */ +#endif /* CORE_E500 */ #endif /* ENABLE_L2_CACHE */ @@ -734,7 +734,7 @@ l1_tlb: #ifdef CACHE_SRAM_ADDR cache_sram_init: - lis r3, CACHE_SRAM_ADDR@h + lis r3, CACHE_SRAM_ADDR@h ori r3, r3, CACHE_SRAM_ADDR@l /* read the cache size */ mfspr r2, L1CFG0 @@ -770,13 +770,13 @@ setup_stack: stwu r0, -4(r1) stwu r0, -4(r1) /* Terminate Back chain */ stwu r1, -8(r1) /* Save back chain and move SP */ - lis r0, RESET_VECTOR@h /* Address of reset vector */ + lis r0, RESET_VECTOR@h /* Address of reset vector */ ori r0, r0, RESET_VECTOR@l stwu r1, -8(r1) /* Save back chain and move SP */ stw r0, +12(r1) /* Save return addr (underflow vect) */ /* switch back to AS/TS=0 */ - lis r3, (MSR_CE | MSR_ME | MSR_DE)@h + lis r3, (MSR_CE | MSR_ME | MSR_DE)@h ori r3, r3, (MSR_CE | MSR_ME | MSR_DE)@l mtmsr r3 isync @@ -788,7 +788,7 @@ setup_stack: #ifdef USE_LONG_JUMP /* load absolute address into "LR" and branch return to it */ /* Enables long jump in 32-bit */ - lis r3, boot_entry_C@h + lis r3, boot_entry_C@h ori r3, r3, boot_entry_C@l mtlr r3 blr