From c80937bdead1dfad20152af10b59e57888ff5354 Mon Sep 17 00:00:00 2001 From: Daniele Lacamera Date: Wed, 2 Oct 2024 10:25:36 +0200 Subject: [PATCH] Addressed reviewer's comments --- config/examples/sama5d3.config | 2 +- hal/sama5d3.c | 172 ++++++++++++++++----------------- hal/sama5d3.h | 56 +++++++++-- test-app/app_sama5d3.c | 20 +--- 4 files changed, 136 insertions(+), 114 deletions(-) diff --git a/config/examples/sama5d3.config b/config/examples/sama5d3.config index e42c3ae86..f52f84794 100644 --- a/config/examples/sama5d3.config +++ b/config/examples/sama5d3.config @@ -2,7 +2,7 @@ ARCH?=ARM TARGET?=sama5d3 SIGN?=ECC256 HASH?=SHA256 -DEBUG?=1 +DEBUG?=0 VTOR?=1 CORTEX_M0?=0 NO_ASM?=0 diff --git a/hal/sama5d3.c b/hal/sama5d3.c index 82fffaa7d..804dc3d5a 100644 --- a/hal/sama5d3.c +++ b/hal/sama5d3.c @@ -32,82 +32,82 @@ void sleep_us(uint32_t usec); /* Manual division operation */ static int division(uint32_t dividend, - uint32_t divisor, - uint32_t *quotient, - uint32_t *remainder) -{ - uint32_t shift; - uint32_t divisor_shift; - uint32_t factor = 0; - unsigned char end_flag = 0; - - if (!divisor) - return 0xffffffff; - - if (dividend < divisor) { - *quotient = 0; - *remainder = dividend; - return 0; - } + uint32_t divisor, + uint32_t *quotient, + uint32_t *remainder) +{ + uint32_t shift; + uint32_t divisor_shift; + uint32_t factor = 0; + unsigned char end_flag = 0; + + if (!divisor) + return 0xffffffff; + + if (dividend < divisor) { + *quotient = 0; + *remainder = dividend; + return 0; + } - while (dividend >= divisor) { - for (shift = 0, divisor_shift = divisor; - dividend >= divisor_shift; - divisor_shift <<= 1, shift++) { - if (dividend - divisor_shift < divisor_shift) { - factor += 1 << shift; - dividend -= divisor_shift; - end_flag = 1; - break; - } - } + while (dividend >= divisor) { + for (shift = 0, divisor_shift = divisor; + dividend >= divisor_shift; + divisor_shift <<= 1, shift++) { + if (dividend - divisor_shift < divisor_shift) { + factor += 1 << shift; + dividend -= divisor_shift; + end_flag = 1; + break; + } + } - if (end_flag) - continue; + if (end_flag) + continue; - factor += 1 << (shift - 1); - dividend -= divisor_shift >> 1; - } + factor += 1 << (shift - 1); + dividend -= divisor_shift >> 1; + } - if (quotient) - *quotient = factor; + if (quotient) + *quotient = factor; - if (remainder) - *remainder = dividend; + if (remainder) + *remainder = dividend; - return 0; + return 0; } static uint32_t div(uint32_t dividend, uint32_t divisor) { - uint32_t quotient = 0; - uint32_t remainder = 0; - int ret; + uint32_t quotient = 0; + uint32_t remainder = 0; + int ret; - ret = division(dividend, divisor, "ient, &remainder); - if (ret) - return 0xffffffff; + ret = division(dividend, divisor, "ient, &remainder); + if (ret) + return 0xffffffff; - return quotient; + return quotient; } static uint32_t mod(uint32_t dividend, uint32_t divisor) { - uint32_t quotient = 0; - uint32_t remainder = 0; - int ret; + uint32_t quotient = 0; + uint32_t remainder = 0; + int ret; - ret = division(dividend, divisor, "ient, &remainder); - if (ret) - return 0xffffffff; + ret = division(dividend, divisor, "ient, &remainder); + if (ret) + return 0xffffffff; - return remainder; + return remainder; } /* RAM configuration: 2 x MT47H64M16 on SAMA5D3-Xplained * 8 Mwords x 8 Banks x 16 bits x 2, total 2 Gbit */ -static struct dram ddram ={ +static const struct dram ddram ={ .timing = { /* Hardcoded for MT47H64M16, */ .tras = 6, .trcd = 2, @@ -132,7 +132,7 @@ static struct dram ddram ={ void master_clock_set(uint32_t prescaler) { - uint32_t mck = PMC_MCKR & (PMC_MDIV_MASK | PMC_CSS_MASK); + uint32_t mck = PMC_MCKR & (PMC_MDIV_MASK | PMC_CSS_MASK); uint32_t diff = mck ^ prescaler; if (diff & PMC_ALTPRES_MASK) { @@ -262,7 +262,6 @@ static void ddr_init(void) cal &= ~(MPDDRC_IOCALIBR_RDIV_MASK); cal |= MPDDRC_IOCALIBR_RDIV_DDR2_RZQ_50; /* 50 ohm */ cal &= ~(MPDDRC_IOCALIBR_TZQIO_MASK); - //cal |= (80 << MPDDRC_IOCALIBR_TZQIO_SHIFT); /* 100 cycles at 133MHz is 0.75 us, 100 cycles at 166MHz is 0.6 us */ cal |= (100 << MPDDRC_IOCALIBR_TZQIO_SHIFT); /* 100 cycles at 133MHz is 0.75 us, 100 cycles at 166MHz is 0.6 us */ MPDDRC_IO_CALIBR = cal; @@ -608,7 +607,7 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len) sz = remaining; do { - ret = nand_check_bad_block(block); + ret = nand_check_bad_block(block); if (ret < 0) { /* Block is bad, skip it */ block++; @@ -661,35 +660,39 @@ void pit_init(void) void sleep_us(uint32_t usec) { - uint32_t base = PIT_PIIR; - uint32_t delay; - uint32_t current; - - /* Since our division function which costs much run time - * causes the delay time error. - * So here using shifting to implement the division. - * to change "1000" to "1024", this cause some inaccuacy, - * but it is acceptable. - * ((MASTER_CLOCK / 1024) * usec) / (16 * 1024) - */ + uint32_t base = PIT_PIIR; + uint32_t delay; + uint32_t current; + + /* Since our division function which costs much run time + * causes the delay time error. + * So here using shifting to implement the division. + * to change "1000" to "1024", this cause some inaccuacy, + * but it is acceptable. + * ((MASTER_CLOCK / 1024) * usec) / (16 * 1024) + */ delay = ((MASTER_FREQ >> 10) * usec) >> 14; - do { - current = PIT_PIIR; - current -= base; - } while (current < delay); + do { + current = PIT_PIIR; + current -= base; + } while (current < delay); } - - - - int ext_flash_write(uintptr_t address, const uint8_t *data, int len) { + /* TODO */ + (void)address; + (void)data; + (void)len; + return 0; } int ext_flash_erase(uintptr_t address, int len) { + /* TODO */ + (void)address; + (void)len; return 0; } @@ -704,22 +707,12 @@ void ext_flash_lock(void) void* hal_get_dts_address(void) { - return (void*)&dts_addr; + return (void*)&dts_addr; } void* hal_get_dts_update_address(void) { - return NULL; /* Not yet supported */ -} - -/* QSPI functions */ -void qspi_init(uint32_t cpu_clock, uint32_t flash_freq) -{ -} - - -void zynq_init(uint32_t cpu_clock) -{ + return NULL; /* Not yet supported */ } @@ -740,6 +733,9 @@ void hal_prepare_boot(void) int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) { + (void)address; + (void)data; + (void)len; return 0; } @@ -754,6 +750,8 @@ void RAMFUNCTION hal_flash_lock(void) int RAMFUNCTION hal_flash_erase(uint32_t address, int len) { + (void)address; + (void)len; return 0; } diff --git a/hal/sama5d3.h b/hal/sama5d3.h index 15748adb5..40b99ab25 100644 --- a/hal/sama5d3.h +++ b/hal/sama5d3.h @@ -1,3 +1,25 @@ +/* sama5d3.h + * + * Header file for SAMA5D3 HAL + * + * Copyright (C) 2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ #ifndef SAMA5D3_HAL_H #define SAMA5D3_HAL_H @@ -5,9 +27,9 @@ #include /* CPU/Board clock settings */ -#define CPU_FREQ 264000000 -#define MASTER_FREQ 132000000 -#define CRYSTAL_FREQ 12000000 +#define CPU_FREQ 264000000UL +#define MASTER_FREQ 132000000UL +#define CRYSTAL_FREQ 12000000UL #define MULA 43 /* PLLA register @@ -309,11 +331,11 @@ extern void *kernel_addr, *update_addr, *dts_addr; #define NAND_FLASH_OOB_SIZE 0x40 /* 64B */ /* Address space mapping for atsama5d3 */ -#define DRAM_BASE 0x20000000 -#define CS1_BASE 0x40000000 -#define CS2_BASE 0x50000000 -#define CS3_BASE 0x60000000 -#define NFC_CMD_BASE 0x70000000 +#define DRAM_BASE 0x20000000UL +#define CS1_BASE 0x40000000UL +#define CS2_BASE 0x50000000UL +#define CS3_BASE 0x60000000UL +#define NFC_CMD_BASE 0x70000000UL /* NAND flash is mapped to CS3 */ #define NAND_BASE CS3_BASE @@ -405,4 +427,22 @@ extern void *kernel_addr, *update_addr, *dts_addr; #define MAX_ECC_BYTES 8 #endif +#define GPIOE_BASE 0xFFFFFA00 + +#define GPIOE_PER *(volatile uint32_t *)(GPIOE_BASE + 0x00) +#define GPIOE_PDR *(volatile uint32_t *)(GPIOE_BASE + 0x04) +#define GPIOE_PSR *(volatile uint32_t *)(GPIOE_BASE + 0x08) +#define GPIOE_OER *(volatile uint32_t *)(GPIOE_BASE + 0x10) +#define GPIOE_ODR *(volatile uint32_t *)(GPIOE_BASE + 0x14) +#define GPIOE_OSR *(volatile uint32_t *)(GPIOE_BASE + 0x18) +#define GPIOE_SODR *(volatile uint32_t *)(GPIOE_BASE + 0x30) +#define GPIOE_CODR *(volatile uint32_t *)(GPIOE_BASE + 0x34) +#define GPIOE_IER *(volatile uint32_t *)(GPIOE_BASE + 0x40) +#define GPIOE_IDR *(volatile uint32_t *)(GPIOE_BASE + 0x44) +#define GPIOE_MDER *(volatile uint32_t *)(GPIOE_BASE + 0x50) +#define GPIOE_MDDR *(volatile uint32_t *)(GPIOE_BASE + 0x54) +#define GPIOE_PPUDR *(volatile uint32_t *)(GPIOE_BASE + 0x60) +#define GPIOE_PPUER *(volatile uint32_t *)(GPIOE_BASE + 0x64) + + #endif diff --git a/test-app/app_sama5d3.c b/test-app/app_sama5d3.c index 2016a7dd6..45de4d452 100644 --- a/test-app/app_sama5d3.c +++ b/test-app/app_sama5d3.c @@ -2,7 +2,7 @@ * * Test bare-metal boot application * - * Copyright (C) 2021 wolfSSL Inc. + * Copyright (C) 2024 wolfSSL Inc. * * This file is part of wolfBoot. * @@ -24,29 +24,13 @@ #include #include #include +#include #include "wolfboot/wolfboot.h" #ifdef TARGET_sama5d3 /* Blue LED is PE23, Red LED is PE24 */ -#define GPIOE_BASE 0xFFFFFA00 - -#define GPIOE_PER *(volatile uint32_t *)(GPIOE_BASE + 0x00) -#define GPIOE_PDR *(volatile uint32_t *)(GPIOE_BASE + 0x04) -#define GPIOE_PSR *(volatile uint32_t *)(GPIOE_BASE + 0x08) -#define GPIOE_OER *(volatile uint32_t *)(GPIOE_BASE + 0x10) -#define GPIOE_ODR *(volatile uint32_t *)(GPIOE_BASE + 0x14) -#define GPIOE_OSR *(volatile uint32_t *)(GPIOE_BASE + 0x18) -#define GPIOE_SODR *(volatile uint32_t *)(GPIOE_BASE + 0x30) -#define GPIOE_CODR *(volatile uint32_t *)(GPIOE_BASE + 0x34) -#define GPIOE_IER *(volatile uint32_t *)(GPIOE_BASE + 0x40) -#define GPIOE_IDR *(volatile uint32_t *)(GPIOE_BASE + 0x44) -#define GPIOE_MDER *(volatile uint32_t *)(GPIOE_BASE + 0x50) -#define GPIOE_MDDR *(volatile uint32_t *)(GPIOE_BASE + 0x54) -#define GPIOE_PPUDR *(volatile uint32_t *)(GPIOE_BASE + 0x60) -#define GPIOE_PPUER *(volatile uint32_t *)(GPIOE_BASE + 0x64) - #define BLUE_LED_PIN 23 #define RED_LED_PIN 24