diff --git a/arch.mk b/arch.mk
index f374561c8..d03f8aeb6 100644
--- a/arch.mk
+++ b/arch.mk
@@ -282,19 +282,19 @@ ifeq ($(ARCH),RENESAS_RX)
   endif
 
   ifeq ($(TARGET),rx65n)
-    CFLAGS+=-misa=v2 -nofpu
+    #CFLAGS+=-misa=v2 -nofpu
   endif
   ifeq ($(TARGET),rx72n)
-    CFLAGS+=-misa=v3 -nofpu
+    #CFLAGS+=-misa=v3 -nofpu
   endif
 
   # RX parts support big or little endian data depending on MDE register
   ifeq ($(BIG_ENDIAN),1)
-    CFLAGS+=-mbig-endian-data
-    LDFLAGS+=-mbig-endian-data
+    CFLAGS+=-mbig-endian-data -fno-use-linker-plugin
+    LDFLAGS+=-mbig-endian-data -fno-use-linker-plugin -Wl,--oformat=elf32-rx-be
   else
-    CFLAGS+=-mlittle-endian-data
-    LDFLAGS+=-mlittle-endian-data
+    CFLAGS+=-mlittle-endian-data -fno-use-linker-plugin
+    LDFLAGS+=-mlittle-endian-data -fno-use-linker-plugin -Wl,--oformat=elf32-rx-le
   endif
 
   ifeq ($(TSIP),1)
diff --git a/config/examples/renesas-rx65n.config b/config/examples/renesas-rx65n.config
index acf7e76ca..40b9103ad 100644
--- a/config/examples/renesas-rx65n.config
+++ b/config/examples/renesas-rx65n.config
@@ -3,12 +3,12 @@ TARGET?=rx65n
 SIGN?=ECC256
 HASH?=SHA256
 DEBUG?=0
-DEBUG_UART?=1
+DEBUG_UART?=0
 VTOR?=1
 NO_ASM?=0
 NO_MPU=1
-EXT_FLASH?=0
-SPI_FLASH?=0
+EXT_FLASH?=1
+SPI_FLASH?=1
 QSPI_FLASH?=0
 ALLOW_DOWNGRADE?=0
 NVM_FLASH_WRITEONCE?=0
@@ -17,8 +17,11 @@ SPMATH?=1
 RAM_CODE?=0
 DUALBANK_SWAP?=0
 
+# reserve 1KB for wolfBoot header
+IMAGE_HEADER_SIZE=1024
+
 # Optionally switch to big endian data if MDE is set
-#BIG_ENDIAN=1
+BIG_ENDIAN=0
 
 # Flash is 2MB with 32KB sector size
 WOLFBOOT_SECTOR_SIZE?=0x8000
@@ -41,3 +44,5 @@ WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFE0000
 
 # TSIP
 PKA?=0
+
+#CFLAGS_EXTRA+=-DTEST_FLASH
diff --git a/hal/rx65n.c b/hal/rx65n.c
index 0e127c52f..78f4c4a25 100644
--- a/hal/rx65n.c
+++ b/hal/rx65n.c
@@ -268,8 +268,11 @@ void spi_init(int polarity, int phase)
     /* Configure P26-27 and P30-31 for alt mode */
     PORT_PMR(0x2) |= ((1 << 6) | (1 << 7));
     PORT_PMR(0x3) |= (1 << 0);
+    PORT_PDR(0x3) &= ~(1 << 0); /* input */
 #ifdef FLASH_SPI_USE_HW_CS
     PORT_PMR(0x3) |= (1 << 1);
+#else
+    PORT_PDR(0x3) |= (1 << 1); /* output */
 #endif
 
     /* Disable MPC Write Protect for PFS */
@@ -291,14 +294,14 @@ void spi_init(int polarity, int phase)
     /* Configure RSPI */
     RSPI_SPPCR(FLASH_RSPI_PORT) = (RSPI_SPPCR_MOIFV | RSPI_SPPCR_MOIDE); /* enable idle fixing */
     RSPI_SPSCR(FLASH_RSPI_PORT) = RSPI_SPSCR_SPSLN(0); /* seq len 1 */
-    RSPI_SPBR(FLASH_RSPI_PORT)  = 3; /* 15Mbps */
-    RSPI_SPDCR(FLASH_RSPI_PORT) = (RSPI_SPDCR_SPFC(0) | RSPI_SPDCR_SPLW); /* frames=1, SPDR=longwords */
+    RSPI_SPBR(FLASH_RSPI_PORT)  = 5; /* 5Mbps */
+    RSPI_SPDCR(FLASH_RSPI_PORT) = (RSPI_SPDCR_SPFC(0) | RSPI_SPDCR_SPBYT); /* frames=1, SPDR=byte */
     RSPI_SPCKD(FLASH_RSPI_PORT) = RSPI_SPCKD_SCKDL(0); /* 1 clock delay (SSL assert and first clock cycle) */
     RSPI_SSLND(FLASH_RSPI_PORT) = RSPI_SSLND_SLNDL(0); /* 1 clock delay (last clock cycle and SSL negation) */
     RSPI_SPND(FLASH_RSPI_PORT)  = RSPI_SPND_SPNDL(0); /* Next-Access Delay: 1RSPCK+2PCLK */
     RSPI_SPCR2(FLASH_RSPI_PORT) = 0; /* no parity */
     RSPI_SPCMD(FLASH_RSPI_PORT, 0) = (
-        RSPI_SPCMD_BRDV(0) | /* no div */
+        RSPI_SPCMD_BRDV(1) | /* div/1 */
         RSPI_SPCMD_SSLA(0) | /* slave select 0 */
         RSPI_SPCMD_SSLKP |   /* keep signal level between transfers */
         RSPI_SPCMD_SPB(7) |  /* 8-bit data */
@@ -310,8 +313,8 @@ void spi_init(int polarity, int phase)
     if (phase)
         RSPI_SPCMD(FLASH_RSPI_PORT, 0) |= RSPI_SPCMD_CPHA;
 
-    /* Enable Master SPI operation (4-wire method) */
-    RSPI_SPCR(FLASH_RSPI_PORT) = (RSPI_SPCR_MSTR | RSPI_SPCR_SPE);
+    /* Master SPI operation (4-wire method) */
+    RSPI_SPCR(FLASH_RSPI_PORT) = RSPI_SPCR_MSTR;
 }
 
 void spi_release(void)
@@ -325,6 +328,8 @@ void spi_cs_on(uint32_t base, int pin)
     (void)base;
     (void)pin;
 #ifdef FLASH_SPI_USE_HW_CS
+    /* Enable SPI Master */
+    RSPI_SPCR(FLASH_RSPI_PORT) |= RSPI_SPCR_SPE;
     RSPI_SPCMD(FLASH_RSPI_PORT, 0) |= RSPI_SPCMD_SSLKP;
 #else
     PORT_PODR(0x3) &= ~(1 << 1); /* drive low */
@@ -336,6 +341,7 @@ void spi_cs_off(uint32_t base, int pin)
     (void)pin;
 #ifdef FLASH_SPI_USE_HW_CS
     RSPI_SPCMD(FLASH_RSPI_PORT, 0) &= ~RSPI_SPCMD_SSLKP;
+    RSPI_SPCR(FLASH_RSPI_PORT) &= ~RSPI_SPCR_SPE;
 #else
     PORT_PODR(0x3) |= (1 << 1); /* drive high */
 #endif
diff --git a/src/spi_flash.c b/src/spi_flash.c
index 0a472a589..6c0ea9873 100644
--- a/src/spi_flash.c
+++ b/src/spi_flash.c
@@ -25,10 +25,11 @@
 
 #include "spi_drv.h"
 #include "spi_flash.h"
+#include "printf.h"
 
 #ifdef SPI_FLASH
 
-#define MDID            0x90
+#define MDID            0x9F
 #define RDSR            0x05
 #define WRSR            0x01
 #   define ST_BUSY (1 << 0)
@@ -197,6 +198,7 @@ uint16_t spi_flash_probe(void)
     spi_read();
     spi_cs_off(SPI_CS_PIO_BASE, SPI_CS_FLASH);
 #endif
+    wolfBoot_printf("SPI Probe: Manuf 0x%x, Product 0x%x\n", manuf, product);
     return (uint16_t)(manuf << 8 | product);
 }