From 5cc99505f592448ee4f93292d4e9e9c303103506 Mon Sep 17 00:00:00 2001 From: Brett Nicholas <7547222+bigbrett@users.noreply.github.com> Date: Mon, 12 Aug 2024 16:34:30 -0600 Subject: [PATCH] Initial wolfHSM support for simulator and AURIX TC3xx --- .github/workflows/test-configs.yml | 6 + .github/workflows/test-wolfhsm-simulator.yml | 66 + .gitignore | 2 + .gitmodules | 3 + IDE/AURIX/README.md | 138 +- .../test-app/.settings/language.settings.xml | 4 +- IDE/AURIX/test-app/Cpu0_Main.c | 2 +- IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl | 205 +- IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl | 918 -------- IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.cproject | 785 +++++++ IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.project | 99 + IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu0_Main.c | 47 + IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu1_Main.c | 42 + IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu2_Main.c | 42 + .../Lcf_Gnuc_Tricore_Tc.lsl | 1845 +++++++++++++++++ .../wolfBoot-tc3xx-wolfHSM/wolfhsm_cfg.h | 30 + IDE/AURIX/wolfBoot-tc3xx/.cproject | 43 +- .../.settings/language.settings.xml | 4 +- .../wolfBoot-tc3xx/Lcf_Gnuc_Tricore_Tc.lsl | 306 +-- .../wolfBoot-tc3xx/Lcf_Tasking_Tricore_Tc.lsl | 918 -------- .../wolfHSM-infineon-tc3xx/placeholder.txt | 1 + Makefile | 2 + arch.mk | 6 + config/examples/sim-wolfHSM.config | 30 + docs/Targets.md | 6 +- docs/keystore.md | 25 +- docs/wolfHSM.md | 145 ++ hal/aurix_tc3xx.c | 139 ++ hal/sim.c | 85 + include/hal.h | 25 + include/user_settings.h | 22 +- lib/wolfHSM | 1 + options.mk | 33 + src/image.c | 108 +- src/loader.c | 5 + src/update_disk.c | 3 + src/update_flash.c | 3 + src/update_flash_hwswap.c | 3 + src/update_ram.c | 5 + test-app/Makefile | 12 +- tools/config.mk | 7 +- tools/keytools/keygen.c | 157 +- tools/scripts/tc3xx/gen-tc3xx-keys.sh | 4 +- .../tc3xx/gen-tc3xx-signed-test-apps-debug.sh | 4 +- .../gen-tc3xx-signed-test-apps-release.sh | 4 +- tools/scripts/tc3xx/gen-tc3xx-target.sh | 10 +- .../scripts/tc3xx/wolfBoot-loadAll-debug.cmm | 2 +- .../tc3xx/wolfBoot-loadAll-release.cmm | 2 +- .../tc3xx/wolfBoot-wolfHSM-keys.nvminit | 5 + .../tc3xx/wolfBoot-wolfHSM-loadAll-debug.cmm | 34 + .../wolfBoot-wolfHSM-loadAll-release.cmm | 34 + 51 files changed, 4272 insertions(+), 2155 deletions(-) create mode 100644 .github/workflows/test-wolfhsm-simulator.yml delete mode 100644 IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl create mode 100644 IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.cproject create mode 100644 IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.project create mode 100644 IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu0_Main.c create mode 100644 IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu1_Main.c create mode 100644 IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu2_Main.c create mode 100644 IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Lcf_Gnuc_Tricore_Tc.lsl create mode 100644 IDE/AURIX/wolfBoot-tc3xx-wolfHSM/wolfhsm_cfg.h delete mode 100644 IDE/AURIX/wolfBoot-tc3xx/Lcf_Tasking_Tricore_Tc.lsl create mode 100644 IDE/AURIX/wolfHSM-infineon-tc3xx/placeholder.txt create mode 100644 config/examples/sim-wolfHSM.config create mode 100644 docs/wolfHSM.md create mode 160000 lib/wolfHSM create mode 100644 tools/scripts/tc3xx/wolfBoot-wolfHSM-keys.nvminit create mode 100644 tools/scripts/tc3xx/wolfBoot-wolfHSM-loadAll-debug.cmm create mode 100644 tools/scripts/tc3xx/wolfBoot-wolfHSM-loadAll-release.cmm diff --git a/.github/workflows/test-configs.yml b/.github/workflows/test-configs.yml index 4bd44470b..69209c457 100644 --- a/.github/workflows/test-configs.yml +++ b/.github/workflows/test-configs.yml @@ -433,3 +433,9 @@ jobs: arch: aarch64 config-file: ./config/examples/zynqmp.config make-args: CROSS_COMPILE=aarch64-linux-gnu- + + sim_wolfhsm_test: + uses: ./.github/workflows/test-build.yml + with: + arch: host + config-file: ./config/examples/sim-wolfHSM.config diff --git a/.github/workflows/test-wolfhsm-simulator.yml b/.github/workflows/test-wolfhsm-simulator.yml new file mode 100644 index 000000000..ac4349bb7 --- /dev/null +++ b/.github/workflows/test-wolfhsm-simulator.yml @@ -0,0 +1,66 @@ +name: wolfHSM simulator test + +on: + push: + branches: [ 'master', 'main', 'release/**' ] + pull_request: + branches: [ '*' ] + workflow_dispatch: + +jobs: + wolfhsm_simulator_test: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + with: + submodules: true + + - name: Workaround for sources.list + run: sudo sed -i 's|http://azure.archive.ubuntu.com/ubuntu/|http://mirror.arizona.edu/ubuntu/|g' /etc/apt/sources.list + + - name: Update repository + run: sudo apt-get update + + - name: make clean + run: | + make distclean + + - name: Select config (wolfHSM simulator) + run: | + cp config/examples/sim-wolfHSM.config .config + + - name: Build tools + run: | + make -C tools/keytools && make -C tools/bin-assemble + + - name: Build wolfboot.elf + run: | + make clean && make test-sim-internal-flash-with-update + + # checkout and build wolfHSM examples repo + - name: Checkout wolfHSM-examples + uses: actions/checkout@v3 + with: + repository: wolfssl/wolfHSM-examples + path: wolfHSM-examples + + - name: Build example POSIX TCP server + run: cd wolfHSM-examples/posix/tcp/wh_server_tcp && make WOLFSSL_DIR=../../../../lib/wolfssl WOLFHSM_DIR=../../../../lib/wolfHSM + + # Start the server in the background + - name: Run POSIX TCP server + run: | + cd wolfHSM-examples/posix/tcp/wh_server_tcp + ./Build/wh_server_tcp.elf --client 12 --id 255 --key ../../../../wolfboot_signing_private_key_pub.der & + TCP_SERVER_PID=$! + echo "TCP_SERVER_PID=$TCP_SERVER_PID" >> $GITHUB_ENV + + # Run the sunny day update test against the server + - name: Run sunny day update test + run: | + tools/scripts/sim-sunnyday-update.sh + + # Kill the server if it is still running + - name: Kill POSIX TCP server + run: | + kill $TCP_SERVER_PID diff --git a/.gitignore b/.gitignore index ab287f854..598c26416 100644 --- a/.gitignore +++ b/.gitignore @@ -209,6 +209,8 @@ IDE/AURIX/SDK/* !IDE/AURIX/SDK/placeholder.txt IDE/AURIX/Configurations/* !IDE/AURIX/Configurations/placeholder.txt +IDE/AURIX/wolfHSM-infineon-tc3xx/* +!IDE/AURIX/wolfHSM-infineon-tc3xx/placeholder.txt tpm_seal_key.key diff --git a/.gitmodules b/.gitmodules index a6476b5f7..29bca89a6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,3 +7,6 @@ [submodule "lib/wolfPKCS11"] path = lib/wolfPKCS11 url = https://github.com/wolfSSL/wolfPKCS11.git +[submodule "lib/wolfHSM"] + path = lib/wolfHSM + url = https://github.com/wolfssl/wolfhsm.git diff --git a/IDE/AURIX/README.md b/IDE/AURIX/README.md index 881c62df5..907a38c25 100644 --- a/IDE/AURIX/README.md +++ b/IDE/AURIX/README.md @@ -1,12 +1,32 @@ -# Overview +# WolfBoot on Infineon AURIX TC3xx This example demonstrates using wolfBoot on the Infineon AURIX TC3xx family of microcontrollers. The example is based on the TC375 Lite-Kit V2, but should be easily adaptable to other TC3xx devices. This README assumes basic familiarity with the TC375 SoC, the AURIX IDE, and Lauterbach Trace32 debugger. +## Overview + +- [WolfBoot on Infineon AURIX TC3xx](#wolfboot-on-infineon-aurix-tc3xx) + - [Overview](#overview) + - [Important notes](#important-notes) + - [Flash Partitioning](#flash-partitioning) + - [Building and running the wolfBoot demo](#building-and-running-the-wolfboot-demo) + - [Prerequisites](#prerequisites) + - [Clone wolfBoot](#clone-wolfboot) + - [Build wolfBoot keytools and generate keys](#build-wolfboot-keytools-and-generate-keys) + - [Install the Infineon TC3xx SDK into the wolfBoot project](#install-the-infineon-tc3xx-sdk-into-the-wolfboot-project) + - [Build wolfBoot](#build-wolfboot) + - [Connect the Lauterbach to the TC375 Device in TRACE32](#connect-the-lauterbach-to-the-tc375-device-in-trace32) + - [Update the start address in UCBs using TRACE32](#update-the-start-address-in-ucbs-using-trace32) + - [Load and run the wolfBoot demo in TRACE32](#load-and-run-the-wolfboot-demo-in-trace32) + - [wolfHSM Compatibility](#wolfhsm-compatibility) + - [Building wolfBoot with wolfHSM](#building-wolfboot-with-wolfhsm) + - [Troubleshooting](#troubleshooting) + - [WSL "bad interpreter" error](#wsl-bad-interpreter-error) + The example contains two projects: `wolfBoot-tc3xx` and `test-app`. The `wolfBoot-tc3xx` project contains the wolfBoot bootloader, and the `test-app` project contains a simple firmware application that will be loaded and executed by wolfBoot. The `test-app` project is a simple blinky application that blinks LED2 on the TC375 Lite-Kit V2 once per second when running the base image, and rapidly (~3x/sec) when running the update image. The test app determines if it is a base or update image by inspecting the firmware version (obtained through the wolfBoot API). The firmware version is set in the image header by the wolfBoot keytools when signing the test app binaries. The same test app binary is used for both the base and update images, with the only difference being the firmware version set by the keytools. ## Important notes -- In the TC375 UCBs, BMDHx.STAD must point to the wolfBoot entrypoint `0xA000_0000`. This is the default value of the TC375 and so need not be changed unless it has already been modified or you wish to rearrange the memory map. +- In the TC375 UCBs, BMDHx.STAD must point to the wolfBoot entrypoint `0xA00A_0000`. You can modify this in the `UCB` section of the TRACE32 IDE as described in the steps later in this document. Please refer to the TRACE32 manual and the TC37xx user manual for more information on the UCBs. - Because TC3xx PFLASH ECC prevents reading from erased flash, the `EXT_FLASH` option is used to redirect flash reads to the `ext_flash_read()` HAL API, where the flash pages requested to be read can be blank-checked by hardware before reading. - TC3xx PFLASH is write-once (`NVM_FLASH_WRITEONCE`), however wolfBoot `NVM_FLASH_WRITEONCE` does not support `EXT_FLASH`. Therefore the write-once functionality is re-implemented in the `HAL` layer. - This demo app is only compatible with the GCC toolchain build configurations shipped with the AURIX IDE. The TASKING compiler build configurations are not yet supported. @@ -18,20 +38,22 @@ The TC3xx AURIX port of wolfBoot places all images in PFLASH, and uses both PFLA ``` +==========+ | PFLASH0 | -+==========+ <-- 0x8000_0000 -| wolfBoot | 128K -+----------+ <-- 0x8002_0000 -| SWAP | 16K -+----------+ <-- 0x8002_4000 -| Unused | ~2.86M ++----------+ <-- 0x8000_0000 +| Unused | 640K ++==========+ <-- 0x800A_0000 +| wolfBoot | 172K ++----------+ <-- 0x8002_B000 +| Unused | ~2.8M +----------+ <-- 0x8030_0000 +==========+ | PFLASH1 | +==========+ <-- 0x8030_0000 -| BOOT | 1.5M -+----------+ <-- 0x8048_0000 -| UPDATE | 1.5M +| BOOT | 1.5M (0x17E000) ++----------+ <-- 0x8047_E000 +| UPDATE | 1.5M (0x17E000) ++----------+ <-- 0x805F_C000 +| SWAP | 16K (0x4000) +----------+ <-- 0x8060_0000 ``` @@ -54,20 +76,19 @@ Please refer to the [wolfBoot](wolfBoot-tc3xx/Lcf_Gnu_Tricore_Tc.lsl) and [test- 1. Open a WSL2 terminal and navigate to the top level `wolfBoot` directory 2. Compile the keytools by running `make keytools` -3. Use the helper script to generate a new signing key pair using RSA 4096 +3. Use the helper script to generate a new signing key pair using ECC 256 1. Navigate to `wolfBoot/tools/scripts/tc3xx` 2. Run `./gen-tc3xx-keys.sh`. This generates the signing private key `wolfBoot/priv.der` and adds the public key to the wolfBoot keystore (see [keygen](https://github.com/wolfSSL/wolfBoot/blob/aurix-tc3xx-support/docs/Signing.md) for more information). If you already have generated a key, you will be prompted to overwrite it. ``` $ ./gen-tc3xx-keys.sh + cd ../../../ -+ ./tools/keytools/keygen -g priv.der --rsa4096 -Keytype: RSA4096 -Generating key (type: RSA4096) -RSA public key len: 550 bytes ++ tools/keytools/keygen --ecc256 -g priv.der +Keytype: ECC256 +Generating key (type: ECC256) Associated key file: priv.der Partition ids mask: ffffffff -Key type : RSA4096 +Key type : ECC256 Public key slot: 0 Done. ``` @@ -125,45 +146,62 @@ wolfBoot/IDE/AURIX/Configurations/ ``` $ ./gen-tc3xx-signed-test-apps-release.sh -+ ../../keytools/sign --rsa4096 --sha256 '../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin' ../../../priv.der 1 ++ ../../keytools/sign --ecc256 --sha256 '../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin' ../../../priv.der 1 wolfBoot KeyTools (Compiled C version) -wolfBoot version 2010000 +wolfBoot version 2020000 Update type: Firmware Input image: ../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin -Selected cipher: RSA4096 +Selected cipher: ECC256 Selected hash : SHA256 Public key: ../../../priv.der Output image: ../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app_v1_signed.bin Target partition id : 1 -Found RSA512 key -image header size calculated at runtime (1024 bytes) +image header size calculated at runtime (256 bytes) Calculating SHA256 digest... Signing the digest... Output image(s) successfully created. -+ ../../keytools/sign --rsa4096 --sha256 '../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin' ../../../priv.der 2 ++ ../../keytools/sign --ecc256 --sha256 '../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin' ../../../priv.der 2 wolfBoot KeyTools (Compiled C version) -wolfBoot version 2010000 +wolfBoot version 2020000 Update type: Firmware Input image: ../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app.bin -Selected cipher: RSA4096 +Selected cipher: ECC256 Selected hash : SHA256 Public key: ../../../priv.der Output image: ../../../IDE/AURIX/test-app/TriCore Release (GCC)/test-app_v2_signed.bin Target partition id : 1 -Found RSA512 key -image header size calculated at runtime (1024 bytes) +image header size calculated at runtime (256 bytes) Calculating SHA256 digest... Signing the digest... Output image(s) successfully created. ``` -### Load and run the wolfBoot demo +### Connect the Lauterbach to the TC375 Device in TRACE32 + +1. Ensure the Lauterbach probe is connected to the debug port of the tc375 LiteKit +2. Open Trace32 Power View for Tricore +3. Open the SYStem menu and click "DETECT" to detect the tc375 device. Click "CONTINUE" in the pop-up window, and then choose "Set TC375xx" when the device is detected + +### Update the start address in UCBs using TRACE32 + +The default Boot Mode Header (BMHD) start address on a new TC375 `0xA0000000` but the wolfBoot application has a start address of `0xA00A0000`. We must therefore update the BMHD UCBs with the correct entry point such that it can boot wolfBoot out of reset. + +1. Select the TC37x dropdown menu and click UCBs +2. Expand `BMHD0_COPY` +3. Click "Edit" +4. Set the `STAD` to `0xA00A0000` +5. Click "Update" to recompute the CRC +6. Click "Check" to verify the new CRC +7. Click "Write" to update the UCB in flash +8. Perform the same operations (2-7) on the `BMHD0_ORIG` UCB -1. Load wolfBoot and the firmware application images to the tc3xx device using Trace32 and a Lauterbach probe - 1. Ensure the Lauterbach probe is connected to the debug port of the tc375 LiteKit - 2. Open Trace32 Power View for Tricore - 3. Open the SYStem menu and click "DETECT" to detect the tc375 device. Click "CONTINUE" in the pop-up window, and then choose "Set TC375xx" when the device is detected - 4. Click "File" -> "ChangeDir and Run Script" and choose the `wolfBoot/tools/scripts/tc3xx/wolfBoot-loadAll-$BUILD.cmm` script, where $BUILD should be either "debug" or "release" depending on your build type in (4) and (6). +The device is now configured to boot from `0xA00A0000` out of reset. + +### Load and run the wolfBoot demo in TRACE32 + +We can now load wolfBoot and the firmware application images to the tc3xx device using Trace32 and a Lauterbach probe + +1. Click "File" -> "ChangeDir and Run Script" and choose the `wolfBoot/tools/scripts/tc3xx/wolfBoot-loadAll-$BUILD.cmm` script, where $BUILD should be either "debug" or "release" depending on your build type in (4) and (6). wolfBoot and the demo applications are now loaded into flash, and core0 will be halted at the wolfBoot entry point (`core0_main()`). @@ -173,15 +211,45 @@ wolfBoot and the demo applications are now loaded into flash, and core0 will be To rerun the demo, simply rerun the loader script in Trace32 and repeat the above steps +## wolfHSM Compatibility + +wolfBoot has full support for wolfHSM on the AURIX TC3xx platform. The wolfBoot application functions as the HSM client, and all cryptographic operations required to verify application images are offloaded to the HSM. When used in tandem with wolfHSM, wolfBoot can be configured to use keys stored on the HSM for cryptographic operations, or to store keys in the default keystore and send them on-demand to the HSM for usage. The former option is the default configuration, and is recommended for most use cases, as key material will never leave the secure boundary of the HSM. The latter option is useful for development and testing, before keys have been preloaded onto the HSM. + +Note that information regarding the AURIX TC3xx HSM core is restricted by NDA with Infineon. Source code for the wolfHSM TC3xx platform port is therefore not publicly available and cannot be included for distribution in wolfBoot. Instructions to build wolfBoot with wolfHSM compatibility are provided here, but the wolfHSM TC3xx port must be obtained separately from wolfSSL. To obtain the wolfHSM TC3xx port, please contact wolfSSL at [facts@wolfssl.com](mailto:facts@wolfssl.com). + +### Building wolfBoot with wolfHSM + +Steps to build wolfBoot on TC3xx with wolfHSM are largely similar to the non-HSM case, with a few key differences. + +1. Obtain the wolfHSM release for the AURIX TC3xx from wolfSSL +2. Extract the contents of the `infineon/tc3xx` directory from the wolfHSM TC3xx release you obtained from wolfSSL into the [wolfBoot/IDE/AURIX/wolfHSM-infineon-tc3xx](./wolfHSM-infineon-tc3xx/) directory. The contents of this directory should now be: + +``` +IDE/AURIX/wolfHSM-infineon-tc3xx/ +├── README.md +├── T32 +├── placeholder.txt +├── port +├── tchsm-client +├── tchsm-server +├── wolfHSM +└── wolfssl +``` + +3. Build the wolfHSM server application and load it onto the HSM core, following the instructions provided in the release you obtained from wolfSSL. You do not need to build or load the demo client application, as wolfBoot will act as the client. +4. Follow all of the steps in [Building and Running the wolfBoot Demo](#building-and-running-the-wolfboot-demo) for the non-HSM enabled case, but with the following key differences: + 1. The [wolfBoot-tc3xx-wolfHSM](./wolfBoot-tc3xx-wolfHSM/) AURIX Studio project should be used instead of `wolfBoot-tc3xx` + 2. Use the `wolfBoot-wolfHSM-loadAll-XXX.cmm` lauterbach scripts instead of `wolfBoot-loadAll-XXX.cmm` to load the wolfBoot and test-app images in the TRACE32 GUI +5. If using the default build options in [wolfBoot-tc3xx-wolfHSM](./wolfBoot-tc3xx-wolfHSM/), wolfBoot will expect the public key for image verification to be stored at a specific keyId for the wolfBoot client ID. You can use [whnvmtool](https://github.com/wolfSSL/wolfHSM/tree/main/tools/whnvmtool) to generate a loadable NVM image that contains the required keys. [wolfBoot-wolfHSM-keys.nvminit](../../tools/scripts/tc3xx/wolfBoot-wolfHSM-keys.nvminit) provides an example `whnvmtool` config file that will include the generated key in the NVM image, which can then be loaded to the device via a flash programming tool. See the `whnvmtool` documentation and the documentation included in your wolfHSM AURIX release for more details. Note: if you want to use the standard wolfBoot keystore functionality in conjunction with wolfHSM for testing purposes (doesn't require pre-loading keys on the HSM) you can configure wolfBoot to send the keys to the HSM on-the-fly as ephemeral keys. To do this, ensure `WOLFBOOT_USE_WOLFHSM_PUBKEY_ID` is **NOT** defined, and remove the `--nolocalkeys` argument when invoking `keygen` in the `./gen-tc3xx-keys.sh` script. ## Troubleshooting -### WSL "bad interpreter" error +### WSL "bad interpreter" error When running a shell script in WSL, you may see the following error: ``` -$ ./gen-tc3xx-target.sh: +$ ./gen-tc3xx-target.sh: /bin/bash^M: bad interpreter: No such file or directory ``` diff --git a/IDE/AURIX/test-app/.settings/language.settings.xml b/IDE/AURIX/test-app/.settings/language.settings.xml index 8a8ec65a1..dbcffdbd8 100644 --- a/IDE/AURIX/test-app/.settings/language.settings.xml +++ b/IDE/AURIX/test-app/.settings/language.settings.xml @@ -21,7 +21,7 @@ - + @@ -32,7 +32,7 @@ - + diff --git a/IDE/AURIX/test-app/Cpu0_Main.c b/IDE/AURIX/test-app/Cpu0_Main.c index c96c0bc3f..9ea976bb0 100644 --- a/IDE/AURIX/test-app/Cpu0_Main.c +++ b/IDE/AURIX/test-app/Cpu0_Main.c @@ -27,7 +27,7 @@ IFX_ALIGN(4) IfxCpu_syncEvent g_cpuSyncEvent = 0; -#define LED &MODULE_P00, 6 /* LED: Port, Pin definition */ +#define LED &MODULE_P00, 5 /* LED: Port, Pin definition */ #define BLINK_TIME_BASE 500 /* Wait time constant in milliseconds */ #define BLINK_TIME_UPDATE 100 /* Wait time constant in milliseconds */ diff --git a/IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl b/IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl index 4f4691821..3c0c8b391 100644 --- a/IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl +++ b/IDE/AURIX/test-app/Lcf_Gnuc_Tricore_Tc.lsl @@ -63,28 +63,36 @@ LCF_HEAP1_OFFSET = (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE); LCF_HEAP2_OFFSET = (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE); -LCF_STARTPTR_CPU0 = 0x80300400; -LCF_STARTPTR_CPU1 = 0x80300420; -LCF_STARTPTR_CPU2 = 0x80300440; +LCF_WOLFBOOT_BOOT_PART_BASEADDR = 0xA0300000; +LCF_WOLFBOOT_HEADER_OFFSET = 0x100; -LCF_STARTPTR_NC_CPU0 = 0xA0300400; -LCF_STARTPTR_NC_CPU1 = 0xA0300420; -LCF_STARTPTR_NC_CPU2 = 0xA0300440; +LCF_CODE_BASE_ADDR = LCF_WOLFBOOT_BOOT_PART_BASEADDR + LCF_WOLFBOOT_HEADER_OFFSET; -/* TODO LCF_TRAPVEC_SIZE */ -LCF_TRAPVEC0_START = 0x80300500; -LCF_TRAPVEC1_START = 0x80300600; -LCF_TRAPVEC2_START = 0x80300700; +LCF_START_CODE_SIZE = 0x20; /* space reserved for .start sections (per-cpu) */ +LCF_TRAPVEC_OFFSET = 0x100; /* size/alignment of trap table (also offset from base to first trap table) */ -LCF_INTVEC0_START = 0x80300800; -LCF_INTVEC1_START = 0x80302800; -LCF_INTVEC2_START = 0x80304800; +LCF_STARTPTR_NC_CPU0 = LCF_CODE_BASE_ADDR; +LCF_STARTPTR_NC_CPU1 = LCF_STARTPTR_NC_CPU0 + LCF_START_CODE_SIZE; +LCF_STARTPTR_NC_CPU2 = LCF_STARTPTR_NC_CPU1 + LCF_START_CODE_SIZE; + +/* Offset of the trap table from start address (accounts for size of .start section) */ +LCF_TRAPVEC0_START = (LCF_STARTPTR_NC_CPU0 + LCF_TRAPVEC_OFFSET); /* 0x80000100 */ +LCF_TRAPVEC1_START = (LCF_TRAPVEC0_START + LCF_TRAPVEC_OFFSET); /* 0x80000200 */ +LCF_TRAPVEC2_START = (LCF_TRAPVEC1_START + LCF_TRAPVEC_OFFSET); /* 0x80000300 */ + +LCF_INTVEC_SIZE = 0x2000; /* 8k */ +LCF_INTVEC0_START = (LCF_TRAPVEC2_START + LCF_TRAPVEC_OFFSET); /* 0x80000400; */ +LCF_INTVEC1_START = (LCF_INTVEC0_START + LCF_INTVEC_SIZE); /* 0x80002400; */ +LCF_INTVEC2_START = (LCF_INTVEC1_START + LCF_INTVEC_SIZE); /* 0x80004400; */ __INTTAB_CPU0 = LCF_INTVEC0_START; __INTTAB_CPU1 = LCF_INTVEC1_START; __INTTAB_CPU2 = LCF_INTVEC2_START; - +/* Alias non-cached to cached sections for now */ +LCF_STARTPTR_CPU0 = LCF_STARTPTR_NC_CPU0; +LCF_STARTPTR_CPU1 = LCF_STARTPTR_NC_CPU1; +LCF_STARTPTR_CPU2 = LCF_STARTPTR_NC_CPU2; RESET = LCF_STARTPTR_NC_CPU0; @@ -93,37 +101,40 @@ MEMORY dsram2_local (w!xp): org = 0xd0000000, len = 96K dsram2 (w!xp): org = 0x50000000, len = 96K psram2 (w!xp): org = 0x50100000, len = 64K - + dsram1_local (w!xp): org = 0xd0000000, len = 240K dsram1 (w!xp): org = 0x60000000, len = 240K psram1 (w!xp): org = 0x60100000, len = 64K - + dsram0_local (w!xp): org = 0xd0000000, len = 240K dsram0 (w!xp): org = 0x70000000, len = 240K psram0 (w!xp): org = 0x70100000, len = 64K - + psram_local (w!xp): org = 0xc0000000, len = 64K - + /* Majority of pfls0 is reserved for wolfBoot, swap and HSM */ - pfls0 (rx!p): org = 0x80000000, len = 3M - + pfls0 (rx!p): org = 0xA0000000, len = 3M + /* placeholder for wolfBoot image header */ - pfls1_hdr (rx!p): org = 0x80300000, len = 1024 - + pfls1_hdr (rx!p): org = 0xA0300000, len = 256 + /* pfls1 is the remainder of the wolfBoot BOOT partition. Everything goes here */ - pfls1 (rx!p): org = 0x80300400, len = 0x17FC00 /* 1.5MiB - 1024B*/ - + pfls1 (rx!p): org = 0xA0300100, len = 0x17DF00 /* 0x17E000 - 256B */ + /* reserved for wolfBoot UPDATE partition */ - pfls1_update (rx!p): org = 0x80480000, len = 0x180000 /* 1.5MiB */ - + pfls1_update (rwx!p): org = 0xA047E000, len = 0x17E000 /* ~1.5MiB */ + + /* SWAP sector for wolfBoot image update */ + pfls1_swap (rwx!p): org = 0xA05FC000, len = 16K /* last sector of PFLASH1 */ + dfls0 (rx!p): org = 0xaf000000, len = 256K - + ucb (rx!p): org = 0xaf400000, len = 24K - + cpu0_dlmu (w!xp): org = 0x90000000, len = 64K - + cpu1_dlmu (w!xp): org = 0x90010000, len = 64K - + cpu2_dlmu (w!xp): org = 0x90020000, len = 64K } @@ -134,7 +145,7 @@ REGION_MAP( CPU2 , ORIGIN(dsram2_local), LENGTH(dsram2_local), ORIGIN(dsram2)) /*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ -/* +/* REGION_ALIAS( default_ram , dsram0) REGION_ALIAS( default_rom , pfls1) */ @@ -157,40 +168,40 @@ REGION_ALIAS( default_rom , pfls1) { CORE_SEC(.ustack) (LCF_DSPR2_START + LCF_USTACK2_OFFSET): { PROVIDE(__USTACK2_END = .); . = . + LCF_USTACK2_SIZE; PROVIDE(__USTACK2 = .); } - + CORE_SEC(.istack) (LCF_DSPR2_START + LCF_ISTACK2_OFFSET): { PROVIDE(__ISTACK2_END = .); . = . + LCF_ISTACK2_SIZE; PROVIDE(__ISTACK2 = .); } - + CORE_SEC(.csa) (LCF_DSPR2_START + LCF_CSA2_OFFSET): { PROVIDE(__CSA2 = .); . = . + LCF_CSA2_SIZE; PROVIDE(__CSA2_END = .); } } - + CORE_ID = CPU1; SECTIONS { CORE_SEC(.ustack) (LCF_DSPR1_START + LCF_USTACK1_OFFSET): { PROVIDE(__USTACK1_END = .); . = . + LCF_USTACK1_SIZE; PROVIDE(__USTACK1 = .); } - + CORE_SEC(.istack) (LCF_DSPR1_START + LCF_ISTACK1_OFFSET): { PROVIDE(__ISTACK1_END = .); . = . + LCF_ISTACK1_SIZE; PROVIDE(__ISTACK1 = .); } - + CORE_SEC(.csa) (LCF_DSPR1_START + LCF_CSA1_OFFSET): { PROVIDE(__CSA1 = .); . = . + LCF_CSA1_SIZE; PROVIDE(__CSA1_END = .); } } - + CORE_ID = CPU0; SECTIONS { CORE_SEC(.ustack) (LCF_DSPR0_START + LCF_USTACK0_OFFSET): { PROVIDE(__USTACK0_END = .); . = . + LCF_USTACK0_SIZE; PROVIDE(__USTACK0 = .); } - + CORE_SEC(.istack) (LCF_DSPR0_START + LCF_ISTACK0_OFFSET): { PROVIDE(__ISTACK0_END = .); . = . + LCF_ISTACK0_SIZE; PROVIDE(__ISTACK0 = .); } - + CORE_SEC(.csa) (LCF_DSPR0_START + LCF_CSA0_OFFSET): { PROVIDE(__CSA0 = .); . = . + LCF_CSA0_SIZE; PROVIDE(__CSA0_END = .); } } - + /*Fixed memory Allocations for _START*/ CORE_ID = GLOBAL ; SECTIONS @@ -201,12 +212,12 @@ REGION_ALIAS( default_rom , pfls1) PROVIDE(__START1 = LCF_STARTPTR_NC_CPU1); .start_tc2 (LCF_STARTPTR_CPU2) : FLAGS(rxl) { KEEP (*(.start_cpu2)); } > pfls1 PROVIDE(__START2 = LCF_STARTPTR_NC_CPU2); - + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); /* Not used */ PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 0); PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 0); } - + /*Fixed memory Allocations for Trap Vector Table*/ CORE_ID = GLOBAL; SECTIONS @@ -214,28 +225,28 @@ REGION_ALIAS( default_rom , pfls1) .traptab_tc0 (LCF_TRAPVEC0_START) : { . = ALIGN(8); - PROVIDE(__TRAPTAB_CPU0 = .); + PROVIDE(__TRAPTAB_CPU0 = .); KEEP (*(.traptab_cpu0)); PROVIDE(__TRAPTAB_CPU0_END = .); } > pfls1 - .traptab_tc1 (__TRAPTAB_CPU0_END) : + .traptab_tc1 (__TRAPTAB_CPU0_END) : { . = ALIGN(8); - PROVIDE(__TRAPTAB_CPU1 = .); - KEEP (*(.traptab_cpu1)); - PROVIDE(__TRAPTAB_CPU1_END = .); + PROVIDE(__TRAPTAB_CPU1 = .); + KEEP (*(.traptab_cpu1)); + PROVIDE(__TRAPTAB_CPU1_END = .); } > pfls1 - .traptab_tc2 (__TRAPTAB_CPU1_END) : + .traptab_tc2 (__TRAPTAB_CPU1_END) : { . = ALIGN(8); - PROVIDE(__TRAPTAB_CPU2 = .); - KEEP (*(.traptab_cpu2)); - PROVIDE(__TRAPTAB_CPU2_END = .); + PROVIDE(__TRAPTAB_CPU2 = .); + KEEP (*(.traptab_cpu2)); + PROVIDE(__TRAPTAB_CPU2_END = .); } > pfls1 - } - + } + /*Fixed memory Allocations for Interrupt Vector Table*/ SECTIONS { @@ -1048,7 +1059,7 @@ REGION_ALIAS( default_rom , pfls1) *(.zdata_cpu2.*) . = ALIGN(2); } > dsram2 AT> pfls1 - + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) { *Ifx_Ssw_Tc2.* (.zbss) @@ -1068,7 +1079,7 @@ REGION_ALIAS( default_rom , pfls1) *(.zdata_cpu1.*) . = ALIGN(2); } > dsram1 AT> pfls1 - + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) { *Ifx_Ssw_Tc1.* (.zbss) @@ -1088,7 +1099,7 @@ REGION_ALIAS( default_rom , pfls1) *(.zdata_cpu0.*) . = ALIGN(2); } > dsram0 AT> pfls1 - + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) { *Ifx_Ssw_Tc0.* (.zbss) @@ -1097,11 +1108,11 @@ REGION_ALIAS( default_rom , pfls1) *(.zbss_cpu0.*) } > dsram0 } - + /*Near Absolute Data, selectable by toolchain*/ CORE_ID = GLOBAL; SECTIONS - { + { CORE_SEC(.zdata_powerOn) : FLAGS(awzl) { *(.zdata.dsprPowerOnInit.cpu0.32bit) @@ -1109,7 +1120,7 @@ REGION_ALIAS( default_rom , pfls1) *(.zdata.dsprPowerOnInit.cpu0.8bit) . = ALIGN(2); } > default_ram AT> pfls1 - + CORE_SEC(.zdata) : FLAGS(awzl) { *(.zdata.dsprInit.cpu0.32bit) @@ -1120,21 +1131,21 @@ REGION_ALIAS( default_rom , pfls1) *(.gnu.linkonce.z.*) . = ALIGN(2); } > default_ram AT> pfls1 - + CORE_SEC(.zbss_powerOn) (NOLOAD) : FLAGS(awz) { *(.zbss.dsprPowerOnClear.cpu0.32bit) *(.zbss.dsprPowerOnClear.cpu0.16bit) *(.zbss.dsprPowerOnClear.cpu0.8bit) } > default_ram - + CORE_SEC(.zbss_noClear) (NOLOAD) : FLAGS(awz) { *(.zbss.dsprNoInit.cpu0.32bit) *(.zbss.dsprNoInit.cpu0.16bit) *(.zbss.dsprNoInit.cpu0.8bit) } > default_ram - + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) { *(.zbss.dsprClearOnInit.cpu0.32bit) @@ -1158,14 +1169,14 @@ REGION_ALIAS( default_rom , pfls1) *(.zlmudata.*) . = ALIGN(2); } > cpu0_dlmu AT> pfls1 - + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) { *(.zlmubss) *(.zlmubss.*) } > cpu0_dlmu } - + /*Near Absolute Const, selectable with patterns and user defined sections*/ CORE_ID = GLOBAL; SECTIONS @@ -1177,7 +1188,7 @@ REGION_ALIAS( default_rom , pfls1) *(.zrodata_cpu?) } > pfls1 } - + /*Near Absolute Const, selectable by toolchain*/ CORE_ID = GLOBAL; SECTIONS @@ -1241,7 +1252,7 @@ SECTIONS *(.rodata_a8) *(.rodata_a8.*) } > default_rom - + _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; __A8_MEM = _SMALL_DATA3_; } @@ -1260,7 +1271,7 @@ SECTIONS *(.data_cpu2.*) . = ALIGN(2); } > dsram2 AT> pfls1 - + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) { *Ifx_Ssw_Tc2.* (.bss) @@ -1268,7 +1279,7 @@ SECTIONS *(.bss_cpu2) *(.bss_cpu2.*) } > dsram2 - + /*DLMU2 Sections*/ CORE_SEC(.lmudata) : FLAGS(awl) { @@ -1276,7 +1287,7 @@ SECTIONS *(.lmudata_cpu2.*) . = ALIGN(2); } > cpu2_dlmu AT> pfls1 - + CORE_SEC(.lmubss) : FLAGS(aw) { *(.lmubss_cpu2) @@ -1295,7 +1306,7 @@ SECTIONS *(.data_cpu1.*) . = ALIGN(2); } > dsram1 AT> pfls1 - + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) { *Ifx_Ssw_Tc1.* (.bss) @@ -1303,7 +1314,7 @@ SECTIONS *(.bss_cpu1) *(.bss_cpu1.*) } > dsram1 - + /*DLMU1 Sections*/ CORE_SEC(.lmudata) : FLAGS(awl) { @@ -1311,7 +1322,7 @@ SECTIONS *(.lmudata_cpu1.*) . = ALIGN(2); } > cpu1_dlmu AT> pfls1 - + CORE_SEC(.lmubss) : FLAGS(aw) { *(.lmubss_cpu1) @@ -1330,7 +1341,7 @@ SECTIONS *(.data_cpu0.*) . = ALIGN(2); } > dsram0 AT> pfls1 - + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) { *Ifx_Ssw_Tc0.* (.bss) @@ -1338,7 +1349,7 @@ SECTIONS *(.bss_cpu0) *(.bss_cpu0.*) } > dsram0 - + /*DLMU0 Sections*/ CORE_SEC(.lmudata) : FLAGS(awl) { @@ -1346,7 +1357,7 @@ SECTIONS *(.lmudata_cpu0.*) . = ALIGN(2); } > cpu0_dlmu AT> pfls1 - + CORE_SEC(.lmubss) : FLAGS(aw) { *(.lmubss_cpu0) @@ -1364,13 +1375,13 @@ SECTIONS *(.a9sdata.*) . = ALIGN(2); } > cpu0_dlmu AT> pfls1 - + CORE_SEC(.sbss4) : { *(.a9sbss) - *(.a9sbss.*) + *(.a9sbss.*) } > cpu0_dlmu - + _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; __A9_MEM = _SMALL_DATA4_; } @@ -1385,7 +1396,7 @@ SECTIONS *(.bss.farDsprNoInit.cpu0.16bit) *(.bss.farDsprNoInit.cpu0.8bit) } > default_ram - + CORE_SEC(.data) : FLAGS(awl) { *(.data.farDsprInit.cpu0.32bit) @@ -1396,7 +1407,7 @@ SECTIONS *(.gnu.linkonce.d.*) . = ALIGN(2); } > default_ram AT> pfls1 - + CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) { *(.bss.farDsprClearOnInit.cpu0.32bit) @@ -1406,7 +1417,7 @@ SECTIONS *(.bss.*) *(.gnu.linkonce.b.*) } > default_ram - + .heap : FLAGS(aw) { . = ALIGN(4); @@ -1414,14 +1425,14 @@ SECTIONS . += LCF_HEAP_SIZE; __HEAP_END = .; } > default_ram - + CORE_SEC(.lmudata) : FLAGS(awl) { *(.lmudata) *(.lmudata.*) . = ALIGN(2); } > cpu0_dlmu AT> pfls1 - + CORE_SEC(.lmubss) : FLAGS(aw) { *(.lmubss) @@ -1542,7 +1553,7 @@ SECTIONS *(.text_cpu0) *(.text_cpu0.*) } > pfls1 - + /* * Code executed before calling main extra section for C++ constructor init * -------------------------Start----------------------------------------- @@ -1554,9 +1565,9 @@ SECTIONS KEEP(*(.init*)) PROVIDE(__init_end = .); . = ALIGN(8); - + } > pfls1 - + .fini : { PROVIDE(__fini_start = .); @@ -1565,7 +1576,7 @@ SECTIONS PROVIDE(__fini_end = .); . = ALIGN(8); } > pfls1 - + /* * Code executed before calling main extra section for C++ constructor init * -------------------------End----------------------------------------- @@ -1660,10 +1671,10 @@ SECTIONS * the .eh_frame section from the executable. */ .eh_frame_hdr : - { + { *(.eh_frame_hdr) } > default_rom - + .eh_frame : { __EH_FRAME_BEGIN__ = . ; @@ -1671,14 +1682,14 @@ SECTIONS __EH_FRAME_END__ = . ; . = ALIGN(8); } > default_rom - - .gcc_except_table : - { - __GCC_EXCEPT_TABLE_BEGIN__ = . ; - KEEP (*(.gcc_except_table)) - __GCC_EXCEPT_TABLE_END__ = . ; - . = ALIGN(8); - } > default_rom + + .gcc_except_table : + { + __GCC_EXCEPT_TABLE_BEGIN__ = . ; + KEEP (*(.gcc_except_table)) + __GCC_EXCEPT_TABLE_END__ = . ; + . = ALIGN(8); + } > default_rom /* * Constructors and destructors. diff --git a/IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl b/IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl deleted file mode 100644 index da9305ff4..000000000 --- a/IDE/AURIX/test-app/Lcf_Tasking_Tricore_Tc.lsl +++ /dev/null @@ -1,918 +0,0 @@ -/* Lcf_Tasking_Tricore_Tc.lsl - * - * Copyright (C) 2014-2024 wolfSSL Inc. - * - * This file is part of wolfBoot. - * - * wolfBoot is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * wolfBoot is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with wolfBoot. If not, see . - */ -#define LCF_CSA0_SIZE 8k -#define LCF_USTACK0_SIZE 2k -#define LCF_ISTACK0_SIZE 1k - -#define LCF_CSA1_SIZE 8k -#define LCF_USTACK1_SIZE 2k -#define LCF_ISTACK1_SIZE 1k - -#define LCF_CSA2_SIZE 8k -#define LCF_USTACK2_SIZE 2k -#define LCF_ISTACK2_SIZE 1k - -#define LCF_HEAP_SIZE 4k - -#define LCF_CPU0 0 -#define LCF_CPU1 1 -#define LCF_CPU2 2 - -/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ -#define LCF_DEFAULT_HOST LCF_CPU0 -/*#define LCF_DEFAULT_HOST LCF_CPU1*/ -/*#define LCF_DEFAULT_HOST LCF_CPU2*/ - -#define LCF_DSPR2_START 0x50000000 -#define LCF_DSPR2_SIZE 96k - -#define LCF_DSPR1_START 0x60000000 -#define LCF_DSPR1_SIZE 240k - -#define LCF_DSPR0_START 0x70000000 -#define LCF_DSPR0_SIZE 240k - -#define LCF_CSA2_OFFSET (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE) -#define LCF_ISTACK2_OFFSET (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE) -#define LCF_USTACK2_OFFSET (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE) - -#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE) -#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE) -#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE) - -#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE) -#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE) -#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE) - -#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE) -#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE) -#define LCF_HEAP2_OFFSET (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE) - -#define LCF_INTVEC0_START 0x802FE000 -#define LCF_INTVEC1_START 0x805FC000 -#define LCF_INTVEC2_START 0x805FE000 - -#define LCF_TRAPVEC0_START 0x80000100 -#define LCF_TRAPVEC1_START 0x80300000 -#define LCF_TRAPVEC2_START 0x80300100 - -#define LCF_STARTPTR_CPU0 0x80000000 -#define LCF_STARTPTR_CPU1 0x80300200 -#define LCF_STARTPTR_CPU2 0x80300220 - -#define LCF_STARTPTR_NC_CPU0 0xA0000000 -#define LCF_STARTPTR_NC_CPU1 0xA0300200 -#define LCF_STARTPTR_NC_CPU2 0xA0300220 - -#define INTTAB0 (LCF_INTVEC0_START) -#define INTTAB1 (LCF_INTVEC1_START) -#define INTTAB2 (LCF_INTVEC2_START) -#define TRAPTAB0 (LCF_TRAPVEC0_START) -#define TRAPTAB1 (LCF_TRAPVEC1_START) -#define TRAPTAB2 (LCF_TRAPVEC2_START) - -#define RESET LCF_STARTPTR_NC_CPU0 - -#include "tc1v1_6_2.lsl" - -// Specify a multi-core processor environment (mpe) - -processor mpe -{ - derivative = tc37; -} - -derivative tc37 -{ - core tc0 - { - architecture = TC1V1.6.2; - space_id_offset = 100; // add 100 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core tc1 // core 1 TC16E - { - architecture = TC1V1.6.2; - space_id_offset = 200; // add 200 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core tc2 // core 2 TC16P - { - architecture = TC1V1.6.2; - space_id_offset = 300; // add 300 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core vtc - { - architecture = TC1V1.6.2; - import tc0; // add all address spaces of core tc0 to core vtc for linking and locating - import tc1; // tc1 - import tc2; // tc2 - } - - bus sri - { - mau = 8; - width = 32; - - // map shared addresses one-to-one to real cores and virtual cores - map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:tc2:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - } - - memory dsram2 // Data Scratch Pad Ram - { - mau = 8; - size = 96k; - type = ram; - map (dest=bus:tc2:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); - map (dest=bus:sri, dest_offset=0x50000000, size=96k); - } - - memory psram2 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc2:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x50100000, size=64k); - } - - memory dsram1 // Data Scratch Pad Ram - { - mau = 8; - size = 240k; - type = ram; - map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); - map (dest=bus:sri, dest_offset=0x60000000, size=240k); - } - - memory psram1 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x60100000, size=64k); - } - - memory dsram0 // Data Scratch Pad Ram - { - mau = 8; - size = 240k; - type = ram; - map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); - map (dest=bus:sri, dest_offset=0x70000000, size=240k); - } - - memory psram0 // Program Scratch Pad Ram - { - mau = 8; - size = 64k; - type = ram; - map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); - map (dest=bus:sri, dest_offset=0x70100000, size=64k); - } - - memory pfls0 - { - mau = 8; - size = 3M; - type = rom; - map cached (dest=bus:sri, dest_offset=0x80000000, size=3M); - map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=3M); - } - - memory pfls1 - { - mau = 8; - size = 3M; - type = rom; - map cached (dest=bus:sri, dest_offset=0x80300000, size=3M); - map not_cached (dest=bus:sri, dest_offset=0xa0300000, reserved, size=3M); - } - - memory dfls0 - { - mau = 8; - size = 256K; - type = reserved nvram; - map (dest=bus:sri, dest_offset=0xaf000000, size=256K); - } - - memory ucb - { - mau = 8; - size = 24k; - type = rom; - map (dest=bus:sri, dest_offset=0xaf400000, reserved, size=24k); - } - - memory cpu0_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90000000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=64k); - } - - memory cpu1_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90010000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0010000, reserved, size=64k); - } - - memory cpu2_dlmu - { - mau = 8; - size = 64k; - type = ram; - map cached (dest=bus:sri, dest_offset=0x90020000, size=64k); - map not_cached (dest=bus:sri, dest_offset=0xb0020000, reserved, size=64k); - } - -#if (__VERSION__ >= 6003) - section_setup :vtc:linear - { - heap "heap" (min_size = (1k), fixed, align = 8); - } -#endif - - section_setup :vtc:linear - { - start_address - ( - symbol = "_START" - ); - } - - section_setup :vtc:linear - { - stack "ustack_tc0" (min_size = 1k, fixed, align = 8); - stack "istack_tc0" (min_size = 1k, fixed, align = 8); - stack "ustack_tc1" (min_size = 1k, fixed, align = 8); - stack "istack_tc1" (min_size = 1k, fixed, align = 8); - stack "ustack_tc2" (min_size = 1k, fixed, align = 8); - stack "istack_tc2" (min_size = 1k, fixed, align = 8); - } - - /*Section setup for the copy table*/ - section_setup :vtc:linear - { - copytable - ( - align = 4, - dest = linear, - table - { - symbol = "_lc_ub_table_tc0"; - space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa; - }, - table - { - symbol = "_lc_ub_table_tc1"; - space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa; - }, - table - { - symbol = "_lc_ub_table_tc2"; - space = :tc2:linear, :tc2:abs24, :tc2:abs18, :tc2:csa; - } - ); - } - - /*Sections located at absolute fixed address*/ - - section_layout :vtc:linear - { - /*Fixed memory Allocations for stack memory and CSA*/ - group (ordered) - { - group ustack2(align = 8, run_addr = mem:dsram2[LCF_USTACK2_OFFSET]) - { - stack "ustack_tc2" (size = LCF_USTACK2_SIZE); - } - "__USTACK2":= sizeof(group:ustack2) > 0 ? "_lc_ue_ustack_tc2" : 0; - "__USTACK2_END"="_lc_gb_ustack2"; - - group istack2(align = 8, run_addr = mem:dsram2[LCF_ISTACK2_OFFSET]) - { - stack "istack_tc2" (size = LCF_ISTACK2_SIZE); - } - "__ISTACK2":= sizeof(group:istack2) > 0 ? "_lc_ue_istack_tc2" : 0; - "__ISTACK2_END"="_lc_gb_istack2"; - - group (align = 64, attributes=rw, run_addr=mem:dsram2[LCF_CSA2_OFFSET]) - reserved "csa_tc2" (size = LCF_CSA2_SIZE); - "__CSA2":= "_lc_ub_csa_tc2"; - "__CSA2_END":= "_lc_ue_csa_tc2"; - } - group (ordered) - { - group ustack1(align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET]) - { - stack "ustack_tc1" (size = LCF_USTACK1_SIZE); - } - "__USTACK1":= sizeof(group:ustack1) > 0 ? "_lc_ue_ustack_tc1" : 0; - "__USTACK1_END"="_lc_gb_ustack1"; - - group istack1(align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET]) - { - stack "istack_tc1" (size = LCF_ISTACK1_SIZE); - } - "__ISTACK1":= sizeof(group:istack1) > 0 ? "_lc_ue_istack_tc1" : 0; - "__ISTACK1_END"="_lc_gb_istack1"; - - group (align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET]) - reserved "csa_tc1" (size = LCF_CSA1_SIZE); - "__CSA1":= "_lc_ub_csa_tc1"; - "__CSA1_END":= "_lc_ue_csa_tc1"; - } - group (ordered) - { - group ustack0(align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET]) - { - stack "ustack_tc0" (size = LCF_USTACK0_SIZE); - } - "__USTACK0":= sizeof(group:ustack0) > 0 ? "_lc_ue_ustack_tc0" : 0; - "__USTACK0_END"="_lc_gb_ustack0"; - - group istack0(align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET]) - { - stack "istack_tc0" (size = LCF_ISTACK0_SIZE); - } - "__ISTACK0":= sizeof(group:istack0) > 0 ? "_lc_ue_istack_tc0" : 0; - "__ISTACK0_END"="_lc_gb_istack0"; - - group (align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET]) - reserved "csa_tc0" (size = LCF_CSA0_SIZE); - "__CSA0":= "_lc_ub_csa_tc0"; - "__CSA0_END":= "_lc_ue_csa_tc0"; - } - - /*Fixed memory Allocations for _START*/ - group (ordered) - { - group reset (run_addr=RESET) - { - section "reset" ( size = 0x20, fill = 0x0800, attributes = r ) - { - select ".text.start"; - } - } - group interface_const (run_addr=mem:pfls0[0x0020]) - { - select "*.interface_const"; - } - "__IF_CONST" := addressof(group:interface_const); - "__START0" := LCF_STARTPTR_NC_CPU0; - "__START1" := LCF_STARTPTR_NC_CPU1; - "__START2" := LCF_STARTPTR_NC_CPU2; - } - - /*Fixed memory Allocations for Trap Vector Table*/ - group (ordered) - { - group trapvec_tc0 (align = 8, run_addr=LCF_TRAPVEC0_START) - { - section "trapvec_tc0" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu0*)"; - } - } - group trapvec_tc1 (align = 8, run_addr=LCF_TRAPVEC1_START) - { - section "trapvec_tc1" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu1*)"; - } - } - group trapvec_tc2 (align = 8, run_addr=LCF_TRAPVEC2_START) - { - section "trapvec_tc2" (size=0x100, attributes=rx, fill=0) - { - select "(.text.traptab_cpu2*)"; - } - } - "__TRAPTAB_CPU0" := TRAPTAB0; - "__TRAPTAB_CPU1" := TRAPTAB1; - "__TRAPTAB_CPU2" := TRAPTAB2; - } - - /*Fixed memory Allocations for Start up code*/ - group (ordered) - { - group start_tc0 (run_addr=LCF_STARTPTR_NC_CPU0) - { - select "(.text.start_cpu0*)"; - } - group start_tc1 (run_addr=LCF_STARTPTR_NC_CPU1) - { - section "start_tc1" (size=0x20, attributes=rx, fill=0) - { - select "(.text.start_cpu1*)"; - } - } - group start_tc2 (run_addr=LCF_STARTPTR_NC_CPU2) - { - select "(.text.start_cpu2*)"; - } - "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 0; - "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 0; - } - - /*Fixed memory Allocations for Interrupt Vector Table*/ - group (ordered) - { - group int_tab_tc0 (ordered) - { -# include "inttab0.lsl" - } - group int_tab_tc1 (ordered) - { -# include "inttab1.lsl" - } - group int_tab_tc2 (ordered) - { -# include "inttab2.lsl" - } - "_lc_u_int_tab" = (LCF_INTVEC0_START); - "__INTTAB_CPU0" = (LCF_INTVEC0_START); - "__INTTAB_CPU1" = (LCF_INTVEC1_START); - "__INTTAB_CPU2" = (LCF_INTVEC2_START); - } - - /*Fixed memory Allocations for BMHD*/ - group (ordered) - { - group bmh_0_orig (run_addr=mem:ucb[0x0000]) - { - select ".rodata.bmhd_0_orig"; - } - group bmh_1_orig (run_addr=mem:ucb[0x0200]) - { - select ".rodata.bmhd_1_orig"; - } - group bmh_2_orig (run_addr=mem:ucb[0x0400]) - { - select ".rodata.bmhd_2_orig"; - } - group bmh_3_orig (run_addr=mem:ucb[0x0600]) - { - select ".rodata.bmhd_3_orig"; - } - group bmh_blank (run_addr=mem:ucb[0x0800]) - { - } - group bmh_0_copy (run_addr=mem:ucb[0x1000]) - { - select ".rodata.bmhd_0_copy"; - } - group bmh_1_copy (run_addr=mem:ucb[0x1200]) - { - select ".rodata.bmhd_1_copy"; - } - group bmh_2_copy (run_addr=mem:ucb[0x1400]) - { - select ".rodata.bmhd_2_copy"; - } - group bmh_3_copy (run_addr=mem:ucb[0x1600]) - { - select ".rodata.bmhd_3_copy"; - } - } - } - - /*Near Abbsolute Addressable Data Sections*/ - section_layout :vtc:abs18 - { - /*Near Absolute Data, selectable with patterns and user defined sections*/ - group - { - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) - { - select "(.zdata.zdata_cpu2|.zdata.zdata_cpu2.*)"; - select "(.zbss.zbss_cpu2|.zbss.zbss_cpu2.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) - { - select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1.*)"; - select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) - { - select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0.*)"; - select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0.*)"; - } - - group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) - { - select "(.zdata.zlmudata|.zdata.zlmudata.*)"; - select "(.zbss.zlmubss|.zbss.zlmubss.*)"; - } - } - - /*Near Absolute Data, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) -# endif - { - group zdata_mcal(attributes=rw) - { - select ".zdata.dsprInit.cpu0.32bit"; - select ".zdata.dsprInit.cpu0.16bit"; - select ".zdata.dsprInit.cpu0.8bit"; - } - - group zdata_powerOn(attributes=rw) - { - select ".zdata.dsprPowerOnInit.cpu0.32bit"; - select ".zdata.dsprPowerOnInit.cpu0.16bit"; - select ".zdata.dsprPowerOnInit.cpu0.8bit"; - } - - group zbss_mcal(attributes=rw) - { - select ".zbss.dsprClearOnInit.cpu0.32bit"; - select ".zbss.dsprClearOnInit.cpu0.16bit"; - select ".zbss.dsprClearOnInit.cpu0.8bit"; - } - - group zbss_noClear(attributes=rw) - { - select ".zbss.dsprNoInit.cpu0.32bit"; - select ".zbss.dsprNoInit.cpu0.16bit"; - select ".zbss.dsprNoInit.cpu0.8bit"; - } - - group zbss_powerOn(attributes=rw) - { - select ".zbss.dsprPowerOnClear.cpu0.32bit"; - select ".zbss.dsprPowerOnClear.cpu0.16bit"; - select ".zbss.dsprPowerOnClear.cpu0.8bit"; - } - - group zdata(attributes=rw) - { - select "(.zdata|.zdata.*)"; - select "(.zbss|.zbss.*)"; - } - } - - /*Near Absolute Const, selectable with patterns and user defined sections*/ - group - { - group (ordered, align = 4, contiguous, run_addr=mem:pfls0) - { - select ".zrodata.Ifx_Ssw_Tc0.*"; - select ".zrodata.Ifx_Ssw_Tc1.*"; - select ".zrodata.Ifx_Ssw_Tc2.*"; - select ".zrodata.Cpu0_Main.*"; - select ".zrodata.Cpu1_Main.*"; - select ".zrodata.Cpu2_Main.*"; - - /*Near Absolute Const, selectable by toolchain*/ - select ".zrodata.const.cpu0.32bit"; - select ".zrodata.const.cpu0.16bit"; - select ".zrodata.const.cpu0.8bit"; - select ".zrodata.config.cpu0.32bit"; - select ".zrodata.config.cpu0.16bit"; - select ".zrodata.config.cpu0.8bit"; - select "(.zrodata|.zrodata.*)"; - } - } - } - - /*Relative A0/A1/A8/A9 Addressable Sections*/ - section_layout :vtc:linear - { - /*Relative A0 Addressable Data, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU2 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) -# endif - { - select "(.data_a0.sdata|.data_a0.sdata.*)"; - select "(.bss_a0.sbss|.bss_a0.sbss.*)"; - } - "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; - "__A0_MEM" = "_SMALL_DATA_"; - - /*Relative A1 Addressable Const, selectable by toolchain*/ - /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ -# if LCF_DEFAULT_HOST == LCF_CPU2 - group a1 (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group a1 (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group a1 (ordered, align = 4, run_addr=mem:pfls0) -# endif - { - select "(.rodata_a1.srodata|.rodata_a1.srodata.*)"; - select "(.ldata|.ldata.*)"; - } - "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; - "__A1_MEM" = "_LITERAL_DATA_"; - - /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ - group a9 (ordered, align = 4, run_addr=mem:cpu0_dlmu) - { - select "(.data_a9.a9sdata|.data_a9.a9sdata.*)"; - select "(.bss_a9.a9sbss|.bss_a9.a9sbss.*)"; - } - "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; - "__A9_MEM" = "_A9_DATA_"; - - /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ -# if LCF_DEFAULT_HOST == LCF_CPU2 - group a8 (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group a8 (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group a8 (ordered, align = 4, run_addr=mem:pfls0) -# endif - { - select "(.rodata_a8.a8srodata|.rodata_a8.a8srodata.*)"; - } - "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; - "__A8_MEM" = "_A8_DATA_"; - } - - /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ - section_layout :vtc:linear - { - /*Far Data Sections, selectable with patterns and user defined sections*/ - group - { - /*DSRAM sections*/ - group - { - group (ordered, attributes=rw, run_addr=mem:dsram2) - { - select ".data.Ifx_Ssw_Tc2.*"; - select ".data.Cpu2_Main.*"; - select "(.data.data_cpu2|.data.data_cpu2.*)"; - select ".bss.Ifx_Ssw_Tc2.*"; - select ".bss.Cpu2_Main.*"; - select "(.bss.bss_cpu2|.bss.bss_cpu2.*)"; - } - group (ordered, attributes=rw, run_addr=mem:dsram1) - { - select ".data.Ifx_Ssw_Tc1.*"; - select ".data.Cpu1_Main.*"; - select "(.data.data_cpu1|.data.data_cpu1.*)"; - select ".bss.Ifx_Ssw_Tc1.*"; - select ".bss.Cpu1_Main.*"; - select "(.bss.bss_cpu1|.bss.bss_cpu1.*)"; - } - group (ordered, attributes=rw, run_addr=mem:dsram0) - { - select ".data.Ifx_Ssw_Tc0.*"; - select ".data.Cpu0_Main.*"; - select "(.data.data_cpu0|.data.data_cpu0.*)"; - select ".bss.Ifx_Ssw_Tc0.*"; - select ".bss.Cpu0_Main.*"; - select "(.bss.bss_cpu0|.bss.bss_cpu0.*)"; - } - } - - /*LMU Data sections*/ - group - { - group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) - { - select "(.data.lmudata_cpu0|.data.lmudata_cpu0.*)"; - select "(.bss.lmubss_cpu0|.bss.lmubss_cpu0.*)"; - select "(.data.lmudata|.data.lmudata.*)"; - select "(.bss.lmubss|.bss.lmubss.*)"; - } - group (ordered, attributes=rw, run_addr = mem:cpu1_dlmu) - { - select "(.data.lmudata_cpu1|.data.lmudata_cpu1.*)"; - select "(.bss.lmubss_cpu1|.bss.lmubss_cpu1.*)"; - } - group (ordered, attributes=rw, run_addr = mem:cpu2_dlmu) - { - select "(.data.lmudata_cpu2|.data.lmudata_cpu2.*)"; - select "(.bss.lmubss_cpu2|.bss.lmubss_cpu2.*)"; - } - } - } - - /*Far Data Sections, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) -# endif - { - group data_mcal(attributes=rw) - { - select ".data.farDsprInit.cpu0.32bit"; - select ".data.farDsprInit.cpu0.16bit"; - select ".data.farDsprInit.cpu0.8bit"; - } - - group bss_mcal(attributes=rw) - { - select ".bss.farDsprClearOnInit.cpu0.32bit"; - select ".bss.farDsprClearOnInit.cpu0.16bit"; - select ".bss.farDsprClearOnInit.cpu0.8bit"; - } - - group bss_noInit(attributes=rw) - { - select ".bss.farDsprNoInit.cpu0.32bit"; - select ".bss.farDsprNoInit.cpu0.16bit"; - select ".bss.farDsprNoInit.cpu0.8bit"; - } - - group data(attributes=rw) - { - select "(.data|.data.*)"; - select "(.bss|.bss.*)"; - } - } - - /*Heap allocation*/ -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, align = 4, run_addr = mem:dsram2[LCF_HEAP2_OFFSET]) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET]) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET]) -# endif - { - heap "heap" (size = LCF_HEAP_SIZE); - } - - /*Far Const Sections, selectable with patterns and user defined sections*/ - group - { - group (ordered, align = 4, run_addr=mem:pfls0) - { - select ".rodata.Ifx_Ssw_Tc0.*"; - select ".rodata.Cpu0_Main.*"; - select "(.rodata.rodata_cpu0|.rodata.rodata_cpu0.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls1) - { - select ".rodata.Cpu1_Main.*"; - select ".rodata.Ifx_Ssw_Tc1.*"; - select "(.rodata.rodata_cpu1|.rodata.rodata_cpu1.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls1) - { - select ".rodata.Ifx_Ssw_Tc2.*"; - select ".rodata.Cpu2_Main.*"; - select "(.rodata.rodata_cpu2|.rodata.rodata_cpu2.*)"; - } - } - - /*Far Const Sections, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, align = 4, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, align = 4, run_addr=mem:pfls0) -# endif - { - select ".rodata.farConst.cpu0.32bit"; - select ".rodata.farConst.cpu0.16bit"; - select ".rodata.farConst.cpu0.8bit"; - select "(.rodata|.rodata.*)"; - } - } - - /* PSRAM Code selections*/ - section_layout :vtc:linear - { - /*Code Sections, selectable with patterns and user defined sections*/ - group - { - /*Program Scratchpad Sections*/ - group - { - group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0) - { - select "(.text.cpu0_psram|.text.cpu0_psram.*)"; - select "(.text.psram_text_cpu0|.text.psram_text_cpu0.*)"; - } - group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1) - { - select "(.text.cpu1_psram|.text.cpu1_psram.*)"; - select "(.text.psram_text_cpu1|.text.psram_text_cpu1.*)"; - } - group code_psram2 (ordered, attributes=rwx, copy, run_addr=mem:psram2) - { - select "(.text.cpu2_psram|.text.cpu2_psram.*)"; - select "(.text.psram_text_cpu2|.text.psram_text_cpu2.*)"; - } - } - } - } - - /* FLS Code selections*/ - section_layout :vtc:linear - { - /*Code Sections, selectable with patterns and user defined sections*/ - group - { - /*Cpu specific PFLASH Sections*/ - group - { - group (ordered, align = 4, run_addr=mem:pfls0) - { - select ".text.Ifx_Ssw_Tc0.*"; - select ".text.Cpu0_Main.*"; - select ".text.CompilerTasking.Ifx_C_Init"; - select "(.text.text_cpu0|.text.text_cpu0.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls1) - { - select ".text.Ifx_Ssw_Tc1.*"; - select ".text.Cpu1_Main.*"; - select "(.text.text_cpu1|.text.text_cpu1.*)"; - } - group (ordered, align = 4, run_addr=mem:pfls1) - { - select ".text.Ifx_Ssw_Tc2.*"; - select ".text.Cpu2_Main.*"; - select "(.text.text_cpu2|.text.text_cpu2.*)"; - } - } - } - - /*Code Sections, selectable by toolchain*/ -# if LCF_DEFAULT_HOST == LCF_CPU2 - group (ordered, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU1 - group (ordered, run_addr=mem:pfls1) -# endif -# if LCF_DEFAULT_HOST == LCF_CPU0 - group (ordered, run_addr=mem:pfls0) -# endif - { - select ".text.fast.pfls.cpu0"; - select ".text.slow.pfls.cpu0"; - select ".text.5ms.pfls.cpu0"; - select ".text.10ms.pfls.cpu0"; - select ".text.callout.pfls.cpu0"; - select "(.text|.text.*)"; - } - } -} diff --git a/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.cproject b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.cproject new file mode 100644 index 000000000..b9dec4e76 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.cproject @@ -0,0 +1,785 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.project b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.project new file mode 100644 index 000000000..41c829fdc --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/.project @@ -0,0 +1,99 @@ + + + wolfBoot-tc3xx-wolfHSM + + + + + + com.infineon.aurix.buildsystem.builders.booster + full,incremental, + + + + + com.infineon.aurix.buildsystem.builders.autodiscovery + full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.infineon.aurix.buildsystem.aurixnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Configurations + 2 + SDK_CONFIGURATION_DIR + + + Libraries + 2 + SDK_DIR + + + wolfBoot + 2 + virtual:/virtual + + + wolfhsm-infineon-tc3xx + 2 + WOLFHSM_TC3XX_DIR + + + wolfBoot/hal + 2 + WOLFBOOT_ROOT/hal + + + wolfBoot/include + 2 + WOLFBOOT_ROOT/include + + + wolfBoot/src + 2 + WOLFBOOT_ROOT/src + + + wolfBoot/wolfssl + 2 + WOLFBOOT_ROOT/lib/wolfssl + + + + + SDK_CONFIGURATION_DIR + $%7BPARENT-1-PROJECT_LOC%7D/Configurations + + + SDK_DIR + $%7BPARENT-1-PROJECT_LOC%7D/SDK + + + WOLFBOOT_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + WOLFHSM_TC3XX_DIR + $%7BPARENT-1-PROJECT_LOC%7D/wolfHSM-infineon-tc3xx + + + diff --git a/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu0_Main.c b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu0_Main.c new file mode 100644 index 000000000..26a94e5b4 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu0_Main.c @@ -0,0 +1,47 @@ +/* Cpu0_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "IfxCpu.h" +#include "IfxScuWdt.h" +#include "Ifx_Types.h" + +IFX_ALIGN(4) IfxCpu_syncEvent g_cpuSyncEvent = 0; + +extern void loader_main(void); + +void core0_main(void) +{ + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!! + * Enable the watchdogs and service them periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + /* invoke wolfBoot */ + loader_main(); + + while (1) { + } +} diff --git a/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu1_Main.c b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu1_Main.c new file mode 100644 index 000000000..4a353f526 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu1_Main.c @@ -0,0 +1,42 @@ +/* Cpu1_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "Ifx_Types.h" +#include "IfxCpu.h" +#include "IfxScuWdt.h" + +extern IfxCpu_syncEvent g_cpuSyncEvent; + +void core1_main(void) +{ + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG1 IS DISABLED HERE!! + * Enable the watchdog and service it periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + while(1) + { + } +} diff --git a/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu2_Main.c b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu2_Main.c new file mode 100644 index 000000000..09d82c438 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Cpu2_Main.c @@ -0,0 +1,42 @@ +/* Cpu2_Main.c + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +#include "Ifx_Types.h" +#include "IfxCpu.h" +#include "IfxScuWdt.h" + +extern IfxCpu_syncEvent g_cpuSyncEvent; + +void core2_main(void) +{ + IfxCpu_enableInterrupts(); + + /* !!WATCHDOG2 IS DISABLED HERE!! + * Enable the watchdog and service it periodically if it is required + */ + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + + /* Wait for CPU sync event */ + IfxCpu_emitEvent(&g_cpuSyncEvent); + IfxCpu_waitEvent(&g_cpuSyncEvent, 1); + + while(1) + { + } +} diff --git a/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Lcf_Gnuc_Tricore_Tc.lsl b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Lcf_Gnuc_Tricore_Tc.lsl new file mode 100644 index 000000000..acdcf46a9 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/Lcf_Gnuc_Tricore_Tc.lsl @@ -0,0 +1,1845 @@ +/* Lcf_Gnuc_Tricore_Tc.lsl + * + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH(tricore) +ENTRY(_START) + +__TRICORE_DERIVATE_MEMORY_MAP__ = 0x380; + +LCF_CSA0_SIZE = 8k; +LCF_USTACK0_SIZE = 20k; +LCF_ISTACK0_SIZE = 1k; + +LCF_CSA1_SIZE = 8k; +LCF_USTACK1_SIZE = 2k; +LCF_ISTACK1_SIZE = 1k; + +LCF_CSA2_SIZE = 8k; +LCF_USTACK2_SIZE = 2k; +LCF_ISTACK2_SIZE = 1k; + +LCF_HEAP_SIZE = 40k; + +LCF_DSPR2_START = 0x50000000; +LCF_DSPR2_SIZE = 96k; + +LCF_DSPR1_START = 0x60000000; +LCF_DSPR1_SIZE = 240k; + +LCF_DSPR0_START = 0x70000000; +LCF_DSPR0_SIZE = 240k; + +LCF_CSA2_OFFSET = (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE); +LCF_ISTACK2_OFFSET = (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE); +LCF_USTACK2_OFFSET = (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE); + +LCF_CSA1_OFFSET = (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE); +LCF_ISTACK1_OFFSET = (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE); +LCF_USTACK1_OFFSET = (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE); + +LCF_CSA0_OFFSET = (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE); +LCF_ISTACK0_OFFSET = (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE); +LCF_USTACK0_OFFSET = (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE); + +LCF_HEAP0_OFFSET = (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE); +LCF_HEAP1_OFFSET = (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE); +LCF_HEAP2_OFFSET = (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE); + + +LCF_CODE_BASE_ADDR = 0xA00A0000; + +LCF_START_CODE_SIZE = 0x20; /* space reserved for .start sections (per-cpu) */ +LCF_TRAPVEC_OFFSET = 0x100; /* size/alignment of trap table (also offset from base to first trap table) */ + +LCF_STARTPTR_NC_CPU0 = LCF_CODE_BASE_ADDR; +LCF_STARTPTR_NC_CPU1 = LCF_STARTPTR_NC_CPU0 + LCF_START_CODE_SIZE; +LCF_STARTPTR_NC_CPU2 = LCF_STARTPTR_NC_CPU1 + LCF_START_CODE_SIZE; + +/* Offset of the trap table from start address (accounts for size of .start section) */ +LCF_TRAPVEC0_START = (LCF_STARTPTR_NC_CPU0 + LCF_TRAPVEC_OFFSET); /* 0xA0000100 */ +LCF_TRAPVEC1_START = (LCF_TRAPVEC0_START + LCF_TRAPVEC_OFFSET); /* 0xA0000200 */ +LCF_TRAPVEC2_START = (LCF_TRAPVEC1_START + LCF_TRAPVEC_OFFSET); /* 0xA0000300 */ + +LCF_INTVEC_SIZE = 0x2000; /* 8k */ +/* Intvec start address must be 8k aligned due to sw isr constraints. See comment at IfxCpu_Irq.c:110. + * Make sure this leaves enough space for trap tables */ +LCF_INTVEC0_START = (LCF_STARTPTR_NC_CPU0 + LCF_INTVEC_SIZE); /* 0xA00A2000; */ +LCF_INTVEC1_START = (LCF_INTVEC0_START + LCF_INTVEC_SIZE); /* 0xA00A4000; */ +LCF_INTVEC2_START = (LCF_INTVEC1_START + LCF_INTVEC_SIZE); /* 0xA00A6000; */ +/* TODO: We end up reserving 32K for the startup memory section due to wanting a contiguous region of memory + * but also satisfying the address alignment requirement by infineon SDK for SW controlled interrupts. This is + * a lot of wasted space. See if we can be smarter about this */ + +__INTTAB_CPU0 = LCF_INTVEC0_START; +__INTTAB_CPU1 = LCF_INTVEC1_START; +__INTTAB_CPU2 = LCF_INTVEC2_START; + +RESET = LCF_STARTPTR_NC_CPU0; + +/* Size (bytes) of HSM shared memory buffer */ +HSM_SHM_BUF_SIZE = 4096; +/* Size (bytes) of a HSM shared cancel sequence number */ +HSM_SHM_CANCEL_SEQ_SIZE = 4; + +MEMORY +{ + dsram2_local (w!xp): org = 0xd0000000, len = 96K + dsram2 (w!xp): org = 0x50000000, len = 96K + psram2 (w!xp): org = 0x50100000, len = 64K + + dsram1_local (w!xp): org = 0xd0000000, len = 240K + dsram1 (w!xp): org = 0x60000000, len = 240K + psram1 (w!xp): org = 0x60100000, len = 64K + + /* HSM shared memory buffers */ + dsram_hsm_shm (rw!p): org = 0x70000000, len = 16K + + dsram0_local (w!xp): org = 0xd0004000, len = 224K + dsram0 (w!xp): org = 0x70004000, len = 224K + psram0 (w!xp): org = 0x70100000, len = 64K + + psram_local (w!xp): org = 0xc0000000, len = 64K + + /* Separate region for .start, IVTs, and Trap tables, since tricore-gcc will try + * and place overlapping .text sections here despite fixed addresses (possible compiler bug) */ + pfls0_startup (rx!p): org = 0xA00A0000, len = 0x8000 + /* wolfBoot program code - all of this project's executable code goes here */ + pfls0_nc (rx!p): org = 0xA00A8000, len = 0x23000 /* 140K total (incl 32K for startup) */ + + /* reserved for wolfBoot BOOT partition */ + pfls1_boot (rwx!p): org = 0x80300000, len = 0x17E000 /* ~1.5MiB */ + pfls1_boot_nc (rwx!p): org = 0xA0300000, len = 0x17E000 /* ~1.5MiB */ + + /* reserved for wolfBoot UPDATE partition */ + pfls1_update (rwx!p): org = 0x8047E000, len = 0x17E000 /* ~1.5MiB */ + pfls1_update_nc (rwx!p): org = 0xA047E000, len = 0x17E000 /* ~1.5MiB */ + + /* SWAP sector for wolfBoot image update */ + pfls1_swap (rwx!p): org = 0x805FC000, len = 16K /* last sector of PFLASH1 */ + + dfls0 (rx!p): org = 0xaf000000, len = 256K + + ucb (rx!p): org = 0xaf400000, len = 24K + + cpu0_dlmu (w!xp): org = 0x90000000, len = 64K + cpu0_dlmu_nc (w!xp): org = 0xb0000000, len = 64K + + cpu1_dlmu (w!xp): org = 0x90010000, len = 64K + cpu1_dlmu_nc (w!xp): org = 0xb0010000, len = 64K + + cpu2_dlmu (w!xp): org = 0x90020000, len = 64K + cpu2_dlmu_nc (w!xp): org = 0xb0020000, len = 64K +} + +/* map local memory address to a global address */ +REGION_MAP( CPU0 , ORIGIN(dsram0_local), LENGTH(dsram0_local), ORIGIN(dsram0)) +REGION_MAP( CPU1 , ORIGIN(dsram1_local), LENGTH(dsram1_local), ORIGIN(dsram1)) +REGION_MAP( CPU2 , ORIGIN(dsram2_local), LENGTH(dsram2_local), ORIGIN(dsram2)) +/* map cached and non cached addresses */ +/* REGION_MIRROR("pfls0", "pfls0_nc") */ +REGION_MIRROR("cpu0_dlmu", "cpu0_dlmu_nc") +REGION_MIRROR("cpu1_dlmu", "cpu1_dlmu_nc") +REGION_MIRROR("cpu2_dlmu", "cpu2_dlmu_nc") + +/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ + +REGION_ALIAS( default_ram , dsram0) +REGION_ALIAS( default_rom , pfls0_nc) /* pfls0 */ + +/* +REGION_ALIAS( default_ram , dsram1) +REGION_ALIAS( default_rom , pfls1) +*/ +/* +REGION_ALIAS( default_ram , dsram2) +*/ + +/*Sections located at absolute fixed address*/ + /*Fixed memory Allocations for stack memory and CSA*/ + CORE_ID = CPU2; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR2_START + LCF_USTACK2_OFFSET): + { PROVIDE(__USTACK2_END = .); . = . + LCF_USTACK2_SIZE; PROVIDE(__USTACK2 = .); } + + CORE_SEC(.istack) (LCF_DSPR2_START + LCF_ISTACK2_OFFSET): + { PROVIDE(__ISTACK2_END = .); . = . + LCF_ISTACK2_SIZE; PROVIDE(__ISTACK2 = .); } + + CORE_SEC(.csa) (LCF_DSPR2_START + LCF_CSA2_OFFSET): + { PROVIDE(__CSA2 = .); . = . + LCF_CSA2_SIZE; PROVIDE(__CSA2_END = .); } + } + + CORE_ID = CPU1; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR1_START + LCF_USTACK1_OFFSET): + { PROVIDE(__USTACK1_END = .); . = . + LCF_USTACK1_SIZE; PROVIDE(__USTACK1 = .); } + + CORE_SEC(.istack) (LCF_DSPR1_START + LCF_ISTACK1_OFFSET): + { PROVIDE(__ISTACK1_END = .); . = . + LCF_ISTACK1_SIZE; PROVIDE(__ISTACK1 = .); } + + CORE_SEC(.csa) (LCF_DSPR1_START + LCF_CSA1_OFFSET): + { PROVIDE(__CSA1 = .); . = . + LCF_CSA1_SIZE; PROVIDE(__CSA1_END = .); } + } + + CORE_ID = CPU0; + SECTIONS + { + CORE_SEC(.ustack) (LCF_DSPR0_START + LCF_USTACK0_OFFSET): + { PROVIDE(__USTACK0_END = .); . = . + LCF_USTACK0_SIZE; PROVIDE(__USTACK0 = .); } + + CORE_SEC(.istack) (LCF_DSPR0_START + LCF_ISTACK0_OFFSET): + { PROVIDE(__ISTACK0_END = .); . = . + LCF_ISTACK0_SIZE; PROVIDE(__ISTACK0 = .); } + + CORE_SEC(.csa) (LCF_DSPR0_START + LCF_CSA0_OFFSET): + { PROVIDE(__CSA0 = .); . = . + LCF_CSA0_SIZE; PROVIDE(__CSA0_END = .); } + } + + /*Fixed memory Allocations for _START*/ + CORE_ID = GLOBAL ; + SECTIONS + { + .start_tc0 (LCF_STARTPTR_NC_CPU0) : FLAGS(rxl) + { + PROVIDE(_start_text = .); /* needed by wolfBoot for self update when -DRAM_CODE */ + KEEP (*(.start)); + } > pfls0_startup + PROVIDE(__START0 = LCF_STARTPTR_NC_CPU0); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); /* Not used */ + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 0); + PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 0); + } + + /*Fixed memory Allocations for _START1 to 2*/ + CORE_ID = GLOBAL ; + SECTIONS + { + .start_tc1 (LCF_STARTPTR_NC_CPU1) : FLAGS(rxl) { KEEP (*(.start_cpu1)); } > pfls0_startup + .start_tc2 (LCF_STARTPTR_NC_CPU2) : FLAGS(rxl) { KEEP (*(.start_cpu2)); } > pfls0_startup + PROVIDE(__START1 = LCF_STARTPTR_NC_CPU1); + PROVIDE(__START2 = LCF_STARTPTR_NC_CPU2); + } + + /*Fixed memory Allocations for Trap Vector Table*/ + CORE_ID = GLOBAL; + SECTIONS + { + .traptab_tc0 (LCF_TRAPVEC0_START) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU0 = .); + KEEP (*(.traptab_cpu0)); + PROVIDE(__TRAPTAB_CPU0_END = .); + } > pfls0_startup /* pfls0 */ + + .traptab_tc1 (__TRAPTAB_CPU0_END) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU1 = .); + KEEP (*(.traptab_cpu1)); + PROVIDE(__TRAPTAB_CPU1_END = .); + } > pfls0_startup /* pfls0 */ + + .traptab_tc2 (__TRAPTAB_CPU1_END) : + { + . = ALIGN(8); + PROVIDE(__TRAPTAB_CPU2 = .); + KEEP (*(.traptab_cpu2)); + PROVIDE(__TRAPTAB_CPU2_END = .); + } > pfls0_startup /* pfls0 */ + } + + /*Fixed memory Allocations for Interrupt Vector Table*/ + SECTIONS + { + /*CPU0 Interrupt Vector Table*/ + .inttab_tc0_000 (__INTTAB_CPU0 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_0 )); } + .inttab_tc0_001 (__INTTAB_CPU0 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_1 )); } + .inttab_tc0_002 (__INTTAB_CPU0 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_2 )); } + .inttab_tc0_003 (__INTTAB_CPU0 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_3 )); } + .inttab_tc0_004 (__INTTAB_CPU0 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_4 )); } + .inttab_tc0_005 (__INTTAB_CPU0 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_5 )); } + .inttab_tc0_006 (__INTTAB_CPU0 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_6 )); } + .inttab_tc0_007 (__INTTAB_CPU0 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_7 )); } + .inttab_tc0_008 (__INTTAB_CPU0 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_8 )); } + .inttab_tc0_009 (__INTTAB_CPU0 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_9 )); } + .inttab_tc0_00A (__INTTAB_CPU0 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_10 )); } + .inttab_tc0_00B (__INTTAB_CPU0 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_11 )); } + .inttab_tc0_00C (__INTTAB_CPU0 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_12 )); } + .inttab_tc0_00D (__INTTAB_CPU0 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_13 )); } + .inttab_tc0_00E (__INTTAB_CPU0 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_14 )); } + .inttab_tc0_00F (__INTTAB_CPU0 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_15 )); } + .inttab_tc0_010 (__INTTAB_CPU0 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_16 )); } + .inttab_tc0_011 (__INTTAB_CPU0 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_17 )); } + .inttab_tc0_012 (__INTTAB_CPU0 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_18 )); } + .inttab_tc0_013 (__INTTAB_CPU0 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_19 )); } + .inttab_tc0_014 (__INTTAB_CPU0 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_20 )); } + .inttab_tc0_015 (__INTTAB_CPU0 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_21 )); } + .inttab_tc0_016 (__INTTAB_CPU0 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_22 )); } + .inttab_tc0_017 (__INTTAB_CPU0 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_23 )); } + .inttab_tc0_018 (__INTTAB_CPU0 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_24 )); } + .inttab_tc0_019 (__INTTAB_CPU0 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_25 )); } + .inttab_tc0_01A (__INTTAB_CPU0 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_26 )); } + .inttab_tc0_01B (__INTTAB_CPU0 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_27 )); } + .inttab_tc0_01C (__INTTAB_CPU0 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_28 )); } + .inttab_tc0_01D (__INTTAB_CPU0 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_29 )); } + .inttab_tc0_01E (__INTTAB_CPU0 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_30 )); } + .inttab_tc0_01F (__INTTAB_CPU0 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_31 )); } + .inttab_tc0_020 (__INTTAB_CPU0 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_32 )); } + .inttab_tc0_021 (__INTTAB_CPU0 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_33 )); } + .inttab_tc0_022 (__INTTAB_CPU0 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_34 )); } + .inttab_tc0_023 (__INTTAB_CPU0 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_35 )); } + .inttab_tc0_024 (__INTTAB_CPU0 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_36 )); } + .inttab_tc0_025 (__INTTAB_CPU0 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_37 )); } + .inttab_tc0_026 (__INTTAB_CPU0 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_38 )); } + .inttab_tc0_027 (__INTTAB_CPU0 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_39 )); } + .inttab_tc0_028 (__INTTAB_CPU0 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_40 )); } + .inttab_tc0_029 (__INTTAB_CPU0 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_41 )); } + .inttab_tc0_02A (__INTTAB_CPU0 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_42 )); } + .inttab_tc0_02B (__INTTAB_CPU0 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_43 )); } + .inttab_tc0_02C (__INTTAB_CPU0 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_44 )); } + .inttab_tc0_02D (__INTTAB_CPU0 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_45 )); } + .inttab_tc0_02E (__INTTAB_CPU0 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_46 )); } + .inttab_tc0_02F (__INTTAB_CPU0 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_47 )); } + .inttab_tc0_030 (__INTTAB_CPU0 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_48 )); } + .inttab_tc0_031 (__INTTAB_CPU0 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_49 )); } + .inttab_tc0_032 (__INTTAB_CPU0 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_50 )); } + .inttab_tc0_033 (__INTTAB_CPU0 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_51 )); } + .inttab_tc0_034 (__INTTAB_CPU0 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_52 )); } + .inttab_tc0_035 (__INTTAB_CPU0 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_53 )); } + .inttab_tc0_036 (__INTTAB_CPU0 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_54 )); } + .inttab_tc0_037 (__INTTAB_CPU0 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_55 )); } + .inttab_tc0_038 (__INTTAB_CPU0 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_56 )); } + .inttab_tc0_039 (__INTTAB_CPU0 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_57 )); } + .inttab_tc0_03A (__INTTAB_CPU0 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_58 )); } + .inttab_tc0_03B (__INTTAB_CPU0 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_59 )); } + .inttab_tc0_03C (__INTTAB_CPU0 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_60 )); } + .inttab_tc0_03D (__INTTAB_CPU0 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_61 )); } + .inttab_tc0_03E (__INTTAB_CPU0 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_62 )); } + .inttab_tc0_03F (__INTTAB_CPU0 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_63 )); } + .inttab_tc0_040 (__INTTAB_CPU0 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_64 )); } + .inttab_tc0_041 (__INTTAB_CPU0 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_65 )); } + .inttab_tc0_042 (__INTTAB_CPU0 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_66 )); } + .inttab_tc0_043 (__INTTAB_CPU0 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_67 )); } + .inttab_tc0_044 (__INTTAB_CPU0 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_68 )); } + .inttab_tc0_045 (__INTTAB_CPU0 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_69 )); } + .inttab_tc0_046 (__INTTAB_CPU0 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_70 )); } + .inttab_tc0_047 (__INTTAB_CPU0 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_71 )); } + .inttab_tc0_048 (__INTTAB_CPU0 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_72 )); } + .inttab_tc0_049 (__INTTAB_CPU0 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_73 )); } + .inttab_tc0_04A (__INTTAB_CPU0 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_74 )); } + .inttab_tc0_04B (__INTTAB_CPU0 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_75 )); } + .inttab_tc0_04C (__INTTAB_CPU0 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_76 )); } + .inttab_tc0_04D (__INTTAB_CPU0 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_77 )); } + .inttab_tc0_04E (__INTTAB_CPU0 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_78 )); } + .inttab_tc0_04F (__INTTAB_CPU0 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_79 )); } + .inttab_tc0_050 (__INTTAB_CPU0 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_80 )); } + .inttab_tc0_051 (__INTTAB_CPU0 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_81 )); } + .inttab_tc0_052 (__INTTAB_CPU0 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_82 )); } + .inttab_tc0_053 (__INTTAB_CPU0 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_83 )); } + .inttab_tc0_054 (__INTTAB_CPU0 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_84 )); } + .inttab_tc0_055 (__INTTAB_CPU0 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_85 )); } + .inttab_tc0_056 (__INTTAB_CPU0 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_86 )); } + .inttab_tc0_057 (__INTTAB_CPU0 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_87 )); } + .inttab_tc0_058 (__INTTAB_CPU0 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_88 )); } + .inttab_tc0_059 (__INTTAB_CPU0 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_89 )); } + .inttab_tc0_05A (__INTTAB_CPU0 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_90 )); } + .inttab_tc0_05B (__INTTAB_CPU0 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_91 )); } + .inttab_tc0_05C (__INTTAB_CPU0 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_92 )); } + .inttab_tc0_05D (__INTTAB_CPU0 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_93 )); } + .inttab_tc0_05E (__INTTAB_CPU0 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_94 )); } + .inttab_tc0_05F (__INTTAB_CPU0 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_95 )); } + .inttab_tc0_060 (__INTTAB_CPU0 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_96 )); } + .inttab_tc0_061 (__INTTAB_CPU0 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_97 )); } + .inttab_tc0_062 (__INTTAB_CPU0 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_98 )); } + .inttab_tc0_063 (__INTTAB_CPU0 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_99 )); } + .inttab_tc0_064 (__INTTAB_CPU0 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_100)); } + .inttab_tc0_065 (__INTTAB_CPU0 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_101)); } + .inttab_tc0_066 (__INTTAB_CPU0 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_102)); } + .inttab_tc0_067 (__INTTAB_CPU0 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_103)); } + .inttab_tc0_068 (__INTTAB_CPU0 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_104)); } + .inttab_tc0_069 (__INTTAB_CPU0 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_105)); } + .inttab_tc0_06A (__INTTAB_CPU0 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_106)); } + .inttab_tc0_06B (__INTTAB_CPU0 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_107)); } + .inttab_tc0_06C (__INTTAB_CPU0 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_108)); } + .inttab_tc0_06D (__INTTAB_CPU0 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_109)); } + .inttab_tc0_06E (__INTTAB_CPU0 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_110)); } + .inttab_tc0_06F (__INTTAB_CPU0 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_111)); } + .inttab_tc0_070 (__INTTAB_CPU0 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_112)); } + .inttab_tc0_071 (__INTTAB_CPU0 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_113)); } + .inttab_tc0_072 (__INTTAB_CPU0 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_114)); } + .inttab_tc0_073 (__INTTAB_CPU0 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_115)); } + .inttab_tc0_074 (__INTTAB_CPU0 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_116)); } + .inttab_tc0_075 (__INTTAB_CPU0 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_117)); } + .inttab_tc0_076 (__INTTAB_CPU0 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_118)); } + .inttab_tc0_077 (__INTTAB_CPU0 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_119)); } + .inttab_tc0_078 (__INTTAB_CPU0 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_120)); } + .inttab_tc0_079 (__INTTAB_CPU0 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_121)); } + .inttab_tc0_07A (__INTTAB_CPU0 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_122)); } + .inttab_tc0_07B (__INTTAB_CPU0 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_123)); } + .inttab_tc0_07C (__INTTAB_CPU0 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_124)); } + .inttab_tc0_07D (__INTTAB_CPU0 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_125)); } + .inttab_tc0_07E (__INTTAB_CPU0 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_126)); } + .inttab_tc0_07F (__INTTAB_CPU0 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_127)); } + .inttab_tc0_080 (__INTTAB_CPU0 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_128)); } + .inttab_tc0_081 (__INTTAB_CPU0 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_129)); } + .inttab_tc0_082 (__INTTAB_CPU0 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_130)); } + .inttab_tc0_083 (__INTTAB_CPU0 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_131)); } + .inttab_tc0_084 (__INTTAB_CPU0 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_132)); } + .inttab_tc0_085 (__INTTAB_CPU0 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_133)); } + .inttab_tc0_086 (__INTTAB_CPU0 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_134)); } + .inttab_tc0_087 (__INTTAB_CPU0 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_135)); } + .inttab_tc0_088 (__INTTAB_CPU0 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_136)); } + .inttab_tc0_089 (__INTTAB_CPU0 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_137)); } + .inttab_tc0_08A (__INTTAB_CPU0 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_138)); } + .inttab_tc0_08B (__INTTAB_CPU0 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_139)); } + .inttab_tc0_08C (__INTTAB_CPU0 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_140)); } + .inttab_tc0_08D (__INTTAB_CPU0 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_141)); } + .inttab_tc0_08E (__INTTAB_CPU0 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_142)); } + .inttab_tc0_08F (__INTTAB_CPU0 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_143)); } + .inttab_tc0_090 (__INTTAB_CPU0 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_144)); } + .inttab_tc0_091 (__INTTAB_CPU0 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_145)); } + .inttab_tc0_092 (__INTTAB_CPU0 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_146)); } + .inttab_tc0_093 (__INTTAB_CPU0 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_147)); } + .inttab_tc0_094 (__INTTAB_CPU0 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_148)); } + .inttab_tc0_095 (__INTTAB_CPU0 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_149)); } + .inttab_tc0_096 (__INTTAB_CPU0 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_150)); } + .inttab_tc0_097 (__INTTAB_CPU0 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_151)); } + .inttab_tc0_098 (__INTTAB_CPU0 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_152)); } + .inttab_tc0_099 (__INTTAB_CPU0 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_153)); } + .inttab_tc0_09A (__INTTAB_CPU0 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_154)); } + .inttab_tc0_09B (__INTTAB_CPU0 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_155)); } + .inttab_tc0_09C (__INTTAB_CPU0 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_156)); } + .inttab_tc0_09D (__INTTAB_CPU0 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_157)); } + .inttab_tc0_09E (__INTTAB_CPU0 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_158)); } + .inttab_tc0_09F (__INTTAB_CPU0 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_159)); } + .inttab_tc0_0A0 (__INTTAB_CPU0 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_160)); } + .inttab_tc0_0A1 (__INTTAB_CPU0 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_161)); } + .inttab_tc0_0A2 (__INTTAB_CPU0 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_162)); } + .inttab_tc0_0A3 (__INTTAB_CPU0 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_163)); } + .inttab_tc0_0A4 (__INTTAB_CPU0 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_164)); } + .inttab_tc0_0A5 (__INTTAB_CPU0 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_165)); } + .inttab_tc0_0A6 (__INTTAB_CPU0 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_166)); } + .inttab_tc0_0A7 (__INTTAB_CPU0 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_167)); } + .inttab_tc0_0A8 (__INTTAB_CPU0 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_168)); } + .inttab_tc0_0A9 (__INTTAB_CPU0 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_169)); } + .inttab_tc0_0AA (__INTTAB_CPU0 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_170)); } + .inttab_tc0_0AB (__INTTAB_CPU0 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_171)); } + .inttab_tc0_0AC (__INTTAB_CPU0 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_172)); } + .inttab_tc0_0AD (__INTTAB_CPU0 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_173)); } + .inttab_tc0_0AE (__INTTAB_CPU0 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_174)); } + .inttab_tc0_0AF (__INTTAB_CPU0 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_175)); } + .inttab_tc0_0B0 (__INTTAB_CPU0 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_176)); } + .inttab_tc0_0B1 (__INTTAB_CPU0 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_177)); } + .inttab_tc0_0B2 (__INTTAB_CPU0 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_178)); } + .inttab_tc0_0B3 (__INTTAB_CPU0 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_179)); } + .inttab_tc0_0B4 (__INTTAB_CPU0 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_180)); } + .inttab_tc0_0B5 (__INTTAB_CPU0 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_181)); } + .inttab_tc0_0B6 (__INTTAB_CPU0 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_182)); } + .inttab_tc0_0B7 (__INTTAB_CPU0 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_183)); } + .inttab_tc0_0B8 (__INTTAB_CPU0 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_184)); } + .inttab_tc0_0B9 (__INTTAB_CPU0 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_185)); } + .inttab_tc0_0BA (__INTTAB_CPU0 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_186)); } + .inttab_tc0_0BB (__INTTAB_CPU0 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_187)); } + .inttab_tc0_0BC (__INTTAB_CPU0 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_188)); } + .inttab_tc0_0BD (__INTTAB_CPU0 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_189)); } + .inttab_tc0_0BE (__INTTAB_CPU0 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_190)); } + .inttab_tc0_0BF (__INTTAB_CPU0 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_191)); } + .inttab_tc0_0C0 (__INTTAB_CPU0 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_192)); } + .inttab_tc0_0C1 (__INTTAB_CPU0 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_193)); } + .inttab_tc0_0C2 (__INTTAB_CPU0 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_194)); } + .inttab_tc0_0C3 (__INTTAB_CPU0 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_195)); } + .inttab_tc0_0C4 (__INTTAB_CPU0 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_196)); } + .inttab_tc0_0C5 (__INTTAB_CPU0 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_197)); } + .inttab_tc0_0C6 (__INTTAB_CPU0 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_198)); } + .inttab_tc0_0C7 (__INTTAB_CPU0 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_199)); } + .inttab_tc0_0C8 (__INTTAB_CPU0 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_200)); } + .inttab_tc0_0C9 (__INTTAB_CPU0 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_201)); } + .inttab_tc0_0CA (__INTTAB_CPU0 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_202)); } + .inttab_tc0_0CB (__INTTAB_CPU0 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_203)); } + .inttab_tc0_0CC (__INTTAB_CPU0 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_204)); } + .inttab_tc0_0CD (__INTTAB_CPU0 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_205)); } + .inttab_tc0_0CE (__INTTAB_CPU0 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_206)); } + .inttab_tc0_0CF (__INTTAB_CPU0 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_207)); } + .inttab_tc0_0D0 (__INTTAB_CPU0 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_208)); } + .inttab_tc0_0D1 (__INTTAB_CPU0 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_209)); } + .inttab_tc0_0D2 (__INTTAB_CPU0 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_210)); } + .inttab_tc0_0D3 (__INTTAB_CPU0 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_211)); } + .inttab_tc0_0D4 (__INTTAB_CPU0 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_212)); } + .inttab_tc0_0D5 (__INTTAB_CPU0 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_213)); } + .inttab_tc0_0D6 (__INTTAB_CPU0 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_214)); } + .inttab_tc0_0D7 (__INTTAB_CPU0 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_215)); } + .inttab_tc0_0D8 (__INTTAB_CPU0 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_216)); } + .inttab_tc0_0D9 (__INTTAB_CPU0 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_217)); } + .inttab_tc0_0DA (__INTTAB_CPU0 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_218)); } + .inttab_tc0_0DB (__INTTAB_CPU0 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_219)); } + .inttab_tc0_0DC (__INTTAB_CPU0 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_220)); } + .inttab_tc0_0DD (__INTTAB_CPU0 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_221)); } + .inttab_tc0_0DE (__INTTAB_CPU0 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_222)); } + .inttab_tc0_0DF (__INTTAB_CPU0 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_223)); } + .inttab_tc0_0E0 (__INTTAB_CPU0 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_224)); } + .inttab_tc0_0E1 (__INTTAB_CPU0 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_225)); } + .inttab_tc0_0E2 (__INTTAB_CPU0 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_226)); } + .inttab_tc0_0E3 (__INTTAB_CPU0 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_227)); } + .inttab_tc0_0E4 (__INTTAB_CPU0 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_228)); } + .inttab_tc0_0E5 (__INTTAB_CPU0 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_229)); } + .inttab_tc0_0E6 (__INTTAB_CPU0 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_230)); } + .inttab_tc0_0E7 (__INTTAB_CPU0 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_231)); } + .inttab_tc0_0E8 (__INTTAB_CPU0 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_232)); } + .inttab_tc0_0E9 (__INTTAB_CPU0 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_233)); } + .inttab_tc0_0EA (__INTTAB_CPU0 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_234)); } + .inttab_tc0_0EB (__INTTAB_CPU0 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_235)); } + .inttab_tc0_0EC (__INTTAB_CPU0 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_236)); } + .inttab_tc0_0ED (__INTTAB_CPU0 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_237)); } + .inttab_tc0_0EE (__INTTAB_CPU0 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_238)); } + .inttab_tc0_0EF (__INTTAB_CPU0 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_239)); } + .inttab_tc0_0F0 (__INTTAB_CPU0 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_240)); } + .inttab_tc0_0F1 (__INTTAB_CPU0 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_241)); } + .inttab_tc0_0F2 (__INTTAB_CPU0 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_242)); } + .inttab_tc0_0F3 (__INTTAB_CPU0 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_243)); } + .inttab_tc0_0F4 (__INTTAB_CPU0 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_244)); } + .inttab_tc0_0F5 (__INTTAB_CPU0 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_245)); } + .inttab_tc0_0F6 (__INTTAB_CPU0 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_246)); } + .inttab_tc0_0F7 (__INTTAB_CPU0 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_247)); } + .inttab_tc0_0F8 (__INTTAB_CPU0 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_248)); } + .inttab_tc0_0F9 (__INTTAB_CPU0 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_249)); } + .inttab_tc0_0FA (__INTTAB_CPU0 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_250)); } + .inttab_tc0_0FB (__INTTAB_CPU0 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_251)); } + .inttab_tc0_0FC (__INTTAB_CPU0 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_252)); } + .inttab_tc0_0FD (__INTTAB_CPU0 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_253)); } + .inttab_tc0_0FE (__INTTAB_CPU0 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_254)); } + .inttab_tc0_0FF (__INTTAB_CPU0 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc0_255)); } + } + SECTIONS + { + /*CPU1 Interrupt Vector Table*/ + .inttab_tc1_000 (__INTTAB_CPU1 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_0 )); } + .inttab_tc1_001 (__INTTAB_CPU1 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_1 )); } + .inttab_tc1_002 (__INTTAB_CPU1 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_2 )); } + .inttab_tc1_003 (__INTTAB_CPU1 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_3 )); } + .inttab_tc1_004 (__INTTAB_CPU1 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_4 )); } + .inttab_tc1_005 (__INTTAB_CPU1 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_5 )); } + .inttab_tc1_006 (__INTTAB_CPU1 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_6 )); } + .inttab_tc1_007 (__INTTAB_CPU1 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_7 )); } + .inttab_tc1_008 (__INTTAB_CPU1 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_8 )); } + .inttab_tc1_009 (__INTTAB_CPU1 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_9 )); } + .inttab_tc1_00A (__INTTAB_CPU1 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_10 )); } + .inttab_tc1_00B (__INTTAB_CPU1 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_11 )); } + .inttab_tc1_00C (__INTTAB_CPU1 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_12 )); } + .inttab_tc1_00D (__INTTAB_CPU1 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_13 )); } + .inttab_tc1_00E (__INTTAB_CPU1 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_14 )); } + .inttab_tc1_00F (__INTTAB_CPU1 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_15 )); } + .inttab_tc1_010 (__INTTAB_CPU1 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_16 )); } + .inttab_tc1_011 (__INTTAB_CPU1 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_17 )); } + .inttab_tc1_012 (__INTTAB_CPU1 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_18 )); } + .inttab_tc1_013 (__INTTAB_CPU1 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_19 )); } + .inttab_tc1_014 (__INTTAB_CPU1 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_20 )); } + .inttab_tc1_015 (__INTTAB_CPU1 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_21 )); } + .inttab_tc1_016 (__INTTAB_CPU1 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_22 )); } + .inttab_tc1_017 (__INTTAB_CPU1 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_23 )); } + .inttab_tc1_018 (__INTTAB_CPU1 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_24 )); } + .inttab_tc1_019 (__INTTAB_CPU1 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_25 )); } + .inttab_tc1_01A (__INTTAB_CPU1 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_26 )); } + .inttab_tc1_01B (__INTTAB_CPU1 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_27 )); } + .inttab_tc1_01C (__INTTAB_CPU1 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_28 )); } + .inttab_tc1_01D (__INTTAB_CPU1 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_29 )); } + .inttab_tc1_01E (__INTTAB_CPU1 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_30 )); } + .inttab_tc1_01F (__INTTAB_CPU1 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_31 )); } + .inttab_tc1_020 (__INTTAB_CPU1 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_32 )); } + .inttab_tc1_021 (__INTTAB_CPU1 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_33 )); } + .inttab_tc1_022 (__INTTAB_CPU1 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_34 )); } + .inttab_tc1_023 (__INTTAB_CPU1 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_35 )); } + .inttab_tc1_024 (__INTTAB_CPU1 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_36 )); } + .inttab_tc1_025 (__INTTAB_CPU1 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_37 )); } + .inttab_tc1_026 (__INTTAB_CPU1 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_38 )); } + .inttab_tc1_027 (__INTTAB_CPU1 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_39 )); } + .inttab_tc1_028 (__INTTAB_CPU1 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_40 )); } + .inttab_tc1_029 (__INTTAB_CPU1 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_41 )); } + .inttab_tc1_02A (__INTTAB_CPU1 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_42 )); } + .inttab_tc1_02B (__INTTAB_CPU1 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_43 )); } + .inttab_tc1_02C (__INTTAB_CPU1 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_44 )); } + .inttab_tc1_02D (__INTTAB_CPU1 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_45 )); } + .inttab_tc1_02E (__INTTAB_CPU1 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_46 )); } + .inttab_tc1_02F (__INTTAB_CPU1 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_47 )); } + .inttab_tc1_030 (__INTTAB_CPU1 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_48 )); } + .inttab_tc1_031 (__INTTAB_CPU1 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_49 )); } + .inttab_tc1_032 (__INTTAB_CPU1 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_50 )); } + .inttab_tc1_033 (__INTTAB_CPU1 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_51 )); } + .inttab_tc1_034 (__INTTAB_CPU1 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_52 )); } + .inttab_tc1_035 (__INTTAB_CPU1 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_53 )); } + .inttab_tc1_036 (__INTTAB_CPU1 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_54 )); } + .inttab_tc1_037 (__INTTAB_CPU1 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_55 )); } + .inttab_tc1_038 (__INTTAB_CPU1 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_56 )); } + .inttab_tc1_039 (__INTTAB_CPU1 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_57 )); } + .inttab_tc1_03A (__INTTAB_CPU1 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_58 )); } + .inttab_tc1_03B (__INTTAB_CPU1 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_59 )); } + .inttab_tc1_03C (__INTTAB_CPU1 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_60 )); } + .inttab_tc1_03D (__INTTAB_CPU1 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_61 )); } + .inttab_tc1_03E (__INTTAB_CPU1 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_62 )); } + .inttab_tc1_03F (__INTTAB_CPU1 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_63 )); } + .inttab_tc1_040 (__INTTAB_CPU1 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_64 )); } + .inttab_tc1_041 (__INTTAB_CPU1 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_65 )); } + .inttab_tc1_042 (__INTTAB_CPU1 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_66 )); } + .inttab_tc1_043 (__INTTAB_CPU1 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_67 )); } + .inttab_tc1_044 (__INTTAB_CPU1 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_68 )); } + .inttab_tc1_045 (__INTTAB_CPU1 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_69 )); } + .inttab_tc1_046 (__INTTAB_CPU1 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_70 )); } + .inttab_tc1_047 (__INTTAB_CPU1 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_71 )); } + .inttab_tc1_048 (__INTTAB_CPU1 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_72 )); } + .inttab_tc1_049 (__INTTAB_CPU1 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_73 )); } + .inttab_tc1_04A (__INTTAB_CPU1 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_74 )); } + .inttab_tc1_04B (__INTTAB_CPU1 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_75 )); } + .inttab_tc1_04C (__INTTAB_CPU1 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_76 )); } + .inttab_tc1_04D (__INTTAB_CPU1 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_77 )); } + .inttab_tc1_04E (__INTTAB_CPU1 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_78 )); } + .inttab_tc1_04F (__INTTAB_CPU1 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_79 )); } + .inttab_tc1_050 (__INTTAB_CPU1 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_80 )); } + .inttab_tc1_051 (__INTTAB_CPU1 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_81 )); } + .inttab_tc1_052 (__INTTAB_CPU1 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_82 )); } + .inttab_tc1_053 (__INTTAB_CPU1 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_83 )); } + .inttab_tc1_054 (__INTTAB_CPU1 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_84 )); } + .inttab_tc1_055 (__INTTAB_CPU1 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_85 )); } + .inttab_tc1_056 (__INTTAB_CPU1 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_86 )); } + .inttab_tc1_057 (__INTTAB_CPU1 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_87 )); } + .inttab_tc1_058 (__INTTAB_CPU1 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_88 )); } + .inttab_tc1_059 (__INTTAB_CPU1 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_89 )); } + .inttab_tc1_05A (__INTTAB_CPU1 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_90 )); } + .inttab_tc1_05B (__INTTAB_CPU1 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_91 )); } + .inttab_tc1_05C (__INTTAB_CPU1 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_92 )); } + .inttab_tc1_05D (__INTTAB_CPU1 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_93 )); } + .inttab_tc1_05E (__INTTAB_CPU1 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_94 )); } + .inttab_tc1_05F (__INTTAB_CPU1 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_95 )); } + .inttab_tc1_060 (__INTTAB_CPU1 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_96 )); } + .inttab_tc1_061 (__INTTAB_CPU1 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_97 )); } + .inttab_tc1_062 (__INTTAB_CPU1 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_98 )); } + .inttab_tc1_063 (__INTTAB_CPU1 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_99 )); } + .inttab_tc1_064 (__INTTAB_CPU1 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_100)); } + .inttab_tc1_065 (__INTTAB_CPU1 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_101)); } + .inttab_tc1_066 (__INTTAB_CPU1 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_102)); } + .inttab_tc1_067 (__INTTAB_CPU1 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_103)); } + .inttab_tc1_068 (__INTTAB_CPU1 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_104)); } + .inttab_tc1_069 (__INTTAB_CPU1 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_105)); } + .inttab_tc1_06A (__INTTAB_CPU1 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_106)); } + .inttab_tc1_06B (__INTTAB_CPU1 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_107)); } + .inttab_tc1_06C (__INTTAB_CPU1 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_108)); } + .inttab_tc1_06D (__INTTAB_CPU1 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_109)); } + .inttab_tc1_06E (__INTTAB_CPU1 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_110)); } + .inttab_tc1_06F (__INTTAB_CPU1 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_111)); } + .inttab_tc1_070 (__INTTAB_CPU1 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_112)); } + .inttab_tc1_071 (__INTTAB_CPU1 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_113)); } + .inttab_tc1_072 (__INTTAB_CPU1 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_114)); } + .inttab_tc1_073 (__INTTAB_CPU1 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_115)); } + .inttab_tc1_074 (__INTTAB_CPU1 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_116)); } + .inttab_tc1_075 (__INTTAB_CPU1 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_117)); } + .inttab_tc1_076 (__INTTAB_CPU1 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_118)); } + .inttab_tc1_077 (__INTTAB_CPU1 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_119)); } + .inttab_tc1_078 (__INTTAB_CPU1 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_120)); } + .inttab_tc1_079 (__INTTAB_CPU1 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_121)); } + .inttab_tc1_07A (__INTTAB_CPU1 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_122)); } + .inttab_tc1_07B (__INTTAB_CPU1 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_123)); } + .inttab_tc1_07C (__INTTAB_CPU1 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_124)); } + .inttab_tc1_07D (__INTTAB_CPU1 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_125)); } + .inttab_tc1_07E (__INTTAB_CPU1 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_126)); } + .inttab_tc1_07F (__INTTAB_CPU1 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_127)); } + .inttab_tc1_080 (__INTTAB_CPU1 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_128)); } + .inttab_tc1_081 (__INTTAB_CPU1 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_129)); } + .inttab_tc1_082 (__INTTAB_CPU1 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_130)); } + .inttab_tc1_083 (__INTTAB_CPU1 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_131)); } + .inttab_tc1_084 (__INTTAB_CPU1 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_132)); } + .inttab_tc1_085 (__INTTAB_CPU1 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_133)); } + .inttab_tc1_086 (__INTTAB_CPU1 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_134)); } + .inttab_tc1_087 (__INTTAB_CPU1 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_135)); } + .inttab_tc1_088 (__INTTAB_CPU1 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_136)); } + .inttab_tc1_089 (__INTTAB_CPU1 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_137)); } + .inttab_tc1_08A (__INTTAB_CPU1 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_138)); } + .inttab_tc1_08B (__INTTAB_CPU1 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_139)); } + .inttab_tc1_08C (__INTTAB_CPU1 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_140)); } + .inttab_tc1_08D (__INTTAB_CPU1 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_141)); } + .inttab_tc1_08E (__INTTAB_CPU1 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_142)); } + .inttab_tc1_08F (__INTTAB_CPU1 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_143)); } + .inttab_tc1_090 (__INTTAB_CPU1 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_144)); } + .inttab_tc1_091 (__INTTAB_CPU1 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_145)); } + .inttab_tc1_092 (__INTTAB_CPU1 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_146)); } + .inttab_tc1_093 (__INTTAB_CPU1 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_147)); } + .inttab_tc1_094 (__INTTAB_CPU1 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_148)); } + .inttab_tc1_095 (__INTTAB_CPU1 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_149)); } + .inttab_tc1_096 (__INTTAB_CPU1 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_150)); } + .inttab_tc1_097 (__INTTAB_CPU1 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_151)); } + .inttab_tc1_098 (__INTTAB_CPU1 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_152)); } + .inttab_tc1_099 (__INTTAB_CPU1 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_153)); } + .inttab_tc1_09A (__INTTAB_CPU1 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_154)); } + .inttab_tc1_09B (__INTTAB_CPU1 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_155)); } + .inttab_tc1_09C (__INTTAB_CPU1 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_156)); } + .inttab_tc1_09D (__INTTAB_CPU1 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_157)); } + .inttab_tc1_09E (__INTTAB_CPU1 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_158)); } + .inttab_tc1_09F (__INTTAB_CPU1 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_159)); } + .inttab_tc1_0A0 (__INTTAB_CPU1 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_160)); } + .inttab_tc1_0A1 (__INTTAB_CPU1 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_161)); } + .inttab_tc1_0A2 (__INTTAB_CPU1 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_162)); } + .inttab_tc1_0A3 (__INTTAB_CPU1 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_163)); } + .inttab_tc1_0A4 (__INTTAB_CPU1 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_164)); } + .inttab_tc1_0A5 (__INTTAB_CPU1 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_165)); } + .inttab_tc1_0A6 (__INTTAB_CPU1 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_166)); } + .inttab_tc1_0A7 (__INTTAB_CPU1 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_167)); } + .inttab_tc1_0A8 (__INTTAB_CPU1 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_168)); } + .inttab_tc1_0A9 (__INTTAB_CPU1 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_169)); } + .inttab_tc1_0AA (__INTTAB_CPU1 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_170)); } + .inttab_tc1_0AB (__INTTAB_CPU1 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_171)); } + .inttab_tc1_0AC (__INTTAB_CPU1 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_172)); } + .inttab_tc1_0AD (__INTTAB_CPU1 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_173)); } + .inttab_tc1_0AE (__INTTAB_CPU1 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_174)); } + .inttab_tc1_0AF (__INTTAB_CPU1 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_175)); } + .inttab_tc1_0B0 (__INTTAB_CPU1 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_176)); } + .inttab_tc1_0B1 (__INTTAB_CPU1 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_177)); } + .inttab_tc1_0B2 (__INTTAB_CPU1 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_178)); } + .inttab_tc1_0B3 (__INTTAB_CPU1 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_179)); } + .inttab_tc1_0B4 (__INTTAB_CPU1 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_180)); } + .inttab_tc1_0B5 (__INTTAB_CPU1 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_181)); } + .inttab_tc1_0B6 (__INTTAB_CPU1 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_182)); } + .inttab_tc1_0B7 (__INTTAB_CPU1 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_183)); } + .inttab_tc1_0B8 (__INTTAB_CPU1 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_184)); } + .inttab_tc1_0B9 (__INTTAB_CPU1 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_185)); } + .inttab_tc1_0BA (__INTTAB_CPU1 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_186)); } + .inttab_tc1_0BB (__INTTAB_CPU1 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_187)); } + .inttab_tc1_0BC (__INTTAB_CPU1 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_188)); } + .inttab_tc1_0BD (__INTTAB_CPU1 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_189)); } + .inttab_tc1_0BE (__INTTAB_CPU1 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_190)); } + .inttab_tc1_0BF (__INTTAB_CPU1 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_191)); } + .inttab_tc1_0C0 (__INTTAB_CPU1 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_192)); } + .inttab_tc1_0C1 (__INTTAB_CPU1 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_193)); } + .inttab_tc1_0C2 (__INTTAB_CPU1 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_194)); } + .inttab_tc1_0C3 (__INTTAB_CPU1 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_195)); } + .inttab_tc1_0C4 (__INTTAB_CPU1 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_196)); } + .inttab_tc1_0C5 (__INTTAB_CPU1 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_197)); } + .inttab_tc1_0C6 (__INTTAB_CPU1 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_198)); } + .inttab_tc1_0C7 (__INTTAB_CPU1 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_199)); } + .inttab_tc1_0C8 (__INTTAB_CPU1 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_200)); } + .inttab_tc1_0C9 (__INTTAB_CPU1 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_201)); } + .inttab_tc1_0CA (__INTTAB_CPU1 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_202)); } + .inttab_tc1_0CB (__INTTAB_CPU1 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_203)); } + .inttab_tc1_0CC (__INTTAB_CPU1 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_204)); } + .inttab_tc1_0CD (__INTTAB_CPU1 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_205)); } + .inttab_tc1_0CE (__INTTAB_CPU1 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_206)); } + .inttab_tc1_0CF (__INTTAB_CPU1 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_207)); } + .inttab_tc1_0D0 (__INTTAB_CPU1 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_208)); } + .inttab_tc1_0D1 (__INTTAB_CPU1 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_209)); } + .inttab_tc1_0D2 (__INTTAB_CPU1 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_210)); } + .inttab_tc1_0D3 (__INTTAB_CPU1 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_211)); } + .inttab_tc1_0D4 (__INTTAB_CPU1 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_212)); } + .inttab_tc1_0D5 (__INTTAB_CPU1 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_213)); } + .inttab_tc1_0D6 (__INTTAB_CPU1 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_214)); } + .inttab_tc1_0D7 (__INTTAB_CPU1 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_215)); } + .inttab_tc1_0D8 (__INTTAB_CPU1 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_216)); } + .inttab_tc1_0D9 (__INTTAB_CPU1 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_217)); } + .inttab_tc1_0DA (__INTTAB_CPU1 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_218)); } + .inttab_tc1_0DB (__INTTAB_CPU1 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_219)); } + .inttab_tc1_0DC (__INTTAB_CPU1 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_220)); } + .inttab_tc1_0DD (__INTTAB_CPU1 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_221)); } + .inttab_tc1_0DE (__INTTAB_CPU1 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_222)); } + .inttab_tc1_0DF (__INTTAB_CPU1 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_223)); } + .inttab_tc1_0E0 (__INTTAB_CPU1 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_224)); } + .inttab_tc1_0E1 (__INTTAB_CPU1 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_225)); } + .inttab_tc1_0E2 (__INTTAB_CPU1 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_226)); } + .inttab_tc1_0E3 (__INTTAB_CPU1 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_227)); } + .inttab_tc1_0E4 (__INTTAB_CPU1 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_228)); } + .inttab_tc1_0E5 (__INTTAB_CPU1 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_229)); } + .inttab_tc1_0E6 (__INTTAB_CPU1 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_230)); } + .inttab_tc1_0E7 (__INTTAB_CPU1 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_231)); } + .inttab_tc1_0E8 (__INTTAB_CPU1 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_232)); } + .inttab_tc1_0E9 (__INTTAB_CPU1 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_233)); } + .inttab_tc1_0EA (__INTTAB_CPU1 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_234)); } + .inttab_tc1_0EB (__INTTAB_CPU1 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_235)); } + .inttab_tc1_0EC (__INTTAB_CPU1 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_236)); } + .inttab_tc1_0ED (__INTTAB_CPU1 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_237)); } + .inttab_tc1_0EE (__INTTAB_CPU1 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_238)); } + .inttab_tc1_0EF (__INTTAB_CPU1 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_239)); } + .inttab_tc1_0F0 (__INTTAB_CPU1 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_240)); } + .inttab_tc1_0F1 (__INTTAB_CPU1 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_241)); } + .inttab_tc1_0F2 (__INTTAB_CPU1 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_242)); } + .inttab_tc1_0F3 (__INTTAB_CPU1 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_243)); } + .inttab_tc1_0F4 (__INTTAB_CPU1 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_244)); } + .inttab_tc1_0F5 (__INTTAB_CPU1 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_245)); } + .inttab_tc1_0F6 (__INTTAB_CPU1 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_246)); } + .inttab_tc1_0F7 (__INTTAB_CPU1 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_247)); } + .inttab_tc1_0F8 (__INTTAB_CPU1 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_248)); } + .inttab_tc1_0F9 (__INTTAB_CPU1 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_249)); } + .inttab_tc1_0FA (__INTTAB_CPU1 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_250)); } + .inttab_tc1_0FB (__INTTAB_CPU1 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_251)); } + .inttab_tc1_0FC (__INTTAB_CPU1 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_252)); } + .inttab_tc1_0FD (__INTTAB_CPU1 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_253)); } + .inttab_tc1_0FE (__INTTAB_CPU1 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_254)); } + .inttab_tc1_0FF (__INTTAB_CPU1 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc1_255)); } + } + SECTIONS + { + /*CPU2 Interrupt Vector Table*/ + .inttab_tc2_000 (__INTTAB_CPU2 + 0x0000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_0 )); } + .inttab_tc2_001 (__INTTAB_CPU2 + 0x0020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_1 )); } + .inttab_tc2_002 (__INTTAB_CPU2 + 0x0040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_2 )); } + .inttab_tc2_003 (__INTTAB_CPU2 + 0x0060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_3 )); } + .inttab_tc2_004 (__INTTAB_CPU2 + 0x0080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_4 )); } + .inttab_tc2_005 (__INTTAB_CPU2 + 0x00A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_5 )); } + .inttab_tc2_006 (__INTTAB_CPU2 + 0x00C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_6 )); } + .inttab_tc2_007 (__INTTAB_CPU2 + 0x00E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_7 )); } + .inttab_tc2_008 (__INTTAB_CPU2 + 0x0100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_8 )); } + .inttab_tc2_009 (__INTTAB_CPU2 + 0x0120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_9 )); } + .inttab_tc2_00A (__INTTAB_CPU2 + 0x0140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_10 )); } + .inttab_tc2_00B (__INTTAB_CPU2 + 0x0160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_11 )); } + .inttab_tc2_00C (__INTTAB_CPU2 + 0x0180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_12 )); } + .inttab_tc2_00D (__INTTAB_CPU2 + 0x01A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_13 )); } + .inttab_tc2_00E (__INTTAB_CPU2 + 0x01C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_14 )); } + .inttab_tc2_00F (__INTTAB_CPU2 + 0x01E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_15 )); } + .inttab_tc2_010 (__INTTAB_CPU2 + 0x0200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_16 )); } + .inttab_tc2_011 (__INTTAB_CPU2 + 0x0220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_17 )); } + .inttab_tc2_012 (__INTTAB_CPU2 + 0x0240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_18 )); } + .inttab_tc2_013 (__INTTAB_CPU2 + 0x0260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_19 )); } + .inttab_tc2_014 (__INTTAB_CPU2 + 0x0280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_20 )); } + .inttab_tc2_015 (__INTTAB_CPU2 + 0x02A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_21 )); } + .inttab_tc2_016 (__INTTAB_CPU2 + 0x02C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_22 )); } + .inttab_tc2_017 (__INTTAB_CPU2 + 0x02E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_23 )); } + .inttab_tc2_018 (__INTTAB_CPU2 + 0x0300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_24 )); } + .inttab_tc2_019 (__INTTAB_CPU2 + 0x0320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_25 )); } + .inttab_tc2_01A (__INTTAB_CPU2 + 0x0340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_26 )); } + .inttab_tc2_01B (__INTTAB_CPU2 + 0x0360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_27 )); } + .inttab_tc2_01C (__INTTAB_CPU2 + 0x0380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_28 )); } + .inttab_tc2_01D (__INTTAB_CPU2 + 0x03A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_29 )); } + .inttab_tc2_01E (__INTTAB_CPU2 + 0x03C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_30 )); } + .inttab_tc2_01F (__INTTAB_CPU2 + 0x03E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_31 )); } + .inttab_tc2_020 (__INTTAB_CPU2 + 0x0400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_32 )); } + .inttab_tc2_021 (__INTTAB_CPU2 + 0x0420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_33 )); } + .inttab_tc2_022 (__INTTAB_CPU2 + 0x0440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_34 )); } + .inttab_tc2_023 (__INTTAB_CPU2 + 0x0460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_35 )); } + .inttab_tc2_024 (__INTTAB_CPU2 + 0x0480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_36 )); } + .inttab_tc2_025 (__INTTAB_CPU2 + 0x04A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_37 )); } + .inttab_tc2_026 (__INTTAB_CPU2 + 0x04C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_38 )); } + .inttab_tc2_027 (__INTTAB_CPU2 + 0x04E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_39 )); } + .inttab_tc2_028 (__INTTAB_CPU2 + 0x0500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_40 )); } + .inttab_tc2_029 (__INTTAB_CPU2 + 0x0520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_41 )); } + .inttab_tc2_02A (__INTTAB_CPU2 + 0x0540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_42 )); } + .inttab_tc2_02B (__INTTAB_CPU2 + 0x0560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_43 )); } + .inttab_tc2_02C (__INTTAB_CPU2 + 0x0580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_44 )); } + .inttab_tc2_02D (__INTTAB_CPU2 + 0x05A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_45 )); } + .inttab_tc2_02E (__INTTAB_CPU2 + 0x05C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_46 )); } + .inttab_tc2_02F (__INTTAB_CPU2 + 0x05E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_47 )); } + .inttab_tc2_030 (__INTTAB_CPU2 + 0x0600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_48 )); } + .inttab_tc2_031 (__INTTAB_CPU2 + 0x0620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_49 )); } + .inttab_tc2_032 (__INTTAB_CPU2 + 0x0640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_50 )); } + .inttab_tc2_033 (__INTTAB_CPU2 + 0x0660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_51 )); } + .inttab_tc2_034 (__INTTAB_CPU2 + 0x0680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_52 )); } + .inttab_tc2_035 (__INTTAB_CPU2 + 0x06A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_53 )); } + .inttab_tc2_036 (__INTTAB_CPU2 + 0x06C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_54 )); } + .inttab_tc2_037 (__INTTAB_CPU2 + 0x06E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_55 )); } + .inttab_tc2_038 (__INTTAB_CPU2 + 0x0700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_56 )); } + .inttab_tc2_039 (__INTTAB_CPU2 + 0x0720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_57 )); } + .inttab_tc2_03A (__INTTAB_CPU2 + 0x0740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_58 )); } + .inttab_tc2_03B (__INTTAB_CPU2 + 0x0760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_59 )); } + .inttab_tc2_03C (__INTTAB_CPU2 + 0x0780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_60 )); } + .inttab_tc2_03D (__INTTAB_CPU2 + 0x07A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_61 )); } + .inttab_tc2_03E (__INTTAB_CPU2 + 0x07C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_62 )); } + .inttab_tc2_03F (__INTTAB_CPU2 + 0x07E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_63 )); } + .inttab_tc2_040 (__INTTAB_CPU2 + 0x0800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_64 )); } + .inttab_tc2_041 (__INTTAB_CPU2 + 0x0820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_65 )); } + .inttab_tc2_042 (__INTTAB_CPU2 + 0x0840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_66 )); } + .inttab_tc2_043 (__INTTAB_CPU2 + 0x0860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_67 )); } + .inttab_tc2_044 (__INTTAB_CPU2 + 0x0880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_68 )); } + .inttab_tc2_045 (__INTTAB_CPU2 + 0x08A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_69 )); } + .inttab_tc2_046 (__INTTAB_CPU2 + 0x08C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_70 )); } + .inttab_tc2_047 (__INTTAB_CPU2 + 0x08E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_71 )); } + .inttab_tc2_048 (__INTTAB_CPU2 + 0x0900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_72 )); } + .inttab_tc2_049 (__INTTAB_CPU2 + 0x0920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_73 )); } + .inttab_tc2_04A (__INTTAB_CPU2 + 0x0940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_74 )); } + .inttab_tc2_04B (__INTTAB_CPU2 + 0x0960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_75 )); } + .inttab_tc2_04C (__INTTAB_CPU2 + 0x0980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_76 )); } + .inttab_tc2_04D (__INTTAB_CPU2 + 0x09A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_77 )); } + .inttab_tc2_04E (__INTTAB_CPU2 + 0x09C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_78 )); } + .inttab_tc2_04F (__INTTAB_CPU2 + 0x09E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_79 )); } + .inttab_tc2_050 (__INTTAB_CPU2 + 0x0A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_80 )); } + .inttab_tc2_051 (__INTTAB_CPU2 + 0x0A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_81 )); } + .inttab_tc2_052 (__INTTAB_CPU2 + 0x0A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_82 )); } + .inttab_tc2_053 (__INTTAB_CPU2 + 0x0A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_83 )); } + .inttab_tc2_054 (__INTTAB_CPU2 + 0x0A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_84 )); } + .inttab_tc2_055 (__INTTAB_CPU2 + 0x0AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_85 )); } + .inttab_tc2_056 (__INTTAB_CPU2 + 0x0AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_86 )); } + .inttab_tc2_057 (__INTTAB_CPU2 + 0x0AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_87 )); } + .inttab_tc2_058 (__INTTAB_CPU2 + 0x0B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_88 )); } + .inttab_tc2_059 (__INTTAB_CPU2 + 0x0B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_89 )); } + .inttab_tc2_05A (__INTTAB_CPU2 + 0x0B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_90 )); } + .inttab_tc2_05B (__INTTAB_CPU2 + 0x0B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_91 )); } + .inttab_tc2_05C (__INTTAB_CPU2 + 0x0B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_92 )); } + .inttab_tc2_05D (__INTTAB_CPU2 + 0x0BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_93 )); } + .inttab_tc2_05E (__INTTAB_CPU2 + 0x0BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_94 )); } + .inttab_tc2_05F (__INTTAB_CPU2 + 0x0BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_95 )); } + .inttab_tc2_060 (__INTTAB_CPU2 + 0x0C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_96 )); } + .inttab_tc2_061 (__INTTAB_CPU2 + 0x0C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_97 )); } + .inttab_tc2_062 (__INTTAB_CPU2 + 0x0C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_98 )); } + .inttab_tc2_063 (__INTTAB_CPU2 + 0x0C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_99 )); } + .inttab_tc2_064 (__INTTAB_CPU2 + 0x0C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_100)); } + .inttab_tc2_065 (__INTTAB_CPU2 + 0x0CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_101)); } + .inttab_tc2_066 (__INTTAB_CPU2 + 0x0CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_102)); } + .inttab_tc2_067 (__INTTAB_CPU2 + 0x0CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_103)); } + .inttab_tc2_068 (__INTTAB_CPU2 + 0x0D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_104)); } + .inttab_tc2_069 (__INTTAB_CPU2 + 0x0D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_105)); } + .inttab_tc2_06A (__INTTAB_CPU2 + 0x0D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_106)); } + .inttab_tc2_06B (__INTTAB_CPU2 + 0x0D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_107)); } + .inttab_tc2_06C (__INTTAB_CPU2 + 0x0D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_108)); } + .inttab_tc2_06D (__INTTAB_CPU2 + 0x0DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_109)); } + .inttab_tc2_06E (__INTTAB_CPU2 + 0x0DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_110)); } + .inttab_tc2_06F (__INTTAB_CPU2 + 0x0DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_111)); } + .inttab_tc2_070 (__INTTAB_CPU2 + 0x0E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_112)); } + .inttab_tc2_071 (__INTTAB_CPU2 + 0x0E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_113)); } + .inttab_tc2_072 (__INTTAB_CPU2 + 0x0E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_114)); } + .inttab_tc2_073 (__INTTAB_CPU2 + 0x0E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_115)); } + .inttab_tc2_074 (__INTTAB_CPU2 + 0x0E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_116)); } + .inttab_tc2_075 (__INTTAB_CPU2 + 0x0EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_117)); } + .inttab_tc2_076 (__INTTAB_CPU2 + 0x0EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_118)); } + .inttab_tc2_077 (__INTTAB_CPU2 + 0x0EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_119)); } + .inttab_tc2_078 (__INTTAB_CPU2 + 0x0F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_120)); } + .inttab_tc2_079 (__INTTAB_CPU2 + 0x0F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_121)); } + .inttab_tc2_07A (__INTTAB_CPU2 + 0x0F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_122)); } + .inttab_tc2_07B (__INTTAB_CPU2 + 0x0F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_123)); } + .inttab_tc2_07C (__INTTAB_CPU2 + 0x0F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_124)); } + .inttab_tc2_07D (__INTTAB_CPU2 + 0x0FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_125)); } + .inttab_tc2_07E (__INTTAB_CPU2 + 0x0FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_126)); } + .inttab_tc2_07F (__INTTAB_CPU2 + 0x0FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_127)); } + .inttab_tc2_080 (__INTTAB_CPU2 + 0x1000) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_128)); } + .inttab_tc2_081 (__INTTAB_CPU2 + 0x1020) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_129)); } + .inttab_tc2_082 (__INTTAB_CPU2 + 0x1040) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_130)); } + .inttab_tc2_083 (__INTTAB_CPU2 + 0x1060) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_131)); } + .inttab_tc2_084 (__INTTAB_CPU2 + 0x1080) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_132)); } + .inttab_tc2_085 (__INTTAB_CPU2 + 0x10A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_133)); } + .inttab_tc2_086 (__INTTAB_CPU2 + 0x10C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_134)); } + .inttab_tc2_087 (__INTTAB_CPU2 + 0x10E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_135)); } + .inttab_tc2_088 (__INTTAB_CPU2 + 0x1100) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_136)); } + .inttab_tc2_089 (__INTTAB_CPU2 + 0x1120) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_137)); } + .inttab_tc2_08A (__INTTAB_CPU2 + 0x1140) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_138)); } + .inttab_tc2_08B (__INTTAB_CPU2 + 0x1160) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_139)); } + .inttab_tc2_08C (__INTTAB_CPU2 + 0x1180) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_140)); } + .inttab_tc2_08D (__INTTAB_CPU2 + 0x11A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_141)); } + .inttab_tc2_08E (__INTTAB_CPU2 + 0x11C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_142)); } + .inttab_tc2_08F (__INTTAB_CPU2 + 0x11E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_143)); } + .inttab_tc2_090 (__INTTAB_CPU2 + 0x1200) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_144)); } + .inttab_tc2_091 (__INTTAB_CPU2 + 0x1220) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_145)); } + .inttab_tc2_092 (__INTTAB_CPU2 + 0x1240) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_146)); } + .inttab_tc2_093 (__INTTAB_CPU2 + 0x1260) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_147)); } + .inttab_tc2_094 (__INTTAB_CPU2 + 0x1280) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_148)); } + .inttab_tc2_095 (__INTTAB_CPU2 + 0x12A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_149)); } + .inttab_tc2_096 (__INTTAB_CPU2 + 0x12C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_150)); } + .inttab_tc2_097 (__INTTAB_CPU2 + 0x12E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_151)); } + .inttab_tc2_098 (__INTTAB_CPU2 + 0x1300) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_152)); } + .inttab_tc2_099 (__INTTAB_CPU2 + 0x1320) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_153)); } + .inttab_tc2_09A (__INTTAB_CPU2 + 0x1340) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_154)); } + .inttab_tc2_09B (__INTTAB_CPU2 + 0x1360) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_155)); } + .inttab_tc2_09C (__INTTAB_CPU2 + 0x1380) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_156)); } + .inttab_tc2_09D (__INTTAB_CPU2 + 0x13A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_157)); } + .inttab_tc2_09E (__INTTAB_CPU2 + 0x13C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_158)); } + .inttab_tc2_09F (__INTTAB_CPU2 + 0x13E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_159)); } + .inttab_tc2_0A0 (__INTTAB_CPU2 + 0x1400) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_160)); } + .inttab_tc2_0A1 (__INTTAB_CPU2 + 0x1420) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_161)); } + .inttab_tc2_0A2 (__INTTAB_CPU2 + 0x1440) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_162)); } + .inttab_tc2_0A3 (__INTTAB_CPU2 + 0x1460) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_163)); } + .inttab_tc2_0A4 (__INTTAB_CPU2 + 0x1480) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_164)); } + .inttab_tc2_0A5 (__INTTAB_CPU2 + 0x14A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_165)); } + .inttab_tc2_0A6 (__INTTAB_CPU2 + 0x14C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_166)); } + .inttab_tc2_0A7 (__INTTAB_CPU2 + 0x14E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_167)); } + .inttab_tc2_0A8 (__INTTAB_CPU2 + 0x1500) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_168)); } + .inttab_tc2_0A9 (__INTTAB_CPU2 + 0x1520) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_169)); } + .inttab_tc2_0AA (__INTTAB_CPU2 + 0x1540) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_170)); } + .inttab_tc2_0AB (__INTTAB_CPU2 + 0x1560) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_171)); } + .inttab_tc2_0AC (__INTTAB_CPU2 + 0x1580) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_172)); } + .inttab_tc2_0AD (__INTTAB_CPU2 + 0x15A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_173)); } + .inttab_tc2_0AE (__INTTAB_CPU2 + 0x15C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_174)); } + .inttab_tc2_0AF (__INTTAB_CPU2 + 0x15E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_175)); } + .inttab_tc2_0B0 (__INTTAB_CPU2 + 0x1600) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_176)); } + .inttab_tc2_0B1 (__INTTAB_CPU2 + 0x1620) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_177)); } + .inttab_tc2_0B2 (__INTTAB_CPU2 + 0x1640) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_178)); } + .inttab_tc2_0B3 (__INTTAB_CPU2 + 0x1660) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_179)); } + .inttab_tc2_0B4 (__INTTAB_CPU2 + 0x1680) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_180)); } + .inttab_tc2_0B5 (__INTTAB_CPU2 + 0x16A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_181)); } + .inttab_tc2_0B6 (__INTTAB_CPU2 + 0x16C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_182)); } + .inttab_tc2_0B7 (__INTTAB_CPU2 + 0x16E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_183)); } + .inttab_tc2_0B8 (__INTTAB_CPU2 + 0x1700) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_184)); } + .inttab_tc2_0B9 (__INTTAB_CPU2 + 0x1720) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_185)); } + .inttab_tc2_0BA (__INTTAB_CPU2 + 0x1740) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_186)); } + .inttab_tc2_0BB (__INTTAB_CPU2 + 0x1760) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_187)); } + .inttab_tc2_0BC (__INTTAB_CPU2 + 0x1780) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_188)); } + .inttab_tc2_0BD (__INTTAB_CPU2 + 0x17A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_189)); } + .inttab_tc2_0BE (__INTTAB_CPU2 + 0x17C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_190)); } + .inttab_tc2_0BF (__INTTAB_CPU2 + 0x17E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_191)); } + .inttab_tc2_0C0 (__INTTAB_CPU2 + 0x1800) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_192)); } + .inttab_tc2_0C1 (__INTTAB_CPU2 + 0x1820) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_193)); } + .inttab_tc2_0C2 (__INTTAB_CPU2 + 0x1840) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_194)); } + .inttab_tc2_0C3 (__INTTAB_CPU2 + 0x1860) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_195)); } + .inttab_tc2_0C4 (__INTTAB_CPU2 + 0x1880) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_196)); } + .inttab_tc2_0C5 (__INTTAB_CPU2 + 0x18A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_197)); } + .inttab_tc2_0C6 (__INTTAB_CPU2 + 0x18C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_198)); } + .inttab_tc2_0C7 (__INTTAB_CPU2 + 0x18E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_199)); } + .inttab_tc2_0C8 (__INTTAB_CPU2 + 0x1900) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_200)); } + .inttab_tc2_0C9 (__INTTAB_CPU2 + 0x1920) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_201)); } + .inttab_tc2_0CA (__INTTAB_CPU2 + 0x1940) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_202)); } + .inttab_tc2_0CB (__INTTAB_CPU2 + 0x1960) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_203)); } + .inttab_tc2_0CC (__INTTAB_CPU2 + 0x1980) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_204)); } + .inttab_tc2_0CD (__INTTAB_CPU2 + 0x19A0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_205)); } + .inttab_tc2_0CE (__INTTAB_CPU2 + 0x19C0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_206)); } + .inttab_tc2_0CF (__INTTAB_CPU2 + 0x19E0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_207)); } + .inttab_tc2_0D0 (__INTTAB_CPU2 + 0x1A00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_208)); } + .inttab_tc2_0D1 (__INTTAB_CPU2 + 0x1A20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_209)); } + .inttab_tc2_0D2 (__INTTAB_CPU2 + 0x1A40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_210)); } + .inttab_tc2_0D3 (__INTTAB_CPU2 + 0x1A60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_211)); } + .inttab_tc2_0D4 (__INTTAB_CPU2 + 0x1A80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_212)); } + .inttab_tc2_0D5 (__INTTAB_CPU2 + 0x1AA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_213)); } + .inttab_tc2_0D6 (__INTTAB_CPU2 + 0x1AC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_214)); } + .inttab_tc2_0D7 (__INTTAB_CPU2 + 0x1AE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_215)); } + .inttab_tc2_0D8 (__INTTAB_CPU2 + 0x1B00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_216)); } + .inttab_tc2_0D9 (__INTTAB_CPU2 + 0x1B20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_217)); } + .inttab_tc2_0DA (__INTTAB_CPU2 + 0x1B40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_218)); } + .inttab_tc2_0DB (__INTTAB_CPU2 + 0x1B60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_219)); } + .inttab_tc2_0DC (__INTTAB_CPU2 + 0x1B80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_220)); } + .inttab_tc2_0DD (__INTTAB_CPU2 + 0x1BA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_221)); } + .inttab_tc2_0DE (__INTTAB_CPU2 + 0x1BC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_222)); } + .inttab_tc2_0DF (__INTTAB_CPU2 + 0x1BE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_223)); } + .inttab_tc2_0E0 (__INTTAB_CPU2 + 0x1C00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_224)); } + .inttab_tc2_0E1 (__INTTAB_CPU2 + 0x1C20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_225)); } + .inttab_tc2_0E2 (__INTTAB_CPU2 + 0x1C40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_226)); } + .inttab_tc2_0E3 (__INTTAB_CPU2 + 0x1C60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_227)); } + .inttab_tc2_0E4 (__INTTAB_CPU2 + 0x1C80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_228)); } + .inttab_tc2_0E5 (__INTTAB_CPU2 + 0x1CA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_229)); } + .inttab_tc2_0E6 (__INTTAB_CPU2 + 0x1CC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_230)); } + .inttab_tc2_0E7 (__INTTAB_CPU2 + 0x1CE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_231)); } + .inttab_tc2_0E8 (__INTTAB_CPU2 + 0x1D00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_232)); } + .inttab_tc2_0E9 (__INTTAB_CPU2 + 0x1D20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_233)); } + .inttab_tc2_0EA (__INTTAB_CPU2 + 0x1D40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_234)); } + .inttab_tc2_0EB (__INTTAB_CPU2 + 0x1D60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_235)); } + .inttab_tc2_0EC (__INTTAB_CPU2 + 0x1D80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_236)); } + .inttab_tc2_0ED (__INTTAB_CPU2 + 0x1DA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_237)); } + .inttab_tc2_0EE (__INTTAB_CPU2 + 0x1DC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_238)); } + .inttab_tc2_0EF (__INTTAB_CPU2 + 0x1DE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_239)); } + .inttab_tc2_0F0 (__INTTAB_CPU2 + 0x1E00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_240)); } + .inttab_tc2_0F1 (__INTTAB_CPU2 + 0x1E20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_241)); } + .inttab_tc2_0F2 (__INTTAB_CPU2 + 0x1E40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_242)); } + .inttab_tc2_0F3 (__INTTAB_CPU2 + 0x1E60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_243)); } + .inttab_tc2_0F4 (__INTTAB_CPU2 + 0x1E80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_244)); } + .inttab_tc2_0F5 (__INTTAB_CPU2 + 0x1EA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_245)); } + .inttab_tc2_0F6 (__INTTAB_CPU2 + 0x1EC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_246)); } + .inttab_tc2_0F7 (__INTTAB_CPU2 + 0x1EE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_247)); } + .inttab_tc2_0F8 (__INTTAB_CPU2 + 0x1F00) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_248)); } + .inttab_tc2_0F9 (__INTTAB_CPU2 + 0x1F20) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_249)); } + .inttab_tc2_0FA (__INTTAB_CPU2 + 0x1F40) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_250)); } + .inttab_tc2_0FB (__INTTAB_CPU2 + 0x1F60) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_251)); } + .inttab_tc2_0FC (__INTTAB_CPU2 + 0x1F80) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_252)); } + .inttab_tc2_0FD (__INTTAB_CPU2 + 0x1FA0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_253)); } + .inttab_tc2_0FE (__INTTAB_CPU2 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_254)); } + .inttab_tc2_0FF (__INTTAB_CPU2 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc2_255)); } + } + + /* Explicitly reject all BMHD entries from iLLD SDK - these should be set out-of-band by user */ + CORE_ID = GLOBAL; + SECTIONS + { + /DISCARD/ : + { + *(.bmhd_0_orig) + *(.bmhd_1_orig) + *(.bmhd_2_orig) + *(.bmhd_3_orig) + *(.bmhd_0_copy) + *(.bmhd_1_copy) + *(.bmhd_2_copy) + *(.bmhd_3_copy) + } + } + + /*Near Abbsolute Addressable Data Sections*/ + /*Near Absolute Data, selectable with patterns and user defined sections*/ + CORE_ID = CPU2; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR2_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc2.* (.zdata) + *Cpu2_Main.* (.zdata) + *(.zdata_cpu2) + *(.zdata_cpu2.*) + . = ALIGN(2); + } > dsram2 AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc2.* (.zbss) + *Cpu2_Main.* (.zbss) + *(.zbss_cpu2) + *(.zbss_cpu2.*) + } > dsram2 + } + CORE_ID = CPU1; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR1_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc1.* (.zdata) + *Cpu1_Main.* (.zdata) + *(.zdata_cpu1) + *(.zdata_cpu1.*) + . = ALIGN(2); + } > dsram1 AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc1.* (.zbss) + *Cpu1_Main.* (.zbss) + *(.zbss_cpu1) + *(.zbss_cpu1.*) + } > dsram1 + } + CORE_ID = CPU0; + SECTIONS + { + CORE_SEC(.zdata) (LCF_DSPR0_START): FLAGS(awzl) + { + *Ifx_Ssw_Tc0.* (.zdata) + *Cpu0_Main.* (.zdata) + *(.zdata_cpu0) + *(.zdata_cpu0.*) + . = ALIGN(2); + } > dsram0 AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) + { + *Ifx_Ssw_Tc0.* (.zbss) + *Cpu0_Main.* (.zbss) + *(.zbss_cpu0) + *(.zbss_cpu0.*) + } > dsram0 + } + + /*Near Absolute Data, selectable by toolchain*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zdata_powerOn) : FLAGS(awzl) + { + *(.zdata.dsprPowerOnInit.cpu0.32bit) + *(.zdata.dsprPowerOnInit.cpu0.16bit) + *(.zdata.dsprPowerOnInit.cpu0.8bit) + . = ALIGN(2); + } > default_ram AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.zdata) : FLAGS(awzl) + { + *(.zdata.dsprInit.cpu0.32bit) + *(.zdata.dsprInit.cpu0.16bit) + *(.zdata.dsprInit.cpu0.8bit) + *(.zdata) + *(.zdata.*) + *(.gnu.linkonce.z.*) + . = ALIGN(2); + } > default_ram AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.zbss_powerOn) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprPowerOnClear.cpu0.32bit) + *(.zbss.dsprPowerOnClear.cpu0.16bit) + *(.zbss.dsprPowerOnClear.cpu0.8bit) + } > default_ram + + CORE_SEC(.zbss_noClear) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprNoInit.cpu0.32bit) + *(.zbss.dsprNoInit.cpu0.16bit) + *(.zbss.dsprNoInit.cpu0.8bit) + } > default_ram + + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) + { + *(.zbss.dsprClearOnInit.cpu0.32bit) + *(.zbss.dsprClearOnInit.cpu0.16bit) + *(.zbss.dsprClearOnInit.cpu0.8bit) + *(.zbss) + *(.zbss.*) + *(.bbss) + *(.bbss.*) + *(.gnu.linkonce.zb.*) + } > default_ram + } + + /* HSM Shared memory buffers */ + CORE_ID = GLOBAL; + SECTIONS + { + /* HSM Shared Memory Buffer (Cancel Seqs) */ + CORE_SEC(.hsmShmCancelSeq) (NOLOAD): FLAGS(awz) + { + . = ALIGN(16); /* Align to a 16-byte boundary (cache line size) */ + _hsmShmCore0CancelSeq = .; + . = . + HSM_SHM_CANCEL_SEQ_SIZE; /* Set the section size */ + _hsmShmCore1CancelSeq = .; + . = . + HSM_SHM_CANCEL_SEQ_SIZE; /* Set the section size */ + } > dsram_hsm_shm + + /* HSM Shared Memory Buffer (Comms) */ + CORE_SEC(.hsmShmCore0CommBuf) (NOLOAD): FLAGS(awz) + { + . = ALIGN(16); /* Align to a 16-byte boundary */ + _hsmShmCore0CommBufStart = .; /* Define start symbol */ + . = . + HSM_SHM_BUF_SIZE; /* Set the section size */ + _hsmShmCore0CommBufEnd = .; /* Define end symbol */ + } > dsram_hsm_shm + + CORE_SEC(.hsmShmCore1CommBuf) (NOLOAD): FLAGS(awz) + { + . = ALIGN(16); /* Align to a 16-byte boundary */ + _hsmShmCore1CommBufStart = .; /* Define start symbol */ + . = . + HSM_SHM_BUF_SIZE; /* Set the section size */ + _hsmShmCore1CommBufEnd = .; /* Define end symbol */ + } > dsram_hsm_shm + + /* HSM Shared Memory Buffer (Print) */ + CORE_SEC(.hsmShmPrintBuf) (NOLOAD): FLAGS(awz) + { + . = ALIGN(16); /* Align to a 16-byte boundary */ + _hsmShmPrintBufStart = .; /* Define start symbol */ + . = . + HSM_SHM_BUF_SIZE; /* Set the section size */ + _hsmShmPrintBufEnd = .; /* Define end symbol */ + } > dsram_hsm_shm + } + + CORE_ID = GLOBAL; + SECTIONS + { + /*Cpu0_dlmu also is the segment start, all the near lmu data shll be located here*/ + CORE_SEC(.lmuzdata) : FLAGS(awzl) + { + *(.zlmudata) + *(.zlmudata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) + { + *(.zlmubss) + *(.zlmubss.*) + } > cpu0_dlmu + } + + /*Near Absolute Const, selectable with patterns and user defined sections*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zrodata) : FLAGS(arzl) + { + *Ifx_Ssw_Tc?.* (.zrodata) + *Cpu?_Main.* (.zrodata) + *(.zrodata_cpu?) + } > pfls0_nc /* pfls0 */ + } + + /*Near Absolute Const, selectable by toolchain*/ + CORE_ID = GLOBAL; + SECTIONS + { + CORE_SEC(.zrodata) : FLAGS(arzl) + { + *(.zrodata.const.cpu0.32bit) + *(.zrodata.const.cpu0.16bit) + *(.zrodata.const.cpu0.8bit) + *(.zrodata.config.cpu0.32bit) + *(.zrodata.config.cpu0.16bit) + *(.zrodata.config.cpu0.8bit) + *(.zrodata) + *(.zrodata.*) + } > pfls0_nc /* pfls0 */ + } + +/*Relative A0/A1/A8/A9 Addressable Sections*/ +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A0 Addressable Data, selectable with patterns and user defined sections*/ + /*Note: A0 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A0 Addressable Data, selectable by toolchain*/ + CORE_SEC(.sdata) : FLAGS(awsl) + { + *(.sdata) + *(.sdata.*) + . = ALIGN(2); + } > default_ram AT> pfls0_nc /* pfls0 */ + CORE_SEC(.sbss) (NOLOAD): FLAGS(aws) + { + *(.sbss) + *(.sbss.*) + } > default_ram + _SMALL_DATA_ = SIZEOF(CORE_SEC(.sdata)) ? ADDR(CORE_SEC(.sdata)) : (ADDR(CORE_SEC(.sdata)) & 0xF0000000) + 32k ; + __A0_MEM = _SMALL_DATA_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A1 Addressable Const, selectable with patterns and user defined sections*/ + /*Note: A1 addressable area is common, to make the functions callable in any CPU*/ + /*Relative A1 Addressable Const, selectable by toolchain*/ + CORE_SEC(.sdata2) : FLAGS(arsl) + { + *(.srodata) + *(.srodata.*) + } > default_rom + _SMALL_DATA2_ = SIZEOF(CORE_SEC(.sdata2)) ? ADDR(CORE_SEC(.sdata2)) : (ADDR(CORE_SEC(.sdata2)) & 0xF0000000) + 32k ; + __A1_MEM = _SMALL_DATA2_; +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata3) : FLAGS(arsl) + { + *(.rodata_a8) + *(.rodata_a8.*) + } > default_rom + + _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; + __A8_MEM = _SMALL_DATA3_; +} + +/*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ +/*Far Data Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU2 ; +SECTIONS +{ + /*DSRAM2 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc2.* (.data) + *Cpu2_Main.* (.data) + *(.data_cpu2) + *(.data_cpu2.*) + . = ALIGN(2); + } > dsram2 AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc2.* (.bss) + *Cpu2_Main.* (.bss) + *(.bss_cpu2) + *(.bss_cpu2.*) + } > dsram2 + + /*DLMU2 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu2) + *(.lmudata_cpu2.*) + . = ALIGN(2); + } > cpu2_dlmu AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu2) + *(.lmubss_cpu2.*) + } > cpu2_dlmu +} +CORE_ID = CPU1 ; +SECTIONS +{ + /*DSRAM1 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc1.* (.data) + *Cpu1_Main.* (.data) + *(.data_cpu1) + *(.data_cpu1.*) + . = ALIGN(2); + } > dsram1 AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc1.* (.bss) + *Cpu1_Main.* (.bss) + *(.bss_cpu1) + *(.bss_cpu1.*) + } > dsram1 + + /*DLMU1 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu1) + *(.lmudata_cpu1.*) + . = ALIGN(2); + } > cpu1_dlmu AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu1) + *(.lmubss_cpu1.*) + } > cpu1_dlmu +} +CORE_ID = CPU0 ; +SECTIONS +{ + /*DSRAM0 Sections*/ + CORE_SEC(.data) : FLAGS(awl) + { + *Ifx_Ssw_Tc0.* (.data) + *Cpu0_Main.* (.data) + *(.data_cpu0) + *(.data_cpu0.*) + . = ALIGN(2); + } > dsram0 AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.bss) (NOLOAD): FLAGS(aw) + { + *Ifx_Ssw_Tc0.* (.bss) + *Cpu0_Main.* (.bss) + *(.bss_cpu0) + *(.bss_cpu0.*) + } > dsram0 + + /*DLMU0 Sections*/ + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata_cpu0) + *(.lmudata_cpu0.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss_cpu0) + *(.lmubss_cpu0.*) + } > cpu0_dlmu +} + +CORE_ID = GLOBAL; +SECTIONS +{ + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + CORE_SEC(.sdata4) : + { + *(.a9sdata) + *(.a9sdata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.sbss4) : + { + *(.a9sbss) + *(.a9sbss.*) + } > cpu0_dlmu + + _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; + __A9_MEM = _SMALL_DATA4_; +} + +/*Far Data Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.bss_noClear) (NOLOAD) : FLAGS(aw) + { + *(.bss.farDsprNoInit.cpu0.32bit) + *(.bss.farDsprNoInit.cpu0.16bit) + *(.bss.farDsprNoInit.cpu0.8bit) + } > default_ram + + CORE_SEC(.data) : FLAGS(awl) + { + *(.data.farDsprInit.cpu0.32bit) + *(.data.farDsprInit.cpu0.16bit) + *(.data.farDsprInit.cpu0.8bit) + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(2); + } > default_ram AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) + { + *(.bss.farDsprClearOnInit.cpu0.32bit) + *(.bss.farDsprClearOnInit.cpu0.16bit) + *(.bss.farDsprClearOnInit.cpu0.8bit) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + } > default_ram + + .heap : FLAGS(aw) + { + . = ALIGN(4); + __HEAP = .; + . += LCF_HEAP_SIZE; + __HEAP_END = .; + } > default_ram + + CORE_SEC(.lmudata) : FLAGS(awl) + { + *(.lmudata) + *(.lmudata.*) + . = ALIGN(2); + } > cpu0_dlmu AT> pfls0_nc /* pfls0 */ + + CORE_SEC(.lmubss) : FLAGS(aw) + { + *(.lmubss) + *(.lmubss.*) + } > cpu0_dlmu +} +/*Far Const Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU0; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc0.* (.rodata) + *Cpu0_Main.* (.rodata) + *(.rodata_cpu0) + *(.rodata_cpu0.*) + } > pfls0_nc /* pfls0 */ +} + +CORE_ID = CPU1; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc1.* (.rodata) + *Cpu1_Main.* (.rodata) + *(.rodata_cpu1) + *(.rodata_cpu1.*) + } > pfls0_nc /* pfls0 */ +} + +CORE_ID = CPU2; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *Ifx_Ssw_Tc2.* (.rodata) + *Cpu2_Main.* (.rodata) + *(.rodata_cpu2) + *(.rodata_cpu2.*) + } > pfls0_nc /* pfls0 */ +} + +/*Far Const Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.rodata) : FLAGS(arl) + { + *(.rodata.farConst.cpu0.32bit) + *(.rodata.farConst.cpu0.16bit) + *(.rodata.farConst.cpu0.8bit) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + /* + * Create the clear and copy tables that tell the startup code + * which memory areas to clear and to copy, respectively. + */ + . = ALIGN(4) ; + PROVIDE(__clear_table = .); + LONG(0 + ADDR(.CPU2.zbss)); LONG(SIZEOF(.CPU2.zbss)); + LONG(0 + ADDR(.CPU2.bss)); LONG(SIZEOF(.CPU2.bss)); + LONG(0 + ADDR(.CPU2.lmubss)); LONG(SIZEOF(.CPU2.lmubss)); + LONG(0 + ADDR(.CPU1.zbss)); LONG(SIZEOF(.CPU1.zbss)); + LONG(0 + ADDR(.CPU1.bss)); LONG(SIZEOF(.CPU1.bss)); + LONG(0 + ADDR(.CPU1.lmubss)); LONG(SIZEOF(.CPU1.lmubss)); + LONG(0 + ADDR(.CPU0.zbss)); LONG(SIZEOF(.CPU0.zbss)); + LONG(0 + ADDR(.CPU0.bss)); LONG(SIZEOF(.CPU0.bss)); + LONG(0 + ADDR(.CPU0.lmubss)); LONG(SIZEOF(.CPU0.lmubss)); + LONG(0 + ADDR(.zbss)); LONG(SIZEOF(.zbss)); + LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss)); + LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); + LONG(0 + ADDR(.lmubss)); LONG(SIZEOF(.lmubss)); + LONG(0 + ADDR(.sbss4)); LONG(SIZEOF(.sbss4)); + LONG(-1); LONG(-1); + PROVIDE(__clear_table_powerOn = .); + LONG(0 + ADDR(.zbss_powerOn)); LONG(SIZEOF(.zbss_powerOn)); + LONG(-1); LONG(-1); + PROVIDE(__copy_table = .); + LONG(LOADADDR(.CPU2.zdata)); LONG(0 + ADDR(.CPU2.zdata)); LONG(SIZEOF(.CPU2.zdata)); + LONG(LOADADDR(.CPU2.data)); LONG(0 + ADDR(.CPU2.data)); LONG(SIZEOF(.CPU2.data)); + LONG(LOADADDR(.CPU2.lmudata)); LONG(0 + ADDR(.CPU2.lmudata)); LONG(SIZEOF(.CPU2.lmudata)); + LONG(LOADADDR(.CPU1.zdata)); LONG(0 + ADDR(.CPU1.zdata)); LONG(SIZEOF(.CPU1.zdata)); + LONG(LOADADDR(.CPU1.data)); LONG(0 + ADDR(.CPU1.data)); LONG(SIZEOF(.CPU1.data)); + LONG(LOADADDR(.CPU1.lmudata)); LONG(0 + ADDR(.CPU1.lmudata)); LONG(SIZEOF(.CPU1.lmudata)); + LONG(LOADADDR(.CPU0.zdata)); LONG(0 + ADDR(.CPU0.zdata)); LONG(SIZEOF(.CPU0.zdata)); + LONG(LOADADDR(.CPU0.data)); LONG(0 + ADDR(.CPU0.data)); LONG(SIZEOF(.CPU0.data)); + LONG(LOADADDR(.CPU0.lmudata)); LONG(0 + ADDR(.CPU0.lmudata)); LONG(SIZEOF(.CPU0.lmudata)); + LONG(LOADADDR(.zdata)); LONG(0 + ADDR(.zdata)); LONG(SIZEOF(.zdata)); + LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata)); + LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); + LONG(LOADADDR(.lmudata)); LONG(0 + ADDR(.lmudata)); LONG(SIZEOF(.lmudata)); + LONG(LOADADDR(.sdata4)); LONG(0 + ADDR(.sdata4)); LONG(SIZEOF(.sdata4)); + LONG(LOADADDR(.CPU0.psram_text)); LONG(0 + ADDR(.CPU0.psram_text)); LONG(SIZEOF(.CPU0.psram_text)); + LONG(LOADADDR(.CPU1.psram_text)); LONG(0 + ADDR(.CPU1.psram_text)); LONG(SIZEOF(.CPU1.psram_text)); + LONG(LOADADDR(.CPU2.psram_text)); LONG(0 + ADDR(.CPU2.psram_text)); LONG(SIZEOF(.CPU2.psram_text)); + LONG(-1); LONG(-1); LONG(-1); + PROVIDE(__copy_table_powerOn = .) ; + LONG(LOADADDR(.zdata_powerOn)); LONG(0 + ADDR(.zdata_powerOn)); LONG(SIZEOF(.zdata_powerOn)); + LONG(-1); LONG(-1); LONG(-1); + . = ALIGN(8); + } > default_rom +} + +/*Code selections*/ +/*Code Sections, selectable with patterns and user defined sections*/ +CORE_ID = CPU0; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc0.*(.text) + *Cpu0_Main.*(.text) + *Ifx_Ssw_Tc0.*(.text.*) + *Cpu0_Main.*(.text.*) + *(.text_cpu0) + *(.text_cpu0.*) + } > pfls0_nc /* pfls0 */ + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + .init : + { + PROVIDE(__init_start = .); + KEEP(*(.init)) + KEEP(*(.init*)) + PROVIDE(__init_end = .); + . = ALIGN(8); + + } > pfls0_nc /* pfls0 */ + + .fini : + { + PROVIDE(__fini_start = .); + KEEP(*(.fini)) + KEEP(*(.fini*)) + PROVIDE(__fini_end = .); + . = ALIGN(8); + } > pfls0_nc /* pfls0 */ + + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu0) + *(.psram_text_cpu0.*) + *(.cpu0_psram) + *(.cpu0_psram.*) + *(.ramcode) /* wolfBoot RAM function section, for RAM_CODE=1 */ + *(.ramcode.*) /* future proof subsection matching for wolfBoot RAM function section, for RAM_CODE=1 */ + . = ALIGN(2); + } > psram0 AT> pfls0_nc /* pfls0 */ +} + +CORE_ID = CPU1; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc1.*(.text) + *Cpu1_Main.*(.text) + *Ifx_Ssw_Tc1.*(.text.*) + *Cpu1_Main.*(.text.*) + *(.text_cpu1) + *(.text_cpu1.*) + } > pfls0_nc /* pfls0 */ + + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu1) + *(.psram_text_cpu1.*) + *(.cpu1_psram) + *(.cpu1_psram.*) + . = ALIGN(2); + } > psram1 AT> pfls0_nc /* pfls0 */ +} + +CORE_ID = CPU2; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + . = ALIGN(2); + *Ifx_Ssw_Tc2.*(.text) + *Cpu2_Main.*(.text) + *Ifx_Ssw_Tc2.*(.text.*) + *Cpu2_Main.*(.text.*) + *(.text_cpu2) + *(.text_cpu2.*) + } > pfls0_nc /* pfls0 */ + + CORE_SEC(.psram_text) : FLAGS(awx) + { + . = ALIGN(2); + *(.psram_text_cpu2) + *(.psram_text_cpu2.*) + *(.cpu2_psram) + *(.cpu2_psram.*) + . = ALIGN(2); + } > psram2 AT> pfls0_nc /* pfls0 */ +} + +/*Code Sections, selectable by toolchain*/ +CORE_ID = GLOBAL; +SECTIONS +{ + CORE_SEC(.text) : FLAGS(axl) + { + *(.text.fast.pfls.cpu0) + *(.text.slow.pfls.cpu0) + *(.text.5ms.pfls.cpu0) + *(.text.10ms.pfls.cpu0) + *(.text.callout.pfls.cpu0) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ + . = ALIGN(4); + } > default_rom + + /* + * C++ exception handling tables. NOTE: gcc emits .eh_frame + * sections when compiling C sources with debugging enabled (-g). + * If you can be sure that your final application consists + * exclusively of C objects (i.e., no C++ objects), you may use + * the -R option of the "strip" and "objcopy" utilities to remove + * the .eh_frame section from the executable. + */ + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > default_rom + + .eh_frame : + { + __EH_FRAME_BEGIN__ = . ; + KEEP (*(.eh_frame)) + __EH_FRAME_END__ = . ; + . = ALIGN(8); + } > default_rom + + .gcc_except_table : + { + __GCC_EXCEPT_TABLE_BEGIN__ = . ; + KEEP (*(.gcc_except_table)) + __GCC_EXCEPT_TABLE_END__ = . ; + . = ALIGN(8); + } > default_rom + + /* + * Constructors and destructors. + */ + .ctors : FLAGS(ar) + { + __CTOR_LIST__ = . ; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* + * Code executed before calling main extra section for C++ constructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __CTOR_END__ = . ; + . = ALIGN(8); + } > default_rom + .dtors : FLAGS(ar) + { + __DTOR_LIST__ = . ; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); + /* + * Code executed before calling main extra section for C++ distructor init + * -------------------------Start----------------------------------------- + */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* + * Code executed before calling main extra section for C++ distructor init + * -------------------------End----------------------------------------- + */ + LONG(0) ; + __DTOR_END__ = . ; + . = ALIGN(8); + } > default_rom + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the + * beginning of the section, so we begin them at 0. + */ + /* + * DWARF 1 + */ + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* + * GNU DWARF 1 extensions + */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* + * DWARF 1.1 and DWARF 2 + */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* + * DWARF 2 + */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_ranges 0 : { *(.debug_ranges) } + /* + * SGI/MIPS DWARF 2 extensions + */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* + * Optional sections that may only appear when relocating. + */ + /* + * Optional sections that may appear regardless of relocating. + */ + .version_info 0 : { *(.version_info) } + .boffs 0 : { KEEP (*(.boffs)) } +} + diff --git a/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/wolfhsm_cfg.h b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/wolfhsm_cfg.h new file mode 100644 index 000000000..a66c97d34 --- /dev/null +++ b/IDE/AURIX/wolfBoot-tc3xx-wolfHSM/wolfhsm_cfg.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2014-2024 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with wolfBoot. If not, see . + */ +/* + * wolfhsm_cfg.h + * + * wolfHSM compile-time options. Override here for your application + */ + +#ifndef WOLFHSM_CFG_H_ +#define WOLFHSM_CFG_H_ + +#define WOLFHSM_CFG_DMA + +#endif /* WOLFHSM_CFG_H_ */ diff --git a/IDE/AURIX/wolfBoot-tc3xx/.cproject b/IDE/AURIX/wolfBoot-tc3xx/.cproject index 98356a3ca..d54ccd355 100644 --- a/IDE/AURIX/wolfBoot-tc3xx/.cproject +++ b/IDE/AURIX/wolfBoot-tc3xx/.cproject @@ -20,7 +20,7 @@ - - @@ -115,7 +115,7 @@ - + @@ -140,7 +140,7 @@ - - @@ -297,7 +297,7 @@ - + @@ -316,10 +316,10 @@ - + - - + @@ -693,15 +687,10 @@