From 5000fc7c4b1468f7cd25df98d801fb4517cbb46d Mon Sep 17 00:00:00 2001
From: David Garske <david@wolfssl.com>
Date: Tue, 17 Oct 2023 12:43:45 -0700
Subject: [PATCH] Fixes for PPC spin table based on ePAPR 1.1.

---
 hal/nxp_p1021.ld  |  2 ++
 hal/nxp_ppc.h     | 10 ++++++++--
 hal/nxp_t1024.ld  |  1 +
 hal/nxp_t2080.ld  |  1 +
 src/boot_ppc_mp.S |  7 ++++++-
 5 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/hal/nxp_p1021.ld b/hal/nxp_p1021.ld
index e10f50764..3058dcc99 100644
--- a/hal/nxp_p1021.ld
+++ b/hal/nxp_p1021.ld
@@ -39,6 +39,8 @@ SECTIONS
     {
         _start_vector = .;
         KEEP(*(.isr_vector))
+        . = ALIGN(256);
+        KEEP(*(.bootmp))
         *(.text*)
         *(.rodata*)
         *(.sdata*)
diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h
index 0bf908dba..fc96a22e0 100644
--- a/hal/nxp_ppc.h
+++ b/hal/nxp_ppc.h
@@ -102,6 +102,7 @@
     #define CPU_NUMCORES 4
     #define CORES_PER_CLUSTER 4
     #define LAW_MAX_ENTRIES 32
+    #define ENABLE_PPC64
 
     #define CCSRBAR_DEF (0xFE000000UL) /* T2080RM 4.3.1 default base */
     #define CCSRBAR_SIZE BOOKE_PAGESZ_16M
@@ -704,17 +705,22 @@ extern void dcache_disable(void);
     #define r31 31
 #endif
 
+/* ePAPR 1.1 spin table */
 /* For multiple core spin table communication */
-#define EPAPR_MAGIC       (0x45504150)
+/* The spin table must be WING 0b001x (memory-coherence required) */
+/* For older PPC compat use dcbf to flush spin table entry */
+#define EPAPR_MAGIC       (0x45504150) /* Book III-E CPUs */
 #define ENTRY_ADDR_UPPER  0
 #define ENTRY_ADDR_LOWER  4
 #define ENTRY_R3_UPPER    8
 #define ENTRY_R3_LOWER    12
 #define ENTRY_RESV        16
 #define ENTRY_PIR         20
+
+/* not used for ePAPR 1.1 */
 #define ENTRY_R6_UPPER    24
 #define ENTRY_R6_LOWER    28
-#define ENTRY_SIZE        32
 
+#define ENTRY_SIZE        CACHE_LINE_SIZE /* note: spin-table shall be cache-line size aligned in memory */
 
 #endif /* !_NXP_PPC_H_ */
diff --git a/hal/nxp_t1024.ld b/hal/nxp_t1024.ld
index 863034a87..d7cf8794a 100644
--- a/hal/nxp_t1024.ld
+++ b/hal/nxp_t1024.ld
@@ -37,6 +37,7 @@ SECTIONS
         KEEP(*(.isr_vector))
         . = ALIGN(256);
         _start_text = .;
+        KEEP(*(.bootmp))
         *(.text*)
         *(.rodata*)
         *(.sdata*)
diff --git a/hal/nxp_t2080.ld b/hal/nxp_t2080.ld
index 3ee1be3f4..43e692cab 100644
--- a/hal/nxp_t2080.ld
+++ b/hal/nxp_t2080.ld
@@ -41,6 +41,7 @@ SECTIONS
         _start_vector = .;
         KEEP(*(.isr_vector))
         . = ALIGN(256);
+        KEEP(*(.bootmp))
         *(.text*)
         *(.rodata*)
         *(.sdata*)
diff --git a/src/boot_ppc_mp.S b/src/boot_ppc_mp.S
index 81d3100ab..02c5d2283 100644
--- a/src/boot_ppc_mp.S
+++ b/src/boot_ppc_mp.S
@@ -36,6 +36,7 @@
 /* Additional cores (mp) assembly code for core minimum startup and spin table.
  * All code must fit in 4KB, which gets virtually mapped via the TLB1 (MMU) and
  * loaded by core 0. Spin table entry TLB1(0) mapped for work is 64MB. */
+ .section .bootmp, "ax"
 .globl        _mp_page_start
 .align        12
 _mp_page_start:
@@ -111,7 +112,7 @@ _mp_page_start:
         mr      r4, r0
         mr      r5, r4
 #endif
-        slwi    r8, r5, 5 /* core number * ENTRY_SIZE */
+        slwi    r8, r5, CACHE_LINE_SHIFT /* core number * ENTRY_SIZE */
         add     r10, r3, r8
 
         mtspr   SPRN_PIR, r4 /* write to PIR register */
@@ -228,7 +229,11 @@ _mp_page_start:
         rlwinm  r12, r4, 0, 0, 5
 
         /* setup registers before jump */
+    #ifdef ENABLE_PPC64
+        ld      r3, ENTRY_R3_UPPER(r10)
+    #else
         lwz     r3, ENTRY_R3_LOWER(r10)
+    #endif
         li      r4, 0
         li      r5, 0
         lwz     r6, ENTRY_R6_LOWER(r10)