diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h index 240751179..0bf908dba 100644 --- a/hal/nxp_ppc.h +++ b/hal/nxp_ppc.h @@ -62,8 +62,9 @@ #elif defined(PLATFORM_nxp_t1024) /* NXP T1024 */ - #define CPU_NUMCORES 2 #define CORE_E5500 + #define CPU_NUMCORES 2 + #define CORES_PER_CLUSTER 1 #define LAW_MAX_ENTRIES 16 #define CCSRBAR_DEF (0xFE000000) /* T1024RM 4.4.1 default base */ @@ -97,8 +98,9 @@ #elif defined(PLATFORM_nxp_t2080) /* NXP T0280 */ - #define CPU_NUMCORES 4 #define CORE_E6500 + #define CPU_NUMCORES 4 + #define CORES_PER_CLUSTER 4 #define LAW_MAX_ENTRIES 32 #define CCSRBAR_DEF (0xFE000000UL) /* T2080RM 4.3.1 default base */ diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 99ae14bce..c8ee868f3 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -44,10 +44,11 @@ #define TEST_TPM #endif - //#define ENABLE_CPLD + #define ENABLE_PCIE + #define ENABLE_CPLD #define ENABLE_QE /* QUICC Engine */ - //#define ENABLE_FMAN - //#define ENABLE_MP /* multi-core support */ + //#define ENABLE_FMAN /* not complete */ + #define ENABLE_MP /* multi-core support */ #if defined(WOLFBOOT_TPM) || defined(TEST_TPM) #define ENABLE_ESPI /* SPI for TPM */ #endif @@ -174,11 +175,15 @@ static void hal_flash_unlock_sector(uint32_t sector); * - 2-Kbyte SFDRs * - 256 congestion groups */ +#define QMAN_BASE_PHYS_HIGH 0xF +#define QMAN_BASE_PHYS 0xF6000000 /* T1024RM 10.5.2: Buffer Manager (BMan): * - BMan block base address: 31_A000h * - 64 buffer pools */ +#define BMAN_BASE_PHYS_HIGH 0xF +#define BMAN_BASE_PHYS 0xF4000000 /* T1024RM 10.5.4: Security and Encryption Engine (SEC) * - SEC block base address: 30_0000h @@ -609,7 +614,6 @@ enum ifc_amask_sizes { #define ESPI_CSMODE_CSAFT(x) (((x) & 0xF) << 8) /* CS assertion time in bits after frame end */ #define ESPI_CSMODE_CSCG(x) (((x) & 0xF) << 3) /* Clock gaps between transmitted frames according to this size */ - /* generic share NXP QorIQ driver code */ #include "nxp_ppc.c" @@ -638,8 +642,33 @@ static void udelay(uint32_t delay_us) static void law_init(void) { - /* Buffer Manager (BMan) (control) - probably not required */ - set_law(3, 0xF, 0xF4000000, LAW_TRGT_BMAN, LAW_SIZE_32MB, 1); +#ifndef BUILD_LOADER_STAGE1 + /* Buffer Manager (BMan) (control) - 32MB */ + set_law(3, BMAN_BASE_PHYS_HIGH, BMAN_BASE_PHYS, LAW_TRGT_BMAN, LAW_SIZE_32MB, 1); + set_tlb(1, 5, BMAN_BASE_PHYS, + BMAN_BASE_PHYS, BMAN_BASE_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), 0, 0, BOOKE_PAGESZ_16M, 1); + set_tlb(1, 6, BMAN_BASE_PHYS + 0x01000000, + BMAN_BASE_PHYS + 0x01000000, BMAN_BASE_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_16M, 1); + + /* QMAN - 32MB */ + set_law(4, QMAN_BASE_PHYS_HIGH, QMAN_BASE_PHYS, LAW_TRGT_QMAN, LAW_SIZE_32MB, 1); + set_tlb(1, 7, QMAN_BASE_PHYS, + QMAN_BASE_PHYS, QMAN_BASE_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), 0, 0, BOOKE_PAGESZ_16M, 1); + set_tlb(1, 8, QMAN_BASE_PHYS + 0x01000000, + QMAN_BASE_PHYS + 0x01000000, QMAN_BASE_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_16M, 1); + + /* DCSR - 4MB */ + #define DCSRBAR_BASE_HIGH 0xF + #define DCSRBAR_BASE 0xF0000000 + set_law(5, DCSRBAR_BASE_HIGH, DCSRBAR_BASE, LAW_TRGT_DCSR, LAW_SIZE_4MB, 1); + set_tlb(1, 9, DCSRBAR_BASE, + DCSRBAR_BASE, DCSRBAR_BASE_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_4M, 1); +#endif } @@ -1022,6 +1051,41 @@ void hal_early_init(void) hal_ddr_init(); } +#ifdef ENABLE_PCIE +#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0xC +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x00000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_IO_PHYS_HIGH 0xF +#define CONFIG_SYS_PCIE1_IO_PHYS 0xF8000000 +#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_PHYS + +#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH 0xC +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x10000000 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_IO_PHYS_HIGHT 0xF +#define CONFIG_SYS_PCIE2_IO_PHYS 0xF8010000 +#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_PHYS + +#define CONFIG_SYS_PCIE3_MEM_PHYS_HIGH 0xC +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x20000000 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xA0000000 +#define CONFIG_SYS_PCIE3_IO_PHYS_HIGH 0xF +#define CONFIG_SYS_PCIE3_IO_PHYS 0xF8020000 +#define CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE3_IO_PHYS +static int hal_pcie_init(void) +{ + /* Map TLB for PCIe */ + set_tlb(1, 3, CONFIG_SYS_PCIE1_MEM_VIRT, + CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1G, 1); + set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, + CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + + return 0; +} +#endif + static void hal_cpld_init(void) { #ifdef ENABLE_CPLD @@ -1029,14 +1093,14 @@ static void hal_cpld_init(void) uint32_t fw; #endif /* CPLD IFC Timing Parameters */ - set32(IFC_FTIM0(2), (IFC_FTIM0_GPCM_TACSE(14) | - IFC_FTIM0_GPCM_TEADC(14) | - IFC_FTIM0_GPCM_TEAHC(14))); - set32(IFC_FTIM1(2), (IFC_FTIM1_GPCM_TACO(14) | - IFC_FTIM1_GPCM_TRAD(31))); - set32(IFC_FTIM2(2), (IFC_FTIM2_GPCM_TCS(14) | - IFC_FTIM2_GPCM_TCH(8) | - IFC_FTIM2_GPCM_TWP(31))); + set32(IFC_FTIM0(2), (IFC_FTIM0_GPCM_TACSE(14UL) | + IFC_FTIM0_GPCM_TEADC(14UL) | + IFC_FTIM0_GPCM_TEAHC(14UL))); + set32(IFC_FTIM1(2), (IFC_FTIM1_GPCM_TACO(14UL) | + IFC_FTIM1_GPCM_TRAD(31UL))); + set32(IFC_FTIM2(2), (IFC_FTIM2_GPCM_TCS(14UL) | + IFC_FTIM2_GPCM_TCH(8UL) | + IFC_FTIM2_GPCM_TWP(31UL))); set32(IFC_FTIM3(2), 0); /* CPLD IFC Definitions (CS2) */ @@ -1050,12 +1114,12 @@ static void hal_cpld_init(void) /* IFC - CPLD */ set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE, - LAW_TRGT_IFC, LAW_SIZE_4KB, 1); + LAW_TRGT_IFC, LAW_SIZE_64KB, 1); /* CPLD - TBL=1, Entry 11 */ - set_tlb(1, 11, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, BOOKE_PAGESZ_4K, 1); + set_tlb(1, 11, CPLD_BASE, + CPLD_BASE, CPLD_BASE_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); #ifdef DEBUG fw = get8(CPLD_DATA(HW_VER)); @@ -1327,7 +1391,7 @@ static void hal_mp_up(uint32_t bootpg) /* Set the boot page translation reigster */ set32(LCC_BSTRL, bootpg); set32(LCC_BSTAR, (LCC_BSTAR_EN | - LCC_BSTAR_LAWTRGT(LAW_TRGT_IFC) | + LCC_BSTAR_LAWTRGT(LAW_TRGT_DDR_1) | LAW_SIZE_4KB)); (void)get32(LCC_BSTAR); /* read back to sync */ @@ -1376,10 +1440,10 @@ static void hal_mp_init(void) size_t bootpg; int i_tlb = 0; /* always 0 */ size_t i; - const uint32_t *s; - uint32_t *d; + const volatile uint32_t *s; + volatile uint32_t *d; - /* Assign virtual boot page at end of DDR */ + /* Assign virtual boot page at end of DDR (should be 0x7FFFF000) */ bootpg = DDR_ADDRESS + DDR_SIZE - BOOT_ROM_SIZE; /* Store the boot page address for use by additional CPU cores */ @@ -1388,7 +1452,7 @@ static void hal_mp_init(void) /* map reset page to bootpg so we can copy code there */ disable_tlb1(i_tlb); set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn, urpn */ - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */ + (MAS3_SX | MAS3_SW | MAS3_SR), MAS2_I, /* perms, wimge */ 0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ /* copy startup code to virtually mapped boot address */ @@ -1417,6 +1481,9 @@ void hal_init(void) hal_flash_init(); hal_cpld_init(); +#ifdef ENABLE_PCIE + hal_pcie_init(); +#endif #ifdef ENABLE_QE if (hal_qe_init() != 0) { diff --git a/hal/nxp_t1024.ld b/hal/nxp_t1024.ld index 06baab811..863034a87 100644 --- a/hal/nxp_t1024.ld +++ b/hal/nxp_t1024.ld @@ -6,7 +6,7 @@ MEMORY { /* DDR4 - 2GB (offset by destination address and 4KB boot region) */ DRAM (rwx) : ORIGIN = @WOLFBOOT_STAGE1_LOAD_ADDR@, - LENGTH = 0x7FFFFFFF - @WOLFBOOT_STAGE1_LOAD_ADDR@ + LENGTH = 0x7FFFFFFF - 4K - @WOLFBOOT_STAGE1_LOAD_ADDR@ /* L1 SRAM - 16KB */ L1RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x4000 diff --git a/hal/nxp_t2080.c b/hal/nxp_t2080.c index adbdb302f..ea0f4eb65 100644 --- a/hal/nxp_t2080.c +++ b/hal/nxp_t2080.c @@ -459,14 +459,14 @@ static void hal_cpld_init(void) { #ifdef ENABLE_CPLD /* CPLD IFC Timing Parameters */ - IFC_FTIM0(3) = (IFC_FTIM0_GPCM_TACSE(16) | - IFC_FTIM0_GPCM_TEADC(16) | - IFC_FTIM0_GPCM_TEAHC(16)); - IFC_FTIM1(3) = (IFC_FTIM1_GPCM_TACO(16) | - IFC_FTIM1_GPCM_TRAD(31)); - IFC_FTIM2(3) = (IFC_FTIM2_GPCM_TCS(16) | - IFC_FTIM2_GPCM_TCH(8) | - IFC_FTIM2_GPCM_TWP(31)); + IFC_FTIM0(3) = (IFC_FTIM0_GPCM_TACSE(16UL) | + IFC_FTIM0_GPCM_TEADC(16UL) | + IFC_FTIM0_GPCM_TEAHC(16UL)); + IFC_FTIM1(3) = (IFC_FTIM1_GPCM_TACO(16UL) | + IFC_FTIM1_GPCM_TRAD(31UL)); + IFC_FTIM2(3) = (IFC_FTIM2_GPCM_TCS(16UL) | + IFC_FTIM2_GPCM_TCH(8UL) | + IFC_FTIM2_GPCM_TWP(31UL)); IFC_FTIM3(3) = 0; /* CPLD IFC Definitions (CS3) */ diff --git a/src/boot_ppc_mp.S b/src/boot_ppc_mp.S index 2eb099785..81d3100ab 100644 --- a/src/boot_ppc_mp.S +++ b/src/boot_ppc_mp.S @@ -94,12 +94,35 @@ _mp_page_start: lis r3, TORESET(_spin_table)@h ori r3, r3, TORESET(_spin_table)@l - /* Determine base address for the core (use r10) */ + /* Determine base address for the core + * r10=Core, r4=PIR, r5=Spin Table Index */ mfspr r0, SPRN_PIR +#if defined(CORE_E5500) || defined(CORE_E6500) + rlwinm r8, r0, 29, 0x03 /* r8 = core within cluster */ + srwi r10, r0, 5 /* r10 = cluster */ + + mulli r5, r10, CORES_PER_CLUSTER + add r5, r5, r8 + mulli r4, r5, CORES_PER_CLUSTER +#elif defined(CORE_E500) + rlwinm r4, r0, 27, 27, 31 + mr r5, r4 +#else mr r4, r0 - slwi r8, r4, 5 /* core number * ENTRY_SIZE */ + mr r5, r4 +#endif + slwi r8, r5, 5 /* core number * ENTRY_SIZE */ add r10, r3, r8 + mtspr SPRN_PIR, r4 /* write to PIR register */ + +#if defined(CORE_E5500) || defined(CORE_E6500) + /* set L1 stash id = 32: (coreID * 2) + 32 + L1 CT (0) */ + slwi r8, r4, 1 + addi r8, r8, 32 + mtspr L1CSR2, r8 +#endif + /* Setup the spin table entry */ li r3, 0 li r8, 1 @@ -122,12 +145,19 @@ _mp_page_start: lis r11, (MAS1_VALID | MAS1_IPROT)@h ori r11, r11, (MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K))@l mtspr MAS1, r11 +#if defined(CORE_E5500) || defined(CORE_E6500) + oris r11, r13, (MAS2_M | MAS2_G)@h + ori r11, r13, (MAS2_M | MAS2_G)@l +#else oris r11, r13, (MAS2_I)@h ori r11, r13, (MAS2_I)@l +#endif mtspr MAS2, r11 oris r11, r13, (MAS3_SX | MAS3_SW | MAS3_SR)@h ori r11, r13, (MAS3_SX | MAS3_SW | MAS3_SR)@l mtspr MAS3, r11 + li r11, 0 + mtspr MAS7, r11 tlbwe bl 1f diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index 918b9da95..0b30d47da 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -462,7 +462,7 @@ flash_law: lwz r2, 8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */ isync flash_tlb: - /* Flash: TLB 1, Entry 7, Super X/R/W, W/I/G, TS=0, 64/128M, IPROT */ + /* Flash: TLB 1, Entry 2, Super X/R/W, W/I/G, TS=0, 64/128M, IPROT */ /* Write is required for Write/Erase using CFI commands to base */ #ifdef BUILD_LOADER_STAGE1 /* Using XIP from this flash, so cannot use cache inhibit */ @@ -471,7 +471,7 @@ flash_tlb: /* IFC polling requires cache inhibit */ #define FLASH_TLB_WING (MAS2_I | MAS2_G) #endif - set_tlb(1, 7, + set_tlb(1, 2, FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH, MAS3_SX | MAS3_SW | MAS3_SR, FLASH_TLB_WING, 0, FLASH_TLB_PAGESZ, 1, r3);