diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c
index 77abf5b9c..3e5560c5d 100644
--- a/hal/nxp_t1024.c
+++ b/hal/nxp_t1024.c
@@ -101,6 +101,23 @@ static void hal_flash_unlock_sector(uint32_t sector);
 #define DCFG_BRR       ((volatile uint32_t*)(DCFG_BASE + 0xE4UL))  /* Boot Release Register (DCFG_CCSR_BRR) */
 #define DCFG_DCSR      ((volatile uint32_t*)(DCFG_BASE + 0x704UL)) /* Debug configuration and status */
 
+/* Logical I/O Device Number */
+#define DCFG_USB1LIODNR   ((volatile uint32_t*)(DCFG_BASE + 0x520))
+#define DCFG_USB2LIODNR   ((volatile uint32_t*)(DCFG_BASE + 0x524))
+#define DCFG_SDMMCLIODNR  ((volatile uint32_t*)(DCFG_BASE + 0x530))
+#define DCFG_SATALIODNR   ((volatile uint32_t*)(DCFG_BASE + 0x550))
+#define DCFG_DIULIODNR    ((volatile uint32_t*)(DCFG_BASE + 0x570))
+#define DCFG_TDMDMALIODNR ((volatile uint32_t*)(DCFG_BASE + 0x574))
+#define DCFG_QELIODNR     ((volatile uint32_t*)(DCFG_BASE + 0x578)) /* QUICC Engine Logical I/O Device Number register */
+#define DCFG_DMA1LIODNR   ((volatile uint32_t*)(DCFG_BASE + 0x580))
+#define DCFG_DMA2LIODNR   ((volatile uint32_t*)(DCFG_BASE + 0x584))
+
+/* PCI Express LIODN base register */
+#define PCI_BASE(n)     (0x240000 + ((n) * 0x10000))
+#define PCIE_LIODN(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x40)) /* PEXx_PEX_LBR */
+#define BMAN_LIODNR ((volatile uint32_t*)(BMAN_CCSR_BASE + 0xD08))
+#define QMAN_LIODNR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xD08))
+
 /* SCGG (Supplemental Configuration Unit) T1024RM 6.1 */
 #define SCFG_BASE      (CCSRBAR + 0xFC000)
 #define SCFG_QEIOCLKCR ((volatile uint32_t*)(DCFG_BASE + 0x400UL))
@@ -186,13 +203,16 @@ static void hal_flash_unlock_sector(uint32_t sector);
  * - 2-Kbyte SFDRs
  * - 256 congestion groups
  */
+#define QMAN_CCSR_BASE (CCSRBAR + 0x318000)
 #define QMAN_BASE_PHYS_HIGH 0xF
 #define QMAN_BASE_PHYS 0xF6000000
 
+
 /* T1024RM 10.5.2: Buffer Manager (BMan):
  * - BMan block base address: 31_A000h
  * - 64 buffer pools
  */
+#define BMAN_CCSR_BASE (CCSRBAR + 0x31A000)
 #define BMAN_BASE_PHYS_HIGH 0xF
 #define BMAN_BASE_PHYS 0xF4000000
 
@@ -1300,9 +1320,71 @@ static int qe_check_firmware(const struct qe_firmware *firmware, const char* t)
 #endif /* ENABLE_QE || ENABLE_FMAN */
 
 
+struct liodn_id_table {
+    const char* compat;
+    uint32_t id;
+    void* reg_offset;
+};
+#define SET_LIODN(fdtcomp, liodn, reg) \
+    {.compat = fdtcomp, .id = liodn, .reg_offset = (void*)reg}
+
+static const struct liodn_id_table liodn_tbl[] = {
+    SET_LIODN("fsl-usb2-mph", 553, DCFG_USB1LIODNR),
+    SET_LIODN("fsl-usb2-dr", 554, DCFG_USB2LIODNR),
+    SET_LIODN("fsl,esdhc", 552, DCFG_SDMMCLIODNR),
+    SET_LIODN("fsl,pq-sata-v2", 555, DCFG_SATALIODNR),
+    SET_LIODN("fsl,tdm1.0", 560, DCFG_TDMDMALIODNR),
+    SET_LIODN("fsl,qe", 559, DCFG_QELIODNR),
+    SET_LIODN("fsl,elo3-dma", 147, DCFG_DMA1LIODNR),
+    SET_LIODN("fsl,elo3-dma", 227, DCFG_DMA2LIODNR),
+
+    SET_LIODN("fsl,qman", 62, QMAN_LIODNR),
+    SET_LIODN("fsl,bman", 63, BMAN_LIODNR),
+    SET_LIODN("fsl,qoriq-pcie-v2.4", 148, PCIE_LIODN(1)),
+    SET_LIODN("fsl,qoriq-pcie-v2.4", 228, PCIE_LIODN(2)),
+    SET_LIODN("fsl,qoriq-pcie-v2.4", 308, PCIE_LIODN(3)),
+};
+
+
+/* Logical I/O Device Number */
+void hal_liodn_init(void)
+{
+    int i;
+    for (i=0; i<(int)(sizeof(liodn_tbl)/sizeof(struct liodn_id_table)); i++) {
+        wolfBoot_printf("LIODN %s: %p=%d\n",
+            liodn_tbl[i].compat, liodn_tbl[i].reg_offset, liodn_tbl[i].id);
+        set32(liodn_tbl[i].reg_offset, liodn_tbl[i].id);
+    }
+}
+
 /* ---- QUICC Engine Driver ---- */
 #ifdef ENABLE_QE
 
+#define CONFIG_SYS_QMAN_NUM_PORTALS    10
+struct qportal_info {
+    uint16_t   dliodn;    /* DQRR LIODN */
+    uint16_t   fliodn;    /* frame data LIODN */
+    uint16_t   liodn_offset;
+    uint8_t    sdest;
+};
+
+#define SET_QP_INFO(dqrr, fdata, off, dest) \
+    { .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest }
+
+static const struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+    /* dqrr liodn, frame data liodn, liodn off, sdest */
+    SET_QP_INFO(1, 27, 1, 0),
+    SET_QP_INFO(2, 28, 1, 0),
+    SET_QP_INFO(3, 29, 1, 1),
+    SET_QP_INFO(4, 30, 1, 1),
+    SET_QP_INFO(5, 31, 1, 2),
+    SET_QP_INFO(6, 32, 1, 2),
+    SET_QP_INFO(7, 33, 1, 3),
+    SET_QP_INFO(8, 34, 1, 3),
+    SET_QP_INFO(9, 35, 1, 0),
+    SET_QP_INFO(10, 36, 1, 0)
+};
+
 static void qe_upload_microcode(const struct qe_firmware *firmware,
     const struct qe_microcode *ucode)
 {
@@ -1599,6 +1681,7 @@ void hal_init(void)
     uart_write("wolfBoot HAL Init\n", 18);
 #endif
 
+    hal_liodn_init();
     hal_flash_init();
     hal_cpld_init();
 #ifdef ENABLE_PCIE
@@ -1795,7 +1878,7 @@ int hal_dts_fixup(void* dts_addr)
 {
 #ifndef BUILD_LOADER_STAGE1
     struct fdt_header *fdt = (struct fdt_header *)dts_addr;
-    int off;
+    int off, i;
     uint32_t *reg;
 
     /* display FTD information */
@@ -1826,7 +1909,7 @@ int hal_dts_fixup(void* dts_addr)
         int core;
         uintptr_t core_spin_table;
 
-        reg = (uint32_t*)fdt_getprop(fdt, off, "reg", 0);
+        reg = (uint32_t*)fdt_getprop(fdt, off, "reg", NULL);
         if (reg == NULL || *reg >= CPU_NUMCORES)
             break;
         core = *reg;
@@ -1866,6 +1949,33 @@ int hal_dts_fixup(void* dts_addr)
         fdt_fixup_val(fdt, off, "qe", "brg-frequency", hal_get_bus_clk()/2);
     }
 
+    /* fixup the LIODN */
+    for (i=0; i<(int)(sizeof(liodn_tbl)/sizeof(struct liodn_id_table)); i++) {
+        off = fdt_node_offset_by_compatible(fdt, -1, liodn_tbl[i].compat);
+        if (off >= 0) {
+            fdt_fixup_val(fdt, off, liodn_tbl[i].compat, "fsl,liodn",
+                liodn_tbl[i].id);
+        }
+    }
+
+    /* fixup the QMAN portals */
+    off = fdt_node_offset_by_compatible(fdt, -1, "fsl,qman-portal");
+    while (off != -FDT_ERR_NOTFOUND) {
+        const int *ci = fdt_getprop(fdt, off, "cell-index", NULL);
+        uint32_t liodns[2];
+        if (!ci)
+            break;
+        i = *ci;
+
+        liodns[0] = qp_info[i].dliodn;
+        liodns[1] = qp_info[i].fliodn;
+        wolfBoot_printf("FDT: Set %s@%d (%d), %s=%d,%d\n",
+            "qman-portal", i, off, "fsl,liodn", liodns[0], liodns[1]);
+        fdt_setprop(fdt, off, "fsl,liodn", liodns, sizeof(liodns));
+
+        off = fdt_node_offset_by_compatible(fdt, off, "fsl,qman-portal");
+    }
+
     /* mpic clock */
     off = fdt_find_devtype(fdt, -1, "open-pic");
     if (off != -FDT_ERR_NOTFOUND) {
diff --git a/include/fdt.h b/include/fdt.h
index 87d0ebb45..55b43a3a4 100644
--- a/include/fdt.h
+++ b/include/fdt.h
@@ -131,6 +131,9 @@ int fdt_find_devtype(void* fdt, int startoff, const char* node);
 #define fdt_set_size_dt_strings(fdt, val)   (fdt_set_header(fdt, size_dt_strings, (val)))
 #define fdt_set_size_dt_struct(fdt, val)    (fdt_set_header(fdt, size_dt_struct, (val)))
 
+int fdt_node_check_compatible(const void *fdt, int nodeoffset, const char *compatible);
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset, const char *compatible);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/fdt.c b/src/fdt.c
index 260d73ce3..95aad150c 100644
--- a/src/fdt.c
+++ b/src/fdt.c
@@ -142,7 +142,7 @@ uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
         if (fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 &&
             ((offset - fdt32_to_cpu(*lenp)) % 8) != 0) {
             offset += 4;
-		}
+        }
         break;
 
     case FDT_END:
@@ -574,4 +574,53 @@ int fdt_find_devtype(void* fdt, int startoff, const char* node)
     }
     return off; /* return error from fdt_next_node() */
 }
+
+int fdt_stringlist_contains(const char *strlist, int listlen, const char *str)
+{
+    int len = (int)strlen(str);
+    const char *p;
+
+    while (listlen >= len) {
+        if (memcmp(str, strlist, len+1) == 0) {
+            return 1;
+        }
+        p = memchr(strlist, '\0', listlen);
+        if (!p)
+            break;
+        listlen -= (p-strlist) + 1;
+        strlist = p + 1;
+    }
+    return 0;
+}
+
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+    const char *compatible)
+{
+    int len;
+    const void *prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
+    if (prop) {
+        if (fdt_stringlist_contains(prop, len, compatible)) {
+            return 0;
+        }
+    }
+    return 1;
+}
+
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+    const char *compatible)
+{
+    int offset, err;
+    for (offset = fdt_next_node(fdt, startoffset, NULL);
+         offset >= 0;
+         offset = fdt_next_node(fdt, offset, NULL)) {
+        err = fdt_node_check_compatible(fdt, offset, compatible);
+        if ((err < 0) && (err != -FDT_ERR_NOTFOUND))
+            return err;
+        else if (err == 0)
+            return offset;
+    }
+
+    return offset;
+}
+
 #endif /* MMU && !BUILD_LOADER_STAGE1 */
diff --git a/src/string.c b/src/string.c
index 983db8eeb..74a01d732 100644
--- a/src/string.c
+++ b/src/string.c
@@ -227,6 +227,19 @@ int memcmp(const void *_s1, const void *_s2, size_t n)
 
     return diff;
 }
+
+void* memchr(void const *s, int c_in, size_t n)
+{
+    unsigned char c = (unsigned char)c_in;
+    unsigned char *char_ptr = (unsigned char*)s;
+    for (; n > 0; --n, ++char_ptr) {
+        if (*char_ptr == c) {
+	        return (void*)char_ptr;
+        }
+    }
+    return NULL;
+}
+
 #endif /* __CCRX__ Renesas CCRX */
 #endif /* !BUILD_LOADER_STAGE1 || (PRINTF_ENABLED && DEBUG_UART) */