diff --git a/clang/include/clang/Basic/CodeGenOptions.h b/clang/include/clang/Basic/CodeGenOptions.h index 73d41e3293c66..38979520b90d6 100644 --- a/clang/include/clang/Basic/CodeGenOptions.h +++ b/clang/include/clang/Basic/CodeGenOptions.h @@ -278,19 +278,29 @@ class CodeGenOptions : public CodeGenOptionsBase { /// -fsymbol-partition (see https://lld.llvm.org/Partitions.html). std::string SymbolPartition; + /// Regular expression and the string it was created from. + struct RemarkPattern { + std::string Pattern; + std::shared_ptr Regex; + + explicit operator bool() const { return Regex != nullptr; } + + llvm::Regex *operator->() const { return Regex.get(); } + }; + /// Regular expression to select optimizations for which we should enable /// optimization remarks. Transformation passes whose name matches this /// expression (and support this feature), will emit a diagnostic /// whenever they perform a transformation. This is enabled by the /// -Rpass=regexp flag. - std::shared_ptr OptimizationRemarkPattern; + RemarkPattern OptimizationRemarkPattern; /// Regular expression to select optimizations for which we should enable /// missed optimization remarks. Transformation passes whose name matches this /// expression (and support this feature), will emit a diagnostic /// whenever they tried but failed to perform a transformation. This is /// enabled by the -Rpass-missed=regexp flag. - std::shared_ptr OptimizationRemarkMissedPattern; + RemarkPattern OptimizationRemarkMissedPattern; /// Regular expression to select optimizations for which we should enable /// optimization analyses. Transformation passes whose name matches this @@ -298,7 +308,7 @@ class CodeGenOptions : public CodeGenOptionsBase { /// whenever they want to explain why they decided to apply or not apply /// a given transformation. This is enabled by the -Rpass-analysis=regexp /// flag. - std::shared_ptr OptimizationRemarkAnalysisPattern; + RemarkPattern OptimizationRemarkAnalysisPattern; /// Set of files defining the rules for the symbol rewriting. std::vector RewriteMapFiles; diff --git a/clang/include/clang/Basic/Sanitizers.h b/clang/include/clang/Basic/Sanitizers.h index c6b0446cea4f7..675fa15fdec8f 100644 --- a/clang/include/clang/Basic/Sanitizers.h +++ b/clang/include/clang/Basic/Sanitizers.h @@ -178,6 +178,10 @@ struct SanitizerSet { /// Returns a non-zero SanitizerMask, or \c 0 if \p Value is not known. SanitizerMask parseSanitizerValue(StringRef Value, bool AllowGroups); +/// Serialize a SanitizerSet into values for -fsanitize= or -fno-sanitize=. +void serializeSanitizerSet(SanitizerSet Set, + SmallVectorImpl &Values); + /// For each sanitizer group bit set in \p Kinds, set the bits for sanitizers /// this group enables. SanitizerMask expandSanitizerGroups(SanitizerMask Kinds); diff --git a/clang/include/clang/Basic/XRayInstr.h b/clang/include/clang/Basic/XRayInstr.h index 42ca7773fcceb..23ca2c75fc997 100644 --- a/clang/include/clang/Basic/XRayInstr.h +++ b/clang/include/clang/Basic/XRayInstr.h @@ -65,8 +65,13 @@ struct XRayInstrSet { XRayInstrMask Mask = 0; }; +/// Parses a command line argument into a mask. XRayInstrMask parseXRayInstrValue(StringRef Value); +/// Serializes a set into a list of command line arguments. +void serializeXRayInstrValue(XRayInstrSet Set, + SmallVectorImpl &Values); + } // namespace clang #endif // LLVM_CLANG_BASIC_XRAYINSTR_H diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 7cfc38e95dd45..66abd62c193b7 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -1443,8 +1443,7 @@ def fno_sanitize_EQ : CommaJoined<["-"], "fno-sanitize=">, Group, Flags<[CoreOption, NoXarchOption]>; def fsanitize_blacklist : Joined<["-"], "fsanitize-blacklist=">, Group, - HelpText<"Path to blacklist file for sanitizers">, - MarshallingInfoStringVector>; + HelpText<"Path to blacklist file for sanitizers">; def fsanitize_system_blacklist : Joined<["-"], "fsanitize-system-blacklist=">, HelpText<"Path to system blacklist file for sanitizers">, Flags<[CC1Option]>; @@ -2181,8 +2180,7 @@ def foffload_static_lib_EQ : CommaJoined<["-"], "foffload-static-lib=">, Flags<[ def foffload_whole_static_lib_EQ : CommaJoined<["-"], "foffload-whole-static-lib=">, Flags<[NoXarchOption, CoreOption]>, Group; def fomit_frame_pointer : Flag<["-"], "fomit-frame-pointer">, Group; def fopenmp : Flag<["-"], "fopenmp">, Group, Flags<[CC1Option, NoArgumentUnused]>, - HelpText<"Parse OpenMP pragmas and generate parallel code.">, - MarshallingInfoFlag, "0u">, Normalizer<"makeFlagToValueNormalizer(50u)">; + HelpText<"Parse OpenMP pragmas and generate parallel code.">; def fno_openmp : Flag<["-"], "fno-openmp">, Group, Flags<[NoArgumentUnused]>; def fopenmp_version_EQ : Joined<["-"], "fopenmp-version=">, Group, Flags<[CC1Option, NoArgumentUnused]>; def fopenmp_EQ : Joined<["-"], "fopenmp=">, Group; @@ -4546,12 +4544,7 @@ def migrator_no_finalize_removal : Flag<["-"], "no-finalize-removal">, //===----------------------------------------------------------------------===// let Flags = [CC1Option, CC1AsOption, NoDriverOption] in { -def debug_info_kind_EQ : Joined<["-"], "debug-info-kind=">, - Values<"line-tables-only,line-directives-only,constructor,limited,standalone,unused-types">, - NormalizedValuesScope<"codegenoptions">, - NormalizedValues<["DebugLineTablesOnly", "DebugDirectivesOnly", "DebugInfoConstructor", - "LimitedDebugInfo", "FullDebugInfo", "UnusedTypeInfo"]>, - MarshallingInfoString, "NoDebugInfo">, AutoNormalizeEnum; +def debug_info_kind_EQ : Joined<["-"], "debug-info-kind=">; def debug_info_macro : Flag<["-"], "debug-info-macro">, HelpText<"Emit macro debug information">, MarshallingInfoFlag>; diff --git a/clang/include/clang/Frontend/CompilerInvocation.h b/clang/include/clang/Frontend/CompilerInvocation.h index e880713b71aad..8cd512cbfd89e 100644 --- a/clang/include/clang/Frontend/CompilerInvocation.h +++ b/clang/include/clang/Frontend/CompilerInvocation.h @@ -249,18 +249,43 @@ class CompilerInvocation : public CompilerInvocationBase { DiagnosticsEngine &Diags); /// Parse command line options that map to LangOptions. - static bool ParseLangArgs(LangOptions &Opts, llvm::opt::ArgList &Args, - InputKind IK, const llvm::Triple &T, + static bool ParseLangArgsImpl(LangOptions &Opts, llvm::opt::ArgList &Args, + InputKind IK, const llvm::Triple &T, + std::vector &Includes, + DiagnosticsEngine &Diags); + + static bool ParseLangArgs(CompilerInvocation &Res, LangOptions &Opts, + llvm::opt::ArgList &Args, InputKind IK, + const llvm::Triple &T, std::vector &Includes, DiagnosticsEngine &Diags); + /// Generate command line options from LangOptions. + static void GenerateLangArgs(const LangOptions &Opts, + SmallVectorImpl &Args, + StringAllocator SA, const llvm::Triple &T); + /// Parse command line options that map to CodeGenOptions. - static bool ParseCodeGenArgs(CodeGenOptions &Opts, llvm::opt::ArgList &Args, - InputKind IK, DiagnosticsEngine &Diags, - const llvm::Triple &T, + static bool ParseCodeGenArgsImpl(CodeGenOptions &Opts, + llvm::opt::ArgList &Args, InputKind IK, + DiagnosticsEngine &Diags, + const llvm::Triple &T, + const std::string &OutputFile, + const LangOptions &LangOptsRef); + + static bool ParseCodeGenArgs(CompilerInvocation &Res, CodeGenOptions &Opts, + llvm::opt::ArgList &Args, InputKind IK, + DiagnosticsEngine &Diags, const llvm::Triple &T, const std::string &OutputFile, const LangOptions &LangOptsRef); + // Generate command line options from CodeGenOptions. + static void GenerateCodeGenArgs(const CodeGenOptions &Opts, + SmallVectorImpl &Args, + StringAllocator SA, const llvm::Triple &T, + const std::string &OutputFile, + const LangOptions *LangOpts); + /// Parse command line options that map to HeaderSearchOptions. static void ParseHeaderSearchArgs(CompilerInvocation &Res, HeaderSearchOptions &Opts, diff --git a/clang/lib/Analysis/CalledOnceCheck.cpp b/clang/lib/Analysis/CalledOnceCheck.cpp index 883629a300dcb..92d68d85fbc28 100644 --- a/clang/lib/Analysis/CalledOnceCheck.cpp +++ b/clang/lib/Analysis/CalledOnceCheck.cpp @@ -22,6 +22,7 @@ #include "clang/Analysis/AnalysisDeclContext.h" #include "clang/Analysis/CFG.h" #include "clang/Analysis/FlowSensitive/DataflowWorklist.h" +#include "clang/Basic/Builtins.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/LLVM.h" #include "llvm/ADT/BitVector.h" @@ -330,6 +331,29 @@ class DeclRefFinder return Visit(OVE->getSourceExpr()); } + const DeclRefExpr *VisitCallExpr(const CallExpr *CE) { + if (!ShouldRetrieveFromComparisons) + return nullptr; + + // We want to see through some of the boolean builtin functions + // that we are likely to see in conditions. + switch (CE->getBuiltinCallee()) { + case Builtin::BI__builtin_expect: + case Builtin::BI__builtin_expect_with_probability: { + assert(CE->getNumArgs() >= 2); + + const DeclRefExpr *Candidate = Visit(CE->getArg(0)); + return Candidate != nullptr ? Candidate : Visit(CE->getArg(1)); + } + + case Builtin::BI__builtin_unpredictable: + return Visit(CE->getArg(0)); + + default: + return nullptr; + } + } + const DeclRefExpr *VisitExpr(const Expr *E) { // It is a fallback method that gets called whenever the actual type // of the given expression is not covered. diff --git a/clang/lib/Basic/Sanitizers.cpp b/clang/lib/Basic/Sanitizers.cpp index f5f81b5fb3e5e..19882cdae0f79 100644 --- a/clang/lib/Basic/Sanitizers.cpp +++ b/clang/lib/Basic/Sanitizers.cpp @@ -12,6 +12,7 @@ #include "clang/Basic/Sanitizers.h" #include "llvm/ADT/Hashing.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringSwitch.h" using namespace clang; @@ -34,6 +35,14 @@ SanitizerMask clang::parseSanitizerValue(StringRef Value, bool AllowGroups) { return ParsedKind; } +void clang::serializeSanitizerSet(SanitizerSet Set, + SmallVectorImpl &Values) { +#define SANITIZER(NAME, ID) \ + if (Set.has(SanitizerKind::ID)) \ + Values.push_back(NAME); +#include "clang/Basic/Sanitizers.def" +} + SanitizerMask clang::expandSanitizerGroups(SanitizerMask Kinds) { #define SANITIZER(NAME, ID) #define SANITIZER_GROUP(NAME, ID, ALIAS) \ diff --git a/clang/lib/Basic/XRayInstr.cpp b/clang/lib/Basic/XRayInstr.cpp index 79052e05860ea..822e14bbb622d 100644 --- a/clang/lib/Basic/XRayInstr.cpp +++ b/clang/lib/Basic/XRayInstr.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "clang/Basic/XRayInstr.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringSwitch.h" namespace clang { @@ -30,4 +31,30 @@ XRayInstrMask parseXRayInstrValue(StringRef Value) { return ParsedKind; } +void serializeXRayInstrValue(XRayInstrSet Set, + SmallVectorImpl &Values) { + if (Set.Mask == XRayInstrKind::All) { + Values.push_back("all"); + return; + } + + if (Set.Mask == XRayInstrKind::None) { + Values.push_back("none"); + return; + } + + if (Set.has(XRayInstrKind::Custom)) + Values.push_back("custom"); + + if (Set.has(XRayInstrKind::Typed)) + Values.push_back("typed"); + + if (Set.has(XRayInstrKind::FunctionEntry) && + Set.has(XRayInstrKind::FunctionExit)) + Values.push_back("function"); + else if (Set.has(XRayInstrKind::FunctionEntry)) + Values.push_back("function-entry"); + else if (Set.has(XRayInstrKind::FunctionExit)) + Values.push_back("function-exit"); +} } // namespace clang diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 5ccffbb7e4ddb..ea0c250bcaff7 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -54,6 +54,7 @@ #include "llvm/ADT/Hashing.h" #include "llvm/ADT/None.h" #include "llvm/ADT/Optional.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" @@ -214,6 +215,7 @@ static void denormalizeStringImpl(SmallVectorImpl &Args, Args.push_back(SA(Value)); break; case Option::JoinedClass: + case Option::CommaJoinedClass: Args.push_back(SA(Twine(Spelling) + Value)); break; default: @@ -625,14 +627,17 @@ static bool RoundTrip(ParseFn Parse, GenerateFn Generate, SwapOptsFn SwapOpts, // Run the first parse on the original arguments with dummy options and // diagnostics. SwapOpts(Res); - if (!Parse(Res, OriginalArgs, DummyDiags)) { + if (!Parse(Res, OriginalArgs, DummyDiags) || + DummyDiags.getNumWarnings() != 0) { // If the first parse did not succeed, it must be user mistake (invalid // command line arguments). We won't be able to generate arguments that // would reproduce the same result. Let's fail again with the original // options and diagnostics, so all side-effects of parsing are visible. + unsigned NumWarningsBefore = Diags.getNumWarnings(); SwapOpts(Res); - if (!Parse(Res, OriginalArgs, Diags)) - return false; + auto Success = Parse(Res, OriginalArgs, Diags); + if (!Success || Diags.getNumWarnings() != NumWarningsBefore) + return Success; // Parse with original options and diagnostics succeeded even though it // shouldn't have. Something is off. @@ -749,16 +754,11 @@ static void parseAnalyzerConfigs(AnalyzerOptions &AnOpts, static void getAllNoBuiltinFuncValues(ArgList &Args, std::vector &Funcs) { - SmallVector Values; - for (const auto &Arg : Args) { - const Option &O = Arg->getOption(); - if (O.matches(options::OPT_fno_builtin_)) { - const char *FuncName = Arg->getValue(); - if (Builtin::Context::isBuiltinFunc(FuncName)) - Values.push_back(FuncName); - } - } - Funcs.insert(Funcs.end(), Values.begin(), Values.end()); + std::vector Values = Args.getAllArgValues(OPT_fno_builtin_); + auto BuiltinEnd = llvm::partition(Values, [](const std::string FuncName) { + return Builtin::Context::isBuiltinFunc(FuncName); + }); + Funcs.insert(Funcs.end(), Values.begin(), BuiltinEnd); } static void GenerateAnalyzerArgs(AnalyzerOptions &Opts, @@ -1164,8 +1164,8 @@ static void parseAnalyzerConfigs(AnalyzerOptions &AnOpts, } /// Create a new Regex instance out of the string value in \p RpassArg. -/// It returns a pointer to the newly generated Regex instance. -static std::shared_ptr +/// It returns the string and a pointer to the newly generated Regex instance. +static CodeGenOptions::RemarkPattern GenerateOptimizationRemarkRegex(DiagnosticsEngine &Diags, ArgList &Args, Arg *RpassArg) { StringRef Val = RpassArg->getValue(); @@ -1176,7 +1176,7 @@ GenerateOptimizationRemarkRegex(DiagnosticsEngine &Diags, ArgList &Args, << RegexError << RpassArg->getAsString(Args); Pattern.reset(); } - return Pattern; + return {std::string(Val), Pattern}; } static bool parseDiagnosticLevelMask(StringRef FlagName, @@ -1213,6 +1213,12 @@ static void parseSanitizerKinds(StringRef FlagName, } } +static SmallVector serializeSanitizerKinds(SanitizerSet S) { + SmallVector Values; + serializeSanitizerSet(S, Values); + return Values; +} + static void parseXRayInstrumentationBundle(StringRef FlagName, StringRef Bundle, ArgList &Args, DiagnosticsEngine &D, XRayInstrSet &S) { @@ -1232,6 +1238,15 @@ static void parseXRayInstrumentationBundle(StringRef FlagName, StringRef Bundle, } } +static std::string serializeXRayInstrumentationBundle(const XRayInstrSet &S) { + llvm::SmallVector BundleParts; + serializeXRayInstrValue(S, BundleParts); + std::string Buffer; + llvm::raw_string_ostream OS(Buffer); + llvm::interleave(BundleParts, OS, [&OS](StringRef Part) { OS << Part; }, ","); + return OS.str(); +} + // Set the profile kind using fprofile-instrument-use-path. static void setPGOUseInstrumentor(CodeGenOptions &Opts, const Twine &ProfileName) { @@ -1253,12 +1268,258 @@ static void setPGOUseInstrumentor(CodeGenOptions &Opts, Opts.setProfileUse(CodeGenOptions::ProfileClangInstr); } -bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, - InputKind IK, - DiagnosticsEngine &Diags, - const llvm::Triple &T, - const std::string &OutputFile, - const LangOptions &LangOptsRef) { +void CompilerInvocation::GenerateCodeGenArgs( + const CodeGenOptions &Opts, SmallVectorImpl &Args, + StringAllocator SA, const llvm::Triple &T, const std::string &OutputFile, + const LangOptions *LangOpts) { + const CodeGenOptions &CodeGenOpts = Opts; + + if (Opts.OptimizationLevel == 0) + GenerateArg(Args, OPT_O0, SA); + else + GenerateArg(Args, OPT_O, Twine(Opts.OptimizationLevel), SA); + +#define CODEGEN_OPTION_WITH_MARSHALLING( \ + PREFIX_TYPE, NAME, ID, KIND, GROUP, ALIAS, ALIASARGS, FLAGS, PARAM, \ + HELPTEXT, METAVAR, VALUES, SPELLING, SHOULD_PARSE, ALWAYS_EMIT, KEYPATH, \ + DEFAULT_VALUE, IMPLIED_CHECK, IMPLIED_VALUE, NORMALIZER, DENORMALIZER, \ + MERGER, EXTRACTOR, TABLE_INDEX) \ + GENERATE_OPTION_WITH_MARSHALLING( \ + Args, SA, KIND, FLAGS, SPELLING, ALWAYS_EMIT, KEYPATH, DEFAULT_VALUE, \ + IMPLIED_CHECK, IMPLIED_VALUE, DENORMALIZER, EXTRACTOR, TABLE_INDEX) +#include "clang/Driver/Options.inc" +#undef CODEGEN_OPTION_WITH_MARSHALLING + + if (Opts.OptimizationLevel > 0) { + if (Opts.Inlining == CodeGenOptions::NormalInlining) + GenerateArg(Args, OPT_finline_functions, SA); + else if (Opts.Inlining == CodeGenOptions::OnlyHintInlining) + GenerateArg(Args, OPT_finline_hint_functions, SA); + else if (Opts.Inlining == CodeGenOptions::OnlyAlwaysInlining) + GenerateArg(Args, OPT_fno_inline, SA); + } + + if (Opts.DirectAccessExternalData && LangOpts->PICLevel != 0) + GenerateArg(Args, OPT_fdirect_access_external_data, SA); + else if (!Opts.DirectAccessExternalData && LangOpts->PICLevel == 0) + GenerateArg(Args, OPT_fno_direct_access_external_data, SA); + + Optional DebugInfoVal; + switch (Opts.DebugInfo) { + case codegenoptions::DebugLineTablesOnly: + DebugInfoVal = "line-tables-only"; + break; + case codegenoptions::DebugDirectivesOnly: + DebugInfoVal = "line-directives-only"; + break; + case codegenoptions::DebugInfoConstructor: + DebugInfoVal = "constructor"; + break; + case codegenoptions::LimitedDebugInfo: + DebugInfoVal = "limited"; + break; + case codegenoptions::FullDebugInfo: + DebugInfoVal = "standalone"; + break; + case codegenoptions::UnusedTypeInfo: + DebugInfoVal = "unused-types"; + break; + case codegenoptions::NoDebugInfo: // default value + DebugInfoVal = None; + break; + case codegenoptions::LocTrackingOnly: // implied value + DebugInfoVal = None; + break; + } + if (DebugInfoVal) + GenerateArg(Args, OPT_debug_info_kind_EQ, *DebugInfoVal, SA); + + if (Opts.DebugInfo == codegenoptions::DebugInfoConstructor) + GenerateArg(Args, OPT_fuse_ctor_homing, SA); + + for (const auto &Prefix : Opts.DebugPrefixMap) + GenerateArg(Args, OPT_fdebug_prefix_map_EQ, + Prefix.first + "=" + Prefix.second, SA); + + for (const auto &Prefix : Opts.ProfilePrefixMap) + GenerateArg(Args, OPT_fprofile_prefix_map_EQ, + Prefix.first + "=" + Prefix.second, SA); + + if (Opts.NewStructPathTBAA) + GenerateArg(Args, OPT_new_struct_path_tbaa, SA); + + if (Opts.OptimizeSize == 1) + GenerateArg(Args, OPT_O, "s", SA); + else if (Opts.OptimizeSize == 2) + GenerateArg(Args, OPT_O, "z", SA); + + // SimplifyLibCalls is set only in the absence of -fno-builtin and + // -ffreestanding. We'll consider that when generating them. + + // NoBuiltinFuncs are generated by LangOptions. + + if (Opts.UnrollLoops && Opts.OptimizationLevel <= 1) + GenerateArg(Args, OPT_funroll_loops, SA); + else if (!Opts.UnrollLoops && Opts.OptimizationLevel > 1) + GenerateArg(Args, OPT_fno_unroll_loops, SA); + + if (!Opts.BinutilsVersion.empty()) + GenerateArg(Args, OPT_fbinutils_version_EQ, Opts.BinutilsVersion, SA); + + if (Opts.DebugNameTable == + static_cast(llvm::DICompileUnit::DebugNameTableKind::GNU)) + GenerateArg(Args, OPT_ggnu_pubnames, SA); + else if (Opts.DebugNameTable == + static_cast( + llvm::DICompileUnit::DebugNameTableKind::Default)) + GenerateArg(Args, OPT_gpubnames, SA); + + // ProfileInstrumentUsePath is marshalled automatically, no need to generate + // it or PGOUseInstrumentor. + + if (Opts.TimePasses) { + if (Opts.TimePassesPerRun) + GenerateArg(Args, OPT_ftime_report_EQ, "per-pass-run", SA); + else + GenerateArg(Args, OPT_ftime_report, SA); + } + + if (Opts.FunctionSections && + (Opts.BBSections == "none" || Opts.BBSections == "labels")) + GenerateArg(Args, OPT_ffunction_sections, SA); + + if (Opts.PrepareForLTO && !Opts.PrepareForThinLTO) + GenerateArg(Args, OPT_flto, SA); + + if (Opts.PrepareForThinLTO) + GenerateArg(Args, OPT_flto_EQ, "thin", SA); + + if (!Opts.ThinLTOIndexFile.empty()) + GenerateArg(Args, OPT_fthinlto_index_EQ, Opts.ThinLTOIndexFile, SA); + + if (Opts.SaveTempsFilePrefix == OutputFile) + GenerateArg(Args, OPT_save_temps_EQ, "obj", SA); + + StringRef MemProfileBasename("memprof.profraw"); + if (!Opts.MemoryProfileOutput.empty()) { + if (Opts.MemoryProfileOutput == MemProfileBasename) { + GenerateArg(Args, OPT_fmemory_profile, SA); + } else { + size_t ArgLength = + Opts.MemoryProfileOutput.size() - MemProfileBasename.size(); + GenerateArg(Args, OPT_fmemory_profile_EQ, + Opts.MemoryProfileOutput.substr(0, ArgLength), SA); + } + } + + if (memcmp(Opts.CoverageVersion, "408*", 4) != 0) + GenerateArg(Args, OPT_coverage_version_EQ, Opts.CoverageVersion, SA); + + // TODO: Check if we need to generate arguments stored in CmdArgs. (Namely + // '-fembed_bitcode', which does not map to any CompilerInvocation field and + // won't be generated.) + + if (Opts.XRayInstrumentationBundle.Mask != XRayInstrKind::All) { + std::string InstrBundle = + serializeXRayInstrumentationBundle(Opts.XRayInstrumentationBundle); + if (!InstrBundle.empty()) + GenerateArg(Args, OPT_fxray_instrumentation_bundle, InstrBundle, SA); + } + + if (Opts.CFProtectionReturn && Opts.CFProtectionBranch) + GenerateArg(Args, OPT_fcf_protection_EQ, "full", SA); + else if (Opts.CFProtectionReturn) + GenerateArg(Args, OPT_fcf_protection_EQ, "return", SA); + else if (Opts.CFProtectionBranch) + GenerateArg(Args, OPT_fcf_protection_EQ, "branch", SA); + + for (const auto &F : Opts.LinkBitcodeFiles) { + bool Builtint = F.LinkFlags == llvm::Linker::Flags::LinkOnlyNeeded && + F.PropagateAttrs && F.Internalize; + GenerateArg(Args, + Builtint ? OPT_mlink_builtin_bitcode : OPT_mlink_bitcode_file, + F.Filename, SA); + } + + // TODO: Consider removing marshalling annotations from f[no_]emulated_tls. + // That would make it easy to generate the option only **once** if it was + // explicitly set to non-default value. + if (Opts.ExplicitEmulatedTLS) { + GenerateArg( + Args, Opts.EmulatedTLS ? OPT_femulated_tls : OPT_fno_emulated_tls, SA); + } + + if (Opts.FPDenormalMode != llvm::DenormalMode::getIEEE()) { + std::string Buffer; + llvm::raw_string_ostream OS(Buffer); + Opts.FPDenormalMode.print(OS); + GenerateArg(Args, OPT_fdenormal_fp_math_EQ, OS.str(), SA); + } + + if (Opts.FP32DenormalMode != llvm::DenormalMode::getIEEE()) { + std::string Buffer; + llvm::raw_string_ostream OS(Buffer); + Opts.FP32DenormalMode.print(OS); + GenerateArg(Args, OPT_fdenormal_fp_math_f32_EQ, OS.str(), SA); + } + + if (Opts.StructReturnConvention == CodeGenOptions::SRCK_OnStack) { + OptSpecifier Opt = + T.isPPC32() ? OPT_maix_struct_return : OPT_fpcc_struct_return; + GenerateArg(Args, Opt, SA); + } else if (Opts.StructReturnConvention == CodeGenOptions::SRCK_InRegs) { + OptSpecifier Opt = + T.isPPC32() ? OPT_msvr4_struct_return : OPT_freg_struct_return; + GenerateArg(Args, Opt, SA); + } + + if (Opts.IgnoreXCOFFVisibility) + GenerateArg(Args, OPT_mignore_xcoff_visibility, SA); + + if (Opts.EnableAIXExtendedAltivecABI) + GenerateArg(Args, OPT_mabi_EQ_vec_extabi, SA); + + if (!Opts.OptRecordPasses.empty()) + GenerateArg(Args, OPT_opt_record_passes, Opts.OptRecordPasses, SA); + + if (!Opts.OptRecordFormat.empty()) + GenerateArg(Args, OPT_opt_record_format, Opts.OptRecordFormat, SA); + + if (Opts.OptimizationRemarkPattern) + GenerateArg(Args, OPT_Rpass_EQ, Opts.OptimizationRemarkPattern.Pattern, SA); + + if (Opts.OptimizationRemarkMissedPattern) + GenerateArg(Args, OPT_Rpass_missed_EQ, + Opts.OptimizationRemarkMissedPattern.Pattern, SA); + + if (Opts.OptimizationRemarkAnalysisPattern) + GenerateArg(Args, OPT_Rpass_analysis_EQ, + Opts.OptimizationRemarkAnalysisPattern.Pattern, SA); + + GenerateArg(Args, OPT_fdiagnostics_hotness_threshold_EQ, + Opts.DiagnosticsHotnessThreshold + ? Twine(*Opts.DiagnosticsHotnessThreshold) + : "auto", + SA); + + for (StringRef Sanitizer : serializeSanitizerKinds(Opts.SanitizeRecover)) + GenerateArg(Args, OPT_fsanitize_recover_EQ, Sanitizer, SA); + + for (StringRef Sanitizer : serializeSanitizerKinds(Opts.SanitizeTrap)) + GenerateArg(Args, OPT_fsanitize_trap_EQ, Sanitizer, SA); + + if (!Opts.EmitVersionIdentMetadata) + GenerateArg(Args, OPT_Qn, SA); +} + +bool CompilerInvocation::ParseCodeGenArgsImpl(CodeGenOptions &Opts, + ArgList &Args, InputKind IK, + DiagnosticsEngine &Diags, + const llvm::Triple &T, + const std::string &OutputFile, + const LangOptions &LangOptsRef) { + unsigned NumErrorsBefore = Diags.getNumErrors(); + bool Success = true; unsigned OptimizationLevel = getOptimizationLevel(Args, IK, Diags); @@ -1318,7 +1579,24 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, Opts.DirectAccessExternalData = Args.hasArg(OPT_fdirect_access_external_data) || (!Args.hasArg(OPT_fno_direct_access_external_data) && - getLastArgIntValue(Args, OPT_pic_level, 0, Diags) == 0); + LangOpts->PICLevel == 0); + + if (Arg *A = Args.getLastArg(OPT_debug_info_kind_EQ)) { + unsigned Val = + llvm::StringSwitch(A->getValue()) + .Case("line-tables-only", codegenoptions::DebugLineTablesOnly) + .Case("line-directives-only", codegenoptions::DebugDirectivesOnly) + .Case("constructor", codegenoptions::DebugInfoConstructor) + .Case("limited", codegenoptions::LimitedDebugInfo) + .Case("standalone", codegenoptions::FullDebugInfo) + .Case("unused-types", codegenoptions::UnusedTypeInfo) + .Default(~0U); + if (Val == ~0U) + Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) + << A->getValue(); + else + Opts.setDebugInfo(static_cast(Val)); + } // If -fuse-ctor-homing is set and limited debug info is already on, then use // constructor homing. @@ -1355,10 +1633,9 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, Opts.NewStructPathTBAA = !Args.hasArg(OPT_no_struct_path_tbaa) && Args.hasArg(OPT_new_struct_path_tbaa); Opts.OptimizeSize = getOptimizationLevelSize(Args); - Opts.SimplifyLibCalls = !(Args.hasArg(OPT_fno_builtin) || - Args.hasArg(OPT_ffreestanding)); + Opts.SimplifyLibCalls = !LangOpts->NoBuiltin; if (Opts.SimplifyLibCalls) - getAllNoBuiltinFuncValues(Args, Opts.NoBuiltinFuncs); + Opts.NoBuiltinFuncs = LangOpts->NoBuiltinFuncs; Opts.UnrollLoops = Args.hasFlag(OPT_funroll_loops, OPT_fno_unroll_loops, (Opts.OptimizationLevel > 1)); @@ -1433,6 +1710,7 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, } else if (Args.hasArg(OPT_fmemory_profile)) Opts.MemoryProfileOutput = MemProfileBasename; + memcpy(Opts.CoverageVersion, "408*", 4); if (Opts.EmitGcovArcs || Opts.EmitGcovNotes) { if (Args.hasArg(OPT_coverage_version_EQ)) { StringRef CoverageVersion = Args.getLastArgValue(OPT_coverage_version_EQ); @@ -1649,7 +1927,30 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, Opts.EmitVersionIdentMetadata = Args.hasFlag(OPT_Qy, OPT_Qn, true); - return Success; + return Success && Diags.getNumErrors() == NumErrorsBefore; +} + +bool CompilerInvocation::ParseCodeGenArgs( + CompilerInvocation &Res, CodeGenOptions &Opts, ArgList &Args, InputKind IK, + DiagnosticsEngine &Diags, const llvm::Triple &T, + const std::string &OutputFile, const LangOptions &LangOptsRef) { + CodeGenOptions DummyOpts; + + return RoundTrip( + [&](CompilerInvocation &Res, ArgList &Args, DiagnosticsEngine &Diags) { + Args.getLastArg(OPT_O0, OPT_O4, OPT_O, OPT_Ofast); + return ParseCodeGenArgsImpl(Res.getCodeGenOpts(), Args, IK, Diags, T, + OutputFile, LangOptsRef); + }, + [&](CompilerInvocation &Res, SmallVectorImpl &GeneratedArgs, + StringAllocator SA) { + GenerateCodeGenArgs(Res.getCodeGenOpts(), GeneratedArgs, SA, T, + OutputFile, &LangOptsRef); + }, + [&DummyOpts](CompilerInvocation &Res) { + std::swap(Res.CodeGenOpts, DummyOpts); + }, + Res, Args, Diags, "CodeGenOptions"); } static void ParseDependencyOutputArgs(DependencyOutputOptions &Opts, @@ -2642,19 +2943,232 @@ static const StringRef GetInputKindName(InputKind IK) { llvm_unreachable("unknown input language"); } -static void GenerateLangArgs(const LangOptions &Opts, - SmallVectorImpl &Args, - CompilerInvocation::StringAllocator SA) { +void CompilerInvocation::GenerateLangArgs(const LangOptions &Opts, + SmallVectorImpl &Args, + StringAllocator SA, + const llvm::Triple &T) { + OptSpecifier StdOpt; + switch (Opts.LangStd) { + case LangStandard::lang_opencl10: + case LangStandard::lang_opencl11: + case LangStandard::lang_opencl12: + case LangStandard::lang_opencl20: + case LangStandard::lang_opencl30: + case LangStandard::lang_openclcpp: + StdOpt = OPT_cl_std_EQ; + break; + default: + StdOpt = OPT_std_EQ; + break; + } + + auto LangStandard = LangStandard::getLangStandardForKind(Opts.LangStd); + GenerateArg(Args, StdOpt, LangStandard.getName(), SA); + if (Opts.IncludeDefaultHeader) GenerateArg(Args, OPT_finclude_default_header, SA); if (Opts.DeclareOpenCLBuiltins) GenerateArg(Args, OPT_fdeclare_opencl_builtins, SA); + + const LangOptions *LangOpts = &Opts; + +#define LANG_OPTION_WITH_MARSHALLING( \ + PREFIX_TYPE, NAME, ID, KIND, GROUP, ALIAS, ALIASARGS, FLAGS, PARAM, \ + HELPTEXT, METAVAR, VALUES, SPELLING, SHOULD_PARSE, ALWAYS_EMIT, KEYPATH, \ + DEFAULT_VALUE, IMPLIED_CHECK, IMPLIED_VALUE, NORMALIZER, DENORMALIZER, \ + MERGER, EXTRACTOR, TABLE_INDEX) \ + GENERATE_OPTION_WITH_MARSHALLING( \ + Args, SA, KIND, FLAGS, SPELLING, ALWAYS_EMIT, KEYPATH, DEFAULT_VALUE, \ + IMPLIED_CHECK, IMPLIED_VALUE, DENORMALIZER, EXTRACTOR, TABLE_INDEX) +#include "clang/Driver/Options.inc" +#undef LANG_OPTION_WITH_MARSHALLING + + // The '-fcf-protection=' option is generated by CodeGenOpts generator. + + if (Opts.ObjC) { + std::string Buffer; + llvm::raw_string_ostream Stream(Buffer); + Stream << Opts.ObjCRuntime; + GenerateArg(Args, OPT_fobjc_runtime_EQ, Stream.str(), SA); + + if (Opts.GC == LangOptions::GCOnly) + GenerateArg(Args, OPT_fobjc_gc_only, SA); + else if (Opts.GC == LangOptions::HybridGC) + GenerateArg(Args, OPT_fobjc_gc, SA); + else if (Opts.ObjCAutoRefCount == 1) + GenerateArg(Args, OPT_fobjc_arc, SA); + + if (Opts.ObjCWeakRuntime) + GenerateArg(Args, OPT_fobjc_runtime_has_weak, SA); + + if (Opts.ObjCWeak) + GenerateArg(Args, OPT_fobjc_weak, SA); + + if (Opts.ObjCSubscriptingLegacyRuntime) + GenerateArg(Args, OPT_fobjc_subscripting_legacy_runtime, SA); + } + + if (Opts.GNUCVersion != 0) { + unsigned Major = Opts.GNUCVersion / 100 / 100; + unsigned Minor = (Opts.GNUCVersion / 100) % 100; + unsigned Patch = Opts.GNUCVersion % 100; + GenerateArg(Args, OPT_fgnuc_version_EQ, + Twine(Major) + "." + Twine(Minor) + "." + Twine(Patch), SA); + } + + if (Opts.SignedOverflowBehavior == LangOptions::SOB_Trapping) { + GenerateArg(Args, OPT_ftrapv, SA); + GenerateArg(Args, OPT_ftrapv_handler, Opts.OverflowHandler, SA); + } else if (Opts.SignedOverflowBehavior == LangOptions::SOB_Defined) { + GenerateArg(Args, OPT_fwrapv, SA); + } + + if (Opts.MSCompatibilityVersion != 0) { + unsigned Major = Opts.MSCompatibilityVersion / 10000000; + unsigned Minor = (Opts.MSCompatibilityVersion / 100000) % 100; + unsigned Subminor = Opts.MSCompatibilityVersion % 100000; + GenerateArg(Args, OPT_fms_compatibility_version, + Twine(Major) + "." + Twine(Minor) + "." + Twine(Subminor), SA); + } + + if ((!Opts.GNUMode && !Opts.MSVCCompat && !Opts.CPlusPlus17) || T.isOSzOS()) { + if (!Opts.Trigraphs) + GenerateArg(Args, OPT_fno_trigraphs, SA); + } else { + if (Opts.Trigraphs) + GenerateArg(Args, OPT_ftrigraphs, SA); + } + + if (Opts.Blocks && !(Opts.OpenCL && Opts.OpenCLVersion == 200)) + GenerateArg(Args, OPT_fblocks, SA); + + if (Opts.ConvergentFunctions && + !(Opts.OpenCL || (Opts.CUDA && Opts.CUDAIsDevice) || Opts.SYCLIsDevice)) + GenerateArg(Args, OPT_fconvergent_functions, SA); + + if (Opts.NoBuiltin && !Opts.Freestanding) + GenerateArg(Args, OPT_fno_builtin, SA); + + if (!Opts.NoBuiltin) + for (const auto &Func : Opts.NoBuiltinFuncs) + GenerateArg(Args, OPT_fno_builtin_, Func, SA); + + if (Opts.LongDoubleSize == 128) + GenerateArg(Args, OPT_mlong_double_128, SA); + else if (Opts.LongDoubleSize == 64) + GenerateArg(Args, OPT_mlong_double_64, SA); + + // Not generating '-mrtd', it's just an alias for '-fdefault-calling-conv='. + + // OpenMP was requested via '-fopenmp', not implied by '-fopenmp-simd' or + // '-fopenmp-targets='. + if (Opts.OpenMP && !Opts.OpenMPSimd) { + GenerateArg(Args, OPT_fopenmp, SA); + + if (Opts.OpenMP != 50) + GenerateArg(Args, OPT_fopenmp_version_EQ, Twine(Opts.OpenMP), SA); + + if (!Opts.OpenMPUseTLS) + GenerateArg(Args, OPT_fnoopenmp_use_tls, SA); + + if (Opts.OpenMPIsDevice) + GenerateArg(Args, OPT_fopenmp_is_device, SA); + + if (Opts.OpenMPIRBuilder) + GenerateArg(Args, OPT_fopenmp_enable_irbuilder, SA); + } + + if (Opts.OpenMPSimd) { + GenerateArg(Args, OPT_fopenmp_simd, SA); + + if (Opts.OpenMP != 50) + GenerateArg(Args, OPT_fopenmp_version_EQ, Twine(Opts.OpenMP), SA); + } + + if (Opts.OpenMPCUDANumSMs != 0) + GenerateArg(Args, OPT_fopenmp_cuda_number_of_sm_EQ, + Twine(Opts.OpenMPCUDANumSMs), SA); + + if (Opts.OpenMPCUDABlocksPerSM != 0) + GenerateArg(Args, OPT_fopenmp_cuda_blocks_per_sm_EQ, + Twine(Opts.OpenMPCUDABlocksPerSM), SA); + + if (Opts.OpenMPCUDAReductionBufNum != 1024) + GenerateArg(Args, OPT_fopenmp_cuda_teams_reduction_recs_num_EQ, + Twine(Opts.OpenMPCUDAReductionBufNum), SA); + + if (!Opts.OMPTargetTriples.empty()) { + std::string Targets; + llvm::raw_string_ostream OS(Targets); + llvm::interleave( + Opts.OMPTargetTriples, OS, + [&OS](const llvm::Triple &T) { OS << T.str(); }, ","); + GenerateArg(Args, OPT_fopenmp_targets_EQ, OS.str(), SA); + } + + if (!Opts.OMPHostIRFile.empty()) + GenerateArg(Args, OPT_fopenmp_host_ir_file_path, Opts.OMPHostIRFile, SA); + + if (Opts.OpenMPCUDAMode) + GenerateArg(Args, OPT_fopenmp_cuda_mode, SA); + + if (Opts.OpenMPCUDATargetParallel) + GenerateArg(Args, OPT_fopenmp_cuda_parallel_target_regions, SA); + + if (Opts.OpenMPCUDAForceFullRuntime) + GenerateArg(Args, OPT_fopenmp_cuda_force_full_runtime, SA); + + // The arguments used to set 'Optimize' and 'OptimizeSize' will be generated + // by CodeGenOptions. + + if (Opts.NoInlineDefine && Opts.Optimize) + GenerateArg(Args, OPT_fno_inline, SA); + + if (Opts.DefaultFPContractMode == LangOptions::FPM_Fast) + GenerateArg(Args, OPT_ffp_contract, "fast", SA); + else if (Opts.DefaultFPContractMode == LangOptions::FPM_On) + GenerateArg(Args, OPT_ffp_contract, "on", SA); + else if (Opts.DefaultFPContractMode == LangOptions::FPM_Off) + GenerateArg(Args, OPT_ffp_contract, "off", SA); + else if (Opts.DefaultFPContractMode == LangOptions::FPM_FastHonorPragmas) + GenerateArg(Args, OPT_ffp_contract, "fast-honor-pragmas", SA); + + for (StringRef Sanitizer : serializeSanitizerKinds(Opts.Sanitize)) + GenerateArg(Args, OPT_fsanitize_EQ, Sanitizer, SA); + + // Conflating '-fsanitize-system-blacklist' and '-fsanitize-blacklist'. + for (const std::string &F : Opts.SanitizerBlacklistFiles) + GenerateArg(Args, OPT_fsanitize_blacklist, F, SA); + + if (Opts.getClangABICompat() == LangOptions::ClangABI::Ver3_8) + GenerateArg(Args, OPT_fclang_abi_compat_EQ, "3.8", SA); + else if (Opts.getClangABICompat() == LangOptions::ClangABI::Ver4) + GenerateArg(Args, OPT_fclang_abi_compat_EQ, "4.0", SA); + else if (Opts.getClangABICompat() == LangOptions::ClangABI::Ver6) + GenerateArg(Args, OPT_fclang_abi_compat_EQ, "6.0", SA); + else if (Opts.getClangABICompat() == LangOptions::ClangABI::Ver7) + GenerateArg(Args, OPT_fclang_abi_compat_EQ, "7.0", SA); + else if (Opts.getClangABICompat() == LangOptions::ClangABI::Ver9) + GenerateArg(Args, OPT_fclang_abi_compat_EQ, "9.0", SA); + else if (Opts.getClangABICompat() == LangOptions::ClangABI::Ver11) + GenerateArg(Args, OPT_fclang_abi_compat_EQ, "11.0", SA); + + if (Opts.getSignReturnAddressScope() == + LangOptions::SignReturnAddressScopeKind::All) + GenerateArg(Args, OPT_msign_return_address_EQ, "all", SA); + else if (Opts.getSignReturnAddressScope() == + LangOptions::SignReturnAddressScopeKind::NonLeaf) + GenerateArg(Args, OPT_msign_return_address_EQ, "non-leaf", SA); + + if (Opts.getSignReturnAddressKey() == + LangOptions::SignReturnAddressKeyKind::BKey) + GenerateArg(Args, OPT_msign_return_address_key_EQ, "b_key", SA); } -bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, - InputKind IK, const llvm::Triple &T, - std::vector &Includes, - DiagnosticsEngine &Diags) { +bool CompilerInvocation::ParseLangArgsImpl(LangOptions &Opts, ArgList &Args, + InputKind IK, const llvm::Triple &T, + std::vector &Includes, + DiagnosticsEngine &Diags) { unsigned NumErrorsBefore = Diags.getNumErrors(); // FIXME: Cleanup per-file based stuff. @@ -2898,6 +3412,8 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, } } + // Check if -fopenmp is specified and set default version to 5.0. + Opts.OpenMP = Args.hasArg(OPT_fopenmp) ? 50 : 0; // Check if -fopenmp-simd is specified. bool IsSimdSpecified = Args.hasFlag(options::OPT_fopenmp_simd, options::OPT_fno_openmp_simd, @@ -3041,6 +3557,7 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, // Parse -fsanitize= arguments. parseSanitizerKinds("-fsanitize=", Args.getAllArgValues(OPT_fsanitize_EQ), Diags, Opts.Sanitize); + Opts.SanitizerBlacklistFiles = Args.getAllArgValues(OPT_fsanitize_blacklist); std::vector systemBlacklists = Args.getAllArgValues(OPT_fsanitize_system_blacklist); Opts.SanitizerBlacklistFiles.insert(Opts.SanitizerBlacklistFiles.end(), @@ -3117,6 +3634,55 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, return Success && Diags.getNumErrors() == NumErrorsBefore; } +bool CompilerInvocation::ParseLangArgs(CompilerInvocation &Res, + LangOptions &Opts, + llvm::opt::ArgList &Args, InputKind IK, + const llvm::Triple &T, + std::vector &Includes, + DiagnosticsEngine &Diags) { + auto DummyOpts = std::make_shared(); + + // We need to work around inconsistencies related to optimization flags. Their + // primary consumer is CodeGenOptions. However, the LangOptions parser also + // queries them, which means RoundTrip expects us to generate them. We don't + // want to do it in GenerateLangArgs, because it should eventually be the + // responsibility of GenerateCodeGenArgs. Until we start doing one big + // round-trip, let's do it here. + // + // Our parser always queries OPT_O_Group. When given -O1, -O2 or -O3, it also + // queries OPT_O. To ensure RoundTrip consistently considers us responsible + // for generating all of them, we ensure to proactively query them all. + + return RoundTrip( + [IK, &T, &Includes](CompilerInvocation &Res, ArgList &Args, + DiagnosticsEngine &Diags) { + // Proactively query all optimization flags. + Args.getLastArg(OPT_O0, OPT_O4, OPT_O, OPT_Ofast); + return ParseLangArgsImpl(*Res.getLangOpts(), Args, IK, T, Includes, + Diags); + }, + [&T, &Args](CompilerInvocation &Res, + SmallVectorImpl &GenArgs, StringAllocator SA) { + GenerateLangArgs(*Res.getLangOpts(), GenArgs, SA, T); + // Generate all optimization flags we queried. + if (Arg *A = Args.getLastArg(OPT_O_Group)) { + OptSpecifier Opt = A->getOption().getID(); + + if (A->getNumValues() > 0) + GenerateArg(GenArgs, Opt, A->getValues().back(), SA); + else + GenerateArg(GenArgs, Opt, SA); + } + + // We also queried -fcf-protection, but don't have enough information to + // generate it. Eventually, it will be generated from CodeGenOptions. + if (const Arg *A = Args.getLastArg(OPT_fcf_protection_EQ)) + GenerateArg(GenArgs, OPT_fcf_protection_EQ, A->getValue(), SA); + }, + [&DummyOpts](CompilerInvocation &Res) { Res.LangOpts.swap(DummyOpts); }, + Res, Args, Diags, "LangOptions"); +} + static bool isStrictlyPreprocessorAction(frontend::ActionKind Action) { switch (Action) { case frontend::ASTDeclList: @@ -3455,7 +4021,7 @@ bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res, } else { // Other LangOpts are only initialized when the input is not AST or LLVM IR. // FIXME: Should we really be calling this for an Language::Asm input? - Success &= ParseLangArgs(LangOpts, Args, DashX, T, + Success &= ParseLangArgs(Res, LangOpts, Args, DashX, T, Res.getPreprocessorOpts().Includes, Diags); if (Res.getFrontendOpts().ProgramAction == frontend::RewriteObjC) LangOpts.ObjCExceptions = 1; @@ -3482,7 +4048,7 @@ bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res, if (LangOpts.SYCLIsDevice) Res.getTargetOpts().HostTriple = Res.getFrontendOpts().AuxTriple; - Success &= ParseCodeGenArgs(Res.getCodeGenOpts(), Args, DashX, Diags, T, + Success &= ParseCodeGenArgs(Res, Res.getCodeGenOpts(), Args, DashX, Diags, T, Res.getFrontendOpts().OutputFile, LangOpts); // FIXME: Override value name discarding when asan or msan is used because the @@ -3646,19 +4212,19 @@ void CompilerInvocation::generateCC1CommandLine( EXTRACTOR, TABLE_INDEX) #define DIAG_OPTION_WITH_MARSHALLING OPTION_WITH_MARSHALLING -#define LANG_OPTION_WITH_MARSHALLING OPTION_WITH_MARSHALLING -#define CODEGEN_OPTION_WITH_MARSHALLING OPTION_WITH_MARSHALLING #include "clang/Driver/Options.inc" -#undef CODEGEN_OPTION_WITH_MARSHALLING -#undef LANG_OPTION_WITH_MARSHALLING #undef DIAG_OPTION_WITH_MARSHALLING #undef OPTION_WITH_MARSHALLING + llvm::Triple T(TargetOpts->Triple); + GenerateAnalyzerArgs(*AnalyzerOpts, Args, SA); GenerateHeaderSearchArgs(*HeaderSearchOpts, Args, SA); - GenerateLangArgs(*LangOpts, Args, SA); + GenerateLangArgs(*LangOpts, Args, SA, T); + GenerateCodeGenArgs(CodeGenOpts, Args, SA, T, FrontendOpts.OutputFile, + &*LangOpts); GeneratePreprocessorArgs(*PreprocessorOpts, Args, SA, *LangOpts, FrontendOpts, CodeGenOpts); } diff --git a/clang/test/SemaObjC/warn-called-once.m b/clang/test/SemaObjC/warn-called-once.m index 094f92a49935b..0c11d0e0a15bf 100644 --- a/clang/test/SemaObjC/warn-called-once.m +++ b/clang/test/SemaObjC/warn-called-once.m @@ -4,6 +4,11 @@ #define nil (id)0 #define CALLED_ONCE __attribute__((called_once)) #define NORETURN __attribute__((noreturn)) +#define LIKELY(X) __builtin_expect(!!(X), 1) +#define UNLIKELY(X) __builtin_expect(!!(X), 0) +#define LIKELY_WITH_PROBA(X, P) __builtin_expect_with_probability(!!(X), 1, P) +#define UNLIKELY_WITH_PROBA(X, P) __builtin_expect_with_probability(!!(X), 0, P) +#define UNPRED(X) __builtin_unpredictable((long)(X)) @protocol NSObject @end @@ -547,6 +552,70 @@ int call_with_check_7(int (^callback)(void) CALLED_ONCE) { // no-warning } +void call_with_builtin_check_1(int (^callback)(void) CALLED_ONCE) { + if (LIKELY(callback)) + callback(); + // no-warning +} + +void call_with_builtin_check_2(int (^callback)(void) CALLED_ONCE) { + if (!UNLIKELY(callback)) { + } else { + callback(); + } + // no-warning +} + +void call_with_builtin_check_3(int (^callback)(void) CALLED_ONCE) { + if (__builtin_expect((long)callback, 0L)) { + } else { + callback(); + } + // no-warning +} + +void call_with_builtin_check_4(int (^callback)(void) CALLED_ONCE) { + if (__builtin_expect(0L, (long)callback)) { + } else { + callback(); + } + // no-warning +} + +void call_with_builtin_check_5(int (^callback)(void) CALLED_ONCE) { + if (LIKELY_WITH_PROBA(callback, 0.9)) + callback(); + // no-warning +} + +void call_with_builtin_check_6(int (^callback)(void) CALLED_ONCE) { + if (!UNLIKELY_WITH_PROBA(callback, 0.9)) { + } else { + callback(); + } + // no-warning +} + +void call_with_builtin_check_7(int (^callback)(void) CALLED_ONCE) { + if (UNPRED(callback)) { + } else { + callback(); + } + // no-warning +} + +void call_with_builtin_check_8(int (^callback)(void) CALLED_ONCE) { + if (LIKELY(callback != nil)) + callback(); + // no-warning +} + +void call_with_builtin_check_9(int (^callback)(void) CALLED_ONCE) { + if (!UNLIKELY(callback == NULL)) + callback(); + // no-warning +} + void unreachable_true_branch(void (^callback)(void) CALLED_ONCE) { if (0) { diff --git a/clang/unittests/Basic/CMakeLists.txt b/clang/unittests/Basic/CMakeLists.txt index add190b4ab0fa..9d23a069968a8 100644 --- a/clang/unittests/Basic/CMakeLists.txt +++ b/clang/unittests/Basic/CMakeLists.txt @@ -8,6 +8,7 @@ add_clang_unittest(BasicTests FileEntryTest.cpp FileManagerTest.cpp LineOffsetMappingTest.cpp + SanitizersTest.cpp SourceManagerTest.cpp ) diff --git a/clang/unittests/Basic/SanitizersTest.cpp b/clang/unittests/Basic/SanitizersTest.cpp new file mode 100644 index 0000000000000..c6537cbf71a94 --- /dev/null +++ b/clang/unittests/Basic/SanitizersTest.cpp @@ -0,0 +1,49 @@ +//===- unittests/Basic/SanitizersTest.cpp - Test Sanitizers ---------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "clang/Basic/Sanitizers.h" + +#include "gmock/gmock-matchers.h" +#include "gtest/gtest.h" + +using namespace clang; + +using testing::Contains; +using testing::Not; + +TEST(SanitizersTest, serializeSanitizers) { + SanitizerSet Set; + Set.set(parseSanitizerValue("memory", false), true); + Set.set(parseSanitizerValue("nullability-arg", false), true); + + SmallVector Serialized; + serializeSanitizerSet(Set, Serialized); + + ASSERT_EQ(Serialized.size(), 2u); + ASSERT_THAT(Serialized, Contains("memory")); + ASSERT_THAT(Serialized, Contains("nullability-arg")); +} + +TEST(SanitizersTest, serializeSanitizersIndividual) { + SanitizerSet Set; + Set.set(parseSanitizerValue("memory", false), true); + Set.set(parseSanitizerValue("nullability-arg", false), true); + Set.set(parseSanitizerValue("nullability-assign", false), true); + Set.set(parseSanitizerValue("nullability-return", false), true); + + SmallVector Serialized; + serializeSanitizerSet(Set, Serialized); + + ASSERT_EQ(Serialized.size(), 4u); + ASSERT_THAT(Serialized, Contains("memory")); + ASSERT_THAT(Serialized, Contains("nullability-arg")); + ASSERT_THAT(Serialized, Contains("nullability-assign")); + ASSERT_THAT(Serialized, Contains("nullability-return")); + // Individual sanitizers don't get squashed into a single group. + ASSERT_THAT(Serialized, Not(Contains("nullability"))); +} diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp index fe722ebd48912..4e10b02f04bf8 100644 --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -144,8 +144,7 @@ static std::tuple parseEmulation(StringRef emul) { std::pair ret = StringSwitch>(s) - .Cases("aarch64elf", "aarch64linux", "aarch64_elf64_le_vec", - {ELF64LEKind, EM_AARCH64}) + .Cases("aarch64elf", "aarch64linux", {ELF64LEKind, EM_AARCH64}) .Cases("aarch64elfb", "aarch64linuxb", {ELF64BEKind, EM_AARCH64}) .Cases("armelf", "armelf_linux_eabi", {ELF32LEKind, EM_ARM}) .Case("elf32_x86_64", {ELF32LEKind, EM_X86_64}) diff --git a/lld/ELF/DriverUtils.cpp b/lld/ELF/DriverUtils.cpp index fd649808c0607..a3fc522c708c2 100644 --- a/lld/ELF/DriverUtils.cpp +++ b/lld/ELF/DriverUtils.cpp @@ -186,6 +186,9 @@ std::string elf::createResponseFile(const opt::InputArgList &args) { // Strip directories to prevent the issue. os << "-o " << quote(path::filename(arg->getValue())) << "\n"; break; + case OPT_lto_sample_profile: + os << arg->getSpelling() << quote(rewritePath(arg->getValue())) << "\n"; + break; case OPT_call_graph_ordering_file: case OPT_dynamic_list: case OPT_just_symbols: diff --git a/lld/test/ELF/emulation-aarch64.s b/lld/test/ELF/emulation-aarch64.s index 2d26a1e8e64e2..68db8b4fefb06 100644 --- a/lld/test/ELF/emulation-aarch64.s +++ b/lld/test/ELF/emulation-aarch64.s @@ -9,8 +9,6 @@ # RUN: echo 'OUTPUT_FORMAT(elf64-littleaarch64)' > %t.script # RUN: ld.lld %t.script %t.o -o %t3 # RUN: llvm-readobj --file-headers %t3 | FileCheck --check-prefixes=AARCH64,LE %s -# RUN: ld.lld -m aarch64_elf64_le_vec %t.o -o %taosp -# RUN: llvm-readobj --file-headers %taosp | FileCheck --check-prefixes=AARCH64,LE %s # RUN: llvm-mc -filetype=obj -triple=aarch64_be %s -o %t.be.o # RUN: ld.lld %t.be.o -o %t diff --git a/lld/test/ELF/reproduce-lto.s b/lld/test/ELF/reproduce-lto.s index 36838f21388ef..2e673fdcc32ce 100644 --- a/lld/test/ELF/reproduce-lto.s +++ b/lld/test/ELF/reproduce-lto.s @@ -10,8 +10,13 @@ # RUN: cd %t.dir # RUN: ld.lld build1/foo.o -o /dev/null --reproduce repro1.tar --lto-sample-profile=%t.dir/build1/empty_profile.txt # RUN: tar tvf repro1.tar | FileCheck %s --implicit-check-not={{.}} +# RUN: tar xvf repro1.tar &> %t2 +# RUN: cat repro1/response.txt >> %t2 +# RUN: FileCheck %s --check-prefix=RSP < %t2 # CHECK-DAG: {{.*}} repro1/{{.*}}/empty_profile.txt # CHECK-DAG: {{.*}} repro1/response.txt # CHECK-DAG: {{.*}} repro1/version.txt # CHECK-DAG: {{.*}} repro1/{{.*}}/foo.o +# RSP: repro1/[[PATH:.*]]/empty_profile.txt +# RSP: --lto-sample-profile=[[PATH]]/empty_profile.txt diff --git a/lld/wasm/Driver.cpp b/lld/wasm/Driver.cpp index 830e4bf1744ff..5927d1b53e7d5 100644 --- a/lld/wasm/Driver.cpp +++ b/lld/wasm/Driver.cpp @@ -596,8 +596,7 @@ static GlobalSymbol *createGlobalVariable(StringRef name, bool isMutable) { static GlobalSymbol *createOptionalGlobal(StringRef name, bool isMutable) { InputGlobal *g = createGlobal(name, isMutable); - return symtab->addOptionalGlobalSymbols(name, WASM_SYMBOL_VISIBILITY_HIDDEN, - g); + return symtab->addOptionalGlobalSymbol(name, g); } // Create ABI-defined synthetic symbols diff --git a/lld/wasm/SymbolTable.cpp b/lld/wasm/SymbolTable.cpp index d93b2a14dc5a1..aab97d9de6815 100644 --- a/lld/wasm/SymbolTable.cpp +++ b/lld/wasm/SymbolTable.cpp @@ -258,16 +258,16 @@ DefinedGlobal *SymbolTable::addSyntheticGlobal(StringRef name, uint32_t flags, nullptr, global); } -DefinedGlobal *SymbolTable::addOptionalGlobalSymbols(StringRef name, - uint32_t flags, - InputGlobal *global) { - LLVM_DEBUG(dbgs() << "addOptionalGlobalSymbols: " << name << " -> " << global +DefinedGlobal *SymbolTable::addOptionalGlobalSymbol(StringRef name, + InputGlobal *global) { + LLVM_DEBUG(dbgs() << "addOptionalGlobalSymbol: " << name << " -> " << global << "\n"); Symbol *s = find(name); if (!s || s->isDefined()) return nullptr; syntheticGlobals.emplace_back(global); - return replaceSymbol(s, name, flags, nullptr, global); + return replaceSymbol(s, name, WASM_SYMBOL_VISIBILITY_HIDDEN, + nullptr, global); } DefinedTable *SymbolTable::addSyntheticTable(StringRef name, uint32_t flags, diff --git a/lld/wasm/SymbolTable.h b/lld/wasm/SymbolTable.h index ce7219c3ba4f5..f3510f82fc8a0 100644 --- a/lld/wasm/SymbolTable.h +++ b/lld/wasm/SymbolTable.h @@ -91,8 +91,7 @@ class SymbolTable { DefinedFunction *addSyntheticFunction(StringRef name, uint32_t flags, InputFunction *function); DefinedData *addOptionalDataSymbol(StringRef name, uint64_t value = 0); - DefinedGlobal *addOptionalGlobalSymbols(StringRef name, uint32_t flags, - InputGlobal *global); + DefinedGlobal *addOptionalGlobalSymbol(StringRef name, InputGlobal *global); DefinedTable *addSyntheticTable(StringRef name, uint32_t flags, InputTable *global); diff --git a/llvm/docs/CommandGuide/tblgen.rst b/llvm/docs/CommandGuide/tblgen.rst index db2417120b59a..530649646828a 100644 --- a/llvm/docs/CommandGuide/tblgen.rst +++ b/llvm/docs/CommandGuide/tblgen.rst @@ -138,7 +138,7 @@ llvm-tblgen Options .. option:: -gen-compress-inst-emitter - Generate RISCV compressed instructions. + Generate RISC-V compressed instructions. .. option:: -gen-ctags diff --git a/llvm/include/llvm/Option/OptParser.td b/llvm/include/llvm/Option/OptParser.td index 9a179c511bd6c..c85c6c56c8ea9 100644 --- a/llvm/include/llvm/Option/OptParser.td +++ b/llvm/include/llvm/Option/OptParser.td @@ -175,7 +175,7 @@ class MarshallingInfoString : MarshallingInfo { code Normalizer = "normalizeStringIntegral<"#type#">"; - code Denormalizer = "denormalizeString"; + code Denormalizer = "denormalizeString<"#type#">"; } class MarshallingInfoStringVector diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index dcf7525d74580..123d2795338fd 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -894,6 +894,21 @@ static MCRegister convertFPR64ToFPR32(MCRegister Reg) { return Reg - RISCV::F0_D + RISCV::F0_F; } +static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg, + unsigned Kind) { + unsigned RegClassID; + if (Kind == MCK_VRM2) + RegClassID = RISCV::VRM2RegClassID; + else if (Kind == MCK_VRM4) + RegClassID = RISCV::VRM4RegClassID; + else if (Kind == MCK_VRM8) + RegClassID = RISCV::VRM8RegClassID; + else + return 0; + return RI.getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, + &RISCVMCRegisterClasses[RegClassID]); +} + unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, unsigned Kind) { RISCVOperand &Op = static_cast(AsmOp); @@ -905,6 +920,7 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg); bool IsRegFPR64C = RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg); + bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg); // As the parser couldn't differentiate an FPR32 from an FPR64, coerce the // register from FPR64 to FPR32 or FPR64C to FPR32C if necessary. @@ -919,6 +935,14 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, Op.Reg.RegNum = convertFPR64ToFPR16(Reg); return Match_Success; } + // As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce + // the register from VR to VRM2/VRM4/VRM8 if necessary. + if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) { + Op.Reg.RegNum = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind); + if (Op.Reg.RegNum == 0) + return Match_InvalidOperand; + return Match_Success; + } return Match_InvalidOperand; } diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 623552390f53c..504a78d91f321 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -172,6 +172,66 @@ static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= 32) + return MCDisassembler::Fail; + + if (RegNo % 2) + return MCDisassembler::Fail; + + const RISCVDisassembler *Dis = + static_cast(Decoder); + const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo(); + MCRegister Reg = + RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, + &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]); + + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= 32) + return MCDisassembler::Fail; + + if (RegNo % 4) + return MCDisassembler::Fail; + + const RISCVDisassembler *Dis = + static_cast(Decoder); + const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo(); + MCRegister Reg = + RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, + &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]); + + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= 32) + return MCDisassembler::Fail; + + if (RegNo % 8) + return MCDisassembler::Fail; + + const RISCVDisassembler *Dis = + static_cast(Decoder); + const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo(); + MCRegister Reg = + RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, + &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]); + + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { MCRegister Reg = RISCV::NoRegister; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 86fbc73d81d51..9b2c0a20f5fde 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -110,9 +110,9 @@ class VIndexedLoad "$vd, (${rs1}), $vs2$vm">; // vlr.v vd, (rs1) -class VWholeLoad nf, RISCVWidth width, string opcodestr> +class VWholeLoad nf, RISCVWidth width, string opcodestr, RegisterClass VRC> : RVInstVLU { let vm = 1; let Uses = []; @@ -169,9 +169,9 @@ class VIndexedStore opcodestr, "$vs3, (${rs1}), $vs2$vm">; // vsr.v vd, (rs1) -class VWholeStore nf, string opcodestr> +class VWholeStore nf, string opcodestr, RegisterClass VRC> : RVInstVSU { let vm = 1; let Uses = []; @@ -430,11 +430,11 @@ multiclass VAMO { def _UNWD : VAMONoWd; } -multiclass VWholeLoad nf, string opcodestr> { - def E8_V : VWholeLoad; - def E16_V : VWholeLoad; - def E32_V : VWholeLoad; - def E64_V : VWholeLoad; +multiclass VWholeLoad nf, string opcodestr, RegisterClass VRC> { + def E8_V : VWholeLoad; + def E16_V : VWholeLoad; + def E32_V : VWholeLoad; + def E64_V : VWholeLoad; } //===----------------------------------------------------------------------===// @@ -504,19 +504,19 @@ def VSOXEI16_V : VIndexedStore; def VSOXEI32_V : VIndexedStore; def VSOXEI64_V : VIndexedStore; -defm VL1R : VWholeLoad<1, "vl1r">; -defm VL2R : VWholeLoad<2, "vl2r">; -defm VL4R : VWholeLoad<4, "vl4r">; -defm VL8R : VWholeLoad<8, "vl8r">; +defm VL1R : VWholeLoad<1, "vl1r", VR>; +defm VL2R : VWholeLoad<2, "vl2r", VRM2>; +defm VL4R : VWholeLoad<4, "vl4r", VRM4>; +defm VL8R : VWholeLoad<8, "vl8r", VRM8>; def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; -def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VR:$vd, GPR:$rs1)>; -def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VR:$vd, GPR:$rs1)>; -def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VR:$vd, GPR:$rs1)>; - -def VS1R_V : VWholeStore<1, "vs1r.v">; -def VS2R_V : VWholeStore<2, "vs2r.v">; -def VS4R_V : VWholeStore<4, "vs4r.v">; -def VS8R_V : VWholeStore<8, "vs8r.v">; +def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>; +def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>; +def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>; + +def VS1R_V : VWholeStore<1, "vs1r.v", VR>; +def VS2R_V : VWholeStore<2, "vs2r.v", VRM2>; +def VS4R_V : VWholeStore<4, "vs4r.v", VRM4>; +def VS8R_V : VWholeStore<8, "vs8r.v", VRM8>; // Vector Single-Width Integer Add and Subtract defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 7f71affcb3d94..eb49f20275ca9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -186,14 +186,16 @@ class GroupVTypeInfo AllVectors = { defset list AllIntegerVectors = { defset list NoGroupIntegerVectors = { - def VI8MF8: VTypeInfo; - def VI8MF4: VTypeInfo; - def VI8MF2: VTypeInfo; + defset list FractionalGroupIntegerVectors = { + def VI8MF8: VTypeInfo; + def VI8MF4: VTypeInfo; + def VI8MF2: VTypeInfo; + def VI16MF4: VTypeInfo; + def VI16MF2: VTypeInfo; + def VI32MF2: VTypeInfo; + } def VI8M1: VTypeInfo; - def VI16MF4: VTypeInfo; - def VI16MF2: VTypeInfo; def VI16M1: VTypeInfo; - def VI32MF2: VTypeInfo; def VI32M1: VTypeInfo; def VI64M1: VTypeInfo; } @@ -218,13 +220,13 @@ defset list AllVectors = { defset list AllFloatVectors = { defset list NoGroupFloatVectors = { - def VF16MF4: VTypeInfo; - def VF16MF2: VTypeInfo; + defset list FractionalGroupFloatVectors = { + def VF16MF4: VTypeInfo; + def VF16MF2: VTypeInfo; + def VF32MF2: VTypeInfo; + } def VF16M1: VTypeInfo; - - def VF32MF2: VTypeInfo; def VF32M1: VTypeInfo; - def VF64M1: VTypeInfo; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index f28bbe55560e5..e2d308c220139 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -67,6 +67,30 @@ multiclass VPatUSLoadStoreSDNode; } +multiclass VPatUSLoadStoreWholeVRSDNode +{ + defvar load_instr = + !cond(!eq(vlmul.value, V_M1.value): !cast("VL1RE"#sew#"_V"), + !eq(vlmul.value, V_M2.value): !cast("VL2RE"#sew#"_V"), + !eq(vlmul.value, V_M4.value): !cast("VL4RE"#sew#"_V"), + !eq(vlmul.value, V_M8.value): !cast("VL8RE"#sew#"_V")); + defvar store_instr = + !cond(!eq(vlmul.value, V_M1.value): VS1R_V, + !eq(vlmul.value, V_M2.value): VS2R_V, + !eq(vlmul.value, V_M4.value): VS4R_V, + !eq(vlmul.value, V_M8.value): VS8R_V); + + // Load + def : Pat<(type (load RVVBaseAddr:$rs1)), + (load_instr RVVBaseAddr:$rs1)>; + // Store + def : Pat<(store type:$rs2, RVVBaseAddr:$rs1), + (store_instr reg_class:$rs2, RVVBaseAddr:$rs1)>; +} + multiclass VPatUSLoadStoreMaskSDNode { defvar load_instr = !cast("PseudoVLE1_V_"#m.BX); @@ -380,9 +404,16 @@ multiclass VPatReductionSDNode; +foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VF16M1, VF32M1, VF64M1] in + defm "" : VPatUSLoadStoreWholeVRSDNode; +foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors) in + defm "" : VPatUSLoadStoreWholeVRSDNode; foreach mti = AllMasks in defm "" : VPatUSLoadStoreMaskSDNode; diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp index 419ddc12f8381..cff8bfc8a500e 100644 --- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp @@ -508,7 +508,6 @@ void FrameDataInfo::updateLayoutIndex(FrameTypeBuilder &B) { void FrameTypeBuilder::addFieldForAllocas(const Function &F, FrameDataInfo &FrameData, coro::Shape &Shape) { - DenseMap AllocaIndex; using AllocaSetType = SmallVector; SmallVector NonOverlapedAllocas; @@ -530,7 +529,6 @@ void FrameTypeBuilder::addFieldForAllocas(const Function &F, if (!Shape.ReuseFrameSlot && !EnableReuseStorageInFrame) { for (const auto &A : FrameData.Allocas) { AllocaInst *Alloca = A.Alloca; - AllocaIndex[Alloca] = NonOverlapedAllocas.size(); NonOverlapedAllocas.emplace_back(AllocaSetType(1, Alloca)); } return; @@ -611,13 +609,11 @@ void FrameTypeBuilder::addFieldForAllocas(const Function &F, bool CouldMerge = NoInference && Alignable; if (!CouldMerge) continue; - AllocaIndex[Alloca] = AllocaIndex[*AllocaSet.begin()]; AllocaSet.push_back(Alloca); Merged = true; break; } if (!Merged) { - AllocaIndex[Alloca] = NonOverlapedAllocas.size(); NonOverlapedAllocas.emplace_back(AllocaSetType(1, Alloca)); } } @@ -1288,7 +1284,6 @@ static Instruction *insertSpills(const FrameDataInfo &FrameData, auto *G = GetFramePointer(Alloca); G->setName(Alloca->getName() + Twine(".reload.addr")); - SmallPtrSet SeenDbgBBs; TinyPtrVector DIs = FindDbgDeclareUses(Alloca); if (!DIs.empty()) DIBuilder(*Alloca->getModule(), diff --git a/llvm/lib/Transforms/IPO/ExtractGV.cpp b/llvm/lib/Transforms/IPO/ExtractGV.cpp index b45766a8e7833..ba0efd46af165 100644 --- a/llvm/lib/Transforms/IPO/ExtractGV.cpp +++ b/llvm/lib/Transforms/IPO/ExtractGV.cpp @@ -82,24 +82,23 @@ namespace { // be conservative and simple. // Visit the GlobalVariables. - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); - I != E; ++I) { - bool Delete = - deleteStuff == (bool)Named.count(&*I) && !I->isDeclaration() && - (!I->isConstant() || !keepConstInit); + for (GlobalVariable &GV : M.globals()) { + bool Delete = deleteStuff == (bool)Named.count(&GV) && + !GV.isDeclaration() && + (!GV.isConstant() || !keepConstInit); if (!Delete) { - if (I->hasAvailableExternallyLinkage()) + if (GV.hasAvailableExternallyLinkage()) continue; - if (I->getName() == "llvm.global_ctors") + if (GV.getName() == "llvm.global_ctors") continue; } - makeVisible(*I, Delete); + makeVisible(GV, Delete); if (Delete) { // Make this a declaration and drop it's comdat. - I->setInitializer(nullptr); - I->setComdat(nullptr); + GV.setInitializer(nullptr); + GV.setComdat(nullptr); } } diff --git a/llvm/lib/Transforms/IPO/StripSymbols.cpp b/llvm/lib/Transforms/IPO/StripSymbols.cpp index 4fc71847a0707..168740a1158ef 100644 --- a/llvm/lib/Transforms/IPO/StripSymbols.cpp +++ b/llvm/lib/Transforms/IPO/StripSymbols.cpp @@ -213,11 +213,10 @@ static bool StripSymbolNames(Module &M, bool PreserveDbgInfo) { findUsedValues(M.getGlobalVariable("llvm.used"), llvmUsedValues); findUsedValues(M.getGlobalVariable("llvm.compiler.used"), llvmUsedValues); - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); - I != E; ++I) { - if (I->hasLocalLinkage() && llvmUsedValues.count(&*I) == 0) - if (!PreserveDbgInfo || !I->getName().startswith("llvm.dbg")) - I->setName(""); // Internal symbols can't participate in linkage + for (GlobalVariable &GV : M.globals()) { + if (GV.hasLocalLinkage() && llvmUsedValues.count(&GV) == 0) + if (!PreserveDbgInfo || !GV.getName().startswith("llvm.dbg")) + GV.setName(""); // Internal symbols can't participate in linkage } for (Function &I : M) { diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 4b485a0ad85e6..5526739a016f0 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -661,13 +661,12 @@ bool InstCombinerImpl::simplifyDivRemOfSelectWithZeroOp(BinaryOperator &I) { break; // Replace uses of the select or its condition with the known values. - for (Instruction::op_iterator I = BBI->op_begin(), E = BBI->op_end(); - I != E; ++I) { - if (*I == SI) { - replaceUse(*I, SI->getOperand(NonNullOperand)); + for (Use &Op : BBI->operands()) { + if (Op == SI) { + replaceUse(Op, SI->getOperand(NonNullOperand)); Worklist.push(&*BBI); - } else if (*I == SelectCond) { - replaceUse(*I, NonNullOperand == 1 ? ConstantInt::getTrue(CondTy) + } else if (Op == SelectCond) { + replaceUse(Op, NonNullOperand == 1 ? ConstantInt::getTrue(CondTy) : ConstantInt::getFalse(CondTy)); Worklist.push(&*BBI); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp index 7718c8b0eedd1..37c7e6135501c 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp @@ -479,8 +479,8 @@ LLVM_NODISCARD Optional Negator::run(Value *Root) { if (!Negated) { // We must cleanup newly-inserted instructions, to avoid any potential // endless combine looping. - llvm::for_each(llvm::reverse(NewInstructions), - [&](Instruction *I) { I->eraseFromParent(); }); + for (Instruction *I : llvm::reverse(NewInstructions)) + I->eraseFromParent(); return llvm::None; } return std::make_pair(ArrayRef(NewInstructions), Negated); @@ -523,8 +523,8 @@ LLVM_NODISCARD Value *Negator::Negate(bool LHSIsZero, Value *Root, NegatorNumInstructionsNegatedSuccess += Res->first.size(); // They are in def-use order, so nothing fancy, just insert them in order. - llvm::for_each(Res->first, - [&](Instruction *I) { IC.Builder.Insert(I, I->getName()); }); + for (Instruction *I : Res->first) + IC.Builder.Insert(I, I->getName()); // And return the new root. return Res->second; diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index 518e909e8ab40..6ed63812998a3 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -3083,9 +3083,8 @@ Instruction *InstCombinerImpl::visitExtractValueInst(ExtractValueInst &EV) { SmallVector Indices; // Prefix an i32 0 since we need the first element. Indices.push_back(Builder.getInt32(0)); - for (ExtractValueInst::idx_iterator I = EV.idx_begin(), E = EV.idx_end(); - I != E; ++I) - Indices.push_back(Builder.getInt32(*I)); + for (unsigned Idx : EV.indices()) + Indices.push_back(Builder.getInt32(Idx)); // We need to insert these at the location of the old load, not at that of // the extractvalue. diff --git a/llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp b/llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp index 7f7f2dc89b7e8..74e4eb07b2196 100644 --- a/llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp +++ b/llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp @@ -110,9 +110,8 @@ bool llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, } // Check each operand for a match. - for (User::const_op_iterator OI = Inst->op_begin(), OE = Inst->op_end(); - OI != OE; ++OI) { - const Value *Op = *OI; + for (const Use &U : Inst->operands()) { + const Value *Op = U; if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) && PA.related(Ptr, Op)) return true; } diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp index 5a3b9e9990192..37fce501a23eb 100644 --- a/llvm/lib/Transforms/Scalar/GVN.cpp +++ b/llvm/lib/Transforms/Scalar/GVN.cpp @@ -289,9 +289,8 @@ GVN::Expression GVN::ValueTable::createExpr(Instruction *I) { Expression e; e.type = I->getType(); e.opcode = I->getOpcode(); - for (Instruction::op_iterator OI = I->op_begin(), OE = I->op_end(); - OI != OE; ++OI) - e.varargs.push_back(lookupOrAdd(*OI)); + for (Use &Op : I->operands()) + e.varargs.push_back(lookupOrAdd(Op)); if (I->isCommutative()) { // Ensure that commutative instructions that only differ by a permutation // of their operands get the same value number by sorting the operand value @@ -362,9 +361,8 @@ GVN::Expression GVN::ValueTable::createExtractvalueExpr(ExtractValueInst *EI) { // Not a recognised intrinsic. Fall back to producing an extract value // expression. e.opcode = EI->getOpcode(); - for (Instruction::op_iterator OI = EI->op_begin(), OE = EI->op_end(); - OI != OE; ++OI) - e.varargs.push_back(lookupOrAdd(*OI)); + for (Use &Op : EI->operands()) + e.varargs.push_back(lookupOrAdd(Op)); append_range(e.varargs, EI->indices()); diff --git a/llvm/lib/Transforms/Utils/PredicateInfo.cpp b/llvm/lib/Transforms/Utils/PredicateInfo.cpp index af5a72aa6ad9d..fe69382b4ad8f 100644 --- a/llvm/lib/Transforms/Utils/PredicateInfo.cpp +++ b/llvm/lib/Transforms/Utils/PredicateInfo.cpp @@ -77,8 +77,7 @@ static Instruction *getBranchTerminator(const PredicateBase *PB) { // Given a predicate info that is a type of branching terminator, get the // edge this predicate info represents -const std::pair -getBlockEdge(const PredicateBase *PB) { +std::pair getBlockEdge(const PredicateBase *PB) { assert(isa(PB) && "Not a predicate info type we know how to get an edge from."); const auto *PEdge = cast(PB); @@ -158,8 +157,7 @@ struct ValueDFS_Compare { } // For a phi use, or a non-materialized def, return the edge it represents. - const std::pair - getBlockEdge(const ValueDFS &VD) const { + std::pair getBlockEdge(const ValueDFS &VD) const { if (!VD.Def && VD.U) { auto *PHI = cast(VD.U->getUser()); return std::make_pair(PHI->getIncomingBlock(*VD.U), PHI->getParent()); diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index d6223415c154c..9d8b7c1c07e75 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -1072,8 +1072,8 @@ static Instruction *getDebugLocFromInstOrOperands(Instruction *I) { if (I->getDebugLoc() != Empty) return I; - for (User::op_iterator OI = I->op_begin(), OE = I->op_end(); OI != OE; ++OI) { - if (Instruction *OpInst = dyn_cast(*OI)) + for (Use &Op : I->operands()) { + if (Instruction *OpInst = dyn_cast(Op)) if (OpInst->getDebugLoc() != Empty) return OpInst; } diff --git a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll index eec35b114e790..7b3b926e4e60c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll +++ b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll @@ -20,16 +20,13 @@ define void @vadd_vint64m1( ret void } -; PRE-INSERTER: %3:vr = PseudoVLE64_V_M1 %1, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) -; PRE-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) +; PRE-INSERTER: %3:vr = VL1RE64_V %1 :: (load unknown-size from %ir.pa, align 8) +; PRE-INSERTER: %4:vr = VL1RE64_V %2 :: (load unknown-size from %ir.pb, align 8) ; PRE-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $x0, 64, implicit $vl, implicit $vtype -; PRE-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $x0, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) +; PRE-INSERTER: VS1R_V killed %5, %0 :: (store unknown-size into %ir.pc, align 8) +; POST-INSERTER: %3:vr = VL1RE64_V %1 :: (load unknown-size from %ir.pa, align 8) +; POST-INSERTER: %4:vr = VL1RE64_V %2 :: (load unknown-size from %ir.pb, align 8) ; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype -; POST-INSERTER: %3:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) -; POST-INSERTER: dead %7:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype -; POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) -; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, -1, implicit $vl, implicit $vtype -; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype -; POST-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) +; POST-INSERTER: VS1R_V killed %5, %0 :: (store unknown-size into %ir.pc, align 8) diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll index 9e133c1d95fe2..b446aa021b317 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll @@ -7,11 +7,11 @@ define void @vadd_vint16m1( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint16m1: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e16,m1,ta,mu -; CHECK-NEXT: vle16.v v25, (a1) -; CHECK-NEXT: vle16.v v26, (a2) +; CHECK-NEXT: vl1re16.v v25, (a1) +; CHECK-NEXT: vl1re16.v v26, (a2) +; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu ; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vs1r.v v25, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -23,11 +23,11 @@ define void @vadd_vint16m1( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint16m2: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vle16.v v28, (a2) +; CHECK-NEXT: vl2re16.v v26, (a1) +; CHECK-NEXT: vl2re16.v v28, (a2) +; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vadd.vv v26, v26, v28 -; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: vs2r.v v26, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -39,11 +39,11 @@ define void @vadd_vint16m2( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint16m4: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vl4re16.v v28, (a1) +; CHECK-NEXT: vl4re16.v v8, (a2) +; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu ; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vse16.v v28, (a0) +; CHECK-NEXT: vs4r.v v28, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -55,11 +55,11 @@ define void @vadd_vint16m4( *%pc, *%pa, < define void @vadd_vint16m8( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint16m8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vle16.v v16, (a2) +; CHECK-NEXT: vl8re16.v v8, (a1) +; CHECK-NEXT: vl8re16.v v16, (a2) +; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vadd.vv v8, v8, v16 -; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll index 4ad224f428238..83a6f4e81531b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll @@ -7,11 +7,11 @@ define void @vadd_vint32m1( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint32m1: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e32,m1,ta,mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vle32.v v26, (a2) +; CHECK-NEXT: vl1re32.v v25, (a1) +; CHECK-NEXT: vl1re32.v v26, (a2) +; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu ; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vs1r.v v25, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -23,11 +23,11 @@ define void @vadd_vint32m1( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint32m2: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e32,m2,ta,mu -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vle32.v v28, (a2) +; CHECK-NEXT: vl2re32.v v26, (a1) +; CHECK-NEXT: vl2re32.v v28, (a2) +; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu ; CHECK-NEXT: vadd.vv v26, v26, v28 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vs2r.v v26, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -39,11 +39,11 @@ define void @vadd_vint32m2( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint32m4: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vl4re32.v v28, (a1) +; CHECK-NEXT: vl4re32.v v8, (a2) +; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vse32.v v28, (a0) +; CHECK-NEXT: vs4r.v v28, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -55,11 +55,11 @@ define void @vadd_vint32m4( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint32m8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vle32.v v16, (a2) +; CHECK-NEXT: vl8re32.v v8, (a1) +; CHECK-NEXT: vl8re32.v v16, (a2) +; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu ; CHECK-NEXT: vadd.vv v8, v8, v16 -; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll index 09f74f7092bbf..f4658e71b3cc3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll @@ -7,11 +7,11 @@ define void @vadd_vint64m1( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint64m1: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e64,m1,ta,mu -; CHECK-NEXT: vle64.v v25, (a1) -; CHECK-NEXT: vle64.v v26, (a2) +; CHECK-NEXT: vl1re64.v v25, (a1) +; CHECK-NEXT: vl1re64.v v26, (a2) +; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu ; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vs1r.v v25, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -23,11 +23,11 @@ define void @vadd_vint64m1( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint64m2: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e64,m2,ta,mu -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vle64.v v28, (a2) +; CHECK-NEXT: vl2re64.v v26, (a1) +; CHECK-NEXT: vl2re64.v v28, (a2) +; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu ; CHECK-NEXT: vadd.vv v26, v26, v28 -; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: vs2r.v v26, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -39,11 +39,11 @@ define void @vadd_vint64m2( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint64m4: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a1) -; CHECK-NEXT: vle64.v v8, (a2) +; CHECK-NEXT: vl4re64.v v28, (a1) +; CHECK-NEXT: vl4re64.v v8, (a2) +; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu ; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vse64.v v28, (a0) +; CHECK-NEXT: vs4r.v v28, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -55,11 +55,11 @@ define void @vadd_vint64m4( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint64m8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vle64.v v16, (a2) +; CHECK-NEXT: vl8re64.v v8, (a1) +; CHECK-NEXT: vl8re64.v v16, (a2) +; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vadd.vv v8, v8, v16 -; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll index ae6ea99703250..f7b95ec9eef17 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll @@ -7,11 +7,11 @@ define void @vadd_vint8m1( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint8m1: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vle8.v v26, (a2) +; CHECK-NEXT: vl1r.v v25, (a1) +; CHECK-NEXT: vl1r.v v26, (a2) +; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vs1r.v v25, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -23,11 +23,11 @@ define void @vadd_vint8m1( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint8m2: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vle8.v v28, (a2) +; CHECK-NEXT: vl2r.v v26, (a1) +; CHECK-NEXT: vl2r.v v28, (a2) +; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu ; CHECK-NEXT: vadd.vv v26, v26, v28 -; CHECK-NEXT: vse8.v v26, (a0) +; CHECK-NEXT: vs2r.v v26, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -39,11 +39,11 @@ define void @vadd_vint8m2( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint8m4: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a2) +; CHECK-NEXT: vl4r.v v28, (a1) +; CHECK-NEXT: vl4r.v v8, (a2) +; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu ; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vse8.v v28, (a0) +; CHECK-NEXT: vs4r.v v28, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -55,11 +55,11 @@ define void @vadd_vint8m4( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint8m8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vle8.v v16, (a2) +; CHECK-NEXT: vl8r.v v8, (a1) +; CHECK-NEXT: vl8r.v v16, (a2) +; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu ; CHECK-NEXT: vadd.vv v8, v8, v16 -; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll index 28725c02a50d4..eeead7b007187 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8( define @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16( define @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32( define @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll index 6f83d50244d63..b6af9496bf104 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8( define @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16( define @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32( define @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64( define @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll index cc0cdf7942f39..03b7ba631c57b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8( define @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16( define @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32( define @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll index de4a4839cb487..31fcfcfae3293 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8( define @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16( define @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32( define @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64( define @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll index 4c8b9a20f93f8..76c4e86edc8f3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vadd.mask.nxv64i8.nxv64i8( define @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vadd.mask.nxv32i16.nxv32i16( define @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vadd.mask.nxv16i32.nxv16i32( define @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll index fede6b3b801e5..1bedcca63b640 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vadd.mask.nxv64i8.nxv64i8( define @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vadd.mask.nxv32i16.nxv32i16( define @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vadd.mask.nxv16i32.nxv16i32( define @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vadd.mask.nxv8i64.nxv8i64( define @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll index 2d9c22fb164de..66ad9ac2b366f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vand.mask.nxv64i8.nxv64i8( define @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vand.mask.nxv32i16.nxv32i16( define @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vand.mask.nxv16i32.nxv16i32( define @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll index 9149dbe2f6cb3..94c63dd9c9e59 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vand.mask.nxv64i8.nxv64i8( define @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vand.mask.nxv32i16.nxv32i16( define @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vand.mask.nxv16i32.nxv16i32( define @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vand.mask.nxv8i64.nxv8i64( define @intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll index 3ee1cd75e5906..20ee256a29179 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vasub.mask.nxv64i8.nxv64i8( define @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vasub.mask.nxv32i16.nxv32i16( define @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vasub.mask.nxv16i32.nxv16i32( define @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll index 01826beebd9a1..b097a34b7279c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vasub.mask.nxv64i8.nxv64i8( define @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vasub.mask.nxv32i16.nxv32i16( define @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vasub.mask.nxv16i32.nxv16i32( define @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vasub.mask.nxv8i64.nxv8i64( define @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll index 861d9f8d48bce..de0c6ed941f74 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8( define @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16( define @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32( define @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll index 2d761407279bb..0d14aec38dd1b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8( define @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16( define @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32( define @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64( define @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll index aa96ee914e35a..285a886f19364 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8( define @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16( define @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32( define @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll index 450298f038acb..99ce81cafa551 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8( define @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16( define @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32( define @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vdiv.mask.nxv8i64.nxv8i64( define @intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll index ebd7123729a71..f788ef44e3db0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8( define @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16( define @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32( define @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll index 1c07a334722e3..f2b8b85671976 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8( define @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16( define @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32( define @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vdivu.mask.nxv8i64.nxv8i64( define @intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll index 2dc6b88ac1c98..9366b83eb5e45 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16( define @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32( define @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64( define @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll index e21a3c74b76f7..b20c3bed3c9ad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll @@ -252,8 +252,7 @@ declare @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16( define @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -474,8 +473,7 @@ declare @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32( define @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -652,8 +650,7 @@ declare @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64( define @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll index 40edb80447b11..884e8a7adebc8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfdiv.mask.nxv32f16.nxv32f16( define @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32( define @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfdiv.mask.nxv8f64.nxv8f64( define @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll index 2e8f76d91c5d3..9fe5ebb07b8b4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfdiv.mask.nxv32f16( define @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfdiv.mask.nxv16f32( define @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfdiv.mask.nxv8f64( define @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll index 7606bae084d55..bffb4cafadfaa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll @@ -132,8 +132,8 @@ declare @llvm.fma.v32f16(, @vfmadd_vv_nxv32f16( %va, %vb, %vc) { ; CHECK-LABEL: vfmadd_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vfmacc.vv v8, v16, v24 ; CHECK-NEXT: ret %vd = call @llvm.fma.v32f16( %vc, %vb, %va) @@ -253,8 +253,8 @@ declare @llvm.fma.v16f32(, @vfmadd_vv_nxv16f32( %va, %vb, %vc) { ; CHECK-LABEL: vfmadd_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vfmadd.vv v8, v24, v16 ; CHECK-NEXT: ret %vd = call @llvm.fma.v16f32( %vc, %va, %vb) @@ -350,8 +350,8 @@ declare @llvm.fma.v8f64(, @vfmadd_vv_nxv8f64( %va, %vb, %vc) { ; CHECK-LABEL: vfmadd_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vfmacc.vv v8, v16, v24 ; CHECK-NEXT: ret %vd = call @llvm.fma.v8f64( %vb, %vc, %va) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll index 58a136f8d19b1..967c7351e2725 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16( define @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32( define @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64( define @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll index fb82ca7de9ce8..d6f60fdb4799e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16( define @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32( define @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64( define @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll index 5538714a6092f..6e75e42d79372 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16( define @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32( define @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64( define @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll index 6826ef5ba53ad..4365034c7c7f1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16( define @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32( define @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64( define @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll index feeb836dad48f..73b8856bf5e6c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll @@ -142,8 +142,8 @@ declare @llvm.fma.v32f16(, @vfmsub_vv_nxv32f16( %va, %vb, %vc) { ; CHECK-LABEL: vfmsub_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vfmsac.vv v8, v16, v24 ; CHECK-NEXT: ret %neg = fneg %va @@ -273,8 +273,8 @@ declare @llvm.fma.v16f32(, @vfmsub_vv_nxv16f32( %va, %vb, %vc) { ; CHECK-LABEL: vfmsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vfmsub.vv v8, v24, v16 ; CHECK-NEXT: ret %neg = fneg %vb @@ -378,8 +378,8 @@ declare @llvm.fma.v8f64(, @vfmsub_vv_nxv8f64( %va, %vb, %vc) { ; CHECK-LABEL: vfmsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vfmsac.vv v8, v16, v24 ; CHECK-NEXT: ret %neg = fneg %va diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll index 0774be459a206..1a8521f872f17 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfmul.mask.nxv32f16.nxv32f16( define @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfmul.mask.nxv16f32.nxv16f32( define @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfmul.mask.nxv8f64.nxv8f64( define @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll index 2cedbdb8316b1..b285e36b3f85b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfmul.mask.nxv32f16( define @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfmul.mask.nxv16f32( define @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfmul.mask.nxv8f64( define @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll index 43b95228406d2..2fae7ad0f159c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll @@ -152,8 +152,8 @@ declare @llvm.fma.v32f16(, @vfnmsub_vv_nxv32f16( %va, %vb, %vc) { ; CHECK-LABEL: vfnmsub_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vfnmadd.vv v8, v24, v16 ; CHECK-NEXT: ret %neg = fneg %vc @@ -293,8 +293,8 @@ declare @llvm.fma.v16f32(, @vfnmsub_vv_nxv16f32( %va, %vb, %vc) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vfnmadd.vv v8, v24, v16 ; CHECK-NEXT: ret %neg = fneg %va @@ -406,8 +406,8 @@ declare @llvm.fma.v8f64(, @vfnmsub_vv_nxv8f64( %va, %vb, %vc) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vfnmacc.vv v8, v16, v24 ; CHECK-NEXT: ret %neg = fneg %vb diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll index f2a4024d7cb3d..2b5919228f3c8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll @@ -142,8 +142,8 @@ declare @llvm.fma.v32f16(, @vfnmsub_vv_nxv32f16( %va, %vb, %vc) { ; CHECK-LABEL: vfnmsub_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vfnmsub.vv v8, v24, v16 ; CHECK-NEXT: ret %neg = fneg %vc @@ -273,8 +273,8 @@ declare @llvm.fma.v16f32(, @vfnmsub_vv_nxv16f32( %va, %vb, %vc) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vfnmsub.vv v8, v24, v16 ; CHECK-NEXT: ret %neg = fneg %va @@ -378,8 +378,8 @@ declare @llvm.fma.v8f64(, @vfnmsub_vv_nxv8f64( %va, %vb, %vc) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vfnmsac.vv v8, v16, v24 ; CHECK-NEXT: ret %neg = fneg %vb diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll index 427ad0209c8ea..80c04b0bc8c08 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfsgnj.mask.nxv32f16.nxv32f16( define @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfsgnj.mask.nxv16f32.nxv16f32( define @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfsgnj.mask.nxv8f64.nxv8f64( define @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll index f3d80a18caf6a..733e7a8f61c90 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfsgnj.mask.nxv32f16( define @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfsgnj.mask.nxv16f32( define @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfsgnj.mask.nxv8f64( define @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll index a79b0ad72479c..087933bb80e93 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfsgnjn.mask.nxv32f16.nxv32f16( define @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfsgnjn.mask.nxv16f32.nxv16f32( define @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfsgnjn.mask.nxv8f64.nxv8f64( define @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll index 122fe1ba59c16..392d16bca0223 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfsgnjn.mask.nxv32f16( define @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfsgnjn.mask.nxv16f32( define @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfsgnjn.mask.nxv8f64( define @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll index dcd10dd1ee1b9..ee481d2a717e9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfsgnjx.mask.nxv32f16.nxv32f16( define @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfsgnjx.mask.nxv16f32.nxv16f32( define @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfsgnjx.mask.nxv8f64.nxv8f64( define @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll index 2ccd8a51878f9..17c262c89693b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfsgnjx.mask.nxv32f16( define @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfsgnjx.mask.nxv16f32( define @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfsgnjx.mask.nxv8f64( define @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll index b484d99b8b29b..7aa38c082d5d1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll @@ -251,8 +251,7 @@ declare @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16( define @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -473,8 +472,7 @@ declare @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32( define @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -651,8 +649,7 @@ declare @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64( define @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll index 20833122e9bcc..ee6608267735a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll @@ -252,8 +252,7 @@ declare @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16( define @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -474,8 +473,7 @@ declare @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32( define @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -652,8 +650,7 @@ declare @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64( define @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll index 52157474b8b78..5e26abaaafb82 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll @@ -212,8 +212,7 @@ declare @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -394,8 +393,7 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll index 7abcb01bb9bcf..4eb94ab8fcb53 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll @@ -212,8 +212,7 @@ declare @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -394,8 +393,7 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll index 8189709310735..772a81a5928d7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll @@ -212,8 +212,7 @@ declare @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -394,8 +393,7 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll index 95ccdbaf5e742..489b8e3daece4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll @@ -212,8 +212,7 @@ declare @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -394,8 +393,7 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll index ec04106a156ff..2dc38789e7b52 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmax.mask.nxv64i8.nxv64i8( define @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmax.mask.nxv32i16.nxv32i16( define @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmax.mask.nxv16i32.nxv16i32( define @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll index 4eaa70f968df1..792adc817130d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmax.mask.nxv64i8.nxv64i8( define @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmax.mask.nxv32i16.nxv32i16( define @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmax.mask.nxv16i32.nxv16i32( define @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vmax.mask.nxv8i64.nxv8i64( define @intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll index 7f277edc6e963..74c9987d43b37 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8( define @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16( define @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32( define @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll index 25c3ac340750d..77a8506fab6da 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8( define @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16( define @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32( define @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vmaxu.mask.nxv8i64.nxv8i64( define @intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll index 311faa6e12703..eeb89f2cfaf3b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmin.mask.nxv64i8.nxv64i8( define @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmin.mask.nxv32i16.nxv32i16( define @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmin.mask.nxv16i32.nxv16i32( define @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll index f7da50fb60204..634b2680283e9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmin.mask.nxv64i8.nxv64i8( define @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmin.mask.nxv32i16.nxv32i16( define @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmin.mask.nxv16i32.nxv16i32( define @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vmin.mask.nxv8i64.nxv8i64( define @intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll index 12f506d67d009..1034e0396f227 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vminu.mask.nxv64i8.nxv64i8( define @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vminu.mask.nxv32i16.nxv32i16( define @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vminu.mask.nxv16i32.nxv16i32( define @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll index 15693832867d2..d068f9ab1dcd5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vminu.mask.nxv64i8.nxv64i8( define @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vminu.mask.nxv32i16.nxv32i16( define @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vminu.mask.nxv16i32.nxv16i32( define @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vminu.mask.nxv8i64.nxv8i64( define @intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll index b5c1829350a6a..3159a6198ade8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmul.mask.nxv64i8.nxv64i8( define @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmul.mask.nxv32i16.nxv32i16( define @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmul.mask.nxv16i32.nxv16i32( define @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll index 3f436742c9585..78f2e63357d1c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmul.mask.nxv64i8.nxv64i8( define @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmul.mask.nxv32i16.nxv32i16( define @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmul.mask.nxv16i32.nxv16i32( define @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vmul.mask.nxv8i64.nxv8i64( define @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll index dbdd58c3883ee..95a42fd39c38a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8( define @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16( define @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32( define @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll index b9c7a5836d030..84ff58458dbd6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8( define @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16( define @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32( define @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64( define @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll index 1ad0e79fd79af..0739983510631 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8( define @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16( define @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32( define @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll index 8b67b1c9f8663..ef8fc76ebd06f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8( define @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16( define @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32( define @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64( define @intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll index 97b110031095d..e6fa6ee070ca4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8( define @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16( define @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32( define @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll index 89e4f394845ab..9bfe1fcae7aab 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8( define @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16( define @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32( define @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vmulhu.mask.nxv8i64.nxv8i64( define @intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll index 838a51f2903fe..2027ad0376f1a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vor.mask.nxv64i8.nxv64i8( define @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vor.mask.nxv32i16.nxv32i16( define @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vor.mask.nxv16i32.nxv16i32( define @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll index 1ca2f84e9c838..980191a1197a6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vor.mask.nxv64i8.nxv64i8( define @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vor.mask.nxv32i16.nxv32i16( define @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vor.mask.nxv16i32.nxv16i32( define @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vor.mask.nxv8i64.nxv8i64( define @intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll index 299d61cdd9900..c75e0c01c8664 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vrem.mask.nxv64i8.nxv64i8( define @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vrem.mask.nxv32i16.nxv32i16( define @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vrem.mask.nxv16i32.nxv16i32( define @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll index ec17004c771bd..fbce5aa44e79a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vrem.mask.nxv64i8.nxv64i8( define @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vrem.mask.nxv32i16.nxv32i16( define @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vrem.mask.nxv16i32.nxv16i32( define @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vrem.mask.nxv8i64.nxv8i64( define @intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll index 7df2efc53cfb1..7c7ecc7d2c84e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vremu.mask.nxv64i8.nxv64i8( define @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vremu.mask.nxv32i16.nxv32i16( define @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vremu.mask.nxv16i32.nxv16i32( define @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll index 3bffd3af819a6..57f4952b12a33 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vremu.mask.nxv64i8.nxv64i8( define @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vremu.mask.nxv32i16.nxv32i16( define @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vremu.mask.nxv16i32.nxv16i32( define @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vremu.mask.nxv8i64.nxv8i64( define @intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll index ebe7976c6d3e7..fe9aa32b6b03b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll @@ -302,8 +302,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv64i8.i32( define @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -574,8 +573,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv32i16.i32( define @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -801,8 +799,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv16i32.i32( define @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1073,8 +1070,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv32f16.i32( define @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1300,8 +1296,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv16f32.i32( define @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1482,8 +1477,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv8f64.i32( define @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll index 2686c1bdccac6..963f795c0dc9b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll @@ -302,8 +302,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv64i8.i64( define @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -574,8 +573,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv32i16.i64( define @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -801,8 +799,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv16i32.i64( define @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -983,8 +980,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv8i64.i64( define @intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1255,8 +1251,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv32f16.i64( define @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1482,8 +1477,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv16f32.i64( define @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1664,8 +1658,7 @@ declare @llvm.riscv.vrgather.vv.mask.nxv8f64.i64( define @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll index f771860701696..3d46c7ef6c6a3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll @@ -527,8 +527,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv32i16( define @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -709,8 +708,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv16i32( define @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -981,8 +979,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv32f16( define @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1163,8 +1160,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv16f32( define @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1255,8 +1251,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv8f64( define @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll index b855559940ebc..f6d8f1ba9e3bd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll @@ -527,8 +527,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv32i16( define @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -709,8 +708,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv16i32( define @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -801,8 +799,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv8i64( define @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1073,8 +1070,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv32f16( define @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1255,8 +1251,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv16f32( define @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -1347,8 +1342,7 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv8f64( define @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll index 546c28a825461..d808bb0040d25 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8( define @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16( define @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32( define @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll index f6caea4fc2fd7..89a5b9d4cf6a9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8( define @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16( define @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32( define @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vsadd.mask.nxv8i64.nxv8i64( define @intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll index 8d1f18638c177..ff2efcd1a9ce4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8( define @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16( define @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32( define @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll index bf2791973370d..05da897920bf3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8( define @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16( define @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32( define @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vsaddu.mask.nxv8i64.nxv8i64( define @intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll index 8977e3b36ca96..0e2be1ad194f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsll.mask.nxv64i8.nxv64i8( define @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsll.mask.nxv32i16.nxv32i16( define @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsll.mask.nxv16i32.nxv16i32( define @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll index 65be550f17e19..f0356fb8100c1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsll.mask.nxv64i8.nxv64i8( define @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsll.mask.nxv32i16.nxv32i16( define @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsll.mask.nxv16i32.nxv16i32( define @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vsll.mask.nxv8i64.nxv8i64( define @intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll index 94e531640907f..90fcf4ca29bbe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8( define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16( define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32( define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll index 433c4f4c55934..083b4d5670a58 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8( define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16( define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32( define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vsmul.mask.nxv8i64.nxv8i64( define @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll index 5797354578c97..1a48652e1863b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsra.mask.nxv64i8.nxv64i8( define @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsra.mask.nxv32i16.nxv32i16( define @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsra.mask.nxv16i32.nxv16i32( define @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll index 045a6d998b0f0..7c1f4cf787768 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsra.mask.nxv64i8.nxv64i8( define @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsra.mask.nxv32i16.nxv32i16( define @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsra.mask.nxv16i32.nxv16i32( define @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vsra.mask.nxv8i64.nxv8i64( define @intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll index f939e2981bd37..eba2d4bd383b7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8( define @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16( define @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32( define @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll index 6f4b1d5ff4330..58e6ef3d730cc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8( define @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16( define @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32( define @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vsrl.mask.nxv8i64.nxv8i64( define @intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll index bd50388b2d70b..bcd745c6d24b2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vssra.mask.nxv64i8.nxv64i8( define @intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vssra.mask.nxv32i16.nxv32i16( define @intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vssra.mask.nxv16i32.nxv16i32( define @intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll index 48127a297e6fb..6aaef72bc7fa6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vssra.mask.nxv64i8.nxv64i8( define @intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vssra.mask.nxv32i16.nxv32i16( define @intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vssra.mask.nxv16i32.nxv16i32( define @intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vssra.mask.nxv8i64.nxv8i64( define @intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll index 293e6a463b605..5fbf26950040a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8( define @intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16( define @intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32( define @intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll index f1803dd0807b6..369519f72caed 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8( define @intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16( define @intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32( define @intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64( define @intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll index fe85ae8fef676..c3f5643d34b63 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vssub.mask.nxv64i8.nxv64i8( define @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vssub.mask.nxv32i16.nxv32i16( define @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vssub.mask.nxv16i32.nxv16i32( define @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll index e2dbe7fd75d1e..b58822384bb14 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vssub.mask.nxv64i8.nxv64i8( define @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vssub.mask.nxv32i16.nxv32i16( define @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vssub.mask.nxv16i32.nxv16i32( define @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vssub.mask.nxv8i64.nxv8i64( define @intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll index bdf4ee1a9b0e2..4adeda63c7a03 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8( define @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16( define @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32( define @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll index b5ef9eb100fb6..05e4dc9d14de6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8( define @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16( define @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32( define @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vssubu.mask.nxv8i64.nxv8i64( define @intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll index 5a3690ea492c6..e8c9cb77155d7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsub.mask.nxv64i8.nxv64i8( define @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsub.mask.nxv32i16.nxv32i16( define @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsub.mask.nxv16i32.nxv16i32( define @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll index c82919097cde3..0336f23f2b52a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vsub.mask.nxv64i8.nxv64i8( define @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vsub.mask.nxv32i16.nxv32i16( define @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vsub.mask.nxv16i32.nxv16i32( define @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vsub.mask.nxv8i64.nxv8i64( define @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll index d78017454a75c..84986de92dbc3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll @@ -257,8 +257,7 @@ declare @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vl4re8.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -484,8 +483,7 @@ declare @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll index 150f4a9408f57..b5e489c38fae1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll @@ -257,8 +257,7 @@ declare @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vl4re8.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -484,8 +483,7 @@ declare @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -666,8 +664,7 @@ declare @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll index c078b126f1067..d851ba59996e6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll @@ -257,8 +257,7 @@ declare @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vl4re8.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -484,8 +483,7 @@ declare @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll index f6f8a5edb45c3..d526f0f7c6e0c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll @@ -257,8 +257,7 @@ declare @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vl4re8.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -484,8 +483,7 @@ declare @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -666,8 +664,7 @@ declare @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll index 7f7f826f227e5..c2e3a1c8b7c64 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll @@ -257,8 +257,7 @@ declare @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vl4re8.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -484,8 +483,7 @@ declare @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll index 60de793fbc9c7..5e61485b3043a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll @@ -257,8 +257,7 @@ declare @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vl4re8.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -484,8 +483,7 @@ declare @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -666,8 +664,7 @@ declare @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll index 6e72f26f41245..c60be3fb4403f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll @@ -257,8 +257,7 @@ declare @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vl4re8.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -484,8 +483,7 @@ declare @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll index 9734d9d18a0df..604cf9b9abcf8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll @@ -257,8 +257,7 @@ declare @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vl4re8.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -484,8 +483,7 @@ declare @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -666,8 +664,7 @@ declare @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll index e0de54e09f1cb..a0d37c90f511e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vxor.mask.nxv64i8.nxv64i8( define @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vxor.mask.nxv32i16.nxv32i16( define @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vxor.mask.nxv16i32.nxv16i32( define @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll index b41813e0fc7a2..2024fafce7ee0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll @@ -295,8 +295,7 @@ declare @llvm.riscv.vxor.mask.nxv64i8.nxv64i8( define @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vl8re8.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -561,8 +560,7 @@ declare @llvm.riscv.vxor.mask.nxv32i16.nxv32i16( define @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -783,8 +781,7 @@ declare @llvm.riscv.vxor.mask.nxv16i32.nxv16i32( define @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) @@ -961,8 +958,7 @@ declare @llvm.riscv.vxor.mask.nxv8i64.nxv8i64( define @intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/scalable-vector-struct.ll b/llvm/test/CodeGen/RISCV/scalable-vector-struct.ll index 48e72e4204419..ca71df0713cb1 100644 --- a/llvm/test/CodeGen/RISCV/scalable-vector-struct.ll +++ b/llvm/test/CodeGen/RISCV/scalable-vector-struct.ll @@ -7,9 +7,8 @@ define i32 @foo({ {, }, i32 } %x, * %y, * %z) { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m1,ta,mu -; CHECK-NEXT: vse32.v v8, (a1) -; CHECK-NEXT: vse32.v v9, (a2) +; CHECK-NEXT: vs1r.v v8, (a1) +; CHECK-NEXT: vs1r.v v9, (a2) ; CHECK-NEXT: ret entry: br label %return diff --git a/llvm/test/CodeGen/X86/pr49087.ll b/llvm/test/CodeGen/X86/pr49087.ll new file mode 100644 index 0000000000000..258ea352d1f9d --- /dev/null +++ b/llvm/test/CodeGen/X86/pr49087.ll @@ -0,0 +1,30 @@ +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -global-isel < %s 2>&1 | FileCheck %s +; REQUIRES: asserts +; XFAIL: * + +define i32 @test_01(i32* %p, i64 %len, i32 %x) { +; CHECK-LABEL: test_01 + +entry: + %scevgep = getelementptr i32, i32* %p, i64 -1 + br label %loop + +loop: ; preds = %backedge, %entry + %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ] + %iv.next = add i64 %iv, -1 + %cond_1 = icmp eq i64 %iv, 0 + br i1 %cond_1, label %exit, label %backedge + +backedge: ; preds = %loop + %scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv + %loaded = load atomic i32, i32* %scevgep1 unordered, align 4 + %cond_2 = icmp eq i32 %loaded, %x + br i1 %cond_2, label %failure, label %loop + +exit: ; preds = %loop + ret i32 -1 + +failure: + unreachable +} + diff --git a/llvm/test/DebugInfo/Generic/missing-abstract-variable.ll b/llvm/test/DebugInfo/Generic/missing-abstract-variable.ll index d6f78b516a10d..0cdfe0b7728d2 100644 --- a/llvm/test/DebugInfo/Generic/missing-abstract-variable.ll +++ b/llvm/test/DebugInfo/Generic/missing-abstract-variable.ll @@ -1,10 +1,5 @@ ; RUN: %llc_dwarf -O0 -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s -; The formal parameter 'b' for Function 'x' when inlined within 'a' is lost on -; powerpc64 (and on x86_64 at at least -O2). Presumably this is a SelectionDAG -; issue. -; XFAIL: powerpc64, aarch64 - ; Build from the following source with clang -O2. ; The important details are that 'x's abstract definition is first built during @@ -83,7 +78,6 @@ ; fastisel succeeds). ; CHECK: DW_TAG_formal_parameter ; CHECK-NOT: DW_TAG -; CHECK: DW_AT_location ; CHECK: DW_AT_abstract_origin {{.*}} "b" ; CHECK-NOT: {{DW_TAG|NULL}} diff --git a/llvm/test/DebugInfo/Symbolize/ELF/symtab-file.s b/llvm/test/DebugInfo/Symbolize/ELF/symtab-file.s index 485345efc5689..04761635828b1 100644 --- a/llvm/test/DebugInfo/Symbolize/ELF/symtab-file.s +++ b/llvm/test/DebugInfo/Symbolize/ELF/symtab-file.s @@ -1,3 +1,4 @@ +# REQUIRES: x86-registered-target ## When locating a local symbol, we can obtain the filename according to the ## preceding STT_FILE symbol. # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t diff --git a/llvm/test/DebugInfo/Symbolize/ELF/symtab-ifunc.s b/llvm/test/DebugInfo/Symbolize/ELF/symtab-ifunc.s index 382cbaf8ba2f8..228c4a6c1c9ef 100644 --- a/llvm/test/DebugInfo/Symbolize/ELF/symtab-ifunc.s +++ b/llvm/test/DebugInfo/Symbolize/ELF/symtab-ifunc.s @@ -1,3 +1,4 @@ +# REQUIRES: x86-registered-target ## Test we can symbolize STT_GNU_IFUNC symbols. # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t # RUN: llvm-symbolizer --obj=%t 0 1 diff --git a/llvm/test/DebugInfo/Symbolize/ELF/symtab-ignored.s b/llvm/test/DebugInfo/Symbolize/ELF/symtab-ignored.s index 57454c04c6b65..37ece2b390a1b 100644 --- a/llvm/test/DebugInfo/Symbolize/ELF/symtab-ignored.s +++ b/llvm/test/DebugInfo/Symbolize/ELF/symtab-ignored.s @@ -1,3 +1,4 @@ +# REQUIRES: x86-registered-target ## Ignore STT_SECTION and STT_TLS symbols for .symtab symbolization. # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t # RUN: llvm-symbolizer --obj=%t 0 | FileCheck %s diff --git a/llvm/test/DebugInfo/Symbolize/ELF/symtab-notype.s b/llvm/test/DebugInfo/Symbolize/ELF/symtab-notype.s index 91ce8073a25da..ff6727560eff1 100644 --- a/llvm/test/DebugInfo/Symbolize/ELF/symtab-notype.s +++ b/llvm/test/DebugInfo/Symbolize/ELF/symtab-notype.s @@ -1,3 +1,4 @@ +# REQUIRES: x86-registered-target ## STT_NOTYPE symbols are common in assembly files. Test we can symbolize them. # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t # RUN: llvm-symbolizer --obj=%t --inlines 0 1 2 3 4 5 6 7 | FileCheck %s diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s index d298e2572636b..f659e0b76dca9 100644 --- a/llvm/test/MC/RISCV/rvv/invalid.s +++ b/llvm/test/MC/RISCV/rvv/invalid.s @@ -589,3 +589,70 @@ vnsrl.wv v0, v4, v20, v0.t vfncvt.xu.f.w v0, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfncvt.xu.f.w v0, v4, v0.t + +vl2re8.v v1, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl4re8.v v1, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl4re8.v v2, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl4re8.v v3, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl8re8.v v1, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl8re8.v v2, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl8re8.v v3, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl8re8.v v4, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl8re8.v v5, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl8re8.v v6, (a0) +# CHECK-ERROR: invalid operand for instruction + +vl8re8.v v7, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs2r.v v1, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs4r.v v1, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs4r.v v2, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs4r.v v3, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs8r.v v1, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs8r.v v2, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs8r.v v3, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs8r.v v4, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs8r.v v5, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs8r.v v6, (a0) +# CHECK-ERROR: invalid operand for instruction + +vs8r.v v7, (a0) +# CHECK-ERROR: invalid operand for instruction + diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp index b2633a0cf97b5..7803848aafc4c 100644 --- a/llvm/utils/TableGen/SearchableTableEmitter.cpp +++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp @@ -348,17 +348,13 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table, IndexRowsStorage.push_back(Entry.first); OS << " { "; - bool NeedComma = false; + ListSeparator LS; for (const auto &Field : Index.Fields) { - if (NeedComma) - OS << ", "; - NeedComma = true; - std::string Repr = primaryRepresentation( Index.Loc, Field, Entry.first->getValueInit(Field.Name)); if (isa(Field.RecType)) Repr = StringRef(Repr).upper(); - OS << Repr; + OS << LS << Repr; } OS << ", " << Entry.second << " },\n"; } @@ -509,15 +505,11 @@ void SearchableTableEmitter::emitGenericTable(const GenericTable &Table, Record *Entry = Table.Entries[i]; OS << " { "; - bool NeedComma = false; - for (const auto &Field : Table.Fields) { - if (NeedComma) - OS << ", "; - NeedComma = true; - - OS << primaryRepresentation(Table.Locs[0], Field, + ListSeparator LS; + for (const auto &Field : Table.Fields) + OS << LS + << primaryRepresentation(Table.Locs[0], Field, Entry->getValueInit(Field.Name)); - } OS << " }, // " << i << "\n"; } diff --git a/llvm/utils/gn/secondary/clang/unittests/Basic/BUILD.gn b/llvm/utils/gn/secondary/clang/unittests/Basic/BUILD.gn index 9b17cb19cd937..499f9c42bb179 100644 --- a/llvm/utils/gn/secondary/clang/unittests/Basic/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/unittests/Basic/BUILD.gn @@ -13,6 +13,7 @@ unittest("BasicTests") { "FileEntryTest.cpp", "FileManagerTest.cpp", "LineOffsetMappingTest.cpp", + "SanitizersTest.cpp", "SourceManagerTest.cpp", ] } diff --git a/mlir/CMakeLists.txt b/mlir/CMakeLists.txt index 5d21312bccc31..91ad37f77f529 100644 --- a/mlir/CMakeLists.txt +++ b/mlir/CMakeLists.txt @@ -141,6 +141,9 @@ if (MLIR_INCLUDE_TESTS) add_subdirectory(test) endif() if (MLIR_INCLUDE_INTEGRATION_TESTS) + set(INTEL_SDE_EXECUTABLE "" CACHE STRING + "If set, arch-specific integration tests are run with Intel SDE.") + option(MLIR_RUN_AVX512_TESTS "Run AVX512 tests.") add_definitions(-DMLIR_INCLUDE_INTEGRATION_TESTS) add_subdirectory(integration_test) endif() diff --git a/mlir/include/mlir-c/IR.h b/mlir/include/mlir-c/IR.h index 8bee618213ff6..65c097a7604e3 100644 --- a/mlir/include/mlir-c/IR.h +++ b/mlir/include/mlir-c/IR.h @@ -322,6 +322,9 @@ static inline bool mlirOperationIsNull(MlirOperation op) { return !op.ptr; } MLIR_CAPI_EXPORTED bool mlirOperationEqual(MlirOperation op, MlirOperation other); +/// Gets the context this operation is associated with +MLIR_CAPI_EXPORTED MlirContext mlirOperationGetContext(MlirOperation op); + /// Gets the name of the operation as an identifier. MLIR_CAPI_EXPORTED MlirIdentifier mlirOperationGetName(MlirOperation op); @@ -467,6 +470,9 @@ static inline bool mlirBlockIsNull(MlirBlock block) { return !block.ptr; } /// perform deep comparison. MLIR_CAPI_EXPORTED bool mlirBlockEqual(MlirBlock block, MlirBlock other); +/// Returns the closest surrounding operation that contains this block. +MLIR_CAPI_EXPORTED MlirOperation mlirBlockGetParentOperation(MlirBlock); + /// Returns the block immediately following the given block in its parent /// region. MLIR_CAPI_EXPORTED MlirBlock mlirBlockGetNextInRegion(MlirBlock block); diff --git a/mlir/integration_test/CMakeLists.txt b/mlir/integration_test/CMakeLists.txt index fb2be5256dcce..81f7c8e7b2c6d 100644 --- a/mlir/integration_test/CMakeLists.txt +++ b/mlir/integration_test/CMakeLists.txt @@ -3,6 +3,7 @@ set(MLIR_INTEGRATION_TEST_DIR ${CMAKE_LIBRARY_OUTPUT_DIRECTORY}) set(MLIR_INTEGRATION_TEST_DEPENDS FileCheck count not + lli mlir-cpu-runner mlir-opt mlir_runner_utils diff --git a/mlir/integration_test/Dialect/Vector/CPU/AVX512/lit.local.cfg b/mlir/integration_test/Dialect/Vector/CPU/AVX512/lit.local.cfg new file mode 100644 index 0000000000000..6e6803e231fb1 --- /dev/null +++ b/mlir/integration_test/Dialect/Vector/CPU/AVX512/lit.local.cfg @@ -0,0 +1,15 @@ +import sys + +# AVX512 tests must be enabled via build flag. +if config.mlir_run_avx512_tests != 'ON': + config.unsupported = True + +# No JIT on win32. +if sys.platform == 'win32': + config.unsupported = True + +if config.intel_sde_executable: + # Run test in emulator (Intel SDE). + config.substitutions.append(('%lli', config.intel_sde_executable + ' -tgl -- lli')) +else: + config.substitutions.append(('%lli', 'lli')) diff --git a/mlir/integration_test/Dialect/Vector/CPU/AVX512/test-vp2intersect-i32.mlir b/mlir/integration_test/Dialect/Vector/CPU/AVX512/test-vp2intersect-i32.mlir new file mode 100644 index 0000000000000..d29789a280677 --- /dev/null +++ b/mlir/integration_test/Dialect/Vector/CPU/AVX512/test-vp2intersect-i32.mlir @@ -0,0 +1,52 @@ +// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-avx512" -convert-std-to-llvm | \ +// RUN: mlir-translate --avx512-mlir-to-llvmir | \ +// RUN: %lli --entry-function=entry --mattr="avx512bw,avx512vp2intersect" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \ +// RUN: FileCheck %s + +// Note: To run this test, your CPU must support AVX512 vp2intersect. + +func @entry() -> i32 { + %i0 = constant 0 : i32 + %i1 = constant 1: i32 + %i2 = constant 2: i32 + %i3 = constant 7: i32 + %i4 = constant 12: i32 + %i5 = constant -10: i32 + %i6 = constant -219: i32 + + %v0 = vector.broadcast %i1 : i32 to vector<16xi32> + %v1 = vector.insert %i2, %v0[1] : i32 into vector<16xi32> + %v2 = vector.insert %i3, %v1[4] : i32 into vector<16xi32> + %v3 = vector.insert %i4, %v2[6] : i32 into vector<16xi32> + %v4 = vector.insert %i5, %v3[7] : i32 into vector<16xi32> + %v5 = vector.insert %i0, %v4[10] : i32 into vector<16xi32> + %v6 = vector.insert %i0, %v5[12] : i32 into vector<16xi32> + %v7 = vector.insert %i3, %v6[13] : i32 into vector<16xi32> + %v8 = vector.insert %i3, %v7[14] : i32 into vector<16xi32> + %v9 = vector.insert %i0, %v8[15] : i32 into vector<16xi32> + vector.print %v9 : vector<16xi32> + // CHECK: ( 1, 2, 1, 1, 7, 1, 12, -10, 1, 1, 0, 1, 0, 7, 7, 0 ) + + %w0 = vector.broadcast %i1 : i32 to vector<16xi32> + %w1 = vector.insert %i2, %w0[4] : i32 into vector<16xi32> + %w2 = vector.insert %i6, %w1[7] : i32 into vector<16xi32> + %w3 = vector.insert %i4, %w2[8] : i32 into vector<16xi32> + %w4 = vector.insert %i4, %w3[9] : i32 into vector<16xi32> + %w5 = vector.insert %i4, %w4[10] : i32 into vector<16xi32> + %w6 = vector.insert %i0, %w5[11] : i32 into vector<16xi32> + %w7 = vector.insert %i0, %w6[12] : i32 into vector<16xi32> + %w8 = vector.insert %i0, %w7[13] : i32 into vector<16xi32> + %w9 = vector.insert %i0, %w8[15] : i32 into vector<16xi32> + vector.print %w9 : vector<16xi32> + // CHECK: ( 1, 1, 1, 1, 2, 1, 1, -219, 12, 12, 12, 0, 0, 0, 1, 0 ) + + %k1, %k2 = avx512.vp2intersect %v9, %w9 : vector<16xi32> + + vector.print %k1 : vector<16xi1> + // CHECK: ( 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1 ) + + vector.print %k2 : vector<16xi1> + // CHECK: ( 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1 ) + + return %i0 : i32 +} diff --git a/mlir/integration_test/lit.site.cfg.py.in b/mlir/integration_test/lit.site.cfg.py.in index bd0ccf4cce24c..6d2a7170482fe 100644 --- a/mlir/integration_test/lit.site.cfg.py.in +++ b/mlir/integration_test/lit.site.cfg.py.in @@ -33,6 +33,8 @@ config.mlir_src_root = "@MLIR_SOURCE_DIR@" config.mlir_obj_root = "@MLIR_BINARY_DIR@" config.mlir_tools_dir = "@MLIR_TOOLS_DIR@" config.mlir_integration_test_dir = "@MLIR_INTEGRATION_TEST_DIR@" +config.intel_sde_executable = "@INTEL_SDE_EXECUTABLE@" +config.mlir_run_avx512_tests = "@MLIR_RUN_AVX512_TESTS@" # Support substitution of the tools_dir with user parameters. This is # used when we can't determine the tool dir at configuration time. diff --git a/mlir/lib/CAPI/IR/IR.cpp b/mlir/lib/CAPI/IR/IR.cpp index fdb830e4940f0..87c09944c77ce 100644 --- a/mlir/lib/CAPI/IR/IR.cpp +++ b/mlir/lib/CAPI/IR/IR.cpp @@ -305,6 +305,10 @@ bool mlirOperationEqual(MlirOperation op, MlirOperation other) { return unwrap(op) == unwrap(other); } +MlirContext mlirOperationGetContext(MlirOperation op) { + return wrap(unwrap(op)->getContext()); +} + MlirIdentifier mlirOperationGetName(MlirOperation op) { return wrap(unwrap(op)->getName().getIdentifier()); } @@ -461,6 +465,10 @@ bool mlirBlockEqual(MlirBlock block, MlirBlock other) { return unwrap(block) == unwrap(other); } +MlirOperation mlirBlockGetParentOperation(MlirBlock block) { + return wrap(unwrap(block)->getParentOp()); +} + MlirBlock mlirBlockGetNextInRegion(MlirBlock block) { return wrap(unwrap(block)->getNextNode()); } diff --git a/mlir/test/CAPI/ir.c b/mlir/test/CAPI/ir.c index c2b13d55473f4..2f81d13160c26 100644 --- a/mlir/test/CAPI/ir.c +++ b/mlir/test/CAPI/ir.c @@ -1439,6 +1439,37 @@ int registerOnlyStd() { return 0; } +/// Tests backreference APIs +static int testBackreferences() { + fprintf(stderr, "@test_backreferences\n"); + + MlirContext ctx = mlirContextCreate(); + mlirContextSetAllowUnregisteredDialects(ctx, true); + MlirLocation loc = mlirLocationUnknownGet(ctx); + + MlirOperationState opState = mlirOperationStateGet(mlirStringRefCreateFromCString("invalid.op"), loc); + MlirRegion region = mlirRegionCreate(); + MlirBlock block = mlirBlockCreate(0, NULL); + mlirRegionAppendOwnedBlock(region, block); + mlirOperationStateAddOwnedRegions(&opState, 1, ®ion); + MlirOperation op = mlirOperationCreate(&opState); + + if (!mlirContextEqual(ctx, mlirOperationGetContext(op))) { + fprintf(stderr, "ERROR: Getting context from operation failed\n"); + return 1; + } + if (!mlirOperationEqual(op, mlirBlockGetParentOperation(block))) { + fprintf(stderr, "ERROR: Getting parent operation from block failed\n"); + return 2; + } + + mlirOperationDestroy(op); + mlirContextDestroy(ctx); + + // CHECK-LABEL: @test_backreferences + return 0; +} + // Wraps a diagnostic into additional text we can match against. MlirLogicalResult errorHandler(MlirDiagnostic diagnostic, void *userData) { fprintf(stderr, "processing diagnostic (userData: %ld) <<\n", (long)userData); @@ -1514,6 +1545,8 @@ int main() { return 8; if (registerOnlyStd()) return 9; + if (testBackreferences()) + return 10; mlirContextDestroy(ctx);