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New daily trending repos in Verilog #50

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vitalets opened this issue Jan 31, 2018 · 11 comments
Open

New daily trending repos in Verilog #50

vitalets opened this issue Jan 31, 2018 · 11 comments

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@vitalets
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Repository owner locked and limited conversation to collaborators Jan 31, 2018
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New daily trending repos in Verilog!

efabless / caravel_user_project
https://caravel-user-project.readthedocs.io

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New daily trending repos in Verilog!

ucb-bar / nvdla-wrapper
Wraps the NVDLA project for Chipyard integration

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New daily trending repos in Verilog!

vortexgpgpu / vortex

IObundle / iob-cache
Verilog Configurable Cache

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New daily trending repos in Verilog!

The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

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New daily trending repos in Verilog!

riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
+1 stars today

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New daily trending repos in Verilog!

pulp-platform / cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

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New daily trending repos in Verilog!

alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
+5 stars today

YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
+4 stars today

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New daily trending repos in Verilog!

lnis-uofu / OpenFPGA
An Open-source FPGA IP Generator
+1 stars today

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New daily trending repos in Verilog!

nvdla / hw
RTL, Cmodel, and testbench for NVDLA

Wren6991 / Hazard3
3-stage RV32IMACZb* processor with debug

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New daily trending repos in Verilog!

OSCPU / yosys-sta

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New daily trending repos in Verilog!

EttusResearch / uhd
The USRP™ Hardware Driver Repository
+2 stars today

analogdevicesinc / hdl
HDL libraries and projects
+1 stars today

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