diff --git a/src/main/scala/channel/Parameters.scala b/src/main/scala/channel/Parameters.scala index b9a5577..100814b 100644 --- a/src/main/scala/channel/Parameters.scala +++ b/src/main/scala/channel/Parameters.scala @@ -25,6 +25,7 @@ case class UserChannelParams( p => u => u, crossingType: ClockCrossingType = NoCrossing, useOutputQueues: Boolean = true, + unifiedBuffer: Boolean = true, srcSpeedup: Int = 1, destSpeedup: Int = 1 ) { @@ -101,6 +102,7 @@ case class ChannelParams( destSpeedup: Int, channelGen: Parameters => ChannelOutwardNode => ChannelOutwardNode = { p => u => u }, useOutputQueues: Boolean, + unifiedBuffer: Boolean ) extends BaseChannelParams { val nVirtualChannels = virtualChannelParams.size val maxBufferSize = virtualChannelParams.map(_.bufferSize).max @@ -131,7 +133,8 @@ object ChannelParams { virtualChannelParams = user.virtualChannelParams.zipWithIndex.map { case (vP, vc) => VirtualChannelParams(srcId, destId, vc, vP.bufferSize, Set[FlowRoutingInfo]()) }, - useOutputQueues = user.useOutputQueues + useOutputQueues = user.useOutputQueues, + unifiedBuffer = user.unifiedBuffer ) } } diff --git a/src/main/scala/router/EgressUnit.scala b/src/main/scala/router/EgressUnit.scala index c8a9102..9f47f60 100644 --- a/src/main/scala/router/EgressUnit.scala +++ b/src/main/scala/router/EgressUnit.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} -class EgressUnit(coupleSAVA: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) +class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { @@ -19,7 +19,7 @@ class EgressUnit(coupleSAVA: Boolean, inParams: Seq[ChannelParams], ingressParam val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) - val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3, flow=true)) + val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail diff --git a/src/main/scala/router/Router.scala b/src/main/scala/router/Router.scala index beb244d..787f4c5 100644 --- a/src/main/scala/router/Router.scala +++ b/src/main/scala/router/Router.scala @@ -122,7 +122,9 @@ class Router( Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => - Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, inParams, ingressParams, u)) + Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, + routerParams.user.combineSAST, + inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units