Verilog.YAML-tmLanguage

---
"$schema": https://raw.githubusercontent.com/martinring/tmlanguage/master/tmlanguage.json
name: Verilog

variables:
  startOfIdentifier: '(?<![_$[:alnum:]])(?<!\.)'
  normalIdentifier: "[_a-zA-Z][_$a-zA-Z0-9]*"
  escapedIdentifier: '\\[!-~]+(?=\s)'
  systemIdentifier: '\$[[:alnum:]_$]+'
  identifier: "[_a-zA-Z][_$a-zA-Z0-9]*|{{escapedIdentifier}}|{{systemIdentifier}}"
  variableIdentifier: "[_a-zA-Z][_$a-zA-Z0-9]*|{{escapedIdentifier}}"
  unsignedNum: "[0-9][_0-9]*"
  nonZeroUnsignedNum: "[1-9][_0-9]*"
  commentOrSpace: '(/\*(?:[^\*]|\*(?!/))*\*/)|(//.*\n)|\s'
  # avoid /**/ (something) /**/ be tokenized as single comment
  constantIdentifier: '[_[:upper:]][_$[:digit:][:upper:]]*'
  constantVar: '({{constantIdentifier}})(?![_$[:alnum:]])'
  netTypes: 'supply0|supply1|tri|triand|trior|tri0|tri1|uwire|wire|wand|wor'
  varTypes: 'event|real|realtime|integer|time|genvar'
  strength: 'supply0|strong0|pull0|weak0|supply1|strong1|pull1|weak1'
  primitiveTypes: 'cmos|rcmos|bufif0|bufif1|notif0|notif1|nmos|pmos|rnmos|rpmos|and|nand|or|nor|xor|xnor|buf|not|tranif0|tranif1|rtranif1|rtranif0|tran|rtran|pulldown|pullup'
  nonInstantiationKeywords: 'initial|always|else|forever|default|assign|localparam|parameter|defparam|begin|end|endtask|endfunction|fork|join|input|output|inout|{{netTypes}}|trireg|reg|{{varTypes}}'
  moduleGenerateKeywords: '{{netTypes}}|trireg|reg|{{varTypes}}|task|function|parameter|localparam|specparam|defparam|assign|{{primitiveTypes}}|initial|always|for|if|case'

# TODO: check (begin:) and (end:) does not match `begin, `end, \begin ...
patterns:
  - include: "#module-declaration"
  - include: '#udp-declaration'
  - include: '#config-declaration'
  - include: '#compiler-directive'
  - include: '#library-declaration'
  - include: '#include-statement'
  - include: "#keywords"
  - include: "#strings"
  - include: "#comments"
  - include: "#constants"

repository:
  keywords:
    comment: "Used when keyword is typed, but the statement is incomplete"
    patterns:
      - name: keyword.control.verilog
        match: '\b(if|else|ifnone|while|for|forever|repeat|wait|disable|case|casex|casez|default|endcase)\b'
      - name: storage.type.module.verilog
        match: '\b(module|macromodule|endmodule)\b'
      - name: storage.type.udp.verilog
        match: '\b(primitive|endprimitive)\b'
      - name: storage.type.function.verilog
        match: '\b(function|endfunction)\b'
      - name: storage.type.task.verilog
        match: '\b(task|endtask)\b'
      - name: storage.type.config.verilog
        match: '\b(config|endconfig)\b'
      - name: keyword.control.verilog
        match: '\b(always|initial)\b'
      - name: keyword.other.verilog
        match: '\b(posedge|negedge|or|edge)\b'
      - name: support.type.verilog
        match: '\b(event|reg|trireg)\b'
      - name: keyword.other.block.verilog
        match: '\b(begin|end|fork|join)\b'
      - name: keyword.other.verilog
        match: '\b(assign|deassign|force|release)\b'
      - name: keyword.other.port.verilog
        match: '\b(input|output|inout)\b'
      - name: keyword.other.verilog
        match: '\b(parameter|localparam|specparam|defparam)\b'
      - name: keyword.other.verilog
        match: '\b(design|default|instance|cell|liblist|use)\b'
      - name: keyword.other.verilog
        match: '\b(signed|automatic|vectored|scalared)\b'
      - include: '#system-tasks-and-functions'
      - name: constant.language.strength.verilog
        match: '\b({{strength}}|small|medium|large|highz0|highz1)\b'
      - include: '#net-types'
      - include: "#parameter-types"
      - name: support.type.verilog
        match: '\b({{primitiveTypes}})\b'
  net-types:
    name: support.type.verilog
    match: '\b({{netTypes}})\b'
  parameter-types:
    patterns:
      - include: "#output-variable-types"
      - include: "#real-types"
  output-variable-types:
    name: support.type.verilog
    match: '\b(time|integer)\b'
  real-types:
    name: support.type.verilog
    match: '\b(real|realtime)\b'
# A.1.1
  library-declaration:
    begin: '\b(library)\s+({{variableIdentifier}})'
    beginCaptures:
      '1': { name: keyword.other.verilog }
      '2': { name: variable.other.readwrite.verilog }
    end: ';'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - include: '#file-path-spec'
      - name: keyword.other.verilog
        match: '-incdir'
      - include: '#identifiers'
      - include: '#punctuation-comma'
  include-statement:
    begin: '\b(include)\b'
    beginCaptures:
      '1': { name: keyword.other.verilog }
    end: ';'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - include: '#file-path-spec'
  file-path-spec:
    name: string.other.path.verilog
    match: '([\.?\*\/a-zA-Z]+)'
# A.1.2
  module-declaration:
    name: meta.module.verilog
    begin: '\b(module|macromodule)'
    beginCaptures:
      "1": { name: storage.type.module.verilog }
    end: '\b(endmodule)\b'
    endCaptures:
      "1": { name: storage.type.module.verilog }
    patterns:
      - include: "#module-declaration-header"
      - include: '#comments'
      - include: '#module-body'
  module-declaration-header:
    begin: '(?<=module|macromodule)'
    end: ";"
    endCaptures:
      '0': { name: punctuation.section.module.begin.verilog }
    patterns:
      - include: '#comments'
      - name: entity.name.type.module.verilog
        match: '{{variableIdentifier}}'
      - include: "#module-parameter"
      - include: '#list-of-ports'
  module-body:
    name: meta.module.body.verilog
    begin: '(?<=;)'
    end: '(?=endmodule)'
    patterns:
      - include: "#module-item"
# A.1.3
  list-of-ports:
    begin: '\('
    beginCaptures:
      '0': { name: punctuation.definition.ports.begin.verilog }
    end: '\)'
    endCaptures:
      '0': { name: punctuation.definition.ports.end.verilog }
    patterns:
      - include: '#comments'
      - include: '#port-declarations'
      - include: '#punctuation-comma'
      - include: '#identifiers'
      - begin: '\('
        end: '\)'
        patterns:
          - include: '#port-expression'
      - name: punctuation.accessor.port.verilog
        match: '\.'
      - include: '#port-expression'
  port-expression:
    patterns:
      - include: '#punctuation-comma'
      - include: '#port-reference'
  port-reference:
    patterns:
      - include: '#identifiers'
      - include: '#item-access'
# A.1.4
  module-item:
    patterns:
      - include: '#comments'
      - include: '#port-declaration-statement'
      - include: '#non-port-module-item'
  non-port-module-item:
    patterns:
      - include: '#generate-region'
      - include: '#specify-block'
      - include: '#specparam-declaration'
      - include: '#module-or-generate-item'
  module-or-generate-item:
    patterns:
      - include: '#compiler-directive'
      - include: '#local-parameter-declaration'
      - include: '#parameter-override'
      - include: '#module-or-generate-item-declaration'
      - include: '#continuous-assignment'
      - include: '#gate-instantiation'
      - name: keyword.control.verilog
        match: '\b(always|initial)\b'
      # Textmate can't easily capture `always`, `inital`, (no simply way to tell apart module instantiation and variable assignment)
      # moving `statement` and `timing control` to this level is easier
      - include: "#statement"
      # loop-generate-construct is treated as loop-statement
      # conditional-generate-construct is treated as conditional-statement
  module-or-generate-item-declaration:
    patterns:
      - include: '#net-declaration'
      - include: '#reg-declaration'
      - include: '#var-declaration'
      - include: '#function-declaration'
      - include: '#task-declaration'
  parameter-override:
    begin: '\b(defparam)\b'
    beginCaptures:
      '1': { name: keyword.other.verilog }
    end: ';|(?=\b({{moduleGenerateKeywords}})\b)'
    # Matches the beginning of other module-items to properly match incomplete items
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - include: '#comments'
      - include: '#assignment'
      - include: '#punctuation-comma'
# A.1.5
  config-declaration:
    name: meta.config.verilog
    begin: '\b(config)'
    beginCaptures:
      "1": { name: storage.type.config.verilog }
    end: '\b(endconfig)\b'
    endCaptures:
      "1": { name: storage.type.config.verilog }
    patterns:
      - include: "#config-declaration-header"
      - include: '#comments'
      - include: '#config-body'
  config-declaration-header:
    begin: '(?<=config)'
    end: ";"
    endCaptures:
      '0': { name: punctuation.section.config.begin.verilog }
    patterns:
      - include: '#comments'
      - name: entity.name.type.config.verilog
        match: '{{variableIdentifier}}'
  config-body:
    name: meta.config.body.verilog
    begin: '(?<=;)'
    end: '(?=endconfig)'
    patterns:
      - begin: '\b(design|default|instance|cell)\b'
        beginCaptures:
          '1': { name: keyword.other.verilog }
        end: ';'
        endCaptures:
          '0': { name: punctuation.terminator.statement.verilog }
        patterns:
          - name: keyword.other.verilog
            match: '\b(use|liblist)\b'
          - include: '#hierarchical-identifier'
      - include: '#comments'
# A.2.1.1
  module-parameter:
    begin: '#\('
    beginCaptures:
      "0": { name: punctuation.definition.parameters.begin.verilog }
    endCaptures:
      "0": { name: punctuation.definition.parameters.end.verilog }
    end: '\)'
    patterns:
      - name: keyword.other.verilog
        match: '\b(parameter|signed)\b'
      - include: '#range'
      - include: '#parameter-types'
      - include: '#parameter-assignment'
      - include: '#punctuation-comma'
  parameter-assignment:
    patterns:
      - include: '#comments'
      - include: '#identifiers'
      - include: '#punctuation-assignment'
      - include: '#expression'
  local-parameter-declaration: # merge parameter and localparam for brevity
    begin: '\b(localparam|parameter)\b'
    beginCaptures:
      '1': { name: keyword.other.verilog }
    end: ';|(?=\b({{moduleGenerateKeywords}})\b)'
    endCaptures:
      '0': { name: punctution.terminator.statement.verilog }
    patterns:
      - name: keyword.other.verilog
        match: '\b(signed)\b'
      - include: '#range'
      - include: '#parameter-types'
      - include: '#parameter-assignment'
      - include: '#punctuation-comma'
      - include: '#comments'
  specparam-declaration:
    begin: '\b(specparam)\b'
    beginCaptures:
      '1': { name: keyword.other.verilog }
    end: ';|(?=\b({{moduleGenerateKeywords}})\b)'
    endCaptures:
      '0': { name: punctution.terminator.statement.verilog }
    patterns:
      - name: keyword.other.verilog
        match: '\b(signed)\b'
      - include: '#range'
      - include: '#pulse-control-specparam'
      - include: '#parameter-types'
      - include: '#parameter-assignment'
      - include: '#punctuation-comma'
      - include: '#comments'
# A.2.1.2
  port-declarations:
    begin: '\b(inout|output|input)\b'
    beginCaptures:
      '1': { name: keyword.other.port.verilog }
    end: '(?=\b(inout|output|input)|\);)' # TODO: ) and ; may not be on the same line
    patterns:
      - include: '#port-declaration-content'
  port-declaration-statement:
    begin: '\b(inout|output|input)\b'
    beginCaptures:
      '1': { name: keyword.other.port.verilog }
    end: ';|(?=\b({{moduleGenerateKeywords}})\b)'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - include: '#port-declaration-content'
      - include: '#comments'
  port-declaration-content:
    patterns:
      - name: support.type.reg.verilog
        match: '\breg\b'
      - include: '#net-types'
      - name: keyword.other.verilog
        match: '\bsigned\b'
      - include: '#range'
      - include: '#list-of-identifiers'
      - include: '#list-of-variable-port-identifiers'
# A.2.1.3
  net-declaration:
    begin: '\b({{netTypes}}|trireg)\b'
    beginCaptures:
      '1': { name: support.type.verilog }
    end: ';|(?=\b({{moduleGenerateKeywords}})\b)'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - name: keyword.other.verilog
        match: '\b(vectored|scalared)\b'
      - name: keyword.other.verilog
        match: '\b(signed)\b'
      - include: '#drive-charge-strength'
      - include: '#range'
      - include: '#delay-2-or-3'
      - include: '#list-of-net-assignments'
      - include: '#comments'
  reg-declaration:
    begin: '\b(reg)\b'
    beginCaptures:
      '1': { name: support.type.verilog }
    end: ';|(?=\b({{moduleGenerateKeywords}})\b)'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - name: keyword.other.verilog
        match: '\b(signed)\b'
      - include: '#range'
      - include: '#list-of-variable-port-identifiers'
      - include: '#comments'
  var-declaration:
    begin: '\b({{varTypes}})\b'
    beginCaptures:
      '1': { name: support.type.verilog }
    end: ';|(?=\b({{moduleGenerateKeywords}})\b)'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - include: '#list-of-variable-port-identifiers'
      - include: '#comments'
# A.2.2
  drive-charge-strength:
    patterns:
      - include: '#charge-strength'
      - include: '#drive-strength'
  drive-strength:
    match: '(\()\s*({{strength}}|highz0|highz1)\s*(,)\s*({{strength}}|highz0|highz1)\s*(\))'
    # assume no one would put comment inside drive-strength
    captures:
      '1': { name: punctuation.definition.strength.begin.verilog }
      '2': { name: constant.language.strength.verilog }
      '3': { name: punctuation.separator.comma.verilog }
      '4': { name: constant.language.strength.verilog }
      '5': { name: punctuation.definition.strength.end.verilog }
  charge-strength:
    match: '(\()\s*(small|medium|large)\s*(\))'
    # assume no one would put comment inside drive-strength
    captures:
      '1': { name: punctuation.definition.strength.begin.verilog }
      '2': { name: constant.language.strength.verilog }
      '3': { name: punctuation.definition.strength.end.verilog }
# A.2.2.3
  delay-value:
    patterns:
      - name: constant.numeric.unsigned.verilog
        match: "{{unsignedNum}}(?!')"
      - include: '#number-real'
      - include: '#identifier'
  delay-2-or-3:
    patterns:
      - begin: '#(?=({{commentOrSpace}})*[\(\n])' # Make sure there's nothing between # and (
        beginCaptures:
          '0': { name: keyword.operator.delay.verilog }
        end: '\)'
        endCaptures:
          '0': { name: punctuation.definition.delay-expression.end.verilog }
        patterns:
          - include: '#comments'
          - name: punctuation.definition.delay-expression.begin.verilog
            match: '\('
          - name: punctuation.separator.colon.verilog
            match: ':'
          - include: '#expression'
      - name: keyword.operator.delay.verilog
        match: '#'
      - include: '#delay-value'
# A.2.3
  list-of-identifiers:
    patterns:
      - include: '#identifiers'
      - include: "#punctuation-comma"
  list-of-variable-port-identifiers:
    patterns:
      - include: '#identifiers'
      - include: '#punctuation-assignment'
      - include: '#expression'
      - include: "#punctuation-comma"
# A.2.4
  pulse-control-specparam:
    begin: 'PATHPULSE\$'
    beginCaptures:
      '0': { name: keyword.other.verilog }
    end: '(?=\s|\/\/|\/\*|=)'
    patterns:
      - name: keyword.other.verilog
        match: '\$'
      - name: variable.other.readwrite.verilog
        # assume there's no \$ in input / output identifiers
        match: '[_a-zA-Z][_a-zA-Z0-9]*|{{escapedIdentifier}}'
      - include: '#item-access'
# A.2.5
  range:
    patterns:
      - include: "#item-access"
# A.2.6
  function-declaration:
    begin: '\b(function)\b'
    beginCaptures:
      '1': { name: storage.type.function }
    end: '\b(endfunction)\b'
    endCaptures:
      '1': { name: storage.type.function }
    patterns:
      - include: '#function-declaration-header'
      - include: '#block-item-declaration'
      - include: '#port-declaration-statement'
      - include: '#statement'
  function-declaration-header:
    begin: '(?<=function)'
    end: ";"
    endCaptures:
      '0': { name: punctuation.section.function.begin.verilog }
    patterns:
      - include: '#comments'
      - name: keyword.other.verilog
        match: '\b(automatic|signed)\b'
      - include: '#output-variable-types'
      - include: '#real-types'
      - include: '#range'
      - name: entity.name.function.verilog
        match: '{{variableIdentifier}}'
      - include: '#list-of-ports'
# A.2.7
  task-declaration:
    begin: '\b(task)\b'
    beginCaptures:
      '1': { name: storage.type.task }
    end: '\b(endtask)\b'
    endCaptures:
      '1': { name: storage.type.task }
    patterns:
      - include: '#task-declaration-header'
      - include: '#block-item-declaration'
      - include: '#port-declaration-statement'
      - include: '#statement'
  task-declaration-header:
    begin: '(?<=task)'
    end: ";"
    endCaptures:
      '0': { name: punctuation.section.task.begin.verilog }
    patterns:
      - include: '#comments'
      - name: keyword.other.verilog
        match: '\b(automatic)\b'
      - name: entity.name.function.task.verilog
        match: '{{variableIdentifier}}'
      - include: '#list-of-ports'
# A.2.8
  block-item-declaration:
    patterns:
      - include: '#net-declaration'
      - include: '#reg-declaration'
      - include: '#var-declaration'
      - include: '#local-parameter-declaration'
# A.3.1
  gate-instantiation:
    begin: '\b({{primitiveTypes}})\b'
    beginCaptures:
      '1': { name: support.type.verilog }
    end: ';|(?=\b({{moduleGenerateKeywords}})\b)'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - include: '#delay-2-or-3'
      - include: '#drive-charge-strength'
      - include: '#round-braces'
      - include: '#identifiers'
      - include: '#item-access'
      - include: '#comments'
# A.4.1
  instantiation:
    # highlight module type when two identifiers are separated by space and on the same line
    # the cost of distinguishing the form of module instantiation and assignment is too high
    #
    # current implementation is from: https://github.com/mshr-h/vscode-verilog-hdl-support
    #
    # This makes adjcent two word followed by ( or end-of-line become module instantiation
    #    which can lead to some undesired effects, for example:
    #      assign a
    #      = 3;
    # Structure like this would become instatiation.
    # A possible fix is to exclude all `module-or-generate-item` keywords from module type identifier.
    #
    # drive-strength and delay2 of udp instantiation is not fully tested/implemented
    patterns:
      - begin: '^\s*(?!(?:{{nonInstantiationKeywords}})\b)({{identifier}})(?:{{commentOrSpace}})+({{identifier}})(?<!begin|if)(?:{{commentOrSpace}})*(?=\(|\[|$)'
        beginCaptures:
          '1': { name: entity.name.type.module.verilog }
          '2': { name: comment.block.verilog }
          '3': { name: comment.line.double-slash.verilog }
          '4': { name: entity.name.variable.module.verilog }
          '5': { name: comment.block.verilog }
          '6': { name: comment.line.double-slash.verilog }
        end: ';'
        endCaptures:
          '0': { name: punctuation.terminator.statement.verilog }
        patterns:
          - include: '#comments'
          - include: '#range'
          - include: '#round-braces'
          - name: entity.name.variable.module.verilog
            match: '{{variableIdentifier}}'
      # instation with parameters
      - begin: '^\s*(?!(?:{{nonInstantiationKeywords}})\b)({{identifier}})(?:{{commentOrSpace}})+(?=#\()'
        beginCaptures:
          '1': { name: entity.name.type.module.verilog }
          '2': { name: comment.block.verilog }
          '3': { name: comment.line.double-slash.verilog }
        end: ';'
        endCaptures:
          '0': { name: punctuation.terminator.statement.verilog }
        patterns:
          - include: '#comments'
          - include: '#parameter-value-assignment'
          - include: '#round-braces'
          - name: entity.name.variable.module.verilog
            match: '{{variableIdentifier}}'
  parameter-value-assignment:
    begin: '#\('
    # begin: '#(?=({{commentOrSpace}})*[\(\n])' TODO if there's space between # and (, it won't be matched
    beginCaptures:
      '0': { name: keyword.operator.delay.verilog }
    end: '\)'
    endCaptures:
      '0': { name: punctuation.definition.parameter.end.verilog }
    patterns:
      - name: punctuation.definition.parameter.begin.verilog
        match: '\('
      - include: '#expression-list'
# A.4.2
  generate-region:
    name: meta.generate.verilog
    begin: '\b(generate)\b'
    beginCaptures:
      '1': { name: storage.type.generate.verilog } # use storage.type for consistency
    end: '\b(endgenerate)\b'
    endCaptures:
      '1': { name: storage.type.generate.verilog }
    patterns:
      - include: '#module-or-generate-item'
# A.5
  udp-declaration:
    name: meta.udp.verilog
    begin: '\b(primitive)'
    beginCaptures:
      "1": { name: storage.type.udp.verilog }
    end: '\b(endprimitive)\b'
    endCaptures:
      "1": { name: storage.type.udp.verilog }
    patterns:
      - include: "#udp-declaration-header"
      - include: '#comments'
      - include: '#udp-body'
  udp-declaration-header:
    begin: '(?<=primitive)'
    end: ";"
    endCaptures:
      '0': { name: punctuation.section.udp.begin.verilog }
    patterns:
      - include: '#comments'
      - name: entity.name.type.udp.verilog
        match: '{{variableIdentifier}}'
      - include: '#list-of-ports'
  udp-body:
    name: meta.udp.body.verilog
    patterns:
      - include: '#port-declaration-statement'
      - include: '#reg-declaration'
      - include: "#udp-table"
      - begin: '\b(initial)\b'
        beginCaptures:
          '1': { name: keyword.control.verilog }
        end: ';'
        endCaptures:
          '0': { name: punctuation.terminator.statement.verilog }
        patterns:
          - include: '#punctuation-assignment'
          - include: '#identifiers'
          - include: '#constants'
      - include: '#comments'
  udp-table:
    begin: '\b(table)\b'
    beginCaptures:
      '1': { name: storage.type.udp.verilog }
    end: '\b(endtable)\b'
    endCaptures:
      '1': { name: storage.type.udp.verilog }
    patterns:
      - name: constant.numeric.level.verilog
        match: '[01xX?bBrRfFpPnN\*\-]'
      - name: punctuation.separator.colon.verilog
        match: ':'
      - name: punctuation.terminator.statement.verilog
        match: ';'
      - name: punctuation.parenthesis.begin.verilog
        match: '\('
      - name: punctuation.parenthesis.end.verilog
        match: '\)'
      - include: '#comments'
# A.6.1
  continuous-assignment:
    name: meta.continuous-assignment.verilog
    begin: '\b(assign)\b'
    beginCaptures:
      '1': { name: keyword.other.verilog }
    end: ';'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - include: '#list-of-net-assignments'
      - include: '#drive-charge-strength'
      - include: '#delay-2-or-3'
  list-of-net-assignments:
    patterns:
      - include: '#comments'
      - include: '#assignment'
      - include: '#punctuation-comma'
  assignment:
    patterns:
      - include: '#comments'
      - include: '#punctuation-assignment'
      # function-call is stricter than lvalue,
      # putting function-call before lvalue to avoid function call being parsed as identifier + ( expression )
      - include: '#function-call'
      - include: '#lvalue'
      - include: '#expression' # rvalue
# A.6.2
  blocking-assignment:
    patterns:
      - include: '#comments'
      - begin: '='
        beginCaptures:
          '0': { name: keyword.operator.assign.verilog }
        end: ';'
        endCaptures:
          '0': { name: punctuation.terminator.statement.verilog }
        patterns:
          - include: '#repeat-statement'
          # capture expressions in-between = and ; to avoid ternary operators being parsed as block labels
          - include: '#expression'
          - include: '#delay-or-event-control'
      - include: '#lvalue'
  nonblocking-assignment:
    patterns:
      - include: '#comments'
      - begin: '<='
        beginCaptures:
          '0': { name: keyword.operator.nonblocking-assignment.verilog }
        end: ';'
        endCaptures:
          '0': { name: punctuation.terminator.statement.verilog }
        patterns:
          - include: '#repeat-statement'
          # capture expressions in-between <= and ; to avoid ternary operators being parsed as block labels
          - include: '#expression'
          - include: '#delay-or-event-control'
      - include: '#lvalue'
  procedural-continuous-assignment:
    patterns:
      - begin: '\b(release|deassign)\b'
        beginCaptures:
          '1': { name: keyword.other.verilog }
        end: ';'
        endCaptures:
          '0': { name: punctuation.terminator.statement.verilog }
        patterns:
          - include: '#lvalue'
      - include: '#list-of-net-assignments'
      - include: '#drive-charge-strength'
      - include: '#delay-2-or-3'
# A.6.3
  parallel-block:
    name: meta.parallel-block.verilog
    begin: '\b(fork)\b'
    beginCaptures:
      '1': { name: keyword.other.block.verilog }
    end: '\b(join)\b'
    endCaptures:
      '1': { name: keyword.other.block.verilog }
    patterns:
      - include: '#block-label'
      - include: '#statement'
  sequential-block:
    name: meta.sequential-block.verilog
    begin: '\b(begin)\b'
    beginCaptures:
      '1': { name: keyword.other.block.verilog }
    end: '\b(end)\b'
    endCaptures:
      '1': { name: keyword.other.block.verilog }
    patterns:
      - include: '#block-label'
      - include: '#statement'
  block-label:
    begin: ':(?!=({{commentOrSpace}})*[^_$[:alnum:]`\\])'
    beginCaptures:
      '0': { name: entity.name.label }
    end: '({{variableIdentifier}})'
    endCaptures:
      '0': { name: entity.name.label }
    patterns:
      - include: '#comments'
# A.6.4
  statement:
    patterns:
      - include: '#comments'
      - include: '#compiler-directive'
      - include: '#parallel-block'
      - include: '#sequential-block'
      - include: '#conditional-statement'
      - include: '#loop-statement'
      - include: '#wait-statement'
      - include: '#disable-statement'
      - include: '#case-statement'
      - include: '#task-enable' # need to be before assignments
      - include: '#event-trigger'
      - include: '#instantiation'
      - include: '#blocking-assignment'
      - include: '#nonblocking-assignment'
      - include: '#procedural-timing-control'
      - begin: '\(' # condition of for loop
        end: '\)'
        patterns:
          - include: '#assignment'
          - name: punctuation.separator.statement.verilog
            match: ';'
          - include: '#expression'
      # null statement
      - name: punctuation.terminator.statement.verilog
        match: ';'
# A.6.5
  delay-control:
    patterns:
      - begin: '#(?=({{commentOrSpace}})*[\(\n])' # Make sure there's nothing between # and (
        beginCaptures:
          '0': { name: keyword.operator.delay.verilog }
        end: '\)'
        endCaptures:
          '0': { name: punctuation.definition.delay-expression.end.verilog }
        patterns:
          - include: '#comments'
          - name: punctuation.definition.delay-expression.begin.verilog
            match: '\('
          - include: '#expression'
      - name: keyword.operator.delay.verilog
        match: '#'
      - include: '#delay-value'
  event-control:
    name: entity.event-control.verilog
    # assumes most people would write `@(` or `@*` on the same line
    patterns:
      - begin: '(@)(?=({{commentOrSpace}})*[\(\n])' # Make sure there's nothing between @ and (
        beginCaptures:
          '1': { name: keyword.operator.event.verilog }
        end: '(\))'
        endCaptures:
          '1': { name: punctuation.definition.event.end.verilog }
        patterns:
          - name: punctuation.definition.event.begin.verilog
            match: '\('
          - name: keyword.other.event.verilog
            match: '\*'
          - include: '#comments'
          - include: '#event-expression'
      - begin: '(@)'
        beginCaptures:
          '1': { name: keyword.operator.event.verilog }
        end: '(\*)'
        endCaptures:
          '1': { name: keyword.other.event.verilog }
        patterns:
          - include: '#comments'
      - name: keyword.operator.event.verilog
        match: '@'
      - include: '#hierarchical-identifier'
  delay-or-event-control:
    patterns:
      - include: '#delay-control'
      - include: '#event-control'
      # repeat is separated for higher precedence
  event-trigger:
    begin: '->'
    beginCaptures:
      '0': { name: keyword.operator.verilog }
    end: ';'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - include: '#hierarchical-identifier'
      - include: '#item-access'
  event-expression:
    patterns:
      - name: keyword.other.verilog
        match: '\b(posedge|negedge|or)\b'
      - include: '#expression'
  procedural-timing-control:
    patterns:
      - include: '#delay-control'
      - include: '#event-control'
  wait-statement:
    patterns:
      - name: keyword.control.verilog
        match: '\b(wait)\b'
  disable-statement:
    patterns:
      - name: keyword.control.verilog
        match: '\b(disable)\b'
# A.6.6
  conditional-statement:
    patterns:
      - name: keyword.control.verilog
        match: '\b(if|else)\b'
# A.6.7
  case-statement:
    begin: '\b(case|casez|casex)\b'
    beginCaptures:
      '1': { name: keyword.control.verilog }
    end: '\b(endcase)\b'
    endCaptures:
      '1': { name: keyword.control.verilog }
    patterns:
      - begin: '\('
        beginCaptures:
          '0': { name: punctuation.definition.case-expression.begin.verilog }
        end: '\)'
        endCaptures:
          '0': { name: punctuation.definition.case-expression.end.verilog }
        patterns:
          - include: '#expression'
      - name: keyword.control.verilog
        match: '\bdefault\b'
      - name: punctuaton.definition.section.case.verilog
        match: ':'
      - include: '#statement'
      - include: '#expression-list'
# A.6.8
  loop-statement:
    patterns:
      - name: keyword.control.verilog
        match: '\b(forever|repeat|while|for)\b'
  repeat-statement: # used in delay-or-event-control
    name: keyword.contorl.verilog
    match: '\b(repeat)\b'
# A.6.9
  task-enable:
    # Most of the cases are matched as function calls,
    # The rule exists to highlight the task identifier
    match: '({{variableIdentifier}})(?=[\(;])'
    captures:
      '1': { name: entity.name.function.call.verilog }
# A.7.1
  specify-block:
    name: meta.specify.verilog
    begin: '\b(specify)\b'
    beginCaptures:
      '1': { name: storage.type.specify } # use storage.type for consistency
    end: '\b(endspecify)\b'
    endCaptures:
      '1': { name: storage.type.specify }
    patterns:
      - include: '#specify-item'
  specify-item:
    patterns:
      - include: '#comments'
      - include: '#compiler-directive'
      - include: '#specparam-declaration'
      - include: '#pulsestyle-showcancelled-declaration'
      - include: '#path-declaration'
      - include: '#system-timing-check'
  pulsestyle-showcancelled-declaration:
    begin: '\b(pulsestyle_on(event|detect)|(no)?showcancelled)\b'
    beginCaptures:
      '1': { name: keyword.other.verilog}
    end: ';'
    endCaptures:
      '0': { name: punctution.terminator.statement.verilog }
    patterns:
      - include: '#list-of-path-input-output'
# A.7.2
  path-declaration:
    patterns:
      - include: '#simple-and-edge-sensitive-path-declaration'
      - name: keyword.control.verilog
        match: '\b(if|ifnone)\b'
  simple-and-edge-sensitive-path-declaration:
    begin: '(?=\()'
    end: ';'
    endCaptures:
      '0': { name: punctution.terminator.statement.verilog }
    patterns:
      - include: '#path-description'
      - include: '#path-delay-value'
  path-description:
    begin: '\('
    beginCaptures:
      '0': { name: punctuation.definition.path.begin.verilog }
    end: '\)'
    endCaptures:
      '0': { name: punctuation.definition.path.end.verilog }
    patterns:
      - name: keyword.operator.path.verilog
        match: '[\*=]>'
      - name: punctuation.sepeartor.colon.verilog
        match: ':'
      - name: keyword.other.verilog
        match: '\b(posedge|negedge)\b'
      - include: '#polarity-operator'
      - include: '#list-of-path-input-output'
  list-of-path-input-output:
    patterns:
      - include: '#punctuation-comma'
      - include: '#expression' # for module-path-expression and terminal-descriptor
# A.7.4
  polarity-operator:
    name: keyword.operator.verilog
    match: '[+-]'
  path-delay-value:
    begin: '='
    beginCaptures:
      '0': { name: keyword.operator.assignment.verilog }
    end: '(?=;)'
    patterns:
      - include: '#expression' # path-delay-expression is expression
# A.7.5
  system-timing-check:
    begin: '(\$(?:setup|hold|setuphold|recovery|removal|recrem|skew|timeskew|fullskew|period|width|nochange))\b'
    beginCaptures:
      '1': { name: entity.name.function.call.timing-check.verilog }
    end: ';'
    endCaptures:
      '0': { name: punctuation.terminator.statement.verilog }
    patterns:
      - begin: '\('
        end: '\)'
        patterns:
          - name: keyword.operator.verilog
            match: '&&&'
          - include: '#edge-control-specifier'
          - name: keyword.other.verilog
            match: '\b(posedge|negedge|or|edge)\b'
          - include: '#punctuation-comma'
          - include: '#expression'
  edge-control-specifier:
    begin: '\b(edge)\b'
    beginCaptures:
      '1': { name: keyword.other.verilog }
    end: '\]'
    endCaptures:
      '0': { name: punctuation.definition.edge.end.verilog }
    patterns:
      - name: punctuation.definition.edge.begin.verilog
        match: '\['
      - include: '#punctuation-comma'
      - name: constant.numeric.verilog
        match: '[01xXzZ]'
# A.8.1
  concatenation:
    name: meta.concatenation.verilog
    begin: '{'
    beginCaptures:
      '0': { name: punctuation.concatenation.begin.verilog }
    end: '}'
    endCaptures:
      '0': { name: punctuation.concatenation.end.verilog }
    patterns:
      - include: "#expression"
      - include: "#punctuation-comma"

# A.8.2
  function-call: # multiline would fail
    name: meta.function-call.verilog
    begin: |-
      (?x)
        (?=({{identifier}}) ({{commentOrSpace}})* (\())
    end: '(\))'
    endCaptures:
      '1': { name: punctuation.definition.arguments.end.verilog }
    patterns:
      - include: '#comments'
      - include: "#function-name"
      - include: "#function-arguments"
  function-name:
    patterns:
      - include: "#system-tasks-and-functions"
      - name: entity.name.function.call.system.verilog
        match: '{{systemIdentifier}}'
      - name: entity.name.function.call.verilog
        match: '{{variableIdentifier}}'
      - name: entity.name.function.preprocessor.verilog
        match: '`({{variableIdentifier}})'
  system-tasks-and-functions:
    name: support.function.builtin.verilog
    match: |-
      (?x)
        \b(
          \$display[bho]?|\$strobe[bho]?|\$write[bho]?|\$monitor[bho]?|\$monitoroff|\$monitoron|                            # Display tasks
          \$fclose|\$fdisplay[bho]?|\$swrite[bho]?|\$fscanf|\$fread|\$fseek|\$fflush|\$feof|\$sdf_annotate|                 # File I/O tasks
          \$fopen|\$fwrite[bho]?|\$fmonitor[bho]?|\$sformat|\$fgetc|\$ungetc|
          \$fgets|\$sscanf|\$rewind|\$ftell|\$ferror|\$readmem[bh]|
          \$printtimescale|\$timeformat|                                                                                    # Timescale tasks
          \$finish|\$stop|                                                                                                  # Simulation control tasks
          \$async\$(?:and|nand|or|nor)\$array|\$async\$(?:and|nand|or|nor)\$plane|                                          # PLA modeling tasks
          \$sync\$(?:and|nand|or|nor)\$array|\$sync\$(?:and|nand|or|nor)\$plane|
          \$q_initialize|\$q_add|\$q_remove|\$q_full|\$q_exam|                                                              # Stochastic analysis tasks
          \$realtime|\$stime|\$time|                                                                                        # Simulation time functions
          \$bitstoreal|\$realtobits|\$itor|\$rtoi|\$signed|\$unsigned|                                                      # Conversion functions
          \$random|\$dist_chi_square|\$dist_erlang|\$dist_normal|\$dist_exponential|\$dist_poisson|\$dist_t|\$dist_uniform| # Probabilistic distribution functions
          \$test\$plusargs|\$value\$plusargs|                                                                               # Command line input
          \$clog2|\$asin|\$ln|\$acos|\$log10|\$atan|\$exp|\$atan2|\$sqrt|\$hypot|\$pow|\$sinh|\$floor|                      # Math functions
          \$cosh|\$ceil|\$tanh|\$sin|\$asinh|\$cos|\$acosh|\$tna|\$atanh|
          \$dumpfile|\$dumpvars|\$dumpoff|\$dumpon|\$dumpall|\$dumplimit|\$dumpflush|                                       # VCD related
          \$countdrivers|\$getpattern|\$incsave|\$input|\$key|\$list|\$log|\$nokey|\$nolog|\$reset|\$reset_count|           # Annex C
          \$reset_value|\$restart|\$save|\$scale|\$scope|\$showscopes|\$showvars|\$sreadmemb|\$sreadmemh
        )\b
  function-arguments:
    begin: '(\()'
    beginCaptures:
      '1': { name: punctuation.definition.arguments.begin.verilog }
    end: '(?=\))'
    patterns:
      - include: "#expression-list"
# A.8.3
  expression:
    patterns:
      - include: '#keywords'
      - include: "#expression-without-identifiers"
      - include: "#hierarchical-identifier"
  expression-without-identifiers:
    patterns:
      - include: "#comments"
      - include: "#strings"
      - include: "#constants"
      - include: "#operator"
      - include: "#concatenation"
      - include: "#item-access"
      - include: "#round-braces"
      - include: "#function-call"
  round-braces:
    begin: '\('
    end: '\)'
    beginCaptures:
      "0": { name: punctuation.parenthesis.begin.verilog }
    endCaptures:
      "0": { name: punctuation.parenthesis.end.verilog }
    patterns:
      - include: "#expression"
  expression-list:
    patterns:
      - include: "#expression"
      - include: "#punctuation-comma"
# A.8.4
  item-access:
    name: meta.item-aceess.verilog
    begin: '(?=\[)'
    end: '\]'
    endCaptures:
      '0': { name: punctuation.definition.end.bracket.verilog }
    patterns:
      - include: "#item-index"
      - include: "#expression"
  item-index: # merge item access and range expression
    name: meta.item-index.verilog
    begin: '\['
    beginCaptures:
      '0': { name: punctuation.definition.begin.bracket.verilog }
    end: '(?=\])'
    patterns:
      - name: punctuation.separator.range.verilog
        match: '\+:'
      - name: punctuation.separator.range.verilog
        match: '-:'
      - name: punctuation.seperator.range.verilog
        match: ':'
      - include: '#expression'
# A.8.5
  lvalue:
    patterns:
      # - include: "#comments"
      - include: "#hierarchical-identifier"
      - include: "#concatenation"
      - include: "#item-access"
# A.8.6
  operator:
    comment: "Operators are order in a way such that more specific operators will come first (e.g. !== comes before !=)"
    match: |-
      (?x)
        (!== | === | != | == | >= | <=) # comparison operator
        | (&& | \|\| | !) # logical operator
        | (>>> | <<< | >> | << | ~& | ~\| | ~\^ | ~ | & | \| | \^~ | \^) # bitwise operator
        | (\*\* | \* | \+ | - | % | /) # arithmetic operator
        | (> | <) # comparison operator
        | (\? | :) # ternary operator
    captures:
      "1": { name: keyword.operator.comparison.verilog }
      "2": { name: keyword.operator.logical.verilog }
      "3": { name: keyword.operator.bitwise.verilog }
      "4": { name: keyword.operator.arithmetic.verilog }
      "5": { name: keyword.operator.comparison.verilog }
      "6": { name: keyword.operator.ternary.verilog }
# A.8.7
  constants:
    patterns:
      - name: constant.numeric.verilog
        patterns:
          - include: "#number-real"
          - include: "#number-dec"
          - include: "#number-hex"
          - include: "#number-oct"
          - include: "#number-bin"
          - name: invalid.illegal.name.verilog"
            match: '\b[0-9]+\w+' # identifier can't start with number
  number-bin:
    name: constant.numeric.bin.verilog
    match: |-
      (?x)
        (?<![\w\.]) # not precede by a word
        (
          ({{nonZeroUnsignedNum}})? # size
          '[sS]?[bB] # binary base
        )
        [01xXzZ?][_01xXzZ?]* # binary value
        ((?=[^a-zA-Z0-9_])|(?=\?(?![:;?]))) # boundary
    captures:
      "1": { name: storage.type.number.verilog }
  number-oct:
    name: constant.numeric.oct.verilog
    match: |-
      (?x)
        (?<![\w\.]) # not precede by a word
        (
          ({{nonZeroUnsignedNum}})? # size
          '[sS]?[oO] # octal base
        )
        [0-7xXzZ?][_0-7xXzZ?]* # octal value
        ((?=[^a-zA-Z0-9_])|(?=\?(?![:;?]))) # boundary
    captures:
      "1": { name: storage.type.number.verilog }
  number-hex:
    name: constant.numeric.hex.verilog
    match: |-
      (?x)
        (?<![\w\.]) # not precede by a word
        (
          ({{nonZeroUnsignedNum}})? # size
          '[sS]?[hH] # hex base
        )
        [0-9a-fA-FxXzZ?][_0-9a-fA-FxXzZ?]* # hex value
        ((?=[^a-zA-Z0-9_])|(?=\?(?![:;?]))) # boundary
    captures:
      "1": { name: storage.type.number.verilog }
  number-dec:
    name: constant.numeric.dec.verilog
    match: |-
      (?x)
        (?:
          (?<![\w\.]) # not precede by a word
            {{unsignedNum}}
          | (?:
            (
              ({{nonZeroUnsignedNum}})? # size
              '[sS]?[dD] # decimal base
            )
              {{unsignedNum}} # unsigned number
            | (?<='[sS]?[dD])[xXzZ?]_*
          )
        )
        (?!') # not followed by a ' (allowing bin, hex ... to match)
        ((?=[^a-zA-Z0-9_])|(?=\?(?![:;?]))) # boundary
    captures:
      "1":
        name: storage.type.number.verilog
  number-real:
    name: constant.numeric.float.verilog
    match: |-
      (?x)
        (?<![\w\.]) # not precede by a word
        (?:
            {{unsignedNum}}\. {{unsignedNum}} # unsigned number . unsigned number
          | {{unsignedNum}}(?:\. {{unsignedNum}})?
            [eE] [+-]? {{unsignedNum}} # exp sign unsigned number
        )
        (?!') # not followed by a ' (allowing dec, bin ... to match)
        \b # boundary
    captures:
      "1":
        name: storage.type.number.verilog
# A.8.8
  strings:
    name: string.quoted.double.verilog
    begin: '"'
    beginCaptures:
      '0': { name: punctuation.definition.string.begin.verilog }
    end: '(")|(\n$)'
    endCaptures:
      '1': { name: punctuation.definition.string.end.verilog }
      '2': { name: invalid.illegal.newline.verilog }
    patterns:
      - name: constant.character.escape.verilog
        match: '\\([nt\\"]|[0-7]{1,3})'
      # Table 17-2, 17-3
      - name: constant.other.placeholder.verilog
        match: '%[%hHdDoObBcClLvVmMsStTuUzZeEfFgGxX]'
      - name: constant.other.placeholder.verilog
        match: '%[+-0]*\d*(\.\d*)?[%hHdDoObBcClLvVmMsStTuUzZeEfFgGxX]'
# A.9.1
  attribute: # implement attribute as comment
    name: comment.attribute.verilog
    begin: '\(\*(?!\))'
    beginCaptures:
      '0': { name: punctuation.definition.attribute.begin.verilog }
    end: '\*\)'
    endCaptures:
      '0': { name: punctuation.definition.attribute.end.verilog }
# A.9.2
  comments: # from https://github.com/atom/language-c/blob/master/grammars/c.cson
    patterns:
      - name: comment.block.verilog
        begin: '/\*'
        beginCaptures:
          "0": { name: punctuation.definition.comment.begin.verilog }
        end: '\*/'
        endCaptures:
          "0": { name: punctuation.definition.comment.end.verilog }
      - name: invalid.illegal.stry-comment-end.verilog
        match: '\*/.*\n'
      - begin: '(^[ \t]+)?(?=//)'
        beginCaptures:
          "1": { name: punctuation.whitespace.comment.leading.verilog }
        end: '(?!\G)'
        patterns:
          - name: comment.line.double-slash.verilog
            begin: "//"
            beginCaptures:
              "0": { name: punctuation.definition.comment.verilog }
            end: '\n'
      - include: '#attribute'
      - name: comment.block.protected.verilog
        begin: '(`protected)\b'
        beginCaptures:
          '1': { name: keyword.control.directive.verilog }
        end: '(`endprotected)\b'
        endCaptures:
          '1': { name: keyword.control.directive.verilog }
# A.9.3
  text-macro:
    name: macro.verilog entity.name.function.preprocessor.verilog
    match: '`({{variableIdentifier}})'
  identifiers:
    patterns:
      - include: '#keywords' # fallback
      - include: '#text-macro'
      - name: entity.name.function.call.system.verilog
        match: '{{systemIdentifier}}'
      - name: variable.other.constant.verilog
        match: '{{constantVar}}'
      - name: variable.other.readwrite.verilog
        match: '{{variableIdentifier}}'
  hierarchical-identifier:
    patterns:
      - include: '#identifiers'
      - include: '#item-access'
      - name: punctuation.accessor.verilog
        match: '\.'
  punctuation-comma:
    name: punctuation.separator.comma.verilog
    match: ','
  punctuation-assignment:
    name: keyword.operator.assignment.verilog
    match: '='
# 19 / Annex D
  compiler-directive:
    name: meta.directive.verilog
    begin: |-
      (?x)
        `(begin_keywords|celldefine|default_nettype|define|else|elsif|end_keywords|
          endcelldefine|endif|ifdef|ifndef|include|line|nounconnected_drive|pragma|
          resetall|timescale|unconnected_drive|undef|default_decay_time|default_trireg_strength|
          delay_mode_distributed|delay_mode_path|delay_mode_unit|delay_mode_zero
          )\b
    beginCaptures:
      '0': { name: keyword.control.directive.verilog }
    end: '(\n|(?=\/\/))' # line comment may consume newline
    patterns:
      - include: '#comments'
      - name: keyword.other.verilog
        match: '\b(infinite)\b' # default decay time
      - name: support.type.verilog
        match: '\b({{netTypes}}|trireg|none)\b' # default net-types
      - match: '(10{0,2})\s*([munpf]?s)\b'
        captures:
          '1': { name: constant.numeric.dec.verilog }
          '2': { name: storage.type.unit.verilog }
      - include: '#constants'
      - include: '#strings'
      - include: '#identifiers' # avoid constant macro parsed as function name (for consistency)
      - name: punctuation.seperator.slash.verilog
        match: '/' # for timescale
      - include: '#expression' # for text macro with argument
scopeName: source.verilog