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Logic Analyzer
hasu@tmk edited this page Nov 24, 2024
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6 revisions
https://github.com/tmk/tmk_keyboard/wiki/Signal-Capture-for-debug
https://deskthority.net/viewtopic.php?f=7&t=4567
This is a script that converters its outputs into VCD format. VCD file can be viewed in PulseView.
#!/usr/bin/python3
# -*- Mode: Python; coding: utf-8; indent-tabs-mode: nil; tab-width: 4 -*-
#
# Converts Soarer's Logic Analyzer output into VCD format
# https://deskthority.net/viewtopic.php?t=4567
#
# 'sctrace' record is comprised of seven hex characters(0-9A-F):
# time: 4 chars/2 bytes; timestamp of event
# stat: 2 chars/1 byte; port state
# flag: 1 char /4 bits; timer event(1) or port state change event(0)
import sys
# https://github.com/westerndigitalcorporation/pyvcd
from vcd import VCDWriter
if len(sys.argv) == 2:
file = open(sys.argv[1])
else:
file = sys.stdin
print(f"Usage: {sys.argv[0]} [infile]", file=sys.stderr)
print('or give data into stdin. Reading from stdin...', file=sys.stderr);
# write VCD
from datetime import datetime, timezone
with VCDWriter(sys.stdout, timescale='1 us', date=datetime.now(timezone.utc).ctime()) as writer:
# prams: scope, name, var_type, size
port = writer.register_var('sctrace', 'port', 'wire', size=8)
# read 'sctrace' output file
ext_time = 0
for line in file:
for record in line.strip().split():
if len(record) == 7:
time = int(record[0:4], 16)
stat = int(record[4:6], 16)
flag = int(record[6:7], 16)
# timer overflow when flag == 1
if flag:
ext_time += 1
# time: 1/16 us(62.5 ns) per tick(@16MHz+Prescaler:1)
writer.change(port, ((ext_time * 0x10000) + time)/16, stat)
https://create.arduino.cc/projecthub/vincenzo-g/diy-logic-analyzer-f61ee5
https://www.instructables.com/id/Arduinolyzerjs-Turn-your-Arduino-into-a-Logic-Anal/
https://hackaday.io/project/1633-arduino-generic-logic-analyzer
https://github.com/gillham/logic_analyzer
https://www.sump.org/projects/analyzer/protocol/