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Transistor-level verilog code #56

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AmentBRT opened this issue Dec 14, 2023 · 1 comment
Open

Transistor-level verilog code #56

AmentBRT opened this issue Dec 14, 2023 · 1 comment

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@AmentBRT
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While I was trying to visualize my transistor-level homework code (it's a simple CMOS circuit), I got this error: "Invalid cell type: nmos".
I understand that all the work is not done here (my thanks for what you have done); So if this problem is not part of this project, can you please check on the other project to see if there's any update on this error?

@tilk
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tilk commented Dec 14, 2023

DigitalJS doesn't support transistor-level circuits and wires with multiple drivers; the focus is on gate-level and RTL description. Implementing this would require a significant redesign of the simulator.

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