From 199b946f3a34fc6cc831584ec97aaa95522b8cba Mon Sep 17 00:00:00 2001 From: Marek Materzok Date: Wed, 8 May 2024 11:40:06 +0200 Subject: [PATCH] Fix synchronous read bug --- package-lock.json | 4 ++-- package.json | 2 +- src/cells/memory.mjs | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/package-lock.json b/package-lock.json index d181f52..ebfddd9 100644 --- a/package-lock.json +++ b/package-lock.json @@ -1,12 +1,12 @@ { "name": "digitaljs", - "version": "0.13.0", + "version": "0.13.1", "lockfileVersion": 2, "requires": true, "packages": { "": { "name": "digitaljs", - "version": "0.13.0", + "version": "0.13.1", "license": "BSD-2-Clause", "dependencies": { "3vl": "^1.0.1", diff --git a/package.json b/package.json index b18d8d1..5f4fc04 100644 --- a/package.json +++ b/package.json @@ -1,6 +1,6 @@ { "name": "digitaljs", - "version": "0.13.0", + "version": "0.13.1", "description": "Digital logic simulator", "main": "./lib/circuit.js", "files": [ diff --git a/src/cells/memory.mjs b/src/cells/memory.mjs index 967e418..124d578 100644 --- a/src/cells/memory.mjs +++ b/src/cells/memory.mjs @@ -171,9 +171,9 @@ export const Memory = Box.define('Memory', { for (const [num, wrport] of this.get('wrports').entries()) { const wrportname = 'wr' + num; const mask_ok = (val, num) => typeof val == 'boolean' ? val : val[num]; - if ('transparent' in port && mask_ok(port.transparent, num) && port_active(wrportname, wrport) && data[portname + 'addr'] == data[wrportname + 'addr']) + if ('transparent' in port && mask_ok(port.transparent, num) && port_active(wrportname, wrport) && is_enabled(wrportname, wrport) && data[portname + 'addr'] == data[wrportname + 'addr']) out[portname + 'data'] = write_value(wrportname, wrport, out[portname + 'data'], data[wrportname + 'data']); - if ('collision' in port && mask_ok(port.collision, num) && port_active(wrportname, wrport) && data[portname + 'addr'] == data[wrportname + 'addr']) + if ('collision' in port && mask_ok(port.collision, num) && port_active(wrportname, wrport) && is_enabled(wrportname, wrport) && data[portname + 'addr'] == data[wrportname + 'addr']) out[portname + 'data'] = write_value(wrportname, wrport, out[portname + 'data'], Vector3vl.xes(bits)); }