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PTL upstream #9185

Merged
merged 9 commits into from
Jun 24, 2024
Merged

PTL upstream #9185

merged 9 commits into from
Jun 24, 2024

Commits on Jun 20, 2024

  1. cmake/zephyr: change if condition to zephyr metod 

    For syntax clearity changed if conditional to zephyr method

Signed-off-by: Dobrowolski, PawelX <[email protected]>
    @pjdobrowolski
    pjdobrowolski committed Jun 20, 2024
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  2. platform: version: add hardware configuration version 

    Due to introducing new platform to sof we need to recognize which
iteration of ace board we are dealing with.

Signed-off-by: Dobrowolski, PawelX <[email protected]>
    @pjdobrowolski
    pjdobrowolski committed Jun 20, 2024
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  3. ptl: Add initial PTL configuration 

    Patch adds PTL configuration basing on MTL

DMIC depends on PM_DEVICE_RUNTIME and PM_DEVICE_POWER_DOMIAN settings.
To effectively enable DMIC these flags must be set.
Additionally DMIC Ownership bit is not supported on ACE 2.0 and ACE 3.0.
Therefore CONFIG_DAI_DMIC_HAS_OWNERSHIP is switched off.

Signed-off-by: Jakub Dabek <[email protected]>
    @jxstelter @pjdobrowolski
    jxstelter authored and pjdobrowolski committed Jun 20, 2024
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  4. intel_adsp: ptl: Enable chain-dma on PTL platform 

    Enable chain-dma hw support on PTL platform

Signed-off-by: Piotr Makaruk <[email protected]>
    @makarukp @pjdobrowolski
    makarukp authored and pjdobrowolski committed Jun 20, 2024
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  5. intel_adsp: ptl: Enable LE HEAP on ptl 

    Enable L3 HEAP to support D3 scenarios on PTL

Signed-off-by: Jakub Dabek <[email protected]>
    @jxstelter @pjdobrowolski
    jxstelter authored and pjdobrowolski committed Jun 20, 2024
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  6. intel_adsp: ptl: Enable D3 flow on PTL 

    This PR enabled D3 flow on PTL platform.

Signed-off-by: Jaroslaw Stelter <[email protected]>
    @jxstelter @pjdobrowolski
    jxstelter authored and pjdobrowolski committed Jun 20, 2024
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  7. ptl: Add FPGA overlay configuration 

    Add PTL configuration changes required to build FW
for FPGA. After next SOF rebase default target will be
build for RVP, so for FPGA we will use configuration
overlay.

Signed-off-by: Jaroslaw Stelter <[email protected]>
    @jxstelter @pjdobrowolski
    jxstelter authored and pjdobrowolski committed Jun 20, 2024
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  8. ptl: lnl: memory: expand HEAPMEM_SIZE 

    FW infrastructure shall support buffering of historic data
from 1ch up to 6 channels 24bit samples in 24bit container.
For this reason, the heap should be extended.Increase HEAPMEM_SIZE
by 0x90000 because for audio format 16000Hz/6ch/24bit
history_buffer_size = 16 * 6 * 3 * 2100s = 604800 bytes (0x93A80)

Signed-off-by: Jaroslaw Stelter <[email protected]>
    @jxstelter @pjdobrowolski
    jxstelter authored and pjdobrowolski committed Jun 20, 2024
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  9. tools: rimage: config: add PTL config 

    Add base PTL config derived from MTL.

Signed-off-by: Jaroslaw Stelter <[email protected]>
    @jxstelter @pjdobrowolski
    jxstelter authored and pjdobrowolski committed Jun 20, 2024
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