imx: clear general purpose pending interrupt #6658
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iuliana-prodan
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paulstelian97,
kv2019i,
LaurentiuM1234,
lgirdwood and
lyakh
dbaluta
approved these changes
Nov 24, 2022
paulstelian97
approved these changes
Nov 24, 2022
lgirdwood
approved these changes
Nov 24, 2022
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SOFCI TEST |
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@iuliana-prodan can you check here, this PR is breaking the qemu boot on IMX ? |
I'm looking into it. |
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@iuliana-prodan any update ? |
Sorry for the late reply, we had some days off (National day in Romania). |
Qemu update merged, not sure if container needs a manual update or not. Have asked. |
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SOFCI TEST |
Clear general purpose pending interrupt before enabling interrupts between host and DSP. The GIPn bit, from MU Status Register is cleared by writing it as “1” in order to de-assert the interrupt request source at the interrupt controller. This fixes a fw loading failure after a soft reboot caused by GIP bit that was 1. The problem was the MU which triggered endless interrupts causing timeout on Kernel side, which was waiting for FW_READY message. Signed-off-by: Iuliana Prodan <[email protected]>
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dbaluta
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Dec 5, 2022
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yes docker updates are always manual (and generally rare). See discussions in |
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Clear general purpose pending interrupt
before enabling interrupts between host and DSP.
The GIPn bit, from MU Status Register is cleared
by writing it as “1” in order to de-assert the
interrupt request source at the interrupt controller.
This fixes a fw loading failure after a soft reboot caused by GIP bit that was 1.
The problem was the MU which triggered endless interrupts causing timeout on Kernel side, which was waiting for FW_READY message.
Signed-off-by: Iuliana Prodan [email protected]