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Status:
NaN's will be represented as follows:
bit31 bits[30:0]
sign 'b7FFF_FFFF
bit15 bits[14:0]
sign 'b7FFF
When an operation is executed that would normally produce NaNs, these will end up being the value. We are going to simply update the tests to reflect this expectation going forward.
@ttmtrajkovic and team will be documenting this and it will eventually get added to the public online documentation.
The text was updated successfully, but these errors were encountered:
NaN is represented as the following, which should be following ieee754 standard:
fp32:
bit31 bits[30:0]
sign 'b7FFF_FFFF
bf16:
bit15 bits[14:0]
sign 'b7FFF
FPU hardware will no recognize it as "special" and treat is as just regular input. SFPU hardware also doesn't do any special handling of this value, but seeing that as part of math will set a sticky bit in on of status registers.
Any special handling on NaN will have to be done by the op writers in sfpu kernels.
Status:
NaN's will be represented as follows:
bit31 bits[30:0]
sign 'b7FFF_FFFF
bit15 bits[14:0]
sign 'b7FFF
When an operation is executed that would normally produce NaNs, these will end up being the value. We are going to simply update the tests to reflect this expectation going forward.
@ttmtrajkovic and team will be documenting this and it will eventually get added to the public online documentation.
The text was updated successfully, but these errors were encountered: