From b2145e77d45a4c512de87b8b3fef3ea0d51c0f66 Mon Sep 17 00:00:00 2001 From: Yen-Fu Chen Date: Sat, 17 Dec 2022 23:44:38 +0800 Subject: [PATCH] Set rv->compressed for instruction ecall and ebreak The exception handler is invoked by the instructions ecall and ebreak, thus we must set rv->compressed for these instructions. --- src/decode.c | 18 +++++++++--------- src/emulate.c | 35 ++++++++++++++++++++--------------- src/map.c | 2 +- src/riscv_private.h | 4 ++-- 4 files changed, 32 insertions(+), 27 deletions(-) diff --git a/src/decode.c b/src/decode.c index 4016eeb70..b38b127aa 100644 --- a/src/decode.c +++ b/src/decode.c @@ -76,7 +76,7 @@ static inline int32_t decode_jtype_imm(const uint32_t insn) */ static inline int32_t decode_itype_imm(const uint32_t insn) { - return ((int32_t) (insn & FI_IMM_11_0)) >> 20; + return ((int32_t)(insn & FI_IMM_11_0)) >> 20; } /* decode B-type instruction immediate. @@ -141,7 +141,7 @@ enum { */ static inline uint16_t c_decode_rs1(const uint16_t insn) { - return (uint16_t) ((insn & FC_RS1) >> 7U); + return (uint16_t)((insn & FC_RS1) >> 7U); } /* decode rs2 field @@ -149,7 +149,7 @@ static inline uint16_t c_decode_rs1(const uint16_t insn) */ static inline uint16_t c_decode_rs2(const uint16_t insn) { - return (uint16_t) ((insn & FC_RS2) >> 2U); + return (uint16_t)((insn & FC_RS2) >> 2U); } /* decode rd field @@ -157,7 +157,7 @@ static inline uint16_t c_decode_rs2(const uint16_t insn) */ static inline uint16_t c_decode_rd(const uint16_t insn) { - return (uint16_t) ((insn & FC_RD) >> 7U); + return (uint16_t)((insn & FC_RD) >> 7U); } /* decode rs1' field @@ -165,7 +165,7 @@ static inline uint16_t c_decode_rd(const uint16_t insn) */ static inline uint16_t c_decode_rs1c(const uint16_t insn) { - return (uint16_t) ((insn & FC_RS1C) >> 7U); + return (uint16_t)((insn & FC_RS1C) >> 7U); } /* decode rs2' field @@ -173,7 +173,7 @@ static inline uint16_t c_decode_rs1c(const uint16_t insn) */ static inline uint16_t c_decode_rs2c(const uint16_t insn) { - return (uint16_t) ((insn & FC_RS2C) >> 2U); + return (uint16_t)((insn & FC_RS2C) >> 2U); } /* decode rd' field @@ -181,7 +181,7 @@ static inline uint16_t c_decode_rs2c(const uint16_t insn) */ static inline uint16_t c_decode_rdc(const uint16_t insn) { - return (uint16_t) ((insn & FC_RDC) >> 2U); + return (uint16_t)((insn & FC_RDC) >> 2U); } /* decode C.ADDI4SPN nzuimm field @@ -238,7 +238,7 @@ static inline int32_t c_decode_caddi_imm(const uint16_t insn) static inline int32_t c_decode_citype_imm(const uint16_t insn) { uint32_t tmp = ((insn & FCI_IMM_12) >> 7) | ((insn & FCI_IMM_6_2) >> 2); - return (tmp & 0x20) ? (int32_t) (0xffffffc0 | tmp) : (int32_t) tmp; + return (tmp & 0x20) ? (int32_t)(0xffffffc0 | tmp) : (int32_t) tmp; } /* decode CJ-format instruction immediate @@ -267,7 +267,7 @@ static inline int32_t c_decode_cjtype_imm(const uint16_t insn) tmp |= (0x0800 & tmp) << i; /* extend to 16 bit */ - return (int32_t) (int16_t) tmp; + return (int32_t)(int16_t) tmp; } /* decode CB-format shamt field diff --git a/src/emulate.c b/src/emulate.c index 8960dbf87..02692430c 100644 --- a/src/emulate.c +++ b/src/emulate.c @@ -567,13 +567,13 @@ static bool emulate(riscv_t *rv, const block_t *block) * bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 * assembler pseudo-instruction. */ - _(addi, rv->X[ir->rd] = (int32_t) (rv->X[ir->rs1]) + ir->imm;) + _(addi, rv->X[ir->rd] = (int32_t)(rv->X[ir->rs1]) + ir->imm;) /* SLTI (Set on Less Than Immediate) places the value 1 in register rd if * register rs1 is less than the signextended immediate when both are * treated as signed numbers, else 0 is written to rd. */ - _(slti, rv->X[ir->rd] = ((int32_t) (rv->X[ir->rs1]) < ir->imm) ? 1 : 0;) + _(slti, rv->X[ir->rd] = ((int32_t)(rv->X[ir->rs1]) < ir->imm) ? 1 : 0;) /* SLTIU (Set on Less Than Immediate Unsigned) places the value 1 in * register rd if register rs1 is less than the immediate when both are @@ -612,11 +612,11 @@ static bool emulate(riscv_t *rv, const block_t *block) /* ADD */ _(add, - rv->X[ir->rd] = (int32_t) (rv->X[ir->rs1]) + (int32_t) (rv->X[ir->rs2]);) + rv->X[ir->rd] = (int32_t)(rv->X[ir->rs1]) + (int32_t)(rv->X[ir->rs2]);) /* SUB: Substract */ _(sub, - rv->X[ir->rd] = (int32_t) (rv->X[ir->rs1]) - (int32_t) (rv->X[ir->rs2]);) + rv->X[ir->rd] = (int32_t)(rv->X[ir->rs1]) - (int32_t)(rv->X[ir->rs2]);) /* SLL: Shift Left Logical */ _(sll, rv->X[ir->rd] = rv->X[ir->rs1] << (rv->X[ir->rs2] & 0x1f);) @@ -624,7 +624,7 @@ static bool emulate(riscv_t *rv, const block_t *block) /* SLT: Set on Less Than */ _(slt, { rv->X[ir->rd] = - ((int32_t) (rv->X[ir->rs1]) < (int32_t) (rv->X[ir->rs2])) ? 1 : 0; + ((int32_t)(rv->X[ir->rs1]) < (int32_t)(rv->X[ir->rs2])) ? 1 : 0; }) /* SLTU: Set on Less Than Unsigned */ @@ -649,6 +649,7 @@ static bool emulate(riscv_t *rv, const block_t *block) /* ECALL: Environment Call */ _(ecall, { + rv->compressed = false; rv->io.on_ecall(rv); /* increment the cycles csr */ rv->csr_cycle++; return true; @@ -656,6 +657,7 @@ static bool emulate(riscv_t *rv, const block_t *block) /* EBREAK: Environment Break */ _(ebreak, { + rv->compressed = false; rv->io.on_ebreak(rv); /* increment the cycles csr */ rv->csr_cycle++; return true; @@ -737,14 +739,14 @@ static bool emulate(riscv_t *rv, const block_t *block) _(mulh, { const int64_t a = (int32_t) rv->X[ir->rs1]; const int64_t b = (int32_t) rv->X[ir->rs2]; - rv->X[ir->rd] = ((uint64_t) (a * b)) >> 32; + rv->X[ir->rd] = ((uint64_t)(a * b)) >> 32; }) /* MULHSU: Multiply High Signed Unsigned */ _(mulhsu, { const int64_t a = (int32_t) rv->X[ir->rs1]; const uint64_t b = rv->X[ir->rs2]; - rv->X[ir->rd] = ((uint64_t) (a * b)) >> 32; + rv->X[ir->rd] = ((uint64_t)(a * b)) >> 32; }) /* MULHU: Multiply High Unsigned Unsigned */ @@ -757,10 +759,11 @@ static bool emulate(riscv_t *rv, const block_t *block) _(div, { const int32_t dividend = (int32_t) rv->X[ir->rs1]; const int32_t divisor = (int32_t) rv->X[ir->rs2]; - rv->X[ir->rd] = !divisor ? ~0U - : (divisor == -1 && rv->X[ir->rs1] == 0x80000000U) - ? rv->X[ir->rs1] /* overflow */ - : (unsigned int) (dividend / divisor); + rv->X[ir->rd] = !divisor + ? ~0U + : (divisor == -1 && rv->X[ir->rs1] == 0x80000000U) + ? rv->X[ir->rs1] /* overflow */ + : (unsigned int) (dividend / divisor); }) /* DIVU: Divide Unsigned */ @@ -774,10 +777,11 @@ static bool emulate(riscv_t *rv, const block_t *block) _(rem, { const int32_t dividend = rv->X[ir->rs1]; const int32_t divisor = rv->X[ir->rs2]; - rv->X[ir->rd] = !divisor ? dividend - : (divisor == -1 && rv->X[ir->rs1] == 0x80000000U) - ? 0 /* overflow */ - : (dividend % divisor); + rv->X[ir->rd] = !divisor + ? dividend + : (divisor == -1 && rv->X[ir->rs1] == 0x80000000U) + ? 0 /* overflow */ + : (dividend % divisor); }) /* REMU: Remainder Unsigned */ @@ -1288,6 +1292,7 @@ static bool emulate(riscv_t *rv, const block_t *block) /* C.EBREAK */ _(cebreak, { + rv->compressed = true; rv->io.on_ebreak(rv); /* increment the cycles csr */ rv->csr_cycle++; diff --git a/src/map.c b/src/map.c index 3b27c7f7f..8c4b87f5c 100644 --- a/src/map.c +++ b/src/map.c @@ -42,7 +42,7 @@ static inline map_node_t *rb_parent(const map_node_t *node) */ static inline map_color_t rb_color(const map_node_t *node) { - return (map_color_t) (node->parent_color & 1LU); + return (map_color_t)(node->parent_color & 1LU); } /* diff --git a/src/riscv_private.h b/src/riscv_private.h index b48f316f2..92be0174d 100644 --- a/src/riscv_private.h +++ b/src/riscv_private.h @@ -104,11 +104,11 @@ struct riscv_internal { /* sign extend a 16 bit value */ static inline uint32_t sign_extend_h(const uint32_t x) { - return (int32_t) ((int16_t) x); + return (int32_t)((int16_t) x); } /* sign extend an 8 bit value */ static inline uint32_t sign_extend_b(const uint32_t x) { - return (int32_t) ((int8_t) x); + return (int32_t)((int8_t) x); }