From 3a972dabd5f2c2870938fa406912577241f3b5f0 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sun, 7 Jul 2024 18:38:10 +0200 Subject: [PATCH] [docs] CFU: minor edit --- docs/datasheet/cpu_cfu.adoc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/datasheet/cpu_cfu.adoc b/docs/datasheet/cpu_cfu.adoc index da904b1b0..8aaf93595 100644 --- a/docs/datasheet/cpu_cfu.adoc +++ b/docs/datasheet/cpu_cfu.adoc @@ -60,10 +60,10 @@ Example operation: `rd <= rs1 xnor rs2` (bit-wise XNOR) .CFU R3-type instruction format image::cfu_r3type_instruction.png[align=left] -* `funct7`: 7-bit immediate (further operand data or function select) +* `funct7`: 7-bit immediate (immediate data or function select) * `rs2`: address of second source register (32-bit source data) * `rs1`: address of first source register (32-bit source data) -* `funct3`: 3-bit immediate (further operand data or function select) +* `funct3`: 3-bit immediate (immediate data or function select) * `rd`: address of destination register (for the 32-bit processing result) * `opcode`: `0001011` (RISC-V "custom-0" opcode) @@ -94,7 +94,7 @@ image::cfu_r4type_instruction.png[align=left] * `rs3`: address of third source register (32-bit source data) * `rs2`: address of second source register (32-bit source data) * `rs1`: address of first source register (32-bit source data) -* `funct3`: 3-bit immediate (further operand data or function select) +* `funct3`: 3-bit immediate (immediate data or function select) * `rd`: address of destination register (for the 32-bit processing result) * `opcode`: `0101011` (RISC-V "custom-1" opcode)