From 064318beced25e14659936805bb122d1d8aea152 Mon Sep 17 00:00:00 2001 From: Unai Sainz-Estebanez Date: Thu, 16 Nov 2023 18:43:02 +0100 Subject: [PATCH] Fix comment mistake --- rtl/core/neorv32_cpu_cp_cfu.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/core/neorv32_cpu_cp_cfu.vhd b/rtl/core/neorv32_cpu_cp_cfu.vhd index fe3fffc2b..bd27ddd8e 100644 --- a/rtl/core/neorv32_cpu_cp_cfu.vhd +++ b/rtl/core/neorv32_cpu_cp_cfu.vhd @@ -177,7 +177,7 @@ begin -- -- Up to 8 RISC-V R4-Type Instructions (RISC-V standard): -- This format consists of three source registers ('rs1', 'rs2', 'rs3'), a destination register ('rd') and one "immediate" - -- bit-field ('funct7'). + -- bit-field ('funct3'). -- -- Two individual RISC-V R5-Type Instructions (NEORV32-specific): -- This format consists of four source registers ('rs1', 'rs2', 'rs3', 'rs4') and a destination register ('rd'). There are