diff --git a/rtl/core/neorv32_cpu_cp_cfu.vhd b/rtl/core/neorv32_cpu_cp_cfu.vhd
index c15e9efd3..a0754322c 100644
--- a/rtl/core/neorv32_cpu_cp_cfu.vhd
+++ b/rtl/core/neorv32_cpu_cp_cfu.vhd
@@ -177,7 +177,7 @@ begin
   --
   -- Up to 8 RISC-V R4-Type Instructions (RISC-V standard):
   -- This format consists of three source registers ('rs1', 'rs2', 'rs3'), a destination register ('rd') and one "immediate"
-  -- bit-field ('funct7').
+  -- bit-field ('funct3').
   --
   -- Two individual RISC-V R5-Type Instructions (NEORV32-specific):
   -- This format consists of four source registers ('rs1', 'rs2', 'rs3', 'rs4') and a destination register ('rd'). There are