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overall option code rework #927

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merged 10 commits into from
Apr 19, 2020
Merged

overall option code rework #927

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ee4a522
st-flash: print proper error in case of option byte read error.
grevaillot Apr 6, 2020
8430a6e
add read, write option byte for g4 and g0
grevaillot Apr 6, 2020
1801fb1
flash.c: move device specific read option stuff to common.c
grevaillot Apr 14, 2020
2aeae8d
chipid: add option bytes info to chip db
grevaillot Apr 14, 2020
92ceb7f
chipid: insert data for supported chips, from common.c
grevaillot Apr 14, 2020
6f0795d
chipid: add some l0 and l4 option info to allow option byte read
grevaillot Apr 14, 2020
72cfd5e
option: refactor option flash code.
grevaillot Apr 14, 2020
e146a28
st-flash: add sanity check to option flash.
grevaillot Apr 14, 2020
3aaec27
common.c: fix define - use Gx Base for Gx defines
grevaillot Apr 16, 2020
19facc9
indent
grevaillot Apr 17, 2020
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14 changes: 10 additions & 4 deletions include/stlink.h
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Original file line number Diff line number Diff line change
Expand Up @@ -170,6 +170,10 @@ typedef struct flash_loader {
stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params()
size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params()

/* option settings */
stm32_addr_t option_base;
size_t option_size;

// bootloader
// sys_base and sys_size are not used by the tools, but are only there to
// download the bootloader code (see tests/sg.c)
Expand Down Expand Up @@ -213,8 +217,6 @@ typedef struct flash_loader {
uint8_t stlink_get_erased_pattern(stlink_t *sl);
int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr);
int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr);
int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val);
int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr);
int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
Expand All @@ -236,8 +238,12 @@ typedef struct flash_loader {
int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size);
int stlink_load_device_params(stlink_t *sl);
int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte);
int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte);

int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte);
int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte);

int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len);
int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr);

#include "stlink/sg.h"
#include "stlink/usb.h"
Expand Down
4 changes: 3 additions & 1 deletion include/stlink/chipid.h
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,7 @@ enum stlink_stm32_chipids {
STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */
STLINK_CHIPID_STM32_L011 = 0x457,
STLINK_CHIPID_STM32_F410 = 0x458,
STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */
STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */
STLINK_CHIPID_STM32_F413 = 0x463,
STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */
STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */
Expand All @@ -79,6 +79,8 @@ struct stlink_chipid_params {
uint32_t sram_size;
uint32_t bootrom_base;
uint32_t bootrom_size;
uint32_t option_base;
uint32_t option_size;
};

const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid);
Expand Down
5 changes: 3 additions & 2 deletions include/stm32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,9 +15,10 @@
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
#define STM32_SRAM_BASE ((uint32_t)0x20000000)
#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_L0_CATx_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000)
#define STM32_L496X_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)

#endif /* STM32_H */
45 changes: 34 additions & 11 deletions src/chipid.c
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Original file line number Diff line number Diff line change
Expand Up @@ -175,7 +175,9 @@ static const struct stlink_chipid_params devices[] = {
.flash_pagesize = 0x100,
.sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
.bootrom_base = 0x1ff00000,
.bootrom_size = 0x1000
.bootrom_size = 0x1000,
.option_base = STM32_L1_OPTION_BYTES_BASE,
.option_size = 8,
},
{
.chip_id = STLINK_CHIPID_STM32_L152_RE,
Expand Down Expand Up @@ -376,7 +378,9 @@ static const struct stlink_chipid_params devices[] = {
.flash_pagesize = 0x80,
.sram_size = 0x2000,
.bootrom_base = 0x1ff0000,
.bootrom_size = 0x1000
.bootrom_size = 0x1000,
.option_base = STM32_L0_CATx_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STM32L0x Category 5
Expand All @@ -388,7 +392,9 @@ static const struct stlink_chipid_params devices[] = {
.flash_pagesize = 0x80,
.sram_size = 0x5000,
.bootrom_base = 0x1ff0000,
.bootrom_size = 0x2000
.bootrom_size = 0x2000,
.option_base = STM32_L0_CATx_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STM32L0x Category 2
Expand All @@ -400,7 +406,9 @@ static const struct stlink_chipid_params devices[] = {
.flash_pagesize = 0x80,
.sram_size = 0x2000,
.bootrom_base = 0x1ff0000,
.bootrom_size = 0x1000
.bootrom_size = 0x1000,
.option_base = STM32_L0_CATx_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STM32F334, STM32F303x6/8, and STM32F328
Expand Down Expand Up @@ -439,7 +447,9 @@ static const struct stlink_chipid_params devices[] = {
// sizes; table 2, page 74 for SRAM2 location)
.sram_size = 0x18000,
.bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
.bootrom_size = 0x7000 // 28k (per bank), same source as base
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.option_base = STM32_L4_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STM32L4RX
Expand Down Expand Up @@ -480,7 +490,9 @@ static const struct stlink_chipid_params devices[] = {
// sizes; table 2, page 74 for SRAM2 location)
.sram_size = 0xc000,
.bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
.bootrom_size = 0x7000 // 28k (per bank), same source as base
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.option_base = STM32_L4_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STLINK_CHIPID_STM32_L496X
Expand All @@ -494,7 +506,9 @@ static const struct stlink_chipid_params devices[] = {
// SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74)
.sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84)
.bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1)
.bootrom_size = 0x7000 // 28k (per bank), same source as base
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.option_base = STM32_L4_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STLINK_CHIPID_STM32_L46X
Expand Down Expand Up @@ -530,7 +544,9 @@ static const struct stlink_chipid_params devices[] = {
.flash_pagesize = 0x800, // 2K (sec 3.2)
.sram_size = 0x2000, // 8K (sec 2.3)
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x2000 // 8K (sec 2.2.2 table 3)
.bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3)
.option_base = STM32_G0_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STM32G071/081 (from RM0444)
Expand All @@ -541,7 +557,9 @@ static const struct stlink_chipid_params devices[] = {
.flash_pagesize = 0x800, // 2K (sec 3.2)
.sram_size = 0x9000, // 36K (sec 2.3)
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7000 // 28K (sec 2.2.2 table 2)
.bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2)
.option_base = STM32_G0_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STM32G431/441 (from RM0440)
Expand All @@ -555,7 +573,10 @@ static const struct stlink_chipid_params devices[] = {
// SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000
.sram_size = 0x8000, // 32K (sec 2.4)
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7000 // 28K (table 2)
.bootrom_size = 0x7000, // 28K (table 2)
.option_base = STM32_G4_OPTION_BYTES_BASE,
.option_size = 4,

},
{
// STM32G471/473/474/483/484 (from RM0440)
Expand All @@ -570,7 +591,9 @@ static const struct stlink_chipid_params devices[] = {
// SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000
.sram_size = 0x18000, // 128K (sec 2.4)
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7000 // 28K (table 2)
.bootrom_size = 0x7000, // 28K (table 2)
.option_base = STM32_G4_OPTION_BYTES_BASE,
.option_size = 4,
},
{
// STM32WB55 (from RM0434)
Expand Down
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