From ee4a52288a68126f3c74fee7d3413fa5ee9900bd Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 6 Apr 2020 14:32:34 +0200 Subject: [PATCH 01/10] st-flash: print proper error in case of option byte read error. User could get a wrong "stlink_fread()" error in case of bad stlink_read_option_foo.. --- src/tools/flash.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index f39b6c6e4..6e7b37103 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -218,6 +218,10 @@ int main(int ac, char** av) printf("%x\n",option_byte); } else { printf("This format is available for STM32F2 and STM32F4 only\n"); + if (err == -1) + { + printf("could not read option bytes\n"); + goto on_error; } } else { if ((o.addr >= sl->flash_base) && (o.size == 0) && @@ -229,11 +233,12 @@ int main(int ac, char** av) o.size = sl->sram_size; } err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); - } - if (err == -1) - { - printf("stlink_fread() == -1\n"); - goto on_error; + + if (err == -1) + { + printf("stlink_fread() == -1\n"); + goto on_error; + } } } From 8430a6e6fa7d507fa5a19ef2552f3ae5422aa24e Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 6 Apr 2020 14:01:35 +0200 Subject: [PATCH 02/10] add read, write option byte for g4 and g0 use g0 code, same logic with different base address. also cleanup some duplicate lock/unlock code. --- include/stlink.h | 1 + include/stm32.h | 1 + src/common.c | 57 +++++++++++++++++++++++++++-------------------- src/tools/flash.c | 9 +++++--- 4 files changed, 41 insertions(+), 27 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 508b50f7d..a21874454 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -236,6 +236,7 @@ typedef struct flash_loader { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); + int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte); int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); diff --git a/include/stm32.h b/include/stm32.h index 9a01baaf4..890d11254 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -15,6 +15,7 @@ #define STM32_FLASH_BASE ((uint32_t)0x08000000) #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) #define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_L496X_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) diff --git a/src/common.c b/src/common.c index e94240351..332b9125d 100644 --- a/src/common.c +++ b/src/common.c @@ -2736,7 +2736,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, uint32_t len) { uint32_t val; @@ -2750,25 +2750,16 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l /* Check if chip is supported and for correct address */ if (sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 && - sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) { - ELOG("Option bytes writing is currently only supported for the STM32G0\n"); + sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2 && + sl->chip_id != STLINK_CHIPID_STM32_G4_CAT2 && + sl->chip_id != STLINK_CHIPID_STM32_G4_CAT3) { + ELOG("Option bytes writing is currently only supported for the STM32G0/G4\n"); return -1; } - /* Unlock flash if necessary (ref manuel page 52) */ - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) { - - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32Gx_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32Gx_FLASH_KEYR, 0xCDEF89AB); - - // check that the lock is no longer set. - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; } /* Unlock option bytes if necessary (ref manuel page 61) */ @@ -2802,7 +2793,9 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l /* Wait for 'busy' bit in FLASH_SR to clear. */ do { stlink_read_debug32(sl, STM32Gx_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); + } while ((val & (1 << STM32Gx_FLASH_SR_BSY)) != 0); + + check_flash_error(sl); /* apply options bytes immediate */ stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2813,10 +2806,9 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); val |= (1u << STM32Gx_FLASH_CR_OPTLOCK); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + /* Re-lock flash. */ - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1u << STM32Gx_FLASH_CR_LOCK); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + lock_flash(sl); return 0; } @@ -3147,6 +3139,19 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint32_t option_byte) { return 0; } +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) +{ + uint32_t ret = stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); + WLOG("option bytes CR = %#010x\n", *option_byte); + return ret; +} + /** * Read option bytes * @param sl @@ -3183,7 +3188,7 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { /** * Read option bytes * @param sl - * @param option_byte value to write + * @param option_byte value to read * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { @@ -3230,9 +3235,13 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui /* Check if chip is supported and for correct address */ if (((sl->chip_id == STLINK_CHIPID_STM32_G0_CAT1) || (sl->chip_id == STLINK_CHIPID_STM32_G0_CAT2)) && (addr == STM32_G0_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_g0x(sl, base, len); + return stlink_write_option_bytes_gx(sl, base, len); + } + else if (((sl->chip_id == STLINK_CHIPID_STM32_G4_CAT2) || + (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3)) && (addr == STM32_G4_OPTION_BYTES_BASE)) { + return stlink_write_option_bytes_gx(sl, base, len); } - else if ((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { + else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_l0_cat2(sl, base, len); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { diff --git a/src/tools/flash.c b/src/tools/flash.c index 6e7b37103..e211a2e81 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -208,16 +208,19 @@ int main(int ac, char** av) else /* read */ { if (o.area == FLASH_OPTION_BYTES){ + uint32_t option_byte = 0; if (sl->chip_id == STLINK_CHIPID_STM32_F2){ - uint32_t option_byte = 0; err = stlink_read_option_bytes_f2(sl,&option_byte); printf("%x\n",option_byte); } else if (sl->chip_id == STLINK_CHIPID_STM32_F446){ - uint32_t option_byte = 0; err = stlink_read_option_bytes_f4(sl,&option_byte); printf("%x\n",option_byte); + }else if(sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + err = stlink_read_option_bytes_Gx(sl,&option_byte); + printf("%x\n",option_byte); } else { - printf("This format is available for STM32F2 and STM32F4 only\n"); + printf("This format is only available for STM32F2, STM32F4, STM32G0 and STM32G4\n"); + } if (err == -1) { printf("could not read option bytes\n"); From 1801fb1f005a93756ea566cb0cdb658611982f99 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 15:03:19 +0200 Subject: [PATCH 03/10] flash.c: move device specific read option stuff to common.c --- include/stlink.h | 9 ++++----- src/common.c | 20 ++++++++++++++++++++ src/tools/flash.c | 26 ++++++++------------------ 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index a21874454..078251cf8 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -213,8 +213,6 @@ typedef struct flash_loader { uint8_t stlink_get_erased_pattern(stlink_t *sl); int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); @@ -236,9 +234,10 @@ typedef struct flash_loader { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); - int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte); - int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); - int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); + + int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte); + int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); #include "stlink/sg.h" #include "stlink/usb.h" diff --git a/src/common.c b/src/common.c index 332b9125d..00d982593 100644 --- a/src/common.c +++ b/src/common.c @@ -3218,6 +3218,26 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { return 0; } +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte) { + int err = -1; + if (sl->chip_id == STLINK_CHIPID_STM32_F2){ + err = stlink_read_option_bytes_f2(sl, option_byte); + }else if(sl->chip_id == STLINK_CHIPID_STM32_F446){ + err = stlink_read_option_bytes_f4(sl, option_byte); + }else if(sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + err = stlink_read_option_bytes_Gx(sl, option_byte); + }else{ + ELOG("This format is only available for STM32F2, STM32F4, STM32G0 and STM32G4\n"); + } + return err; +} + /** * Write option bytes * @param sl diff --git a/src/tools/flash.c b/src/tools/flash.c index e211a2e81..06256823c 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -207,26 +207,16 @@ int main(int ac, char** av) } else /* read */ { - if (o.area == FLASH_OPTION_BYTES){ - uint32_t option_byte = 0; - if (sl->chip_id == STLINK_CHIPID_STM32_F2){ - err = stlink_read_option_bytes_f2(sl,&option_byte); + if(o.area == FLASH_OPTION_BYTES){ + uint32_t option_byte; + err = stlink_read_option_bytes(sl, &option_byte); + if (err == -1) { + printf("could not read option bytes (%d)\n", err); + goto on_error; + } else { printf("%x\n",option_byte); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F446){ - err = stlink_read_option_bytes_f4(sl,&option_byte); - printf("%x\n",option_byte); - }else if(sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { - err = stlink_read_option_bytes_Gx(sl,&option_byte); - printf("%x\n",option_byte); - } else { - printf("This format is only available for STM32F2, STM32F4, STM32G0 and STM32G4\n"); - } - if (err == -1) - { - printf("could not read option bytes\n"); - goto on_error; } - } else { + }else{ if ((o.addr >= sl->flash_base) && (o.size == 0) && (o.addr < sl->flash_base + sl->flash_size)){ o.size = sl->flash_size; From 2aeae8d85f74b00aeb64cfcf5c4d644f8fbecf08 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 16:30:58 +0200 Subject: [PATCH 04/10] chipid: add option bytes info to chip db --- include/stlink.h | 4 ++++ include/stlink/chipid.h | 2 ++ src/common.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/include/stlink.h b/include/stlink.h index 078251cf8..f22abbb42 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -170,6 +170,10 @@ typedef struct flash_loader { stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + /* option settings */ + stm32_addr_t option_base; + size_t option_size; + // bootloader // sys_base and sys_size are not used by the tools, but are only there to // download the bootloader code (see tests/sg.c) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index d23596c0d..64227962b 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -79,6 +79,8 @@ struct stlink_chipid_params { uint32_t sram_size; uint32_t bootrom_base; uint32_t bootrom_size; + uint32_t option_base; + uint32_t option_size; }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); diff --git a/src/common.c b/src/common.c index 00d982593..4525d0222 100644 --- a/src/common.c +++ b/src/common.c @@ -920,6 +920,8 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; + sl->option_base = params->option_base; + sl->option_size = params->option_size; //medium and low devices have the same chipid. ram size depends on flash size. //STM32F100xx datasheet Doc ID 16455 Table 2 From 92ceb7f35a667637b574924be9d43f70e6073eb3 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 16:33:15 +0200 Subject: [PATCH 05/10] chipid: insert data for supported chips, from common.c --- src/chipid.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index b9d3933f0..5d43c3ab0 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -175,7 +175,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .option_base = STM32_L1_OPTION_BYTES_BASE, + .option_size = 8, }, { .chip_id = STLINK_CHIPID_STM32_L152_RE, @@ -400,7 +402,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x80, .sram_size = 0x2000, .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .option_base = STM32_L0_CAT2_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32F334, STM32F303x6/8, and STM32F328 @@ -494,7 +498,9 @@ static const struct stlink_chipid_params devices[] = { // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000 // 28k (per bank), same source as base + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L496X_OPTION_BYTES_BASE, + .option_size = 4, }, { // STLINK_CHIPID_STM32_L46X @@ -530,7 +536,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2K (sec 3.2) .sram_size = 0x2000, // 8K (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000 // 8K (sec 2.2.2 table 3) + .bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32G071/081 (from RM0444) @@ -541,7 +549,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2K (sec 3.2) .sram_size = 0x9000, // 36K (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000 // 28K (sec 2.2.2 table 2) + .bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32G431/441 (from RM0440) @@ -555,7 +565,10 @@ static const struct stlink_chipid_params devices[] = { // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 .sram_size = 0x8000, // 32K (sec 2.4) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000 // 28K (table 2) + .bootrom_size = 0x7000, // 28K (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4*4, + }, { // STM32G471/473/474/483/484 (from RM0440) @@ -570,7 +583,9 @@ static const struct stlink_chipid_params devices[] = { // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 .sram_size = 0x18000, // 128K (sec 2.4) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000 // 28K (table 2) + .bootrom_size = 0x7000, // 28K (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4*4, }, { // STM32WB55 (from RM0434) From 6f0795d931500d556420e27e2d62683a336c1fd2 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 17:35:15 +0200 Subject: [PATCH 06/10] chipid: add some l0 and l4 option info to allow option byte read --- include/stlink/chipid.h | 2 +- include/stm32.h | 4 ++-- src/chipid.c | 26 +++++++++++++++++--------- src/common.c | 2 +- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 64227962b..98164a8fc 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -57,7 +57,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ diff --git a/include/stm32.h b/include/stm32.h index 890d11254..c71718653 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -16,9 +16,9 @@ #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_L0_CATx_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) -#define STM32_L496X_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #endif /* STM32_H */ diff --git a/src/chipid.c b/src/chipid.c index 5d43c3ab0..bc3d37567 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -378,7 +378,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x80, .sram_size = 0x2000, .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32L0x Category 5 @@ -390,7 +392,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x80, .sram_size = 0x5000, .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32L0x Category 2 @@ -403,7 +407,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, - .option_base = STM32_L0_CAT2_OPTION_BYTES_BASE, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, .option_size = 4, }, { @@ -443,7 +447,9 @@ static const struct stlink_chipid_params devices[] = { // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0x18000, .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000 // 28k (per bank), same source as base + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32L4RX @@ -484,7 +490,9 @@ static const struct stlink_chipid_params devices[] = { // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0xc000, .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000 // 28k (per bank), same source as base + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, }, { // STLINK_CHIPID_STM32_L496X @@ -499,7 +507,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L496X_OPTION_BYTES_BASE, + .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, }, { @@ -537,8 +545,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, // 8K (sec 2.3) .bootrom_base = 0x1fff0000, .bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 8*4, }, { // STM32G071/081 (from RM0444) @@ -551,7 +559,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, + .option_size = 8*4, }, { // STM32G431/441 (from RM0440) diff --git a/src/common.c b/src/common.c index 4525d0222..351c74497 100644 --- a/src/common.c +++ b/src/common.c @@ -2863,7 +2863,7 @@ static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, uint32 uint32_t data; write_uint32((unsigned char*) &data, *(uint32_t*) (base)); WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32_L0_CAT2_OPTION_BYTES_BASE, data); + stlink_write_debug32(sl, STM32_L0_CATx_OPTION_BYTES_BASE, data); /* Reload options */ stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); From 72cfd5ee20658cbd9a4cefd01e0099b461018822 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 15:32:47 +0200 Subject: [PATCH 07/10] option: refactor option flash code. unify option bytes read/write, interface, use chipid db to store size and base to provide some write sanity check and generic option read code. --- include/stlink.h | 6 +- src/chipid.c | 8 +- src/common.c | 195 +++++++++++++++++++++++++--------------------- src/tools/flash.c | 12 +-- 4 files changed, 119 insertions(+), 102 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index f22abbb42..db737acb0 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -239,9 +239,11 @@ typedef struct flash_loader { int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); - int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte); + int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); + int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); + + int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); #include "stlink/sg.h" #include "stlink/usb.h" diff --git a/src/chipid.c b/src/chipid.c index bc3d37567..60d0787e9 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -546,7 +546,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3) .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 8*4, + .option_size = 4, }, { // STM32G071/081 (from RM0444) @@ -559,7 +559,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 8*4, + .option_size = 4, }, { // STM32G431/441 (from RM0440) @@ -575,7 +575,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28K (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4*4, + .option_size = 4, }, { @@ -593,7 +593,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28K (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4*4, + .option_size = 4, }, { // STM32WB55 (from RM0434) diff --git a/src/common.c b/src/common.c index 351c74497..66d21b2b4 100644 --- a/src/common.c +++ b/src/common.c @@ -2738,26 +2738,12 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; - if (len != 4) { - ELOG("Wrong length for writing option bytes, must be 4 is %d\n", len); - return -1; - } - - // Make sure we've loaded the context with the chip details - stlink_core_id(sl); - - /* Check if chip is supported and for correct address */ - if (sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 && - sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2 && - sl->chip_id != STLINK_CHIPID_STM32_G4_CAT2 && - sl->chip_id != STLINK_CHIPID_STM32_G4_CAT3) { - ELOG("Option bytes writing is currently only supported for the STM32G0/G4\n"); - return -1; - } + (void) addr; + (void) len; if (unlock_flash_if(sl)) { ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); @@ -2783,7 +2769,7 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, uint32_t le /* Write options bytes */ uint32_t data; write_uint32((unsigned char*) &data, *(uint32_t*) (base)); - WLOG("Writing option bytes 0x%04x\n", data); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); //stlink_write_debug32(sl, addr, data); stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); @@ -2823,14 +2809,12 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, uint32_t le * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; + (void) addr; + (void) len; - if (len != 4) { - ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); - return -1; - } stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); if (val & STM32L0_FLASH_PELOCK_BIT) { WLOG("Unlocking flash\n"); @@ -2885,10 +2869,6 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ uint32_t val; uint32_t data; - if (len != 4 && len != 8) { - ELOG("Wrong length for writting option bytes, must be 4 or 8 is %d\n", len); - return -1; - } stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); if (val & STM32L1_FLASH_PELOCK_BIT) { WLOG("Unlocking flash\n"); @@ -2966,14 +2946,12 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; - if (len != 4) { - ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); - return -1; - } + (void) addr; + (void) len; /* Unlock flash if necessary */ stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); @@ -3047,8 +3025,18 @@ static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, uint32_t * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f2(stlink_t *sl, uint32_t option_byte) { +static int stlink_write_option_bytes_f2(stlink_t *sl, uint8_t *base, stm32_addr_t addr, size_t len) { uint32_t val; + uint32_t option_byte; + + (void) addr; /* todo: add sanitary check */ + + if(len != 4) { + ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); + return -1; + } + + option_byte = *(uint32_t*) (base); stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); if (val & FLASH_F2_OPT_LOCK_BIT) { @@ -3097,8 +3085,18 @@ static int stlink_write_option_bytes_f2(stlink_t *sl, uint32_t option_byte) { * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint32_t option_byte) { +static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; + uint32_t option_byte; + + (void) addr; /* todo: add sanitary check */ + + if(len != 4) { + ELOG("Wrong length for writing option bytes, must be 4 is %d\n", len); + return -1; + } + + option_byte = *(uint32_t*) (base); stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); if (val & FLASH_F4_OPT_LOCK_BIT) { @@ -3219,25 +3217,54 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { return 0; } +/** +* Read first option bytes +* @param sl +* @param option_byte option value +* @return 0 on success, -ve on failure. +*/ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) +{ + return stlink_read_debug32(sl, sl->option_base, option_byte); +} /** * Read option bytes * @param sl - * @param option_byte value to read + * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte) { - int err = -1; - if (sl->chip_id == STLINK_CHIPID_STM32_F2){ - err = stlink_read_option_bytes_f2(sl, option_byte); - }else if(sl->chip_id == STLINK_CHIPID_STM32_F446){ - err = stlink_read_option_bytes_f4(sl, option_byte); - }else if(sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { - err = stlink_read_option_bytes_Gx(sl, option_byte); - }else{ - ELOG("This format is only available for STM32F2, STM32F4, STM32G0 and STM32G4\n"); +int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) +{ + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); } - return err; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) +{ + WLOG("About to write option byte %#10x to target.\n", option_byte); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); } /** @@ -3247,34 +3274,42 @@ int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) +{ + if (sl->option_base == 0) { + ELOG("Option bytes writing is currently not supported for connected chip\n"); + return -1; + } - // Make sure we've loaded the context with the chip details - stlink_core_id(sl); + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return -1; + } - WLOG("Option bytes write chip_id 0x%08x addr 0x%08x\n",sl->chip_id,addr); + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); + return -1; + } - /* Check if chip is supported and for correct address */ - if (((sl->chip_id == STLINK_CHIPID_STM32_G0_CAT1) || - (sl->chip_id == STLINK_CHIPID_STM32_G0_CAT2)) && (addr == STM32_G0_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_gx(sl, base, len); - } - else if (((sl->chip_id == STLINK_CHIPID_STM32_G4_CAT2) || - (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3)) && (addr == STM32_G4_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_gx(sl, base, len); - } - else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_l0_cat2(sl, base, len); - } - else if ((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_l496x(sl, base, len); - } - else if (((sl->chip_id == STLINK_CHIPID_STM32_L152_RE) || (sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH) ) && - ((addr == STM32_L1_OPTION_BYTES_BASE) || (addr == STM32_L1_OPTION_BYTES_BASE+4))) { + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_write_option_bytes_f2(sl, base, addr, len); + case STLINK_CHIPID_STM32_F446: + return stlink_write_option_bytes_f4(sl, base, addr, len); + case STLINK_CHIPID_STM32_L0_CAT2: + return stlink_write_option_bytes_l0_cat2(sl, base, addr, len); + case STLINK_CHIPID_STM32_L496X: + return stlink_write_option_bytes_l496x(sl, base, addr, len); + case STLINK_CHIPID_STM32_L152_RE: + case STLINK_CHIPID_STM32_L1_HIGH: return stlink_write_option_bytes_l1(sl, base, addr, len); - } - else { - ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0, STM32L496x/L4A6x, STM32L1 and STM32L0\n"); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_write_option_bytes_gx(sl, base, addr, len); + default: + ELOG("Option bytes writing is currently not implemented for connected chip\n"); return -1; } @@ -3306,23 +3341,3 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr unmap_file(&mf); return err; } - -/** - * Write the given 32-bit value with option byte - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_option_bytes_32bit(stlink_t *sl, uint32_t val) { - - if (sl->chip_id == STLINK_CHIPID_STM32_F2){ - return stlink_write_option_bytes_f2(sl, val); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F446){ - return stlink_write_option_bytes_f4(sl, val); - } - else - { - ELOG("Option bytes writing is currently only supported for the STM32F2, STM32F4, STM32G0 and STM32L0\n"); - return -1; - } -} diff --git a/src/tools/flash.c b/src/tools/flash.c index 06256823c..20fbacd9a 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -160,9 +160,8 @@ int main(int ac, char** av) goto on_error; } } - else if (o.addr == STM32_G0_OPTION_BYTES_BASE || - o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE || - o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE + 4){ + else if ((o.addr >= sl->option_base) && + (o.addr < sl->option_base + sl->option_size)) { err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { @@ -171,10 +170,11 @@ int main(int ac, char** av) } } else if (o.area == FLASH_OPTION_BYTES){ - err = stlink_fwrite_option_bytes_32bit(sl, o.val); + // XXX some sanity check should be done here to check o.val parsing. + err = stlink_write_option_bytes32(sl, o.val); if (err == -1) { - printf("stlink_fwrite_option_bytes() == -1\n"); + printf("stlink_write_option_bytes32() == -1\n"); goto on_error; } } @@ -209,7 +209,7 @@ int main(int ac, char** av) { if(o.area == FLASH_OPTION_BYTES){ uint32_t option_byte; - err = stlink_read_option_bytes(sl, &option_byte); + err = stlink_read_option_bytes32(sl, &option_byte); if (err == -1) { printf("could not read option bytes (%d)\n", err); goto on_error; From e146a28a67cdfea1d4e9b5bf76471e05fe692494 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 19:01:05 +0200 Subject: [PATCH 08/10] st-flash: add sanity check to option flash. current opt parse code can make bad cmdline parameter attempt to flash bad flash option. ie: calling st-flash write --area=option a_file.bin will make parser attempt to translate "a_file.bon" to an uint32 and will return 0.., --- src/tools/flash.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index 20fbacd9a..e91001659 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -170,7 +170,11 @@ int main(int ac, char** av) } } else if (o.area == FLASH_OPTION_BYTES){ - // XXX some sanity check should be done here to check o.val parsing. + if (o.val == 0) { + printf("attempting to set option byte to 0, abort.\n"); + goto on_error; + } + err = stlink_write_option_bytes32(sl, o.val); if (err == -1) { From 3aaec273da217faf54601c02480ce990baa09894 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 16 Apr 2020 15:12:40 +0200 Subject: [PATCH 09/10] common.c: fix define - use Gx Base for Gx defines avoid some potential issues later. --- src/common.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/common.c b/src/common.c index 66d21b2b4..0ccdeccdb 100644 --- a/src/common.c +++ b/src/common.c @@ -79,13 +79,13 @@ // Flash registers common to STM32G0 and STM32G4 series. #define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32G0_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32G0_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32G0_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32G0_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32G0_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32G0_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32G0_FLASH_REGS_ADDR + 0x20) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) // G0 (RM0444 Table 1, sec 3.7) // Mostly the same as G4 chips, but the notation From 19facc978911790e4f363e4466e7a9d22e7c519a Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 17 Apr 2020 11:41:37 +0200 Subject: [PATCH 10/10] indent --- src/common.c | 132 +++++++++++++++++++++++++-------------------------- 1 file changed, 65 insertions(+), 67 deletions(-) diff --git a/src/common.c b/src/common.c index 0ccdeccdb..9694a8b8e 100644 --- a/src/common.c +++ b/src/common.c @@ -696,7 +696,7 @@ static int check_flash_error(stlink_t *sl) { uint32_t res = 0; if ((sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4)) { + (sl->flash_type == STLINK_FLASH_TYPE_G4)) { res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; } @@ -1172,13 +1172,13 @@ int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct s bool stlink_is_core_halted(stlink_t *sl) { - bool ret = false; + bool ret = false; - stlink_status(sl); - if (sl->q_buf[0] == STLINK_CORE_HALTED) - ret = true; + stlink_status(sl); + if (sl->q_buf[0] == STLINK_CORE_HALTED) + ret = true; - return ret; + return ret; } int stlink_step(stlink_t *sl) { @@ -1204,8 +1204,6 @@ int stlink_current_mode(stlink_t *sl) { } - - // End of delegates.... Common code below here... // Endianness @@ -2915,19 +2913,20 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ if (len==8) { - /* Clear errors */ - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_SR_OFF, 0x00003F00); + /* Clear errors */ + stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_SR_OFF, 0x00003F00); stlink_read_debug32(sl, addr+4, &val); WLOG("2nd option bytes 0x%08x is 0x%08x\n",addr,val); /* Write options bytes */ - write_uint32((unsigned char*) &data, *(uint32_t*) (base+4)); - if ( data != val ) { - WLOG("Writing 2nd option bytes 0x%04x\n", data); - stlink_write_debug32(sl, addr+4, data); - stlink_read_debug32(sl, addr+4, &val); - WLOG("2nd option bytes is 0x%08x\n",val); + write_uint32((unsigned char*) &data, *(uint32_t*) (base+4)); + + if ( data != val ) { + WLOG("Writing 2nd option bytes 0x%04x\n", data); + stlink_write_debug32(sl, addr+4, data); + stlink_read_debug32(sl, addr+4, &val); + WLOG("2nd option bytes is 0x%08x\n",val); } } @@ -3120,7 +3119,6 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ stlink_write_debug32(sl, FLASH_F4_OPT_CR, (option_byte & 0x0FFFFFFC)|0x00000002); - stlink_read_debug32(sl, FLASH_F4_SR, &val); WLOG("wait BSY flag to be 0\n"); @@ -3210,7 +3208,7 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { } stlink_read_debug32(sl, FLASH_F4_OPT_CR, option_byte); - WLOG("option bytes CR = %x\n",option_byte); + WLOG("option bytes CR = %x\n", option_byte); WLOG("Option flash re-lock\n"); stlink_write_debug32(sl, FLASH_F4_OPT_CR, val | 0x00000001); @@ -3236,23 +3234,23 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) */ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); + } } /** @@ -3276,43 +3274,43 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) */ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { - if (sl->option_base == 0) { - ELOG("Option bytes writing is currently not supported for connected chip\n"); - return -1; - } - - if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { - ELOG("Option bytes start address out of Option bytes range\n"); - return -1; - } + if (sl->option_base == 0) { + ELOG("Option bytes writing is currently not supported for connected chip\n"); + return -1; + } - if (addr + len > sl->option_base + sl->option_size) { - ELOG("Option bytes data too long\n"); - return -1; - } + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return -1; + } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_write_option_bytes_f2(sl, base, addr, len); - case STLINK_CHIPID_STM32_F446: - return stlink_write_option_bytes_f4(sl, base, addr, len); - case STLINK_CHIPID_STM32_L0_CAT2: - return stlink_write_option_bytes_l0_cat2(sl, base, addr, len); - case STLINK_CHIPID_STM32_L496X: - return stlink_write_option_bytes_l496x(sl, base, addr, len); - case STLINK_CHIPID_STM32_L152_RE: - case STLINK_CHIPID_STM32_L1_HIGH: - return stlink_write_option_bytes_l1(sl, base, addr, len); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_write_option_bytes_gx(sl, base, addr, len); - default: - ELOG("Option bytes writing is currently not implemented for connected chip\n"); + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); return -1; } + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_write_option_bytes_f2(sl, base, addr, len); + case STLINK_CHIPID_STM32_F446: + return stlink_write_option_bytes_f4(sl, base, addr, len); + case STLINK_CHIPID_STM32_L0_CAT2: + return stlink_write_option_bytes_l0_cat2(sl, base, addr, len); + case STLINK_CHIPID_STM32_L496X: + return stlink_write_option_bytes_l496x(sl, base, addr, len); + case STLINK_CHIPID_STM32_L152_RE: + case STLINK_CHIPID_STM32_L1_HIGH: + return stlink_write_option_bytes_l1(sl, base, addr, len); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_write_option_bytes_gx(sl, base, addr, len); + default: + ELOG("Option bytes writing is currently not implemented for connected chip\n"); + return -1; + } + } /**