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Add simple read/write support for STM32WB55 chips. #786

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Mar 31, 2019
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1 change: 1 addition & 0 deletions include/stlink.h
Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,7 @@ extern "C" {
STLINK_FLASH_TYPE_L4,
STLINK_FLASH_TYPE_F1_XL,
STLINK_FLASH_TYPE_G0,
STLINK_FLASH_TYPE_WB
};

struct stlink_reg {
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3 changes: 2 additions & 1 deletion include/stlink/chipid.h
Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,8 @@ enum stlink_stm32_chipids {
STLINK_CHIPID_STM32_F410 = 0x458,
STLINK_CHIPID_STM32_F413 = 0x463,
STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board
STLINK_CHIPID_STM32_G0X1 = 0x460
STLINK_CHIPID_STM32_G0X1 = 0x460,
STLINK_CHIPID_STM32_WB55 = 0x495
};

/**
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11 changes: 11 additions & 0 deletions src/chipid.c
Original file line number Diff line number Diff line change
Expand Up @@ -518,6 +518,17 @@ static const struct stlink_chipid_params devices[] = {
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7800 // 30K (table 2)
},
{
// STM32WB55 (from RM0434)
.chip_id = STLINK_CHIPID_STM32_WB55,
.description = "WB55 device",
.flash_type = STLINK_FLASH_TYPE_WB,
.flash_size_reg = 0x1FFF75E0,
.flash_pagesize = 0x1000, // 4K
.sram_size = 0x40000,
.bootrom_base = 0x1fff0000, // See the memory map
.bootrom_size = 0x7000
},
{
// unknown
.chip_id = STLINK_CHIPID_UNKNOWN,
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