diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h
index 004fa2e80..d28527aba 100644
--- a/include/stlink/chipid.h
+++ b/include/stlink/chipid.h
@@ -40,10 +40,12 @@ enum stlink_stm32_chipids {
 	* 0x435 covers STM32L43xxx and STM32L44xxx devices
 	* 0x461 covers STM32L496xx and STM32L4A6xx devices
 	* 0x462 covers STM32L45xxx and STM32L46xxx devices
+	* 0x464 covers STM32L41xxx and STM32L42xxx devices
 	*/
 	STLINK_CHIPID_STM32_L43X             = 0x435,
 	STLINK_CHIPID_STM32_L496X            = 0x461,
 	STLINK_CHIPID_STM32_L46X             = 0x462,
+	STLINK_CHIPID_STM32_L41X             = 0x464,
 	/*
 	* 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
 	* and some that are called "High".  0x427 is assigned to the other "Medium-
diff --git a/src/common.c b/src/common.c
index 40a689c7e..fa2a4607a 100644
--- a/src/common.c
+++ b/src/common.c
@@ -1436,13 +1436,19 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
     uint32_t flashopt;
     stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt);
     flashaddr -= STM32_FLASH_BASE;
-    if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
-        uint32_t banksize = (uint32_t) sl->flash_size / 2;
-        if (flashaddr >= banksize) {
-            flashaddr -= banksize;
-            bker = 0x100;
+    if (sl->chip_id == STLINK_CHIPID_STM32_L4 ||
+        sl->chip_id == STLINK_CHIPID_STM32_L496X ||
+        sl->chip_id == STLINK_CHIPID_STM32_L4RX) {
+        // This chip use dual banked flash
+        if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
+            uint32_t banksize = (uint32_t) sl->flash_size / 2;
+            if (flashaddr >= banksize) {
+                flashaddr -= banksize;
+                bker = 0x100;
+            }
         }
     }
+
     // For 1MB chips without the dual-bank option set, the page address will
     // overflow into the BKER bit, which gives us the correct bank:page value.
     return bker | flashaddr/sl->flash_pgsz;