diff --git a/src/common.c b/src/common.c index a064254d3..5f2746e3d 100644 --- a/src/common.c +++ b/src/common.c @@ -1221,43 +1221,23 @@ int stlink_core_id(stlink_t *sl) { int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; - if (sl->core_id == STM32H7_CORE_ID) { - /* STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - * However, the STM32H7 is not the only chip with a JTAG - * IDCODE of 0x6ba02477, so we cannot rely solely on this info - * to select the address to read the chip id */ - - uint32_t cpu_id; - *chip_id = 0; - ret = -1; - - // Read the CPU ID as well to determine if this really is an H7 part - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) - cpu_id = 0; - - // If it is, read the chipid from the new address - if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } - - if (*chip_id == 0) { - // default chipid address - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } + uint32_t cpu_id; + *chip_id = 0; + ret = -1; - } else { - // default chipid address - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } + // Read the CPU ID to determine where to read the core id from + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) + cpu_id = 0; - if (ret == -1) { - return(ret); + // If the chip is an H7, read the chipid from the new address + if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); } if (*chip_id == 0) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + // default chipid address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); } if (*chip_id == 0) {