diff --git a/.github/workflows/arch.yml b/.github/workflows/arch.yml index 35cffb3dfca53..cf858e1b6bfd0 100644 --- a/.github/workflows/arch.yml +++ b/.github/workflows/arch.yml @@ -169,7 +169,7 @@ jobs: # If PR was Created or Modified: Exclude some boards pr=${{github.event.pull_request.number}} if [[ "$pr" != "" ]]; then - echo "Excluding arm-0[248], arm-1[02-9], risc-v-04..06, sim-02, xtensa-02" + echo "Excluding arm-0[248], arm-1[02-9], risc-v-04..06, sim-03, xtensa-02" boards=$( echo '${{ inputs.boards }}' | jq --compact-output \ @@ -177,7 +177,7 @@ jobs: select( test("arm-0[248]") == false and test("arm-1[02-9]") == false and test("risc-v-0[4-9]") == false and - test("sim-0[2-9]") == false and + test("sim-0[3-9]") == false and test("xtensa-0[2-9]") == false ) )' diff --git a/Documentation/applications/examples/spislv_test/index.rst b/Documentation/applications/examples/spislv_test/index.rst new file mode 100644 index 0000000000000..8474d62989ed2 --- /dev/null +++ b/Documentation/applications/examples/spislv_test/index.rst @@ -0,0 +1,42 @@ +``spislv`` SPI slave example +============================ + +A simple example for the device functioning as an SPI slave. +This example can be used to validate communication with another device +operating as an SPI master. If the spitool is used on the other device, +and the following command is sent: + +``spi exch -x 4 deadbeef`` + +The expected response in device running spislv_test app is: + +.. code-block:: bash + + Slave: 4 Bytes reads + Value in hex form from /dev/spislv2: de ad be ef + Slave: Writing value back to /dev/spislv2 + + +This test requires the device to be configured in SPI slave mode.(your +specific spi slave hardware settings might require additional settings). + +Specific configuration options for this example include: +Configs inside <> are the options that you need to find, It are arch de- +pendent and might be different for your board. + +- ```` – Enables SPI peripheral support + in System Type->Peripheral Support. + +- ```` – Configures SPI peripheral in System Type->SPI + configuration. Set here the right pins to be used for SPI communication. + +- ``CONFIG_SPI`` – In the SPI driver support, enable SPI Slave support. + +- ``CONFIG_SPI_SLAVE`` – Enables SPI Slave support. + +- ``SPI_SLAVE_DRIVER`` – Enables SPI Slave character driver. + +- ```` – Return to this option and enable SPI Slave mode. + + + diff --git a/Documentation/platforms/arm/mps/boards/mps2-an500/index.rst b/Documentation/platforms/arm/mps/boards/mps2-an500/index.rst index 09ef63250e097..81caaf4714573 100644 --- a/Documentation/platforms/arm/mps/boards/mps2-an500/index.rst +++ b/Documentation/platforms/arm/mps/boards/mps2-an500/index.rst @@ -1,33 +1,24 @@ -================= +================ MPS2 AN500 Board -================= +================ This board configuration will use QEMU to emulate generic ARM v7-M series hardware platform and provides support for these devices: - - ARM Generic Timer - - CMSDK UART controller - -Contents -======== - - Getting Started - - Status - - Platform Features - - Debugging with QEMU - - FPU Support and Performance - - SMP Support - - References +- ARM Generic Timer +- CMSDK UART controller Getting Started =============== -1. Configuring and running +1. Configuring NuttX and compile:: - Configuring NuttX and compile: $ ./tools/configure.sh -l mps2-an500:nsh $ make - Running with qemu - $ qemu-system-arm -M mps2-an500 -nographic -kernel nuttx.bin + +Running with qemu:: + + $ qemu-system-arm -M mps2-an500 -nographic -kernel nuttx.bin Debugging with QEMU =================== @@ -35,14 +26,14 @@ Debugging with QEMU The nuttx ELF image can be debugged with QEMU. 1. To debug the nuttx (ELF) with symbols, make sure the following change have - applied to defconfig. + applied to defconfig:: -+CONFIG_DEBUG_SYMBOLS=y + +CONFIG_DEBUG_SYMBOLS=y -2. Run QEMU(at shell terminal 1) +2. Run QEMU(at shell terminal 1):: $ qemu-system-arm -M mps2-an500 -nographic -kernel nuttx.bin -S -s -3. Run gdb with TUI, connect to QEMU, load nuttx and continue (at shell terminal 2) +3. Run gdb with TUI, connect to QEMU, load nuttx and continue (at shell terminal 2):: $ arm-none-eabi-gdb -tui --eval-command='target remote localhost:1234' nuttx diff --git a/Documentation/platforms/arm/mps/boards/mps2-an512/index.rst b/Documentation/platforms/arm/mps/boards/mps2-an512/index.rst new file mode 100644 index 0000000000000..37bb9bcfc0b15 --- /dev/null +++ b/Documentation/platforms/arm/mps/boards/mps2-an512/index.rst @@ -0,0 +1,41 @@ +================ +MPS2 AN521 Board +================ + +This board configuration will use QEMU to emulate generic ARM v8-M series +hardware platform and provides support for these devices: + +- ARM Generic Timer +- CMSDK UART controller + +Getting Started +=============== + +1. Configuring NuttX and compile (Single Core):: + + $ ./tools/configure.sh -l mps2-an521:nsh + $ make + +Running with qemu:: + + $ qemu-system-arm -M mps2-an521 -nographic -chardev stdio,id=con,mux=on \ + -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx + +Debugging with QEMU +=================== + +The nuttx ELF image can be debugged with QEMU. + +1. To debug the nuttx (ELF) with symbols, make sure the following change have + applied to defconfig:: + + CONFIG_DEBUG_SYMBOLS=y + +2. Run QEMU (at shell terminal 1):: + + qemu-system-arm -M mps2-an521 -nographic -chardev stdio,id=con,mux=on \ + -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx -S -s + +3. Run gdb with TUI, connect to QEMU, load nuttx and continue (at shell terminal 2):: + + $ arm-none-eabi-gdb -tui --eval-command='target remote localhost:1234' nuttx diff --git a/Documentation/platforms/arm/mps/boards/mps3-an547/index.rst b/Documentation/platforms/arm/mps/boards/mps3-an547/index.rst index 147355527a620..0fea4818b39cd 100644 --- a/Documentation/platforms/arm/mps/boards/mps3-an547/index.rst +++ b/Documentation/platforms/arm/mps/boards/mps3-an547/index.rst @@ -1,8 +1,9 @@ -================= +================ MPS3 AN547 Board -================= +================ -The MPS3 AN547 board configuration uses QEMU to emulate a generic ARM v8-M series hardware platform and provides support for the following devices: +The MPS3 AN547 board configuration uses QEMU to emulate a generic ARM v8-M +series hardware platform and provides support for the following devices: - ARM Generic Timer - CMSDK UART controller @@ -10,76 +11,59 @@ The MPS3 AN547 board configuration uses QEMU to emulate a generic ARM v8-M serie Getting Started =============== -Configuring and Running ------------------------ - -### Single Core - -1. **Configuring NuttX and Compiling:** - - ```bash - $ ./tools/configure.sh -l mps3-an547:nsh - $ make - ``` - -2. **Running with QEMU:** - - ```bash - $ qemu-system-arm -M mps3-an547 -nographic -kernel nuttx.bin - ``` - -3. **Pic ostest:** - - ```bash - $ ./tools/configure.sh mps3-an547:picostest - $ make -j20 - $ genromfs -f romfs.img -d ../apps/bin/ - $ qemu-system-arm -M mps3-an547 -m 2G -nographic \ - -kernel nuttx.bin -gdb tcp::1127 \ - -device loader,file=romfs.img,addr=0x60000000 - $ nsh> /pic/hello - $ nsh> /pic/ostest - ``` - -4. **Pic bootloader boot to ap, and run ostest:** - - ```bash - $ ./tools/configure.sh mps3-an547:ap - $ make -j20 - $ mkdir -p pic - $ arm-none-eabi-strip --remove-section=.rel.text --remove-section=.comment --strip-unneeded nuttx -o pic/boot - $ genromfs -a -f 128 ../romfs.img -d pic - $ make distclean -j20 - $ ./tools/configure.sh mps3-an547:bl - $ make -j20 - $ qemu-system-arm -M mps3-an547 -m 2G -nographic \ - -kernel nuttx.bin -gdb tcp::1127 \ - -device loader,file=../romfs.img,addr=0x60000000 - $ bl> boot /pic/boot - $ ap> ostest - ``` +Configuring and Running (Single Core) +------------------------------------- + +1. Configuring NuttX and Compiling:: + + ./tools/configure.sh -l mps3-an547:nsh + make + +2. Running with QEMU:: + + $ qemu-system-arm -M mps3-an547 -nographic -kernel nuttx.bin + +3. Pic ostest:: + + ./tools/configure.sh mps3-an547:picostest + make -j20 + genromfs -f romfs.img -d ../apps/bin/ + qemu-system-arm -M mps3-an547 -m 2G -nographic \ + -kernel nuttx.bin -gdb tcp::1127 \ + -device loader,file=romfs.img,addr=0x60000000 + nsh> /pic/hello + nsh> /pic/ostest + +4. Pic bootloader boot to ap, and run ostest:: + + ./tools/configure.sh mps3-an547:ap + make -j20 + mkdir -p pic + arm-none-eabi-strip --remove-section=.rel.text --remove-section=.comment --strip-unneeded nuttx -o pic/boot + genromfs -a -f 128 ../romfs.img -d pic + make distclean -j20 + ./tools/configure.sh mps3-an547:bl + make -j20 + qemu-system-arm -M mps3-an547 -m 2G -nographic \ + -kernel nuttx.bin -gdb tcp::1127 \ + -device loader,file=../romfs.img,addr=0x60000000 + bl> boot /pic/boot + ap> ostest Debugging with QEMU =================== The NuttX ELF image can be debugged using QEMU. -1. **Enable Debug Symbols:** - - Ensure the following change is applied to `defconfig`: +1. Enable Debug Symbols. + Ensure the following change is applied to ``defconfig``:: - ```bash - +CONFIG_DEBUG_SYMBOLS=y - ``` + CONFIG_DEBUG_SYMBOLS=y -2. **Run QEMU:** +2. Run QEMU:: - ```bash - $ qemu-system-arm -M mps3-an547 -nographic -kernel nuttx.bin -S -s - ``` + qemu-system-arm -M mps3-an547 -nographic -kernel nuttx.bin -S -s -3. **Run GDB with TUI:** +3. Run GDB with TUI:: - ```bash - $ arm-none-eabi-gdb -tui --eval-command='target remote localhost:1234' nuttx - ``` + arm-none-eabi-gdb -tui --eval-command='target remote localhost:1234' nuttx diff --git a/Documentation/platforms/arm/stm32f4/boards/stm32f401rc-rs485/index.rst b/Documentation/platforms/arm/stm32f4/boards/stm32f401rc-rs485/index.rst index 95c10878124db..196af0e3a305a 100644 --- a/Documentation/platforms/arm/stm32f4/boards/stm32f401rc-rs485/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/stm32f401rc-rs485/index.rst @@ -748,6 +748,27 @@ NSH commands:: WRITING: 0000: 1b5b471b5b30304c1b5b4548656c6c6f 204e75747458 .[G.[00L.[EHello NuttX Test complete - nsh> + nsh> + +ws2812 +------ + +This configuration sets up the NuttShell (NSH) interface over USB Serial (refer to the usbserial +configuration for details). It also enables the driver for an addressable LED WS2812 and the SPI1. +The MOSI pin from SPI must be connected to DIN on WS2812 module and the number of LEDs can be +configured using CONFIG_WS2812_LED_COUNT. + + +======= ==== + WS2812 PINS +======= ==== +DIN PA7 +======= ==== + +NSH commands:: + + NuttShell (NSH) NuttX-12.7.0-RC0 + nsh> ws2812 + diff --git a/Documentation/platforms/risc-v/hpm6000/boards/hpm6360evk/index.rst b/Documentation/platforms/risc-v/hpm6000/boards/hpm6360evk/index.rst new file mode 100644 index 0000000000000..647376c75feee --- /dev/null +++ b/Documentation/platforms/risc-v/hpm6000/boards/hpm6360evk/index.rst @@ -0,0 +1,47 @@ +========== +hpm6360evk +========== + +1. Download and install toolchain:: + + curl https://github.com/hpmicro/riscv-gnu-toolchain/releases/tag/2022.05.15 + +2. Download and install openocd. + + Download hpmicro sdk_env, openocd in the path: sdk_env/tools/openocd + +3. Configure and build NuttX:: + + mkdir ./nuttxspace + cd ./nuttxspace + git clone https://github.com/apache/nuttx.git nuttx + git clone https://github.com/apache/nuttx-apps.git apps + cd nuttx + make distclean + ./tools/configure.sh hpm6750evk2:nsh + make menuconfig + make V=1 + +Note: make menuconfig to config toolchain + +To switch GNU riscv64 toolchain to GNU riscv32 toolchain, the following option must be selected:: + + System Type ---> + Toolchain Selection ---> + [ ] Generic GNU RV64 toolchain + [x] Generic GNU RV32 toolchain + +Make sure HPMicro GNU riscv32 toolchain have been installed and be found in PATH. + +4. Debug the nuttx with openocd and run:: + + picocom -b 115200 /dev/ttyACM0 + + When using fireDAP, command as follows. Those cfg files in the path: ``sdk_env/hpm_sdk/boards/openocd``:: + + $ openocd -f probes/cmsis_dap.cfg -f soc/hpm6750-single-core.cfg -f boards/hpm6750evk2.cfg + + $ riscv32-unknown-elf-gdb ./nuttx + (gdb) target extended-remote [ip_addr]:3333 + (gdb) load + (gdb) c diff --git a/Documentation/platforms/risc-v/hpm6000/index.rst b/Documentation/platforms/risc-v/hpm6000/index.rst new file mode 100644 index 0000000000000..82740ddb3de07 --- /dev/null +++ b/Documentation/platforms/risc-v/hpm6000/index.rst @@ -0,0 +1,12 @@ +=============== +Hpmicro HPM6000 +=============== + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* diff --git a/LICENSE b/LICENSE index 9d9c89e9efd77..c2413baa832eb 100644 --- a/LICENSE +++ b/LICENSE @@ -8667,22 +8667,22 @@ drivers/i3c/internals.h SPDX-License-Identifier: Apache-2.0 -libs/libc/string/lib_memccpy.c -libs/libc/string/lib_memchr.c -libs/libc/string/lib_memcmp.c -libs/libc/string/lib_memcpy.c -libs/libc/string/lib_memrchr.c -libs/libc/string/lib_stpcpy.c -libs/libc/string/lib_stpncpy.c -libs/libc/string/lib_strcat.c -libs/libc/string/lib_strchr.c -libs/libc/string/lib_strchrnul.c -libs/libc/string/lib_strcmp.c -libs/libc/string/lib_strcpy.c -libs/libc/string/lib_strlen.c -libs/libc/string/lib_strncmp.c -libs/libc/string/lib_strncpy.c -libs/libc/string/lib_strrchr.c +libs/libc/string/lib_bsdmemccpy.c +libs/libc/string/lib_bsdmemchr.c +libs/libc/string/lib_bsdmemcmp.c +libs/libc/string/lib_bsdmemcpy.c +libs/libc/string/lib_bsdmemrchr.c +libs/libc/string/lib_bsdstpcpy.c +libs/libc/string/lib_bsdstpncpy.c +libs/libc/string/lib_bsdstrcat.c +libs/libc/string/lib_bsdstrchr.c +libs/libc/string/lib_bsdstrchrnul.c +libs/libc/string/lib_bsdstrcmp.c +libs/libc/string/lib_bsdstrcpy.c +libs/libc/string/lib_bsdstrlen.c +libs/libc/string/lib_bsdstrncmp.c +libs/libc/string/lib_bsdstrncpy.c +libs/libc/string/lib_bsdstrrchr.c ====================== Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 64328c0006a60..9a9b3cca203b0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -524,6 +524,20 @@ config ARCH_CHIP_STM32L4 ---help--- STMicro STM32 architectures (ARM Cortex-M4). +config ARCH_CHIP_STM32H5 + bool "STMicro STM32 H5" + select ARCH_CORTEXM33 + select ARCH_HAVE_MPU + select ARM_HAVE_DSP + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TRUSTZONE + select ARM_HAVE_MPU_UNIFIED + select ARMV8M_HAVE_STACKCHECK + config ARCH_CHIP_STM32L5 bool "STMicro STM32 L5" select ARCH_CORTEXM33 @@ -538,7 +552,7 @@ config ARCH_CHIP_STM32L5 select ARM_HAVE_MPU_UNIFIED select ARMV8M_HAVE_STACKCHECK ---help--- - STMicro STM32 L5 architectures (ARM Cortex-M33). + STMicro STM32 H5 architectures (ARM Cortex-M33). config ARCH_CHIP_STM32U5 bool "STMicro STM32 U5" @@ -1123,6 +1137,7 @@ config ARCH_CHIP default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 default "stm32l4" if ARCH_CHIP_STM32L4 + default "stm32h5" if ARCH_CHIP_STM32H5 default "stm32l5" if ARCH_CHIP_STM32L5 default "stm32u5" if ARCH_CHIP_STM32U5 default "stm32wb" if ARCH_CHIP_STM32WB @@ -1593,6 +1608,9 @@ endif if ARCH_CHIP_STM32L4 source "arch/arm/src/stm32l4/Kconfig" endif +if ARCH_CHIP_STM32H5 +source "arch/arm/src/stm32h5/Kconfig" +endif if ARCH_CHIP_STM32L5 source "arch/arm/src/stm32l5/Kconfig" endif diff --git a/arch/arm/include/stm32h5/chip.h b/arch/arm/include/stm32h5/chip.h new file mode 100644 index 0000000000000..abe3b39d71bb4 --- /dev/null +++ b/arch/arm/include/stm32h5/chip.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * arch/arm/include/stm32h5/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32H5_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32H5_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32H5_SRAM2_SIZE (80*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32H5_SRAM3_SIZE (320*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +#else +# error "Unsupported STM32H5 chip" +#endif + +#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +# define STM32H5_NFSMC 1 /* Have FSMC memory controller */ +# define STM32H5_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32H5_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32H5_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32H5_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32H5_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32H5_NLPTIM 6 /* Six low-power timers, LPTIM1-LPTIM6. */ +# define STM32H5_NRNG 1 /* Random number generator (RNG) */ +# define STM32H5_NUART 6 /* UART 4-5, 7-8, 9, 12 */ +# define STM32H5_NUSART 5 /* USART 1-3, 6, 10-11 */ +# define STM32H5_NLPUART 1 /* LPUART 1 */ +# define STM32H5_QSPI 0 /* No QuadSPI1 */ +# define STM32H5_OCTOSPI 1 /* OCTOSPI1*/ +# define STM32H5_NSPI 6 /* SPI1-SPI6 */ +# define STM32H5_NI2C 4 /* I2C1-4 */ +# define STM32H5_NSWPMI 0 /* No SWPMI1 */ +# define STM32H5_NUSBOTGFS 0 /* USB OTG FS */ +# define STM32H5_NUSBFS 1 /* No USB FS */ +# define STM32H5_NCAN 2 /* CAN1 */ +# define STM32H5_NSAI 2 /* SAI1-2 */ +# define STM32H5_NSDMMC 2 /* SDMMC interface */ +# define STM32H5_NDMA 2 /* DMA1-2 */ +# define STM32H5_NPORTS 8 /* 8 GPIO ports, GPIOA-GPIOI */ +# define STM32H5_NADC 2 /* 12-bit ADC1, up to 20 channels */ +# define STM32H5_NDAC 1 /* 12-bit DAC1 */ +# define STM32H5_NCRC 1 /* CRC */ +# define STM32H5_NCOMP 0 /* Comparators */ +# define STM32H5_NOPAMP 0 /* Operational Amplifiers */ +/* TODO - Add new features for H5 later */ +#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +# define STM32H5_NFSMC 1 /* Have FSMC memory controller */ +# define STM32H5_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32H5_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32H5_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32H5_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32H5_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32H5_NLPTIM 6 /* Six low-power timers, LPTIM1-LPTIM6. */ +# define STM32H5_NRNG 1 /* Random number generator (RNG) */ +# define STM32H5_NUART 2 /* UART 4-5 */ +# define STM32H5_NUSART 4 /* USART 1-3, 6*/ +# define STM32H5_NLPUART 1 /* LPUART 1 */ +# define STM32H5_QSPI 0 /* No QuadSPI1 */ +# define STM32H5_OCTOSPI 1 /* OCTOSPI1*/ +# define STM32H5_NSPI 3 /* SPI1-SPI3 */ +# define STM32H5_NI2C 3 /* I2C1-3 */ +# define STM32H5_NSWPMI 0 /* No SWPMI1 */ +# define STM32H5_NUSBOTGFS 0 /* USB OTG FS */ +# define STM32H5_NUSBFS 1 /* No USB FS */ +# define STM32H5_NCAN 2 /* CAN1 */ +# define STM32H5_NSAI 2 /* SAI1-2 */ +# define STM32H5_NSDMMC 1 /* SDMMC interface */ +# define STM32H5_NDMA 2 /* DMA1-2 */ +# define STM32H5_NPORTS 8 /* 8 GPIO ports, GPIOA-GPIOI */ +# define STM32H5_NADC 2 /* 12-bit ADC1, up to 20 channels */ +# define STM32H5_NDAC 1 /* 12-bit DAC1 */ +# define STM32H5_NCRC 1 /* CRC */ +# define STM32H5_NCOMP 0 /* Comparators */ +# define STM32H5_NOPAMP 0 /* Operational Amplifiers */ +/* TODO - Add new features for H5 later */ +#endif + +/* NVIC priority levels *****************************************************/ + +/* 16 Programmable interrupt levels */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */ diff --git a/arch/arm/include/stm32h5/irq.h b/arch/arm/include/stm32h5/irq.h new file mode 100644 index 0000000000000..d92854bf983c9 --- /dev/null +++ b/arch/arm/include/stm32h5/irq.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/include/stm32h5/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32H5_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32H5_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +# include +#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +# include +#else +# error "Unsupported STM32 H5 chip" +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32H5_IRQ_H */ diff --git a/arch/arm/include/stm32h5/stm32h52x_3x_irq.h b/arch/arm/include/stm32h5/stm32h52x_3x_irq.h new file mode 100644 index 0000000000000..aa3d57c5ed773 --- /dev/null +++ b/arch/arm/include/stm32h5/stm32h52x_3x_irq.h @@ -0,0 +1,193 @@ +/**************************************************************************** + * arch/arm/include/stm32h5/stm32h52xxx_3xxx_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32H5_STM32H52XXX_3XXX_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32H5_STM32H52XXX_3XXX_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/stm32h5/stm32h5_irq.h, which is + * included above. + * + * External interrupts (vectors >= 16) + * + * These interrupts vectors was implemented based on RM0481 Table 145 + * (STM32H53xxx and STM32H53xxx vector table) + * + */ + +#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +# define STM32H5_IRQ_WWDG (STM32H5_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +# define STM32H5_IRQ_PVD_AVD (STM32H5_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ +# define STM32H5_IRQ_RTC (STM32H5_IRQ_FIRST + 2) /* 2: RTC global interrupts */ +# define STM32H5_IRQ_RTC_S (STM32H5_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ +# define STM32H5_IRQ_TAMP (STM32H5_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ +# define STM32H5_IRQ_RAMCFG (STM32H5_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ +# define STM32H5_IRQ_FLASH (STM32H5_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ +# define STM32H5_IRQ_FLASH_S (STM32H5_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ +# define STM32H5_IRQ_GTZC (STM32H5_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ +# define STM32H5_IRQ_RCC (STM32H5_IRQ_FIRST + 9) /* 9: RCC global interrupt */ +# define STM32H5_IRQ_RCC_S (STM32H5_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ +# define STM32H5_IRQ_EXTI0 (STM32H5_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ +# define STM32H5_IRQ_EXTI1 (STM32H5_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ +# define STM32H5_IRQ_EXTI2 (STM32H5_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ +# define STM32H5_IRQ_EXTI3 (STM32H5_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ +# define STM32H5_IRQ_EXTI4 (STM32H5_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ +# define STM32H5_IRQ_EXTI5 (STM32H5_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ +# define STM32H5_IRQ_EXTI6 (STM32H5_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ +# define STM32H5_IRQ_EXTI7 (STM32H5_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ +# define STM32H5_IRQ_EXTI8 (STM32H5_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ +# define STM32H5_IRQ_EXTI9 (STM32H5_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ +# define STM32H5_IRQ_EXTI10 (STM32H5_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ +# define STM32H5_IRQ_EXTI11 (STM32H5_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ +# define STM32H5_IRQ_EXTI12 (STM32H5_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ +# define STM32H5_IRQ_EXTI13 (STM32H5_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ +# define STM32H5_IRQ_EXTI14 (STM32H5_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ +# define STM32H5_IRQ_EXTI15 (STM32H5_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ +# define STM32H5_IRQ_GPDMA1_CH0 (STM32H5_IRQ_FIRST + 27) /* 27: GPDMA1_CH0 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH1 (STM32H5_IRQ_FIRST + 28) /* 28: GPDMA1_CH1 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH2 (STM32H5_IRQ_FIRST + 29) /* 29: GPDMA1_CH2 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH3 (STM32H5_IRQ_FIRST + 30) /* 30: GPDMA1_CH3 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH4 (STM32H5_IRQ_FIRST + 31) /* 31: GPDMA1_CH4 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH5 (STM32H5_IRQ_FIRST + 32) /* 32: GPDMA1_CH5 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH6 (STM32H5_IRQ_FIRST + 33) /* 33: GPDMA1_CH6 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH7 (STM32H5_IRQ_FIRST + 34) /* 34: GPDMA1_CH7 global interrupt */ +# define STM32H5_IRQ_IWDG (STM32H5_IRQ_FIRST + 35) /* 35: IWDG global interrupt */ +# define STM32H5_IRQ_SAES (STM32H5_IRQ_FIRST + 36) /* 36: SAES global interrupt */ +# define STM32H5_IRQ_ADC1 (STM32H5_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ +# define STM32H5_IRQ_DAC1 (STM32H5_IRQ_FIRST + 38) /* 38: DAC global interrupt */ +# define STM32H5_IRQ_FDCAN1_IT0 (STM32H5_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ +# define STM32H5_IRQ_FDCAN1_IT1 (STM32H5_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ +# define STM32H5_IRQ_TIM1_BRK (STM32H5_IRQ_FIRST + 41) /* 41: TIM1 break */ +# define STM32H5_IRQ_TIM1_UP (STM32H5_IRQ_FIRST + 42) /* 42: TIM1 update */ +# define STM32H5_IRQ_TIM1_TRG_COM (STM32H5_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +# define STM32H5_IRQ_TIM1_CC (STM32H5_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +# define STM32H5_IRQ_TIM2 (STM32H5_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ +# define STM32H5_IRQ_TIM3 (STM32H5_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ +# define STM32H5_IRQ_TIM4 (STM32H5_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ +# define STM32H5_IRQ_TIM5 (STM32H5_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ +# define STM32H5_IRQ_TIM6 (STM32H5_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ +# define STM32H5_IRQ_TIM7 (STM32H5_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ +# define STM32H5_IRQ_I2C1_EV (STM32H5_IRQ_FIRST + 51) /* 51: I2C1 Event */ +# define STM32H5_IRQ_I2C1_ER (STM32H5_IRQ_FIRST + 52) /* 52: I2C1 Error */ +# define STM32H5_IRQ_I2C2_EV (STM32H5_IRQ_FIRST + 53) /* 53: I2C2 Event */ +# define STM32H5_IRQ_I2C2_ER (STM32H5_IRQ_FIRST + 54) /* 54: I2C2 Error */ +# define STM32H5_IRQ_SPI1 (STM32H5_IRQ_FIRST + 55) /* 55: SPI1 global interrupt */ +# define STM32H5_IRQ_SPI2 (STM32H5_IRQ_FIRST + 56) /* 56: SPI2 global interrupt */ +# define STM32H5_IRQ_SPI3 (STM32H5_IRQ_FIRST + 57) /* 57: SPI3 global interrupt */ +# define STM32H5_IRQ_USART1 (STM32H5_IRQ_FIRST + 58) /* 58: USART1 error interrupt */ +# define STM32H5_IRQ_USART2 (STM32H5_IRQ_FIRST + 59) /* 59: USART2 global interrupt */ +# define STM32H5_IRQ_USART3 (STM32H5_IRQ_FIRST + 60) /* 60: USART3 global interrupt */ +# define STM32H5_IRQ_UART4 (STM32H5_IRQ_FIRST + 61) /* 61: UART4 global interrupt */ +# define STM32H5_IRQ_UART5 (STM32H5_IRQ_FIRST + 62) /* 62: UART5 global interrupt */ +# define STM32H5_IRQ_LPUART1 (STM32H5_IRQ_FIRST + 63) /* 63: LPUART1 global interrupt */ +# define STM32H5_IRQ_LPTIM1 (STM32H5_IRQ_FIRST + 64) /* 64: LPTIM1 global interrupt */ +# define STM32H5_IRQ_TIM8_BRK (STM32H5_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */ +# define STM32H5_IRQ_TIM8_UP (STM32H5_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */ +# define STM32H5_IRQ_TIM8_TRG_COM (STM32H5_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */ +# define STM32H5_IRQ_TIM8_CC (STM32H5_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */ +# define STM32H5_IRQ_ADC2 (STM32H5_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ +# define STM32H5_IRQ_LPTIM2 (STM32H5_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ +# define STM32H5_IRQ_TIM15 (STM32H5_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ + /* 72: Reserved */ + /* 73: Reserved */ +# define STM32H5_IRQ_USB_FS (STM32H5_IRQ_FIRST + 74) /* 74: USB_FS global interrupt */ +# define STM32H5_IRQ_CRS (STM32H5_IRQ_FIRST + 75) /* 75: CRS global interrupt */ +# define STM32H5_IRQ_UCPD1 (STM32H5_IRQ_FIRST + 76) /* 76: UCPD1 global interrupt */ +# define STM32H5_IRQ_FMC (STM32H5_IRQ_FIRST + 77) /* 77: FMC global interrupt */ +# define STM32H5_IRQ_OCTOSPI1 (STM32H5_IRQ_FIRST + 78) /* 78: OCTOSPI1 global interrupt */ +# define STM32H5_IRQ_SDMMC1 (STM32H5_IRQ_FIRST + 79) /* 79: SDMMC1 global interrupt */ +# define STM32H5_IRQ_I2C3_EV (STM32H5_IRQ_FIRST + 80) /* 80: I2C3_EV global interrupt */ +# define STM32H5_IRQ_I2C3_ER (STM32H5_IRQ_FIRST + 81) /* 81: I2C3_ER global interrupt */ +# define STM32H5_IRQ_SPI4 (STM32H5_IRQ_FIRST + 82) /* 82: SPI4 global interrupt */ + /* 83: Reserved */ + /* 84: Reserved */ +# define STM32H5_IRQ_USART6 (STM32H5_IRQ_FIRST + 85) /* 85: USART6 global interrupt */ + /* 86: Reserved */ + /* 87: Reserved */ + /* 88: Reserved */ + /* 89: Reserved */ +# define STM32H5_IRQ_GPDMA2_CH0 (STM32H5_IRQ_FIRST + 90) /* 90: GPDMA2_CH0 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH1 (STM32H5_IRQ_FIRST + 91) /* 91: GPDMA2_CH1 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH2 (STM32H5_IRQ_FIRST + 92) /* 92: GPDMA2_CH2 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH3 (STM32H5_IRQ_FIRST + 93) /* 93: GPDMA2_CH3 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH4 (STM32H5_IRQ_FIRST + 94) /* 94: GPDMA2_CH4 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH5 (STM32H5_IRQ_FIRST + 95) /* 95: GPDMA2_CH5 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH6 (STM32H5_IRQ_FIRST + 96) /* 96: GPDMA2_CH6 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH7 (STM32H5_IRQ_FIRST + 97) /* 97: GPDMA2_CH7 global interrupt */ + /* 98: Reserved */ + /* 99: Reserved */ + /* 100: Reserved */ + /* 101: Reserved */ + /* 102: Reserved */ +# define STM32H5_IRQ_FPU (STM32H5_IRQ_FIRST + 103) /* 103: FPU global interrupt */ +# define STM32H5_IRQ_ICACHE (STM32H5_IRQ_FIRST + 104) /* 104: ICACHE global interrupt */ +# define STM32H5_IRQ_DCACHE (STM32H5_IRQ_FIRST + 105) /* 105: DCACHE global interrupt */ + /* 106: Reserved */ + /* 107: Reserved */ +# define STM32H5_IRQ_DCMI_PSSI (STM32H5_IRQ_FIRST + 108) /* 108: DCMI PSSI global interrupt */ +# define STM32H5_IRQ_FDCAN2_IT0 (STM32H5_IRQ_FIRST + 109) /* 109: FDCAN2_IT0 global interrupt */ +# define STM32H5_IRQ_FDCAN2_IT1 (STM32H5_IRQ_FIRST + 110) /* 110: FDCAN2_IT1 global interrupt */ + /* 111: Reserved */ + /* 112: Reserved */ +# define STM32H5_IRQ_DTS (STM32H5_IRQ_FIRST + 113) /* 113: DTS global interrupt */ +# define STM32H5_IRQ_RNG (STM32H5_IRQ_FIRST + 114) /* 114: RNG global interrupt */ +# define STM32H5_IRQ_OTFDEC1 (STM32H5_IRQ_FIRST + 115) /* 115: OTFDEC1 global interrupt */ +# define STM32H5_IRQ_AES (STM32H5_IRQ_FIRST + 116) /* 116: AES global interrupt */ +# define STM32H5_IRQ_HASH (STM32H5_IRQ_FIRST + 117) /* 117: HASH global interrupt */ +# define STM32H5_IRQ_PKA (STM32H5_IRQ_FIRST + 118) /* 118: PKA global interrupt */ +# define STM32H5_IRQ_CEC (STM32H5_IRQ_FIRST + 119) /* 119: CEC global interrupt */ +# define STM32H5_IRQ_TIM12 (STM32H5_IRQ_FIRST + 120) /* 120: TIM12 global interrupt */ + /* 121: Reserved */ + /* 122: Reserved */ +# define STM32H5_IRQ_I3C1_EV (STM32H5_IRQ_FIRST + 123) /* 123: I3C1_EV global interrupt */ +# define STM32H5_IRQ_I3C1_ER (STM32H5_IRQ_FIRST + 124) /* 124: I3C1_ER global interrupt */ + /* 125: Reserved */ + /* 126: Reserved */ + /* 127: Reserved */ + /* 128: Reserved */ + /* 129: Reserved */ + /* 130: Reserved */ +# define STM32H5_IRQ_I3C2_EV (STM32H5_IRQ_FIRST + 131) /* 123: I3C2_EV global interrupt */ +# define STM32H5_IRQ_I3C2_ER (STM32H5_IRQ_FIRST + 132) /* 124: I3C2_ER global interrupt */ +# define STM32H5_IRQ_NEXTINTS 133 +#else +# error "Unsupported STM32H52X or STM32H53X chip" +#endif + +/* (EXTI interrupts do not use IRQ numbers) */ + +#define NR_IRQS (STM32H5_IRQ_FIRST + STM32H5_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32H5_STM32H52XXX_3XXX_IRQ_H */ diff --git a/arch/arm/include/stm32h5/stm32h56x_7x_irq.h b/arch/arm/include/stm32h5/stm32h56x_7x_irq.h new file mode 100644 index 0000000000000..c00758ac0c8f6 --- /dev/null +++ b/arch/arm/include/stm32h5/stm32h56x_7x_irq.h @@ -0,0 +1,191 @@ +/**************************************************************************** + * arch/arm/include/stm32h5/stm32h56xxx_7xxx_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32H5_STM32H56XXX_7XXX_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32H5_STM32H56XXX_7XXX_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/stm32h5/stm32h5_irq.h, which is + * included above. + * + * External interrupts (vectors >= 16) + * + * These interrupts vectors was implemented based on RM0481 Table 144 + * (STM32H56xxx and STM32H57xxx vector table) and should work for + * + */ + +#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +# define STM32H5_IRQ_WWDG (STM32H5_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +# define STM32H5_IRQ_PVD_AVD (STM32H5_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ +# define STM32H5_IRQ_RTC (STM32H5_IRQ_FIRST + 2) /* 2: RTC global interrupts */ +# define STM32H5_IRQ_RTC_S (STM32H5_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ +# define STM32H5_IRQ_TAMP (STM32H5_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ +# define STM32H5_IRQ_RAMCFG (STM32H5_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ +# define STM32H5_IRQ_FLASH (STM32H5_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ +# define STM32H5_IRQ_FLASH_S (STM32H5_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ +# define STM32H5_IRQ_GTZC (STM32H5_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ +# define STM32H5_IRQ_RCC (STM32H5_IRQ_FIRST + 9) /* 9: RCC global interrupt */ +# define STM32H5_IRQ_RCC_S (STM32H5_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ +# define STM32H5_IRQ_EXTI0 (STM32H5_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ +# define STM32H5_IRQ_EXTI1 (STM32H5_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ +# define STM32H5_IRQ_EXTI2 (STM32H5_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ +# define STM32H5_IRQ_EXTI3 (STM32H5_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ +# define STM32H5_IRQ_EXTI4 (STM32H5_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ +# define STM32H5_IRQ_EXTI5 (STM32H5_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ +# define STM32H5_IRQ_EXTI6 (STM32H5_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ +# define STM32H5_IRQ_EXTI7 (STM32H5_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ +# define STM32H5_IRQ_EXTI8 (STM32H5_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ +# define STM32H5_IRQ_EXTI9 (STM32H5_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ +# define STM32H5_IRQ_EXTI10 (STM32H5_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ +# define STM32H5_IRQ_EXTI11 (STM32H5_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ +# define STM32H5_IRQ_EXTI12 (STM32H5_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ +# define STM32H5_IRQ_EXTI13 (STM32H5_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ +# define STM32H5_IRQ_EXTI14 (STM32H5_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ +# define STM32H5_IRQ_EXTI15 (STM32H5_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ +# define STM32H5_IRQ_GPDMA1_CH0 (STM32H5_IRQ_FIRST + 27) /* 27: GPDMA1_CH0 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH1 (STM32H5_IRQ_FIRST + 28) /* 28: GPDMA1_CH1 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH2 (STM32H5_IRQ_FIRST + 29) /* 29: GPDMA1_CH2 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH3 (STM32H5_IRQ_FIRST + 30) /* 30: GPDMA1_CH3 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH4 (STM32H5_IRQ_FIRST + 31) /* 31: GPDMA1_CH4 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH5 (STM32H5_IRQ_FIRST + 32) /* 32: GPDMA1_CH5 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH6 (STM32H5_IRQ_FIRST + 33) /* 33: GPDMA1_CH6 global interrupt */ +# define STM32H5_IRQ_GPDMA1_CH7 (STM32H5_IRQ_FIRST + 34) /* 34: GPDMA1_CH7 global interrupt */ +# define STM32H5_IRQ_IWDG (STM32H5_IRQ_FIRST + 35) /* 35: IWDG global interrupt */ +# define STM32H5_IRQ_SAES (STM32H5_IRQ_FIRST + 36) /* 36: SAES global interrupt */ +# define STM32H5_IRQ_ADC1 (STM32H5_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ +# define STM32H5_IRQ_DAC1 (STM32H5_IRQ_FIRST + 38) /* 38: DAC global interrupt */ +# define STM32H5_IRQ_FDCAN1_IT0 (STM32H5_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ +# define STM32H5_IRQ_FDCAN1_IT1 (STM32H5_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ +# define STM32H5_IRQ_TIM1_BRK (STM32H5_IRQ_FIRST + 41) /* 41: TIM1 break */ +# define STM32H5_IRQ_TIM1_UP (STM32H5_IRQ_FIRST + 42) /* 42: TIM1 update */ +# define STM32H5_IRQ_TIM1_TRG_COM (STM32H5_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +# define STM32H5_IRQ_TIM1_CC (STM32H5_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +# define STM32H5_IRQ_TIM2 (STM32H5_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ +# define STM32H5_IRQ_TIM3 (STM32H5_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ +# define STM32H5_IRQ_TIM4 (STM32H5_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ +# define STM32H5_IRQ_TIM5 (STM32H5_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ +# define STM32H5_IRQ_TIM6 (STM32H5_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ +# define STM32H5_IRQ_TIM7 (STM32H5_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ +# define STM32H5_IRQ_I2C1_EV (STM32H5_IRQ_FIRST + 51) /* 51: I2C1 Event */ +# define STM32H5_IRQ_I2C1_ER (STM32H5_IRQ_FIRST + 52) /* 52: I2C1 Error */ +# define STM32H5_IRQ_I2C2_EV (STM32H5_IRQ_FIRST + 53) /* 53: I2C2 Event */ +# define STM32H5_IRQ_I2C2_ER (STM32H5_IRQ_FIRST + 54) /* 54: I2C2 Error */ +# define STM32H5_IRQ_SPI1 (STM32H5_IRQ_FIRST + 55) /* 55: SPI1 global interrupt */ +# define STM32H5_IRQ_SPI2 (STM32H5_IRQ_FIRST + 56) /* 56: SPI2 global interrupt */ +# define STM32H5_IRQ_SPI3 (STM32H5_IRQ_FIRST + 57) /* 57: SPI3 global interrupt */ +# define STM32H5_IRQ_USART1 (STM32H5_IRQ_FIRST + 58) /* 58: USART1 error interrupt */ +# define STM32H5_IRQ_USART2 (STM32H5_IRQ_FIRST + 59) /* 59: USART2 global interrupt */ +# define STM32H5_IRQ_USART3 (STM32H5_IRQ_FIRST + 60) /* 60: USART3 global interrupt */ +# define STM32H5_IRQ_UART4 (STM32H5_IRQ_FIRST + 61) /* 61: UART4 global interrupt */ +# define STM32H5_IRQ_UART5 (STM32H5_IRQ_FIRST + 62) /* 62: UART5 global interrupt */ +# define STM32H5_IRQ_LPUART1 (STM32H5_IRQ_FIRST + 63) /* 63: LPUART1 global interrupt */ +# define STM32H5_IRQ_LPTIM1 (STM32H5_IRQ_FIRST + 64) /* 64: LPTIM1 global interrupt */ +# define STM32H5_IRQ_TIM8_BRK (STM32H5_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */ +# define STM32H5_IRQ_TIM8_UP (STM32H5_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */ +# define STM32H5_IRQ_TIM8_TRG_COM (STM32H5_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */ +# define STM32H5_IRQ_TIM8_CC (STM32H5_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */ +# define STM32H5_IRQ_ADC2 (STM32H5_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ +# define STM32H5_IRQ_LPTIM2 (STM32H5_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ +# define STM32H5_IRQ_TIM15 (STM32H5_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ +# define STM32H5_IRQ_TIM16 (STM32H5_IRQ_FIRST + 72) /* 72: TIM16 global interrupt */ +# define STM32H5_IRQ_TIM17 (STM32H5_IRQ_FIRST + 73) /* 73: TIM17 global interrupt */ +# define STM32H5_IRQ_USB_FS (STM32H5_IRQ_FIRST + 74) /* 74: USB_FS global interrupt */ +# define STM32H5_IRQ_CRS (STM32H5_IRQ_FIRST + 75) /* 75: CRS global interrupt */ +# define STM32H5_IRQ_UCPD1 (STM32H5_IRQ_FIRST + 76) /* 76: UCPD1 global interrupt */ +# define STM32H5_IRQ_FMC (STM32H5_IRQ_FIRST + 77) /* 77: FMC global interrupt */ +# define STM32H5_IRQ_OCTOSPI1 (STM32H5_IRQ_FIRST + 78) /* 78: OCTOSPI1 global interrupt */ +# define STM32H5_IRQ_SDMMC1 (STM32H5_IRQ_FIRST + 79) /* 79: SDMMC1 global interrupt */ +# define STM32H5_IRQ_I2C3_EV (STM32H5_IRQ_FIRST + 80) /* 80: I2C3_EV global interrupt */ +# define STM32H5_IRQ_I2C3_ER (STM32H5_IRQ_FIRST + 81) /* 81: I2C3_ER global interrupt */ +# define STM32H5_IRQ_SPI4 (STM32H5_IRQ_FIRST + 82) /* 82: SPI4 global interrupt */ +# define STM32H5_IRQ_SPI5 (STM32H5_IRQ_FIRST + 83) /* 83: SPI5 global interrupt */ +# define STM32H5_IRQ_SPI6 (STM32H5_IRQ_FIRST + 84) /* 84: SPI6 global interrupt */ +# define STM32H5_IRQ_USART6 (STM32H5_IRQ_FIRST + 85) /* 85: USART6 global interrupt */ +# define STM32H5_IRQ_USART10 (STM32H5_IRQ_FIRST + 86) /* 86: USART10 global interrupt */ +# define STM32H5_IRQ_USART11 (STM32H5_IRQ_FIRST + 87) /* 87: USART11 global interrupt */ +# define STM32H5_IRQ_SAI1 (STM32H5_IRQ_FIRST + 88) /* 88: SAI1 global interrupt */ +# define STM32H5_IRQ_SAI2 (STM32H5_IRQ_FIRST + 89) /* 89: SAI2 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH0 (STM32H5_IRQ_FIRST + 90) /* 90: GPDMA2_CH0 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH1 (STM32H5_IRQ_FIRST + 91) /* 91: GPDMA2_CH1 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH2 (STM32H5_IRQ_FIRST + 92) /* 92: GPDMA2_CH2 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH3 (STM32H5_IRQ_FIRST + 93) /* 93: GPDMA2_CH3 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH4 (STM32H5_IRQ_FIRST + 94) /* 94: GPDMA2_CH4 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH5 (STM32H5_IRQ_FIRST + 95) /* 95: GPDMA2_CH5 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH6 (STM32H5_IRQ_FIRST + 96) /* 96: GPDMA2_CH6 global interrupt */ +# define STM32H5_IRQ_GPDMA2_CH7 (STM32H5_IRQ_FIRST + 97) /* 97: GPDMA2_CH7 global interrupt */ +# define STM32H5_IRQ_UART7 (STM32H5_IRQ_FIRST + 98) /* 98: UART7 global interrupt */ +# define STM32H5_IRQ_UART8 (STM32H5_IRQ_FIRST + 99) /* 99: UART8 global interrupt */ +# define STM32H5_IRQ_UART9 (STM32H5_IRQ_FIRST + 100) /* 100: UART9 global interrupt */ +# define STM32H5_IRQ_UART12 (STM32H5_IRQ_FIRST + 101) /* 101: UART12 global interrupt */ +# define STM32H5_IRQ_SDMMC2 (STM32H5_IRQ_FIRST + 102) /* 102: SDMMC2 global interrupt */ +# define STM32H5_IRQ_FPU (STM32H5_IRQ_FIRST + 103) /* 103: FPU global interrupt */ +# define STM32H5_IRQ_ICACHE (STM32H5_IRQ_FIRST + 104) /* 104: ICACHE global interrupt */ +# define STM32H5_IRQ_DCACHE (STM32H5_IRQ_FIRST + 105) /* 105: DCACHE global interrupt */ +# define STM32H5_IRQ_ETH (STM32H5_IRQ_FIRST + 106) /* 106: ETH global interrupt */ +# define STM32H5_IRQ_ETH_WKUP (STM32H5_IRQ_FIRST + 107) /* 107: ETH_WKUP global interrupt */ +# define STM32H5_IRQ_DCMI_PSSI (STM32H5_IRQ_FIRST + 108) /* 108: DCMI PSSI global interrupt */ +# define STM32H5_IRQ_FDCAN2_IT0 (STM32H5_IRQ_FIRST + 109) /* 109: FDCAN2_IT0 global interrupt */ +# define STM32H5_IRQ_FDCAN2_IT1 (STM32H5_IRQ_FIRST + 110) /* 110: FDCAN2_IT1 global interrupt */ +# define STM32H5_IRQ_CORDIC (STM32H5_IRQ_FIRST + 111) /* 111: CORDIC global interrupt */ +# define STM32H5_IRQ_FMAC (STM32H5_IRQ_FIRST + 112) /* 112: FMAC global interrupt */ +# define STM32H5_IRQ_DTS (STM32H5_IRQ_FIRST + 113) /* 113: DTS global interrupt */ +# define STM32H5_IRQ_RNG (STM32H5_IRQ_FIRST + 114) /* 114: RNG global interrupt */ +# define STM32H5_IRQ_OTFDEC1 (STM32H5_IRQ_FIRST + 115) /* 115: OTFDEC1 global interrupt */ +# define STM32H5_IRQ_AES (STM32H5_IRQ_FIRST + 116) /* 116: AES global interrupt */ +# define STM32H5_IRQ_HASH (STM32H5_IRQ_FIRST + 117) /* 117: HASH global interrupt */ +# define STM32H5_IRQ_PKA (STM32H5_IRQ_FIRST + 118) /* 118: PKA global interrupt */ +# define STM32H5_IRQ_CEC (STM32H5_IRQ_FIRST + 119) /* 119: CEC global interrupt */ +# define STM32H5_IRQ_TIM12 (STM32H5_IRQ_FIRST + 120) /* 120: TIM12 global interrupt */ +# define STM32H5_IRQ_TIM13 (STM32H5_IRQ_FIRST + 121) /* 121: TIM13 global interrupt */ +# define STM32H5_IRQ_TIM14 (STM32H5_IRQ_FIRST + 122) /* 122: TIM14 global interrupt */ +# define STM32H5_IRQ_I3C1_EV (STM32H5_IRQ_FIRST + 123) /* 123: I3C1_EV global interrupt */ +# define STM32H5_IRQ_I3C1_ER (STM32H5_IRQ_FIRST + 124) /* 124: I3C1_ER global interrupt */ +# define STM32H5_IRQ_I2C4_EV (STM32H5_IRQ_FIRST + 125) /* 125: I2C4_EV global interrupt */ +# define STM32H5_IRQ_I2C4_ER (STM32H5_IRQ_FIRST + 126) /* 126: I2C4_ER global interrupt */ +# define STM32H5_IRQ_LPTIM3 (STM32H5_IRQ_FIRST + 127) /* 127: LPTIM3 global interrupt */ +# define STM32H5_IRQ_LPTIM4 (STM32H5_IRQ_FIRST + 128) /* 128: LPTIM4 global interrupt */ +# define STM32H5_IRQ_LPTIM5 (STM32H5_IRQ_FIRST + 129) /* 129: LPTIM5 global interrupt */ +# define STM32H5_IRQ_LPTIM6 (STM32H5_IRQ_FIRST + 130) /* 130: LPTIM6 global interrupt */ +# define STM32H5_IRQ_NEXTINTS 131 +#else +# error "Unsupported STM32H56X or STM32H57X chip" +#endif + +/* (EXTI interrupts do not use IRQ numbers) */ + +#define NR_IRQS (STM32H5_IRQ_FIRST + STM32H5_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32H5_STM32H56XXX_7XXX_IRQ_H */ diff --git a/arch/arm/include/stm32h5/stm32h5_irq.h b/arch/arm/include/stm32h5/stm32h5_irq.h new file mode 100644 index 0000000000000..86162d497f0d1 --- /dev/null +++ b/arch/arm/include/stm32h5/stm32h5_irq.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/arm/include/stm32h5/stm32h5_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly by the chip type specific header files + * (e.g. stm32h562xx_irq.h) + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32H5_STM32H5_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32H5_STM32H5_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to bits + * in the NVIC. This does, however, waste several words of memory in the + * IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32H5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32H5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32H5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32H5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32H5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32H5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32H5_IRQ_SECUREFAULT (7) /* Vector 7: Usage fault */ + /* Vectors 8-10: Reserved */ +#define STM32H5_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32H5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32H5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32H5_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32H5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32H5_STM32H5_IRQ_H */ diff --git a/arch/arm/src/cmake/armv8-m.cmake b/arch/arm/src/cmake/armv8-m.cmake index 514006f5afac1..3c9d515965862 100644 --- a/arch/arm/src/cmake/armv8-m.cmake +++ b/arch/arm/src/cmake/armv8-m.cmake @@ -24,6 +24,36 @@ if(CONFIG_ARM_DSP) set(EXTCPUFLAGS +dsp) endif() +if(CONFIG_ARM_TOOLCHAIN_CLANG) + if(CONFIG_ARCH_CORTEXM23) + set(TOOLCHAIN_CLANG_CONFIG armv8m.main_soft_nofp) + elseif(CONFIG_ARCH_CORTEXM33) + if(CONFIG_ARCH_FPU) + set(TOOLCHAIN_CLANG_CONFIG armv8m.main_hard_fp) + else() + set(TOOLCHAIN_CLANG_CONFIG armv8m.main_soft_nofp) + endif() + elseif(CONFIG_ARCH_CORTEXM35P) + if(CONFIG_ARCH_FPU) + set(TOOLCHAIN_CLANG_CONFIG armv8m.main_hard_fp) + else() + set(TOOLCHAIN_CLANG_CONFIG armv8m.main_soft_nofp) + endif() + elseif(CONFIG_ARCH_CORTEXM55) + if(CONFIG_ARCH_FPU) + set(TOOLCHAIN_CLANG_CONFIG armv8.1m.main_hard_fp) + else() + set(TOOLCHAIN_CLANG_CONFIG armv8.1m.main_soft_nofp_nomve) + endif() + elseif(CONFIG_ARCH_CORTEXM85) + if(CONFIG_ARCH_FPU) + set(TOOLCHAIN_CLANG_CONFIG armv8.1m.main_hard_fp) + else() + set(TOOLCHAIN_CLANG_CONFIG armv8.1m.main_soft_nofp_nomve) + endif() + endif() +endif() + if(CONFIG_ARCH_CORTEXM23) list(APPEND PLATFORM_FLAGS -mtune=cortex-m23 -march=armv8-m.main -mfloat-abi=soft) diff --git a/arch/arm/src/cmake/gcc.cmake b/arch/arm/src/cmake/gcc.cmake index f4ec91b0bfe70..7ad27f60727ba 100644 --- a/arch/arm/src/cmake/gcc.cmake +++ b/arch/arm/src/cmake/gcc.cmake @@ -66,7 +66,7 @@ if(CONFIG_ARCH_TOOLCHAIN_GNU) if(GCCVER GREATER_EQUAL 12) add_compile_options(--param=min-pagesize=0) - if(CONFIG_ARCH_RAMFUNCS) + if(CONFIG_ARCH_RAMFUNCS OR NOT CONFIG_BOOT_RUNFROMFLASH) add_link_options(-Wl,--no-warn-rwx-segments) endif() endif() @@ -229,6 +229,8 @@ if(CONFIG_DEBUG_LINK_MAP) add_link_options(-Wl,--cref -Wl,-Map=nuttx.map) endif() +add_link_options(-Wl,--print-memory-usage) + if(CONFIG_DEBUG_SYMBOLS) add_compile_options(${CONFIG_DEBUG_SYMBOLS_LEVEL}) endif() diff --git a/arch/arm/src/cmake/platform.cmake b/arch/arm/src/cmake/platform.cmake index 1bce5f6678a5f..26e9adaebd8f0 100644 --- a/arch/arm/src/cmake/platform.cmake +++ b/arch/arm/src/cmake/platform.cmake @@ -79,7 +79,7 @@ if(NOT CONFIG_LIBM) nuttx_find_toolchain_lib(libm.a) endif() -if(CONFIG_LIBSUPCXX) +if(CONFIG_LIBSUPCXX_TOOLCHAIN) nuttx_find_toolchain_lib(libsupc++.a) endif() diff --git a/arch/arm/src/common/Toolchain.defs b/arch/arm/src/common/Toolchain.defs index 202d989051a2c..e5f7fd923cbb3 100644 --- a/arch/arm/src/common/Toolchain.defs +++ b/arch/arm/src/common/Toolchain.defs @@ -317,11 +317,14 @@ else ARCHOPTIMIZATION += --param=min-pagesize=0 ifeq ($(CONFIG_ARCH_RAMFUNCS),y) LDFLAGS += --no-warn-rwx-segments + else ifeq ($(CONFIG_BOOT_RUNFROMFLASH),) + LDFLAGS += --no-warn-rwx-segments endif endif endif LDFLAGS += --entry=__start + LDFLAGS += --print-memory-usage endif @@ -488,7 +491,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) endif endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 85ce6075a723a..25d12711b48a2 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig new file mode 100644 index 0000000000000..5a3927d70f211 --- /dev/null +++ b/arch/arm/src/stm32h5/Kconfig @@ -0,0 +1,3312 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_STM32H5 + +comment "STM32H5 Configuration Options" + +choice + prompt "STM32 H5 Chip Selection" + default ARCH_CHIP_STM32H563ZI + depends on ARCH_CHIP_STM32H5 + +config ARCH_CHIP_STM32H563ZI + bool "STM32H563ZI" + select STM32H5_STM32H5XXXX + select STM32H5_STM32H56XXX + select STM32H5_STM32H563XX + select STM32H5_FLASH_CONFIG_I + select STM32H5_IO_CONFIG_Z + ---help--- + STM32 H5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM + +endchoice # STM32 H5 Chip Selection + +# Chip families: + +config STM32H5_STM32H5XXXX + bool + default n + select ARCH_HAVE_FPU + +config STM32H5_STM32H56XXX + bool + default n + select STM32H5_HAVE_LPUART1 + select STM32H5_HAVE_USART1 + select STM32H5_HAVE_USART2 + select STM32H5_HAVE_USART3 + select STM32H5_HAVE_UART4 + select STM32H5_HAVE_UART5 + select STM32H5_HAVE_USART6 + select STM32H5_HAVE_UART7 + select STM32H5_HAVE_UART8 + select STM32H5_HAVE_UART9 + select STM32H5_HAVE_USART10 + select STM32H5_HAVE_USART11 + select STM32H5_HAVE_UART12 + +config STM32H5_STM32H563XX + # STM32H552 and STM32H562 devices documented in RM0439 + bool + default n + +choice + prompt "Override Flash Size Designator" + depends on ARCH_CHIP_STM32H5 + default STM32H5_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32H5 series parts numbering (sans the package type) ends with a letter + that designates the FLASH size. + + Designator Size in KiB + 8 64 + B 128 + C 256 + E 512 + G 1024 + I 2048 + + This configuration option defaults to using the configuration based on that designator + or the default smaller size if there is no last character designator is present in the + STM32 Chip Selection. + + Examples: + If the STM32H576VE is chosen, the Flash configuration would be 'E', if a variant of + the part with a 1024 KiB Flash is released in the future one could simply select + the 'G' designator here. + + If an STM32H5xxx Series parts is chosen the default Flash configuration will be set + herein and can be changed. + +config STM32H5_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32H5_FLASH_OVERRIDE_8 + bool "8 64 KB" + +config STM32H5_FLASH_OVERRIDE_B + bool "B 128 KB" + +config STM32H5_FLASH_OVERRIDE_C + bool "C 256 KB" + +config STM32H5_FLASH_OVERRIDE_E + bool "E 512 KB" + +config STM32H5_FLASH_OVERRIDE_G + bool "G 1024 KB" + +config STM32H5_FLASH_OVERRIDE_I + bool "I 2048 KB" + +endchoice # "Override Flash Size Designator" + +# Flash configurations + +config STM32H5_FLASH_CONFIG_B + bool + default n + depends on STM32H5_STM32H50XXX + +config STM32H5_FLASH_CONFIG_C + bool + default n + depends on STM32H5_STM32H52XXX + +config STM32H5_FLASH_CONFIG_E + bool + default n + depends on STM32H5_STM32H52XXX || STM32H5_STM32H53XXX + +config STM32H5_FLASH_CONFIG_G + bool + default n + depends on STM32H5_STM32H6XXX + +config STM32H5_FLASH_CONFIG_I + bool + default n + depends on STM32H5_STM32H56XXX || STM32H5_STM32H57XXX + +# Pin/package configurations + +config STM32H5_IO_CONFIG_K + bool + default n + +config STM32H5_IO_CONFIG_T + bool + default n + +config STM32H5_IO_CONFIG_C + bool + default n + +config STM32H5_IO_CONFIG_R + bool + default n + +config STM32H5_IO_CONFIG_J + bool + default n + +config STM32H5_IO_CONFIG_M + bool + default n + +config STM32H5_IO_CONFIG_V + bool + default n + +config STM32H5_IO_CONFIG_Q + bool + default n + +config STM32H5_IO_CONFIG_Z + bool + default n + +config STM32H5_IO_CONFIG_A + bool + default n + +comment "STM32H5 SRAM2 Options" + +config STM32H5_SRAM2_HEAP + bool "SRAM2 is used for heap" + default n + select STM32H5_SRAM2_INIT + ---help--- + The STM32H5 SRAM2 region has special properties (power, protection, parity) + which may be used by the application for special purposes. But if these + special properties are not needed, it may be instead added to the heap for + use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32H5_SRAM2_INIT + bool "SRAM2 is initialized to zero" + default n + ---help--- + The STM32H5 SRAM2 region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2 is being used for it's battery-backed capability, + this may be undesirable (because it will destroy the contents). In that + case, the board should handle the initialization itself at the appropriate + time. + +config STM32H5_USE_LEGACY_PINMAP + bool "Use the legacy pinmap with GPIO_SPEED_xxx included." + default n + ---help--- + In the past, pinmap files included GPIO_SPEED_xxxMhz. These speed + settings should have come from the board.h as it describes the wiring + of the SoC to the board. The speed is really slew rate control and + therefore is related to the layout and can only be properly set + in board.h. + + CONFIG_STM32H5_USE_LEGACY_PINMAP is provided, to allow lazy migration to + using pinmaps without speeds. The work required to do this can be aided + by running tools/stm32_pinmap_tool.py. The tools will take a board.h + file and a legacy pinmap and output the required changes that one needs + to make to a board.h file. + + Eventually, CONFIG_STM32H5_USE_LEGACY_PINMAP will be deprecated and the + legacy pinmaps removed from NuttX. Any new boards added should set + CONFIG_STM32H5_USE_LEGACY_PINMAP=n and fully define the pins in board.h + +comment "STM32H5 Peripherals" + +menu "STM32H5 Peripheral Support" + +# These "hidden" settings determine is a peripheral option is available for the +# selection MCU + +config STM32H5_HAVE_LPUART1 + bool + default n + +config STM32H5_HAVE_USART1 + bool + default n + +config STM32H5_HAVE_USART2 + bool + default n + +config STM32H5_HAVE_USART3 + bool + default n + +config STM32H5_HAVE_UART4 + bool + default n + +config STM32H5_HAVE_UART5 + bool + default n + +# These "hidden" settings are the OR of individual peripheral selections +# indicating that the general capability is required. + +config STM32H5_SPI + bool + default n + +config STM32H5_USART + bool + default n + +# These are the peripheral selections proper + +comment "AHB1 Peripherals" + +comment "AHB2 Peripherals" + +comment "AHB3 Peripherals" + +comment "APB1 Peripherals" + +config STM32H5_PWR + bool "PWR" + default n + +config STM32H5_RTC + bool "RTC" + default n + +config STM32H5_SPI2 + bool "SPI2" + default n + select SPI + select STM32H5_SPI + +config STM32H5_SPI3 + bool "SPI3" + default n + select SPI + select STM32H5_SPI + +config STM32H5_LPUART1 + bool "LPUART1" + default n + depends on STM32H5_HAVE_LPUART1 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32H5_USART + +config STM32H5_USART2 + bool "USART2" + default n + depends on STM32H5_HAVE_USART2 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32H5_USART + +config STM32H5_USART3 + bool "USART3" + default n + depends on STM32H5_HAVE_USART3 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32H5_USART + +config STM32H5_UART4 + bool "UART4" + default n + depends on STM32H5_HAVE_UART4 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32H5_USART + +config STM32H5_UART5 + bool "UART5" + default n + depends on STM32H5_HAVE_UART5 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32H5_USART + +comment "APB2 Peripherals" + +config STM32H5_SYSCFG + bool "SYSCFG" + default y + +config STM32H5_SPI1 + bool "SPI1" + default n + select SPI + select STM32H5_SPI + +config STM32H5_USART1 + bool "USART1" + default n + depends on STM32H5_HAVE_USART1 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32H5_USART + +endmenu + +config STM32H5_SAI1PLL + bool "SAI1PLL" + default n + ---help--- + The STM32H5 has a separate PLL for the SAI1 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32H5_SAI2PLL + bool "SAI2PLL" + default n + depends on STM32H5_HAVE_SAI2 + ---help--- + The STM32H5 has a separate PLL for the SAI2 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32H5_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + default y + ---help--- + Enable FLASH prefetch + +config STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG + bool "Disable IDLE Sleep (WFI) in debug mode" + default n + ---help--- + In debug configuration, disables the WFI instruction in the IDLE loop + to prevent the JTAG from disconnecting. With some JTAG debuggers, such + as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI + instruction, the debugger will disconnect, terminating the debug session. + +config ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" + default n + ---help--- + Enables special, board-specific STM32 clock configuration. + +config STM32H5_HAVE_RTC_SUBSECONDS + bool + select ARCH_HAVE_RTC_SUBSECONDS + default y + +menu "RTC Configuration" + depends on STM32H5_RTC + +config STM32H5_RTC_MAGIC_REG + int "BKP register" + default 0 + range 0 31 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config STM32H5_RTC_MAGIC + hex "RTC Magic 1" + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +config STM32H5_RTC_MAGIC_TIME_SET + hex "RTC Magic 2" + default 0xf00dface + ---help--- + Value used as Magic to determine if the RTC has been setup and has + time set + +choice + prompt "RTC clock source" + default STM32H5_RTC_LSECLOCK + depends on STM32H5_RTC + +config STM32H5_RTC_LSECLOCK + bool "LSE clock" + ---help--- + Drive the RTC with the LSE clock + +config STM32H5_RTC_LSICLOCK + bool "LSI clock" + ---help--- + Drive the RTC with the LSI clock + +config STM32H5_RTC_HSECLOCK + bool "HSE clock" + ---help--- + Drive the RTC with the HSE clock, divided down to 1MHz. + +endchoice + +if STM32H5_RTC_LSECLOCK + +config STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" + default n + ---help--- + This will cycle through the values from low to high. To avoid + damaging the the crystal. We want to use the lowest setting that gets + the OSC running. See app note AN2867 + + 0 = Low drive capability (default) + 1 = Medium low drive capability + 2 = Medium high drive capability + 3 = High drive capability + +config STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY + int "LSE oscillator drive capability level at LSE start-up" + default 0 + range 0 3 + depends on !STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + 0 = Low drive capability (default) + 1 = Medium low drive capability + 2 = Medium high drive capability + 3 = High drive capability + +config STM32H5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + bool "Decrease LSE oscillator drive capability after LSE start-up" + default n + depends on !STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + The LSE oscillator drive capability can remain at the level used + during LSE start-up at run-time, or it can be reduced to the + 'Low drive capability' once the LSE started up successfully. + +endif # STM32H5_RTC_LSECLOCK + +endmenu # RTC Configuration + +menu "Timer Configuration" + +if SCHED_TICKLESS + +config STM32H5_ONESHOT + bool + default y + +config STM32H5_FREERUN + bool + default y + +config STM32H5_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + default 2 + range 1 8 + depends on STM32H5_ONESHOT + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the one-shot timer needed by the OS. + +config STM32H5_TICKLESS_FREERUN + int "Tickless free-running timer channel" + default 5 + range 1 8 + depends on STM32H5_FREERUN + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the free-running timer needed by the OS. + +endif # SCHED_TICKLESS + +if !SCHED_TICKLESS + +config STM32H5_ONESHOT + bool "TIM one-shot wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32H5_FREERUN + bool "TIM free-running wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +endif # !SCHED_TICKLESS + +config STM32H5_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + default 1 + range 1 8 + depends on STM32H5_ONESHOT + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +config STM32H5_LPTIM1_PWM + bool "LPTIM1 PWM" + default n + depends on STM32H5_LPTIM1 + select PWM + ---help--- + Reserve low-power timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_LPTIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_LPTIM1_PWM + +choice + prompt "LPTIM1 clock source" + default STM32H5_LPTIM1_CLK_APB1 + +config STM32H5_LPTIM1_CLK_APB1 + bool "Clock LPTIM1 from APB1" + +config STM32H5_LPTIM1_CLK_LSE + bool "Clock LPTIM1 from LSE" + +config STM32H5_LPTIM1_CLK_LSI + bool "Clock LPTIM1 from LSI" + +config STM32H5_LPTIM1_CLK_HSI + bool "Clock LPTIM1 from HSI" +endchoice + +endif # STM32H5_LPTIM1_PWM + +config STM32H5_LPTIM2_PWM + bool "LPTIM2 PWM" + default n + depends on STM32H5_LPTIM2 + select PWM + ---help--- + Reserve low-power timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_LPTIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_LPTIM2_PWM + +choice + prompt "LPTIM2 clock source" + default STM32H5_LPTIM2_CLK_APB1 + +config STM32H5_LPTIM2_CLK_APB1 + bool "Clock LPTIM2 from APB1" + +config STM32H5_LPTIM2_CLK_LSE + bool "Clock LPTIM2 from LSE" + +config STM32H5_LPTIM2_CLK_LSI + bool "Clock LPTIM2 from LSI" + +config STM32H5_LPTIM2_CLK_HSI + bool "Clock LPTIM2 from HSI" +endchoice + +endif # STM32H5_LPTIM2_PWM + +config STM32H5_TIM1_PWM + bool "TIM1 PWM" + default n + depends on STM32H5_TIM1 + select PWM + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM1_PWM + +config STM32H5_TIM1_MODE + int "TIM1 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM1_CHANNEL1 + +config STM32H5_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config STM32H5_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + default n + depends on STM32H5_TIM1_CH1OUT + ---help--- + Enables channel 1 complementary output. + +endif # STM32H5_TIM1_CHANNEL1 + +config STM32H5_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32H5_TIM1_CHANNEL2 + +config STM32H5_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +config STM32H5_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complemenrary Output" + default n + depends on STM32H5_TIM1_CH2OUT + ---help--- + Enables channel 2 complementary output. + +endif # STM32H5_TIM1_CHANNEL2 + +config STM32H5_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32H5_TIM1_CHANNEL3 + +config STM32H5_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +config STM32H5_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + default n + depends on STM32H5_TIM1_CH3OUT + ---help--- + Enables channel 3 complementary output. + +endif # STM32H5_TIM1_CHANNEL3 + +config STM32H5_TIM1_CHANNEL5 + bool "TIM1 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32H5_TIM1_CHANNEL5 + +config STM32H5_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H5_TIM1_CHANNEL5 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32H5_TIM1_CHMODE + int "TIM1 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM1_PWM + +config STM32H5_TIM2_PWM + bool "TIM2 PWM" + default n + depends on STM32H5_TIM2 + select PWM + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM2_PWM + +config STM32H5_TIM2_MODE + int "TIM2 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM2_CHANNEL1 + +config STM32H5_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H5_TIM2_CHANNEL1 + +config STM32H5_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32H5_TIM2_CHANNEL2 + +config STM32H5_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H5_TIM2_CHANNEL2 + +config STM32H5_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32H5_TIM2_CHANNEL3 + +config STM32H5_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32H5_TIM2_CHANNEL3 + +config STM32H5_TIM2_CHANNEL5 + bool "TIM2 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32H5_TIM2_CHANNEL5 + +config STM32H5_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H5_TIM2_CHANNEL5 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32H5_TIM2_CHMODE + int "TIM2 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM2_PWM + +config STM32H5_TIM3_PWM + bool "TIM3 PWM" + default n + depends on STM32H5_TIM3 + select PWM + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM3_PWM + +config STM32H5_TIM3_MODE + int "TIM3 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM3_CHANNEL1 + +config STM32H5_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H5_TIM3_CHANNEL1 + +config STM32H5_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32H5_TIM3_CHANNEL2 + +config STM32H5_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H5_TIM3_CHANNEL2 + +config STM32H5_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32H5_TIM3_CHANNEL3 + +config STM32H5_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32H5_TIM3_CHANNEL3 + +config STM32H5_TIM3_CHANNEL5 + bool "TIM3 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32H5_TIM3_CHANNEL5 + +config STM32H5_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H5_TIM3_CHANNEL5 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32H5_TIM3_CHMODE + int "TIM3 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM3_PWM + +config STM32H5_TIM4_PWM + bool "TIM4 PWM" + default n + depends on STM32H5_TIM4 + select PWM + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM4_PWM + +config STM32H5_TIM4_MODE + int "TIM4 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM4_CHANNEL1 + +config STM32H5_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H5_TIM4_CHANNEL1 + +config STM32H5_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32H5_TIM4_CHANNEL2 + +config STM32H5_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H5_TIM4_CHANNEL2 + +config STM32H5_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32H5_TIM4_CHANNEL3 + +config STM32H5_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32H5_TIM4_CHANNEL3 + +config STM32H5_TIM4_CHANNEL5 + bool "TIM4 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32H5_TIM4_CHANNEL5 + +config STM32H5_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H5_TIM4_CHANNEL5 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32H5_TIM4_CHMODE + int "TIM4 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM4_PWM + +config STM32H5_TIM5_PWM + bool "TIM5 PWM" + default n + depends on STM32H5_TIM5 + select PWM + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM5_PWM + +config STM32H5_TIM5_MODE + int "TIM5 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM5_CHANNEL1 + +config STM32H5_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H5_TIM5_CHANNEL1 + +config STM32H5_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32H5_TIM5_CHANNEL2 + +config STM32H5_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H5_TIM5_CHANNEL2 + +config STM32H5_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32H5_TIM5_CHANNEL3 + +config STM32H5_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32H5_TIM5_CHANNEL3 + +config STM32H5_TIM5_CHANNEL5 + bool "TIM5 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32H5_TIM5_CHANNEL5 + +config STM32H5_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H5_TIM5_CHANNEL5 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32H5_TIM5_CHMODE + int "TIM5 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM5_PWM + +config STM32H5_TIM8_PWM + bool "TIM8 PWM" + default n + depends on STM32H5_TIM8 + select PWM + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM8_PWM + +config STM32H5_TIM8_MODE + int "TIM8 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM8_CHANNEL1 + +config STM32H5_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config STM32H5_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + default n + depends on STM32H5_TIM8_CH1OUT + ---help--- + Enables channel 1 complementary output. + +endif # STM32H5_TIM8_CHANNEL1 + +config STM32H5_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32H5_TIM8_CHANNEL2 + +config STM32H5_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +config STM32H5_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + default n + depends on STM32H5_TIM8_CH2OUT + ---help--- + Enables channel 2 complementary output. + +endif # STM32H5_TIM8_CHANNEL2 + +config STM32H5_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32H5_TIM8_CHANNEL3 + +config STM32H5_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +config STM32H5_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + default n + depends on STM32H5_TIM8_CH3OUT + ---help--- + Enables channel 3 complementary output. + +endif # STM32H5_TIM8_CHANNEL3 + +config STM32H5_TIM8_CHANNEL5 + bool "TIM8 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32H5_TIM8_CHANNEL5 + +config STM32H5_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H5_TIM8_CHANNEL5 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32H5_TIM8_CHMODE + int "TIM8 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM8_PWM + +config STM32H5_TIM15_PWM + bool "TIM15 PWM" + default n + depends on STM32H5_TIM15 + select PWM + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM15_PWM + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM15_CHANNEL1 + +config STM32H5_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + default 0 + range 0 3 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config STM32H5_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + default n + depends on STM32H5_TIM15_CH1OUT + ---help--- + Enables channel 1 complementary output. + +endif # STM32H5_TIM15_CHANNEL1 + +config STM32H5_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32H5_TIM15_CHANNEL2 + +config STM32H5_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + default 0 + range 0 3 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H5_TIM15_CHANNEL2 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32H5_TIM15_CHMODE + int "TIM15 Channel Mode" + default 0 + range 0 3 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM15_PWM + +config STM32H5_TIM16_PWM + bool "TIM16 PWM" + default n + depends on STM32H5_TIM16 + select PWM + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM16_PWM + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM16_CHANNEL1 + +config STM32H5_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config STM32H5_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + default n + depends on STM32H5_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + +endif # STM32H5_TIM16_CHANNEL1 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32H5_TIM16_CHMODE + int "TIM16 Channel Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM16_PWM + +config STM32H5_TIM17_PWM + bool "TIM17 PWM" + default n + depends on STM32H5_TIM17 + select PWM + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32H5_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32H5_TIM17_PWM + +if STM32H5_PWM_MULTICHAN + +config STM32H5_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H5_TIM17_CHANNEL1 + +config STM32H5_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +config STM32H5_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config STM32H5_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + default n + depends on STM32H5_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + +endif # STM32H5_TIM17_CHANNEL1 + +endif # STM32H5_PWM_MULTICHAN + +if !STM32H5_PWM_MULTICHAN + +config STM32H5_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32H5_TIM17_CHMODE + int "TIM17 Channel Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +endif # !STM32H5_PWM_MULTICHAN + +endif # STM32H5_TIM17_PWM + +config STM32H5_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + default n + depends on STM32H5_TIM1_PWM || STM32H5_TIM2_PWM || STM32H5_TIM3_PWM || STM32H5_TIM4_PWM || STM32H5_TIM5_PWM || STM32H5_TIM8_PWM || STM32H5_TIM15_PWM || STM32H5_TIM16_PWM || STM32H5_TIM17_PWM + select ARCH_HAVE_PWM_MULTICHAN + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32H5_TIM1_ADC + bool "TIM1 ADC" + default n + depends on STM32H5_TIM1 && STM32H5_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32H5_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM1 ADC channel" + default STM32H5_TIM1_ADC1 + depends on STM32H5_TIM1_ADC + +config STM32H5_TIM1_ADC1 + bool "TIM1 ADC channel 1" + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER + ---help--- + Reserve TIM1 to trigger ADC1 + +config STM32H5_TIM1_ADC2 + bool "TIM1 ADC channel 2" + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER + ---help--- + Reserve TIM1 to trigger ADC2 + +config STM32H5_TIM1_ADC3 + bool "TIM1 ADC channel 3" + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER + ---help--- + Reserve TIM1 to trigger ADC3 + +endchoice + +config STM32H5_TIM2_ADC + bool "TIM2 ADC" + default n + depends on STM32H5_TIM2 && STM32H5_ADC + ---help--- + Reserve timer 2 for use by ADC + + Timer devices may be used for different purposes. If STM32H5_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM2 ADC channel" + default STM32H5_TIM2_ADC1 + depends on STM32H5_TIM2_ADC + +config STM32H5_TIM2_ADC1 + bool "TIM2 ADC channel 1" + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER + ---help--- + Reserve TIM2 to trigger ADC1 + +config STM32H5_TIM2_ADC2 + bool "TIM2 ADC channel 2" + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER + ---help--- + Reserve TIM2 to trigger ADC2 + +config STM32H5_TIM2_ADC3 + bool "TIM2 ADC channel 3" + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER + ---help--- + Reserve TIM2 to trigger ADC3 + +endchoice + +config STM32H5_TIM3_ADC + bool "TIM3 ADC" + default n + depends on STM32H5_TIM3 && STM32H5_ADC + ---help--- + Reserve timer 3 for use by ADC + + Timer devices may be used for different purposes. If STM32H5_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM3 ADC channel" + default STM32H5_TIM3_ADC1 + depends on STM32H5_TIM3_ADC + +config STM32H5_TIM3_ADC1 + bool "TIM3 ADC channel 1" + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER + ---help--- + Reserve TIM3 to trigger ADC1 + +config STM32H5_TIM3_ADC2 + bool "TIM3 ADC channel 2" + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER + ---help--- + Reserve TIM3 to trigger ADC2 + +config STM32H5_TIM3_ADC3 + bool "TIM3 ADC channel 3" + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER + ---help--- + Reserve TIM3 to trigger ADC3 + +endchoice + +config STM32H5_TIM4_ADC + bool "TIM4 ADC" + default n + depends on STM32H5_TIM4 && STM32H5_ADC + ---help--- + Reserve timer 4 for use by ADC + + Timer devices may be used for different purposes. If STM32H5_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM4 ADC channel" + default STM32H5_TIM4_ADC1 + depends on STM32H5_TIM4_ADC + +config STM32H5_TIM4_ADC1 + bool "TIM4 ADC channel 1" + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER + ---help--- + Reserve TIM4 to trigger ADC1 + +config STM32H5_TIM4_ADC2 + bool "TIM4 ADC channel 2" + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER + ---help--- + Reserve TIM4 to trigger ADC2 + +config STM32H5_TIM4_ADC3 + bool "TIM4 ADC channel 3" + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER + ---help--- + Reserve TIM4 to trigger ADC3 + +endchoice + +config STM32H5_TIM6_ADC + bool "TIM6 ADC" + default n + depends on STM32H5_TIM6 && STM32H5_ADC + ---help--- + Reserve timer 6 for use by ADC + + Timer devices may be used for different purposes. If STM32H5_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM6 ADC channel" + default STM32H5_TIM6_ADC1 + depends on STM32H5_TIM6_ADC + +config STM32H5_TIM6_ADC1 + bool "TIM6 ADC channel 1" + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER + ---help--- + Reserve TIM6 to trigger ADC1 + +config STM32H5_TIM6_ADC2 + bool "TIM6 ADC channel 2" + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER + ---help--- + Reserve TIM6 to trigger ADC2 + +config STM32H5_TIM6_ADC3 + bool "TIM6 ADC channel 3" + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER + ---help--- + Reserve TIM6 to trigger ADC3 + +endchoice + +config STM32H5_TIM8_ADC + bool "TIM8 ADC" + default n + depends on STM32H5_TIM8 && STM32H5_ADC + ---help--- + Reserve timer 8 for use by ADC + + Timer devices may be used for different purposes. If STM32H5_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM8 ADC channel" + default STM32H5_TIM8_ADC1 + depends on STM32H5_TIM8_ADC + +config STM32H5_TIM8_ADC1 + bool "TIM8 ADC channel 1" + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER + ---help--- + Reserve TIM8 to trigger ADC1 + +config STM32H5_TIM8_ADC2 + bool "TIM8 ADC channel 2" + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER + ---help--- + Reserve TIM8 to trigger ADC2 + +config STM32H5_TIM8_ADC3 + bool "TIM8 ADC channel 3" + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER + ---help--- + Reserve TIM8 to trigger ADC3 + +endchoice + +config STM32H5_TIM15_ADC + bool "TIM15 ADC" + default n + depends on STM32H5_TIM15 && STM32H5_ADC + ---help--- + Reserve timer 15 for use by ADC + + Timer devices may be used for different purposes. If STM32H5_TIM15 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM15 ADC channel" + default STM32H5_TIM15_ADC1 + depends on STM32H5_TIM15_ADC + +config STM32H5_TIM15_ADC1 + bool "TIM15 ADC channel 1" + depends on STM32H5_ADC1 + select STM32H5_HAVE_ADC1_TIMER + ---help--- + Reserve TIM15 to trigger ADC1 + +config STM32H5_TIM15_ADC2 + bool "TIM15 ADC channel 2" + depends on STM32H5_ADC2 + select STM32H5_HAVE_ADC2_TIMER + ---help--- + Reserve TIM15 to trigger ADC2 + +config STM32H5_TIM15_ADC3 + bool "TIM15 ADC channel 3" + depends on STM32H5_ADC3 + select STM32H5_HAVE_ADC3_TIMER + ---help--- + Reserve TIM15 to trigger ADC3 + +endchoice + +config STM32H5_HAVE_ADC1_TIMER + bool + +config STM32H5_HAVE_ADC2_TIMER + bool + +config STM32H5_HAVE_ADC3_TIMER + bool + +config STM32H5_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + default 100 + depends on STM32H5_HAVE_ADC1_TIMER + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32H5_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + default 0 + range 0 4 + depends on STM32H5_HAVE_ADC1_TIMER + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO + +config STM32H5_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + default 100 + depends on STM32H5_HAVE_ADC2_TIMER + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32H5_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + default 0 + range 0 4 + depends on STM32H5_HAVE_ADC2_TIMER + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO + +config STM32H5_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + default 100 + depends on STM32H5_HAVE_ADC3_TIMER + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32H5_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + default 0 + range 0 4 + depends on STM32H5_HAVE_ADC3_TIMER + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO + +config STM32H5_TIM1_DAC + bool "TIM1 DAC" + default n + depends on STM32H5_TIM1 && STM32H5_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32H5_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM1 DAC channel" + default STM32H5_TIM1_DAC1 + depends on STM32H5_TIM1_DAC + +config STM32H5_TIM1_DAC1 + bool "TIM1 DAC channel 1" + ---help--- + Reserve TIM1 to trigger DAC1 + +config STM32H5_TIM1_DAC2 + bool "TIM1 DAC channel 2" + ---help--- + Reserve TIM1 to trigger DAC2 + +endchoice + +config STM32H5_TIM2_DAC + bool "TIM2 DAC" + default n + depends on STM32H5_TIM2 && STM32H5_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32H5_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM2 DAC channel" + default STM32H5_TIM2_DAC1 + depends on STM32H5_TIM2_DAC + +config STM32H5_TIM2_DAC1 + bool "TIM2 DAC channel 1" + ---help--- + Reserve TIM2 to trigger DAC1 + +config STM32H5_TIM2_DAC2 + bool "TIM2 DAC channel 2" + ---help--- + Reserve TIM2 to trigger DAC2 + +endchoice + +config STM32H5_TIM3_DAC + bool "TIM3 DAC" + default n + depends on STM32H5_TIM3 && STM32H5_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32H5_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM3 DAC channel" + default STM32H5_TIM3_DAC1 + depends on STM32H5_TIM3_DAC + +config STM32H5_TIM3_DAC1 + bool "TIM3 DAC channel 1" + ---help--- + Reserve TIM3 to trigger DAC1 + +config STM32H5_TIM3_DAC2 + bool "TIM3 DAC channel 2" + ---help--- + Reserve TIM3 to trigger DAC2 + +endchoice + +config STM32H5_TIM4_DAC + bool "TIM4 DAC" + default n + depends on STM32H5_TIM4 && STM32H5_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32H5_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM4 DAC channel" + default STM32H5_TIM4_DAC1 + depends on STM32H5_TIM4_DAC + +config STM32H5_TIM4_DAC1 + bool "TIM4 DAC channel 1" + ---help--- + Reserve TIM4 to trigger DAC1 + +config STM32H5_TIM4_DAC2 + bool "TIM4 DAC channel 2" + ---help--- + Reserve TIM4 to trigger DAC2 + +endchoice + +config STM32H5_TIM5_DAC + bool "TIM5 DAC" + default n + depends on STM32H5_TIM5 && STM32H5_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32H5_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM5 DAC channel" + default STM32H5_TIM5_DAC1 + depends on STM32H5_TIM5_DAC + +config STM32H5_TIM5_DAC1 + bool "TIM5 DAC channel 1" + ---help--- + Reserve TIM5 to trigger DAC1 + +config STM32H5_TIM5_DAC2 + bool "TIM5 DAC channel 2" + ---help--- + Reserve TIM5 to trigger DAC2 + +endchoice + +config STM32H5_TIM6_DAC + bool "TIM6 DAC" + default n + depends on STM32H5_TIM6 && STM32H5_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32H5_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM6 DAC channel" + default STM32H5_TIM6_DAC1 + depends on STM32H5_TIM6_DAC + +config STM32H5_TIM6_DAC1 + bool "TIM6 DAC channel 1" + ---help--- + Reserve TIM6 to trigger DAC1 + +config STM32H5_TIM6_DAC2 + bool "TIM6 DAC channel 2" + ---help--- + Reserve TIM6 to trigger DAC2 + +endchoice + +config STM32H5_TIM7_DAC + bool "TIM7 DAC" + default n + depends on STM32H5_TIM7 && STM32H5_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32H5_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM7 DAC channel" + default STM32H5_TIM7_DAC1 + depends on STM32H5_TIM7_DAC + +config STM32H5_TIM7_DAC1 + bool "TIM7 DAC channel 1" + ---help--- + Reserve TIM7 to trigger DAC1 + +config STM32H5_TIM7_DAC2 + bool "TIM7 DAC channel 2" + ---help--- + Reserve TIM7 to trigger DAC2 + +endchoice + +config STM32H5_TIM8_DAC + bool "TIM8 DAC" + default n + depends on STM32H5_TIM8 && STM32H5_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32H5_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM8 DAC channel" + default STM32H5_TIM8_DAC1 + depends on STM32H5_TIM8_DAC + +config STM32H5_TIM8_DAC1 + bool "TIM8 DAC channel 1" + ---help--- + Reserve TIM8 to trigger DAC1 + +config STM32H5_TIM8_DAC2 + bool "TIM8 DAC channel 2" + ---help--- + Reserve TIM8 to trigger DAC2 + +endchoice + +config STM32H5_TIM1_CAP + bool "TIM1 Capture" + default n + depends on STM32H5_HAVE_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32H5_TIM2_CAP + bool "TIM2 Capture" + default n + depends on STM32H5_HAVE_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32H5_TIM3_CAP + bool "TIM3 Capture" + default n + depends on STM32H5_HAVE_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32H5_TIM4_CAP + bool "TIM4 Capture" + default n + depends on STM32H5_HAVE_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32H5_TIM5_CAP + bool "TIM5 Capture" + default n + depends on STM32H5_HAVE_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32H5_TIM8_CAP + bool "TIM8 Capture" + default n + depends on STM32H5_HAVE_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +endmenu # Timer Configuration + +menu "ADC Configuration" + depends on STM32H5_ADC + +config STM32H5_ADC1_DMA + bool "ADC1 DMA" + depends on STM32H5_ADC1 + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32H5_ADC2_DMA + bool "ADC2 DMA" + depends on STM32H5_ADC2 + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32H5_ADC3_DMA + bool "ADC3 DMA" + depends on STM32H5_ADC3 + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32H5_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32H5_ADC1 && STM32H5_DFSDM1 && (STM32H5_STM32H596XX || STM32H5_STM32H5XR) + default n + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32H5_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32H5_ADC2 && STM32H5_DFSDM1 && STM32H5_STM32H596XX + default n + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32H5_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32H5_ADC3 && STM32H5_DFSDM1 && STM32H5_STM32H596XX + default n + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +endmenu + +menu "DAC Configuration" + depends on STM32H5_DAC + +config STM32H5_DAC1_DMA + bool "DAC1 DMA" + depends on STM32H5_DAC1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32H5_DAC1_DMA + +config STM32H5_DAC1_TIMER + int "DAC1 timer" + range 2 8 + +config STM32H5_DAC1_TIMER_FREQUENCY + int "DAC1 timer frequency" + default 100 + ---help--- + DAC1 output frequency. Default: 100Hz + +config STM32H5_DAC1_DMA_BUFFER_SIZE + int "DAC1 DMA buffer size" + default 1 + +endif + +config STM32H5_DAC1_OUTPUT_ADC + bool "DAC1 output to ADC" + depends on STM32H5_DAC1 + default n + ---help--- + Route DAC1 output to ADC input instead of external pin. + +config STM32H5_DAC2_DMA + bool "DAC2 DMA" + depends on STM32H5_DAC2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32H5_DAC2_DMA + +config STM32H5_DAC2_TIMER + int "DAC2 timer" + default 0 + range 2 8 + +config STM32H5_DAC2_TIMER_FREQUENCY + int "DAC2 timer frequency" + default 100 + ---help--- + DAC2 output frequency. Default: 100Hz + +config STM32H5_DAC2_DMA_BUFFER_SIZE + int "DAC2 DMA buffer size" + default 1 + +endif + +config STM32H5_DAC2_OUTPUT_ADC + bool "DAC2 output to ADC" + depends on STM32H5_DAC2 + default n + ---help--- + Route DAC2 output to ADC input instead of external pin. + +endmenu + +menu "DFSDM Configuration" + depends on STM32H5_DFSDM1 + +config STM32H5_DFSDM1_FLT0 + bool "DFSDM1 Filter 0" + default n + select STM32H5_DFSDM + +config STM32H5_DFSDM1_FLT1 + bool "DFSDM1 Filter 1" + default n + select STM32H5_DFSDM + +config STM32H5_DFSDM1_FLT2 + bool "DFSDM1 Filter 2" + default n + depends on !STM32H5_STM32H5X3 + select STM32H5_DFSDM + +config STM32H5_DFSDM1_FLT3 + bool "DFSDM1 Filter 3" + default n + depends on !STM32H5_STM32H5X3 + select STM32H5_DFSDM + +config STM32H5_DFSDM1_DMA + bool "DFSDM1 DMA" + depends on STM32H5_DFSDM + default n + ---help--- + If DMA is selected, then the DFSDM may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +endmenu + +config STM32H5_SERIALDRIVER + bool + +config STM32H5_1WIREDRIVER + bool + +menu "[LP]U[S]ART Configuration" + depends on STM32H5_USART + +choice + prompt "LPUART1 Driver Configuration" + default STM32H5_LPUART1_SERIALDRIVER + depends on STM32H5_LPUART1 + +config STM32H5_LPUART1_SERIALDRIVER + bool "Standard serial driver" + select LPUART1_SERIALDRIVER + select STM32H5_SERIALDRIVER + +config STM32H5_LPUART1_1WIREDRIVER + bool "1-Wire driver" + select STM32H5_1WIREDRIVER + +endchoice # LPUART1 Driver Configuration + +if LPUART1_SERIALDRIVER + +config LPUART1_RS485 + bool "RS-485 on LPUART1" + default n + depends on STM32H5_LPUART1 + ---help--- + Enable RS-485 interface on LPUART1. Your board config will have to + provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be + used with LPUART1_RXDMA. + +config LPUART1_RS485_DIR_POLARITY + int "LPUART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on LPUART1_RS485 + ---help--- + Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config LPUART1_RXDMA + bool "LPUART1 Rx DMA" + default n + depends on STM32H5_LPUART1 && (STM32H5_DMA1 || STM32H5_DMA2 || STM32H5_DMAMUX) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # LPUART1_SERIALDRIVER + +choice + prompt "USART1 Driver Configuration" + default STM32H5_USART1_SERIALDRIVER + depends on STM32H5_USART1 + +config STM32H5_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select STM32H5_SERIALDRIVER + +config STM32H5_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32H5_1WIREDRIVER + +endchoice # USART1 Driver Configuration + +if USART1_SERIALDRIVER + +config USART1_RS485 + bool "RS-485 on USART1" + default n + depends on STM32H5_USART1 + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be + used with USART1_RXDMA. + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART1_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART1_RXDMA + bool "USART1 Rx DMA" + default n + depends on STM32H5_USART1 && (STM32H5_DMA1 || STM32H5_DMA2 || STM32H5_DMAMUX) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART1_SERIALDRIVER + +choice + prompt "USART2 Driver Configuration" + default STM32H5_USART2_SERIALDRIVER + depends on STM32H5_USART2 + +config STM32H5_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select STM32H5_SERIALDRIVER + +config STM32H5_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32H5_1WIREDRIVER + +endchoice # USART2 Driver Configuration + +if USART2_SERIALDRIVER + +config USART2_RS485 + bool "RS-485 on USART2" + default n + depends on STM32H5_USART2 + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be + used with USART2_RXDMA. + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART2_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART2_RXDMA + bool "USART2 Rx DMA" + default n + depends on STM32H5_USART2 && (STM32H5_DMA1 || STM32H5_DMAMUX) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART2_SERIALDRIVER + +choice + prompt "USART3 Driver Configuration" + default STM32H5_USART3_SERIALDRIVER + depends on STM32H5_USART3 + +config STM32H5_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select STM32H5_SERIALDRIVER + +config STM32H5_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32H5_1WIREDRIVER + +endchoice # USART3 Driver Configuration + +if USART3_SERIALDRIVER + +config USART3_RS485 + bool "RS-485 on USART3" + default n + depends on STM32H5_USART3 + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be + used with USART3_RXDMA. + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART3_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART3_RXDMA + bool "USART3 Rx DMA" + default n + depends on STM32H5_USART3 && (STM32H5_DMA1 || STM32H5_DMAMUX) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART3_SERIALDRIVER + +choice + prompt "UART4 Driver Configuration" + default STM32H5_UART4_SERIALDRIVER + depends on STM32H5_UART4 + +config STM32H5_UART4_SERIALDRIVER + bool "Standard serial driver" + select UART4_SERIALDRIVER + select STM32H5_SERIALDRIVER + +config STM32H5_UART4_1WIREDRIVER + bool "1-Wire driver" + select STM32H5_1WIREDRIVER + +endchoice # UART4 Driver Configuration + +if UART4_SERIALDRIVER + +config UART4_RS485 + bool "RS-485 on UART4" + default n + depends on STM32H5_UART4 + ---help--- + Enable RS-485 interface on UART4. Your board config will have to + provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be + used with UART4_RXDMA. + +config UART4_RS485_DIR_POLARITY + int "UART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART4_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART4_RXDMA + bool "UART4 Rx DMA" + default n + depends on STM32H5_UART4 && (STM32H5_DMA2 || STM32H5_DMAMUX) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART4_SERIALDRIVER + +choice + prompt "UART5 Driver Configuration" + default STM32H5_UART5_SERIALDRIVER + depends on STM32H5_UART5 + +config STM32H5_UART5_SERIALDRIVER + bool "Standard serial driver" + select UART5_SERIALDRIVER + select STM32H5_SERIALDRIVER + +config STM32H5_UART5_1WIREDRIVER + bool "1-Wire driver" + select STM32H5_1WIREDRIVER + +endchoice # UART5 Driver Configuration + +if UART5_SERIALDRIVER + +config UART5_RS485 + bool "RS-485 on UART5" + default n + depends on STM32H5_UART5 + ---help--- + Enable RS-485 interface on UART5. Your board config will have to + provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be + used with UART5_RXDMA. + +config UART5_RS485_DIR_POLARITY + int "UART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART5_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART5_RXDMA + bool "UART5 Rx DMA" + default n + depends on STM32H5_UART5 && (STM32H5_DMA2 || STM32H5_DMAMUX) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART5_SERIALDRIVER + +if STM32H5_SERIALDRIVER + +comment "Serial Driver Configuration" + +config STM32H5_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + default 32 + depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half this number of bytes. + + Value given here will be rounded up to next multiple of 32 bytes. + +config STM32H5_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + depends on STM32H5_USART1 || STM32H5_USART2 || STM32H5_USART3 || STM32H5_UART4 || STM32H5_UART5 + default n + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some boards and a serial console in other boards, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +config STM32H5_FLOWCONTROL_BROKEN + bool "Use Software UART RTS flow control" + depends on STM32H5_USART + default n + ---help--- + Enable UART RTS flow control using Software. Because STM + Current STM32 have broken HW based RTS behavior (they assert + nRTS after every byte received) Enable this setting workaround + this issue by using software based management of RTS + +config STM32H5_USART_BREAKS + bool "Add TIOxSBRK to support sending Breaks" + depends on STM32H5_USART + default n + ---help--- + Add TIOCxBRK routines to send a line break per the STM32 manual, the + break will be a pulse based on the value M. This is not a BSD compatible + break. + +config STM32H5_SERIALBRK_BSDCOMPAT + bool "Use GPIO To send Break" + depends on STM32H5_USART && STM32H5_USART_BREAKS + default n + ---help--- + Enable using GPIO on the TX pin to send a BSD compatible break: + TIOCSBRK will start the break and TIOCCBRK will end the break. + The current STM32H5 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. + +config STM32H5_USART_SINGLEWIRE + bool "Single Wire Support" + default n + depends on STM32H5_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32H5 serial driver. + +config STM32H5_USART_INVERT + bool "Signal Invert Support" + default n + depends on STM32H5_USART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the STM32H5 serial driver. + +config STM32H5_USART_SWAP + bool "Swap RX/TX pins support" + default n + depends on STM32H5_USART + ---help--- + Enable RX/TX pin swapping support. The option enables support for the + TIOCSSWAP ioctl in the STM32H5 serial driver. + +if PM + +config STM32H5_PM_SERIAL_ACTIVITY + int "PM serial activity" + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +endif +endif # STM32H5_SERIALDRIVER + +endmenu # U[S]ART Configuration + +menu "SPI Configuration" + depends on STM32H5_SPI + +config STM32H5_SPI_INTERRUPTS + bool "Interrupt driver SPI" + default n + ---help--- + Select to enable interrupt driven SPI support. Non-interrupt-driven, + poll-waiting is recommended if the interrupt rate would be to high in + the interrupt driven case. + +config STM32H5_SPI_DMA + bool "SPI DMA" + default n + ---help--- + Use DMA to improve SPI transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT. + +endmenu + +menu "I2C Configuration" + depends on STM32H5_I2C + +config STM32H5_I2C_DYNTIMEO + bool "Use dynamic timeouts" + default n + depends on STM32H5_I2C + +config STM32H5_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + default 500 + depends on STM32H5_I2C_DYNTIMEO + +config STM32H5_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + default 1000 + depends on STM32H5_I2C_DYNTIMEO + +config STM32H5_I2CTIMEOSEC + int "Timeout seconds" + default 0 + depends on STM32H5_I2C + +config STM32H5_I2CTIMEOMS + int "Timeout Milliseconds" + default 500 + depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO + +config STM32H5_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + default 500 + depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO + +endmenu + +menu "SD/MMC Configuration" + depends on STM32H5_SDMMC + +config STM32H5_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO + default n + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +config STM32H5_SDMMC_DMA + bool "Support DMA data transfers" + default n + select SDIO_DMA + depends on STM32H5_DMA + ---help--- + Support DMA data transfers. + +menu "SDMMC1 Configuration" + depends on STM32H5_SDMMC1 + +config STM32H5_SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + default 0x00001000 + ---help--- + Select SDMMC1 DMA priority. + + Options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +endmenu # SDMMC1 Configuration +endmenu # SD/MMC Configuration + +menu "CAN driver configuration" + depends on STM32H5_CAN1 || STM32H5_CAN2 + +config STM32H5_CAN1_BAUD + int "CAN1 BAUD" + default 250000 + depends on STM32H5_CAN1 + ---help--- + CAN1 BAUD rate. Required if CONFIG_STM32H5_CAN1 is defined. + +config STM32H5_CAN2_BAUD + int "CAN2 BAUD" + default 250000 + depends on STM32H5_CAN2 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32H5_CAN2 is defined. + +config STM32H5_CAN_TSEG1 + int "TSEG1 quanta" + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config STM32H5_CAN_TSEG2 + int "TSEG2 quanta" + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config STM32H5_CAN_REGDEBUG + bool "CAN Register level debug" + depends on DEBUG_CAN_INFO + default n + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +endmenu + +menu "QEncoder Driver" + depends on SENSORS_QENCODER + depends on STM32H5_TIM1 || STM32H5_TIM2 || STM32H5_TIM3 || STM32H5_TIM4 || STM32H5_TIM5 || STM32H5_TIM8 + +config STM32H5_TIM1_QE + bool "TIM1" + default n + depends on STM32H5_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +if STM32H5_TIM1_QE + +config STM32H5_TIM1_QEPSC + int "TIM1 pulse prescaler" + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM1." (CONFIG_TIM1_QECLKOUT). + +endif + +config STM32H5_TIM2_QE + bool "TIM2" + default n + depends on STM32H5_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +if STM32H5_TIM2_QE + +config STM32H5_TIM2_QEPSC + int "TIM2 pulse prescaler" + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM2." (CONFIG_TIM2_QECLKOUT). + +endif + +config STM32H5_TIM3_QE + bool "TIM3" + default n + depends on STM32H5_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +if STM32H5_TIM3_QE + +config STM32H5_TIM3_QEPSC + int "TIM3 pulse prescaler" + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM3." (CONFIG_TIM3_QECLKOUT). + +endif + +config STM32H5_TIM4_QE + bool "TIM4" + default n + depends on STM32H5_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +if STM32H5_TIM4_QE + +config STM32H5_TIM4_QEPSC + int "TIM4 pulse prescaler" + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM4." (CONFIG_TIM4_QECLKOUT). + +endif + +config STM32H5_TIM5_QE + bool "TIM5" + default n + depends on STM32H5_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +if STM32H5_TIM5_QE + +config STM32H5_TIM5_QEPSC + int "TIM5 pulse prescaler" + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM5." (CONFIG_TIM5_QECLKOUT). + +endif + +config STM32H5_TIM8_QE + bool "TIM8" + default n + depends on STM32H5_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +if STM32H5_TIM8_QE + +config STM32H5_TIM8_QEPSC + int "TIM8 pulse prescaler" + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM8." (CONFIG_TIM8_QECLKOUT). + +endif + +config STM32H5_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + default y + +choice + depends on STM32H5_QENCODER_FILTER + prompt "Input channel sampling frequency" + default STM32H5_QENCODER_SAMPLE_FDTS_4 + +config STM32H5_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32H5_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32H5_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32H5_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32H5_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32H5_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32H5_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice + +choice + depends on STM32H5_QENCODER_FILTER + prompt "Input channel event count" + default STM32H5_QENCODER_SAMPLE_EVENT_6 + +config STM32H5_QENCODER_SAMPLE_EVENT_1 + depends on STM32H5_QENCODER_SAMPLE_FDTS + bool "1" + +config STM32H5_QENCODER_SAMPLE_EVENT_2 + depends on STM32H5_QENCODER_SAMPLE_CKINT + bool "2" + +config STM32H5_QENCODER_SAMPLE_EVENT_4 + depends on STM32H5_QENCODER_SAMPLE_CKINT + bool "4" + +config STM32H5_QENCODER_SAMPLE_EVENT_5 + depends on STM32H5_QENCODER_SAMPLE_FDTS_16 || STM32H5_QENCODER_SAMPLE_FDTS_32 + bool "5" + +config STM32H5_QENCODER_SAMPLE_EVENT_6 + depends on !STM32H5_QENCODER_SAMPLE_FDTS && !STM32H5_QENCODER_SAMPLE_CKINT + bool "6" + +config STM32H5_QENCODER_SAMPLE_EVENT_8 + depends on !STM32H5_QENCODER_SAMPLE_FDTS + bool "8" + +endchoice + +endmenu + +menu "SAI Configuration" + depends on STM32H5_SAI + +choice + prompt "Operation mode" + default STM32H5_SAI_DMA + ---help--- + Select the operation mode the SAI driver should use. + +config STM32H5_SAI_POLLING + bool "Polling" + ---help--- + The SAI registers are polled for events. + +config STM32H5_SAI_INTERRUPTS + bool "Interrupt" + ---help--- + Select to enable interrupt driven SAI support. + +config STM32H5_SAI_DMA + bool "DMA" + ---help--- + Use DMA to improve SAI transfer performance. + +endchoice # Operation mode + +choice + prompt "SAI1 synchronization enable" + default STM32H5_SAI1_BOTH_ASYNC + depends on STM32H5_SAI1_A && STM32H5_SAI1_B + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32H5_SAI1_BOTH_ASYNC + bool "Both asynchronous" + +config STM32H5_SAI1_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32H5_SAI1_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI1 synchronization enable + +choice + prompt "SAI2 synchronization enable" + default STM32H5_SAI2_BOTH_ASYNC + depends on STM32H5_SAI2_A && STM32H5_SAI2_B + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32H5_SAI2_BOTH_ASYNC + bool "Both asynchronous" + +config STM32H5_SAI2_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32H5_SAI2_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI2 synchronization enable + +endmenu + +endif # ARCH_CHIP_STM32H5 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs new file mode 100644 index 0000000000000..e4132069560c5 --- /dev/null +++ b/arch/arm/src/stm32h5/Make.defs @@ -0,0 +1,63 @@ +############################################################################## +# arch/arm/src/stm32h5/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +# The start-up, "head", file. Only common vectors are support so there +# isn't one. + +HEAD_ASRC = + +# Common ARM and Cortex-M4 files (copied from stm32/Make.defs) + +include armv8-m/Make.defs + +# Required STM32H5 files + +CHIP_ASRCS = +#CHIP_CSRCS = stm32h5_allocateheap.c stm32h5_exti_gpio.c stm32h5_gpio.c +#CHIP_CSRCS += stm32h5_irq.c stm32h5_lowputc.c stm32h5_rcc.c +#CHIP_CSRCS += stm32h5_serial.c stm32h5_start.c stm32h5_waste.c stm32h5_uid.c +#CHIP_CSRCS += stm32h5_spi.c stm32h5_lse.c stm32h5_lsi.c stm32h5_hsi48.c +#CHIP_CSRCS += stm32h5_pwr.c stm32h5_tim.c stm32h5_flash.c stm32h5_timerisr.c +CHIP_CSRCS = stm32h5_allocateheap.c stm32h5_gpio.c +CHIP_CSRCS += stm32h5_irq.c stm32h5_lowputc.c stm32h5_rcc.c +CHIP_CSRCS += stm32h5_serial.c stm32h5_start.c stm32h5_waste.c +CHIP_CSRCS += stm32h5_pwr.c stm32h5_timerisr.c +CHIP_CSRCS += stm32h5_lse.c stm32h5_lsi.c +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32h5_idle.c +endif + +ifeq ($(CONFIG_TIMER),y) +CHIP_CSRCS += stm32h5_tim_lowerhalf.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32h5_userspace.c stm32h5_mpuinit.c +endif + +#ifeq ($(CONFIG_DEBUG_FEATURES),y) +#CHIP_CSRCS += stm32h5_dumpgpio.c +#endif + +# Required chip type specific files + +ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y) +CHIP_CSRCS += stm32h56x_7x_rcc.c +endif diff --git a/arch/arm/src/stm32h5/chip.h b/arch/arm/src/stm32h5/chip.h new file mode 100644 index 0000000000000..2f4e03cc051a4 --- /dev/null +++ b/arch/arm/src/stm32h5/chip.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_CHIP_H +#define __ARCH_ARM_SRC_STM32H5_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. Other chip hardware + * files should then include this file for the proper setup. + */ + +#include +#include +#include "hardware/stm32h5_pinmap.h" +#include "hardware/stm32h5_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If the common ARMv8-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported + * external interrupts which, for this architecture, is provided in the + * arch/stm32h5/chip.h header file. + */ + +#define ARMV8M_PERIPHERAL_INTERRUPTS STM32H5_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32H5_CHIP_H */ diff --git a/arch/arm/src/stm32h5/hardware/review_list.txt b/arch/arm/src/stm32h5/hardware/review_list.txt new file mode 100644 index 0000000000000..026fa037988fa --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/review_list.txt @@ -0,0 +1,38 @@ +# File for Tracking which files have been edited and reviewed + +# Todo +stm32h562xx_adc.h +stm32h562xx_crs.h +stm32h562xx_dac.h +stm32h562xx_dbgmcu.h +stm32h562xx_exti.h +stm32h562xx_fdcan.h +stm32h562xx_flash.h +stm32h562xx_gpio.h +stm32h562xx_i2c.h +stm32h562xx_lptim.h +stm32h562xx_memorymap.h +stm32h562xx_pinmap.h +stm32h562xx_pinmap_legacy.h +stm32h562xx_pwr.h +stm32h562xx_qspi.h +stm32h562xx_rcc.h +stm32h562xx_rng.h +stm32h562xx_rtcc.h +stm32h562xx_sai.h +stm32h562xx_sdmmc.h +stm32h562xx_spi.h +stm32h562xx_syscfg.h +stm32h562xx_tim.h +stm32h562xx_uart.h +stm32h562xx_usbdev.h +stm32h562xx_wdg.h +stm32h5_pinmap.h +stm32h5_syscfg.h +stm32h7x3xx_spi.h + +# Edited + +# Reviewed + + diff --git a/arch/arm/src/stm32h5/hardware/stm32h562xx_dbgmcu.h b/arch/arm/src/stm32h5/hardware/stm32h562xx_dbgmcu.h new file mode 100644 index 0000000000000..c188c4e556ce5 --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h562xx_dbgmcu.h @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h562xx_dbgmcu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XX_DBGMCU_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XX_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +#define STM32_DBGMCU_IDCODE 0xe0044000 /* MCU identifier */ +#define STM32_DBGMCU_CR 0xe0044004 /* MCU debug */ +#define STM32_DBGMCU_APB1L_FZ 0xe0044008 /* Debug MCU APB1L freeze register */ +#define STM32_DBGMCU_APB1H_FZ 0xe004400c /* Debug MCU APB1H freeze register */ +#define STM32_DBGMCU_APB2_FZ 0xe0044010 /* Debug MCU APB2 freeze register */ +#define STM32_DBGMCU_APB3_FZ 0xe0044014 /* Debug MCU APB3 freeze register */ +#define STM32_DBGMCU_AHB1_FZ 0xe0044020 /* Debug MCU AHB1 freeze register */ +#define STM32_DBGMCU_SR 0xe00440fc /* Debug MCU Status Register */ +#define STM32_DBGMCU_DBG_AUTH_HOST 0xe0044100 /* Debug MCU Authorization Host Register */ +#define STM32_DBGMCU_DBG_AUTH_DEVICE 0xe0044104 /* Debug MCU Authorization Device Register */ +#define STM32_DBGMCU_DBG_AUTH_ACK 0xe0044108 /* Debug MCU Authorization Acknowledge Register */ +#define STM32_DBGMCU_PIDR4 0xe0044fd0 /* Debug MCU CoreSight Peripheral Identity Register 4 */ +#define STM32_DBGMCU_PIDR0 0xe0044fe0 /* Debug MCU CoreSight Peripheral Identity Register 0 */ +#define STM32_DBGMCU_PIDR1 0xe0044fe4 /* Debug MCU CoreSight Peripheral Identity Register 1 */ +#define STM32_DBGMCU_PIDR2 0xe0044fe8 /* Debug MCU CoreSight Peripheral Identity Register 2 */ +#define STM32_DBGMCU_PIDR3 0xe0044fec /* Debug MCU CoreSight Peripheral Identity Register 3 */ +#define STM32_DBGMCU_CIDR0 0xe0044ff0 /* Debug MCU CoreSight Component Identity Register 0 */ +#define STM32_DBGMCU_CIDR1 0xe0044ff4 /* Debug MCU CoreSight Component Identity Register 1 */ +#define STM32_DBGMCU_CIDR2 0xe0044ff8 /* Debug MCU CoreSight Component Identity Register 2 */ +#define STM32_DBGMCU_CIDR3 0xe0044ffc /* Debug MCU CoreSight Component Identity Register 3 */ + +/* Register Bitfield Definitions ********************************************/ + +/* MCU identifier */ + +#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */ +#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT) +#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */ +#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT) + +/* MCU debug */ + +#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Allows debug in Stop mode */ +#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Allows debug in Standby mode */ +#define DBGMCU_CR_TRACEIOEN (1 << 4) /* Bit 4: Trace pin enable */ +#define DBGMCU_CR_TRACEEN (1 << 5) /* Bit 5: Trace port and clock enable */ +#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */ +#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT) +#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */ +#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */ +#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ +#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ +#define DBGMCU_CR_DCRT (1 << 16) /* Bit 16: Debug credentials reset type */ + +/* Debug MCU APB1L freeze register */ + +#define DBGMCU_APB1L_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +#define DBGMCU_APB1L_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +#define DBGMCU_APB1L_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ +#define DBGMCU_APB1L_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */ +#define DBGMCU_APB1L_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ +#define DBGMCU_APB1L_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ +#define DBGMCU_APB1L_TIM12STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */ +#define DBGMCU_APB1L_TIM13STOP (1 << 7) /* Bit 6: TIM12 stopped when core is halted */ +#define DBGMCU_APB1L_TIM14STOP (1 << 8) /* Bit 6: TIM12 stopped when core is halted */ +#define DBGMCU_APB1L_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ +#define DBGMCU_APB1L_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ +#define DBGMCU_APB1L_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1L_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1L_I3C1STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */ + +/* Debug MCU APB1H freeze register */ + +#define DBGMCU_APB1H_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopped when core is halted */ + +/* Debug MCU APB2 freeze register */ + +#define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */ +#define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 13: TIM8 stopped when core is halted */ +#define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */ +#define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */ +#define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */ + +/* Debug MCU APB3 freeze register */ + +#define DBGMCU_APB3_I2C3STOP (1 << 10) /* Bit 10: I2C3 SMBUS stop in debug */ +#define DBGMCU_APB3_I2C4STOP (1 << 11) /* Bit 11: I2C4 SMBUS stop in debug */ +#define DBGMCU_APB3_LPTIM1STOP (1 << 17) /* Bit 17: LPTIM1 stopped in debug */ +#define DBGMCU_APB3_LPTIM3STOP (1 << 18) /* Bit 18: LPTIM3 stopped in debug */ +#define DBGMCU_APB3_LPTIM4STOP (1 << 19) /* Bit 19: LPTIM4 stopped in debug */ +#define DBGMCU_APB3_LPTIM5STOP (1 << 20) /* Bit 20: LPTIM5 stopped in debug */ +#define DBGMCU_APB3_LPTIM6STOP (1 << 21) /* Bit 21: LPTIM6 stopped in debug */ +#define DBGMCU_APB3_DBG_RTCSTOP (1 << 30) /* Bit 30: RTC stopped in debug */ + +/* Debug MCU AHB1 freeze register */ + +#define DBGMCU_AHB1_GPDMA1_0_STOP (1 << 0) /* Bit 0: GPDMA1 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA1_1_STOP (1 << 1) /* Bit 1: GPDMA1 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA1_2_STOP (1 << 2) /* Bit 2: GPDMA1 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA1_3_STOP (1 << 3) /* Bit 3: GPDMA1 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA1_4_STOP (1 << 4) /* Bit 4: GPDMA1 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA1_5_STOP (1 << 5) /* Bit 5: GPDMA1 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA1_6_STOP (1 << 6) /* Bit 6: GPDMA1 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA1_7_STOP (1 << 7) /* Bit 7: GPDMA1 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA2_0_STOP (1 << 16) /* Bit 16: GPDMA2 Channel 0 stop in debug */ +#define DBGMCU_AHB1_GPDMA2_1_STOP (1 << 17) /* Bit 17: GPDMA2 Channel 1 stop in debug */ +#define DBGMCU_AHB1_GPDMA2_2_STOP (1 << 18) /* Bit 18: GPDMA2 Channel 2 stop in debug */ +#define DBGMCU_AHB1_GPDMA2_3_STOP (1 << 19) /* Bit 19: GPDMA2 Channel 3 stop in debug */ +#define DBGMCU_AHB1_GPDMA2_4_STOP (1 << 20) /* Bit 20: GPDMA2 Channel 4 stop in debug */ +#define DBGMCU_AHB1_GPDMA2_5_STOP (1 << 21) /* Bit 21: GPDMA2 Channel 5 stop in debug */ +#define DBGMCU_AHB1_GPDMA2_6_STOP (1 << 22) /* Bit 22: GPDMA2 Channel 6 stop in debug */ +#define DBGMCU_AHB1_GPDMA2_7_STOP (1 << 23) /* Bit 23: GPDMA2 Channel 7 stop in debug */ + +/* Debug MCU Status Register */ + +#define DBGMCU_SR_AP_PRESENT_SHIFT (0) +#define DBGMCU_SR_AP_PRESENT_MASK (0xffff << DBGMCU_SR_AP_PRESENT_SHIFT) +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_MASK +#define DBGMCU_SR_AP_ENABLED_SHIFT (16) +#define DBGMCU_SR_AP_ENABLED_MASK (0xffff << DBGMCU_SR_AP_ENABLED_SHIFT) +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_MASK + +/* Debug MCU Authorization Acknowledge Register */ + +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_SHIFT (0) +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_MASK (1 << DBGMCU_DBG_AUTH_ACK_HOST_ACK_SHIFT) +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_MASK +#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_SHIFT (1) +#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_MASK (1 << DBGMCU_DBG_AUTH_ACK_DEV_ACK_SHIFT) +#define DBGMCU_DBG_AUTH_ACK_DEV_ACK DBGMCU_DBG_AUTH_ACK_DEV_ACK_MASK + +/* Debug MCU CoreSight Peripheral Identity Register 4 */ + +#define DBGMCU_PIDR4_JEP106CON_SHIFT (0) +#define DBGMCU_PIDR4_JEP106CON_MASK (0xf << DBGMCU_PIDR4_JEP106CON_SHIFT) +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_MASK +#define DBGMCU_PIDR4_SIZE_SHIFT (0) +#define DBGMCU_PIDR4_SIZE_MASK (0xf << DBGMCU_PIDR4_SIZE_SHIFT) +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_MASK + + +/* Debug MCU CoreSight Peripheral Identity Register 0 */ + +#define DBGMCU_PIDR0_PARTNUM_SHIFT (0) +#define DBGMCU_PIDR0_PARTNUM_MASK (0xff << DBGMCU_PIDR0_PARTNUM_SHIFT) +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_MASK + +/* Debug MCU CoreSight Peripheral Identity Register 1 */ + +#define DBGMCU_PIDR1_PARTNUM_SHIFT (0) +#define DBGMCU_PIDR1_PARTNUM_MASK (0xf << DBGMCU_PIDR1_PARTNUM_SHIFT) +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_MASK +#define DBGMCU_PIDR1_JEP106ID_SHIFT (4) +#define DBGMCU_PIDR1_JEP106ID_MASK (0xf << DBGMCU_PIDR1_JEP106ID_SHIFT) +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_MASK + +/* Debug MCU CoreSight Peripheral Identity Register 2 */ + +#define DBGMCU_PIDR2_JEP106ID_SHIFT (0) +#define DBGMCU_PIDR2_JEP106ID_MASK (0x7 << DBGMCU_PIDR2_JEP106ID_SHIFT) +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_MASK +#define DBGMCU_PIDR2_JEDEC_SHIFT (3) +#define DBGMCU_PIDR2_JEDEC_MASK (0x1 << DBGMCU_PIDR2_JEDEC_SHIFT) +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_MASK +#define DBGMCU_PIDR2_REVISION_SHIFT (4) +#define DBGMCU_PIDR2_REVISION_MASK (0xf << DBGMCU_PIDR2_REVISION_SHIFT) +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_MASK + +/* Debug MCU CoreSight Peripheral Identity Register 3 */ + +#define DBGMCU_PIDR3_CMOD_SHIFT (0) +#define DBGMCU_PIDR3_CMOD_MASK (0xf << DBGMCU_PIDR3_CMOD_SHIFT) +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_MASK +#define DBGMCU_PIDR3_REVAND_SHIFT (4) +#define DBGMCU_PIDR3_REVAND_MASK (0xf << DBGMCU_PIDR3_REVAND_SHIFT) +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_MASK + + +/* Debug MCU CoreSight Component Identity Register 0 */ + +#define DBGMCU_CIDR0_PREAMBLE_SHIFT (0) +#define DBGMCU_CIDR0_PREAMBLE_MASK (0xff << DBGMCU_CIDR0_PREAMBLE_SHIFT) +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_MASK + +/* Debug MCU CoreSight Component Identity Register 1 */ + +#define DBGMCU_CIDR1_PREAMBLE_SHIFT (0) +#define DBGMCU_CIDR1_PREAMBLE_MASK (0xf << DBGMCU_CIDR1_PREAMBLE_SHIFT) +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_MASK +#define DBGMCU_CIDR1_CLASS_SHIFT (4) +#define DBGMCU_CIDR1_CLASS_MASK (0xf << DBGMCU_CIDR1_CLASS_SHIFT) +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_MASK + +/* Debug MCU CoreSight Component Identity Register 2 */ + +#define DBGMCU_CIDR2_PREAMBLE_SHIFT (0) +#define DBGMCU_CIDR2_PREAMBLE_MASK (0xff << DBGMCU_CIDR2_PREAMBLE_SHIFT) +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_MASK + +/* Debug MCU CoreSight Component Identity Register 3 */ + +#define DBGMCU_CIDR3_PREAMBLE_SHIFT (0) +#define DBGMCU_CIDR3_PREAMBLE_MASK (0xff << DBGMCU_CIDR3_PREAMBLE_SHIFT) +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_MASK + + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XXDBGMCU_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h new file mode 100644 index 0000000000000..988af57310058 --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h @@ -0,0 +1,661 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h562xx_pinmap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XX_PINMAP_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XX_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Alternate Pin Functions. All members of the STM32H552xx and STM32H562xx + * families share the same pin multiplexing (although they may differ in the + * pins physically available). See DS12736, Table 22 "Alternate Function AF0 + * to AF7" and Table 23 "Alternate Function AF8 to AF15". + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if FDCAN1_RX connects via PA11 on some board, then the following + * definitions should appear inthe board.h header file for that board: + * + * #define GPIO_FDCAN1_RX GPIO_FDCAN1_RX_1 + * + * The driver will then automatically configure PA11 as the FDCAN1 RX pin. + */ + +/* ADC */ + +/* TODO +#define GPIO_ADC12_IN1_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC12_IN2_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC12_IN3_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC12_IN4_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC12_IN5_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC12_IN6_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC12_IN7_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC12_IN8_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC12_IN9_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC12_IN10_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC12_IN11_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC12_IN12_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC12_IN13_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC12_IN14_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ADC12_IN15_0 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC12_IN16_0 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +*/ + +/* FDCAN */ +/* TODO +#define GPIO_FDCAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN11) +#define GPIO_FDCAN1_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN8) +#define GPIO_FDCAN1_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN0) +#define GPIO_FDCAN1_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN12) +#define GPIO_FDCAN1_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN9) +#define GPIO_FDCAN1_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN1) +*/ + +/* Clocks outputs */ + +#define GPIO_MCO_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN8) + + +/* DAC */ +/* TODO +#define GPIO_DAC1_OUT_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC1_OUT_2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +*/ + + +/* I2C */ +/* TODO +#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN13) +#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN14) +#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN1) +#define GPIO_I2C1_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN14) +#define GPIO_I2C1_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTG|GPIO_PIN15) + +#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11) +#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN14) +#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0) +#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN13) +#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1) +#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN12) +#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTF|GPIO_PIN2) + +#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN4) +#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1) +#define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN8) +#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN7) +#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0) +#define GPIO_I2C3_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN7) +#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN2) +#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTG|GPIO_PIN6) + +#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF5|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF3|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11) +#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13) +#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15) +#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF5|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF3|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12) +#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14) +#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN14) +#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN11) +#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTF|GPIO_PIN14) +*/ + +/* JTAG */ + +#define GPIO_JTCK_SWCLK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_JTDI_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) +#define GPIO_JTDO_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_JTMS_SWDAT_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) +#define GPIO_JTRST_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) + +/* OCTOSPI */ +/* TODO +#define GPIO_OSPI_NCS_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN4) +#define GPIO_OSPI_NCS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN11) +#define GPIO_OSPI_NCS_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN2) +#define GPIO_OSPI_NCS_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11) +#define GPIO_OSPI_NCS_5 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11) +#define GPIO_OSPI_NCLK_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN5) +#define GPIO_OSPI_NCLK_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTF|GPIO_PIN11) +#define GPIO_OSPI_NCLK_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12) +#define GPIO_OSPI_NCLK_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN9) +#define GPIO_OSPI_CLK_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTF|GPIO_PIN10) +#define GPIO_OSPI_CLK_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3) +#define GPIO_OSPI_CLK_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10) +#define GPIO_OSPI_CLK_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10) +#define GPIO_OSPI_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0) +#define GPIO_OSPI_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12) +#define GPIO_OSPI_IO0_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8) +#define GPIO_OSPI_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1) +#define GPIO_OSPI_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13) +#define GPIO_OSPI_IO1_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9) +#define GPIO_OSPI_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14) +#define GPIO_OSPI_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN7) +#define GPIO_OSPI_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6) +#define GPIO_OSPI_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15) +#define GPIO_OSPI_IO3_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN6) +#define GPIO_OSPI_IO4_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7) +#define GPIO_OSPI_IO4_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1) +#define GPIO_OSPI_IO4_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN4) +#define GPIO_OSPI_IO5_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN11) +#define GPIO_OSPI_IO5_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2) +#define GPIO_OSPI_IO5_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN5) +#define GPIO_OSPI_IO6_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3) +#define GPIO_OSPI_IO6_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN6) +#define GPIO_OSPI_IO7_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN0) +#define GPIO_OSPI_IO7_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4) +#define GPIO_OSPI_IO7_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN7) +#define GPIO_OSPI_DQS_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN3) +#define GPIO_OSPI_DQS_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN6) +#define GPIO_OSPI_DQS_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1) +#define GPIO_OSPI_DQS_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2) +*/ + +/* RTC */ +/* TODO +#define GPIO_RTC_REFIN_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN15) +*/ + +/* SAI */ +/* TODO +#define GPIO_SAI1_EXTCLK_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN0) +#define GPIO_SAI1_EXTCLK_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN0) + +#define GPIO_SAI1_D1_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI1_D1_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN10) +#define GPIO_SAI1_D1_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN3) +#define GPIO_SAI1_D1_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SAI1_D1_5 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI1_D2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN4) +#define GPIO_SAI1_D2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SAI1_D2_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN4) +#define GPIO_SAI1_D3_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN10) +#define GPIO_SAI1_D3_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_SAI1_CK1_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN3) +#define GPIO_SAI1_CK1_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SAI1_CK1_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN2) +#define GPIO_SAI1_CK1_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN7) +#define GPIO_SAI1_CK2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN8) +#define GPIO_SAI1_CK2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN5) + +#define GPIO_SAI1_FS_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9) +#define GPIO_SAI1_FS_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SAI1_FS_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4) +#define GPIO_SAI1_SCK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN8) +#define GPIO_SAI1_SCK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN10) +#define GPIO_SAI1_SCK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5) +#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10) +#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN1) +#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN3) +#define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SAI1_SD_A_5 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN3) +#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SAI1_MCLK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN2) +#define GPIO_SAI1_MCLK_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN7) + +#define GPIO_SAI1_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SAI1_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN14) +#define GPIO_SAI1_FS_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6) +#define GPIO_SAI1_FS_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN9) +#define GPIO_SAI1_FS_B_5 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN9) +#define GPIO_SAI1_SCK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SAI1_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN8) +#define GPIO_SAI1_SCK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN8) +#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN13) +#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN3) +#define GPIO_SAI1_SD_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN7) +#define GPIO_SAI1_SD_B_5 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN6) +#define GPIO_SAI1_MCLK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SAI1_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN10) +#define GPIO_SAI1_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN7) + +#define GPIO_SAI2_EXTCLK_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN2) +#define GPIO_SAI2_EXTCLK_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN9) + +#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN12) +#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN0) +#define GPIO_SAI2_FS_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN12) +#define GPIO_SAI2_FS_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN10) +#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN13) +#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN11) +#define GPIO_SAI2_SCK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11) +#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SAI2_MCLK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN9) +#define GPIO_SAI2_MCLK_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11) + +#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN3) +#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10) +#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN2) +#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN5) +#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7) +#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN4) +*/ + +/* SDIO */ +/* TODO +#define GPIO_SDMMC1_CKIN_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SDMMC1_CDIR_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SDMMC1_D0DIR_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SDMMC1_D123DIR_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN7) + +#define GPIO_SDMMC1_D0_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN8) +#define GPIO_SDMMC1_D1_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN9) +#define GPIO_SDMMC1_D2_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN10) +#define GPIO_SDMMC1_D3_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SDMMC1_D4_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SDMMC1_D5_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SDMMC1_D5_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN0) +#define GPIO_SDMMC1_D6_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SDMMC1_D7_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN7) +#define GPIO_SDMMC1_CK_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SDMMC1_CMD_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN2) +*/ + +/* SPI */ +/* TODO +#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN0) +#define GPIO_SPI1_NSS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN12) +#define GPIO_SPI1_NSS_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN5) +#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN1) +#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN5) +#define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI1_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SPI1_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN2) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN12) +#define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI1_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN15) +#define GPIO_SPI1_MOSI_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN4) +#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN11) +#define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI1_MISO_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SPI1_MISO_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN3) + +#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN12) +#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN0) +#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN10) +#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13) +#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN1) +#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN3) +#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN1) +#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN3) +#define GPIO_SPI2_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN4) +#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN2) +#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3) + +#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI3_NSS_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN12) +#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN10) +#define GPIO_SPI3_SCK_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SPI3_MOSI_4 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN11) +#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SPI3_MISO_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN10) +*/ + +/* Timers */ +/* TODO +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN10) +#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12) +#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN12) +#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN12) +#define GPIO_TIM1_BKIN_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN15) +#define GPIO_TIM1_BKIN_5 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN15) +#define GPIO_TIM1_BKIN_6 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM1_BKIN2_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_BKIN2_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_BKIN2_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_BKIN2_4 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN7) + +#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN0) + +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_4 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_4 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4IN_3 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM3_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTD|GPIO_PIN2) +#define GPIO_TIM3_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTE|GPIO_PIN2) + +#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTE|GPIO_PIN0) + +#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7) +#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) +#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8) +#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8) +#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM5_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN6) + +#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM8_BKIN_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM8_BKIN_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM8_BKIN2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM8_BKIN2_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_BKIN2_3 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM8_BKIN2_4 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN0) + +#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM15_CH1N_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_TIM15_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM15_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM15_CH1IN_4 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN10) +#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM15_CH1OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10) +#define GPIO_TIM15_CH2IN_4 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN11) +#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10) +#define GPIO_TIM15_CH2OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) +#define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN12) + +#define GPIO_TIM16_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM16_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM16_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) +#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) +#define GPIO_TIM16_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN5) + +#define GPIO_TIM17_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM17_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1) +#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) +#define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN4) + +#define GPIO_LPTIM1_IN1_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN5) +#define GPIO_LPTIM1_IN1_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN0) +#define GPIO_LPTIM1_IN1_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN10) +#define GPIO_LPTIM1_IN2_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN7) +#define GPIO_LPTIM1_IN2_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN2) +#define GPIO_LPTIM1_IN2_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN11) +#define GPIO_LPTIM1_OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN14) +#define GPIO_LPTIM1_OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN2) +#define GPIO_LPTIM1_OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN1) +#define GPIO_LPTIM1_OUT_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN15) +#define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN6) +#define GPIO_LPTIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN3) +#define GPIO_LPTIM1_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN12) + +#define GPIO_LPTIM2_IN1_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN1) +#define GPIO_LPTIM2_IN1_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN0) +#define GPIO_LPTIM2_IN1_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN12) +#define GPIO_LPTIM2_OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN4) +#define GPIO_LPTIM2_OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN8) +#define GPIO_LPTIM2_OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN13) +#define GPIO_LPTIM2_ETR_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN5) +#define GPIO_LPTIM2_ETR_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN3) +#define GPIO_LPTIM2_ETR_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN11) + +#define GPIO_LPTIM3_IN1_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN13) +#define GPIO_LPTIM3_IN1_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN11) +#define GPIO_LPTIM3_IN1_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN3) +#define GPIO_LPTIM3_OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN10) +#define GPIO_LPTIM3_OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN3) +#define GPIO_LPTIM3_OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN5) +#define GPIO_LPTIM3_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN14) +#define GPIO_LPTIM3_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN10) +#define GPIO_LPTIM3_ETR_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN4) +*/ + + +/* Trace */ + +#define GPIO_TRACECK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2) +#define GPIO_TRACED0_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN1) +#define GPIO_TRACED0_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TRACED0_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TRACED1_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN10) +#define GPIO_TRACED1_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TRACED2_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTD|GPIO_PIN2) +#define GPIO_TRACED2_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TRACED3_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN12) +#define GPIO_TRACED3_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6) + +/* UARTs/USARTs */ + +/* +#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN9) +#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN6) +#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN10) +#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN7) +#define GPIO_USART1_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8) +#define GPIO_USART1_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN5) +#define GPIO_USART1_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11) +#define GPIO_USART1_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4) +#define GPIO_USART1_RTS_DE_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12) +#define GPIO_USART1_RTS_DE_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN3) + +#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN2) +#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN5) +#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN3) +#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN15) +#define GPIO_USART2_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN6) +#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4) +#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7) +#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0) +#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3) +#define GPIO_USART2_RTS_DE_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1) +#define GPIO_USART2_RTS_DE_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4) +*/ + +#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN10) +#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN4) +#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN10) +#define GPIO_USART3_TX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN8) + +#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN11) +#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN5) +#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN11) +#define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN9) + +#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN0) +#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12) +#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12) +#define GPIO_USART3_CK_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10) + +#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN6) +#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13) +#define GPIO_USART3_CTS_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11) + +#define GPIO_USART3_RTS_DE_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN15) +#define GPIO_USART3_RTS_DE_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN1) +#define GPIO_USART3_RTS_DE_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14) +#define GPIO_USART3_RTS_DE_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN2) +#define GPIO_USART3_RTS_DE_5 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12) + +/* +#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN0) +#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN10) +#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN1) +#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN11) +#define GPIO_UART4_CTS_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN7) +#define GPIO_UART4_RTS_DE_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_UART5_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN12) +#define GPIO_UART5_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN2) +#define GPIO_UART5_CTS_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN5) +#define GPIO_UART5_RTS_DE_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN4) +*/ + +#define GPIO_LPUART1_TX_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN9) +#define GPIO_LPUART1_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN6) +#define GPIO_LPUART1_RX_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN10) +#define GPIO_LPUART1_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN7) +#define GPIO_LPUART1_CTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN11) +#define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN12) + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XX_PINMAP_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_crs.h b/arch/arm/src/stm32h5/hardware/stm32h5_crs.h new file mode 100644 index 0000000000000..41478d590809b --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_crs.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/hardware/stm32l4_crs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_CRS_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_CRS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32H5_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32H5_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32H5_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32H5_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ + +/* Register Addresses *******************************************************/ + +#define STM32H5_CRS_CR (STM32H5_CRS_BASE + STM32H5_CRS_CR_OFFSET) +#define STM32H5_CRS_CFGR (STM32H5_CRS_BASE + STM32H5_CRS_CFGR_OFFSET) +#define STM32H5_CRS_ISR (STM32H5_CRS_BASE + STM32H5_CRS_ISR_OFFSET) +#define STM32H5_CRS_ICR (STM32H5_CRS_BASE + STM32H5_CRS_ICR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* CRS control register */ + +#define CRS_CR_SYNCOKIE (1 << 0) /* Bit 0: SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE (1 << 1) /* Bit 1: SYNC warning interrupt enable */ +#define CRS_CR_ERRIE (1 << 2) /* Bit 2: Synchronization or Trimming error interrupt enabled */ +#define CRS_CR_ESYNCIE (1 << 3) /* Bit 3: Expected SYNC interrupt enable */ +#define CRS_CR_CEN (1 << 5) /* Bit 5: Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN (1 << 6) /* Bit 6: Automatic trimming enabled */ +#define CRS_CR_SWSYNC (1 << 7) /* Bit 7: Generate software SYNC event */ +#define CRS_CR_TRIM_SHIFT 8 /* Bits 8-13: HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_MASK (0x3f << CRS_CR_TRIM_SHIFT) + +/* CRS configuration register */ + +#define CRS_CFGR_RELOAD_SHIFT 0 /* Bits 0-15: Counter reload value */ +#define CRS_CFGR_RELOAD_MASK (0xffff << CRS_CFGR_RELOAD_SHIFT) +#define CRS_CFGR_FELIM_SHIFT 16 /* Bits 16-23: Frequency error limit */ +#define CRS_CFGR_FELIM_MASK (0xff << CRS_CFGR_FELIM_SHIFT) +#define CRS_CFGR_SYNCDIV_SHIFT 24 /* Bits 24-26: SYNC divider */ +#define CRS_CFGR_SYNCDIV_MASK (7 << CRS_CFGR_SYNCDIV_SHIFT) +# define CRS_CFGR_SYNCDIV_d1 (0 << CRS_CFGR_SYNCDIV_SHIFT) /* Not divided */ +# define CRS_CFGR_SYNCDIV_d2 (1 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 2 */ +# define CRS_CFGR_SYNCDIV_d4 (2 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 4 */ +# define CRS_CFGR_SYNCDIV_d8 (3 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 8 */ +# define CRS_CFGR_SYNCDIV_d16 (4 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 16 */ +# define CRS_CFGR_SYNCDIV_d32 (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */ +# define CRS_CFGR_SYNCDIV_d64 (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */ +# define CRS_CFGR_SYNCDIV_d128 (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */ + +#define CRS_CFGR_SYNCSRC_SHIFT 28 /* Bits 28-29: SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_MASK (3 << CRS_CFGR_SYNCSRC_SHIFT) +# define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */ +# define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */ +# define CRS_CFGR_SYNCSRC_USBSOF (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */ + +#define CRS_CFGR_SYNCPOL (1 << 31) /* SYNC polarity selection */ + +/* CRS interrupt and status register */ + +#define CRS_ISR_SYNCOKF (1 << 0) /* Bit 0: SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF (1 << 1) /* Bit 1: SYNC warning flag */ +#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Errot flag */ +#define CRS_ISR_ESYNCF (1 << 3) /* Bit 3: Expected SYNC flag */ +#define CRS_ISR_SYNCERR (1 << 8) /* Bit 8: SYNC error */ +#define CRS_ISR_SYNCMISS (1 << 9) /* Bit 9: SYNC missed */ +#define CRS_ISR_TRIMOVF (1 << 10) /* Bit 10: Trimming overflow or underflow */ +#define CRS_ISR_FEDIR (1 << 15) /* Bit 15: Frequency error direction */ +#define CRS_ISR_FECAP_SHIFT 16 /* Bits 16-31: Frequency error capture */ +#define CRS_ISR_FECAP_MASK (0xffff << CRS_ISR_FECAP_SHIFT) + +/* CRS interrupt flag clear register */ + +#define CRS_ICR_SYNCOKC (1 << 0) /* Bit 0: SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC (1 << 1) /* Bit 1: SYNC warning clear flag */ +#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ +#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_CRS_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_flash.h b/arch/arm/src/stm32h5/hardware/stm32h5_flash.h new file mode 100644 index 0000000000000..b359c0b432610 --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_flash.h @@ -0,0 +1,350 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h5_flash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_FLASH_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Flash size is known from the chip selection: + * + * When CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32H5_FLASH_CONFIG_x selects the default FLASH size based on + * the chip part number. This value can be overridden with + * CONFIG_STM32H5_FLASH_OVERRIDE_x + * + * Parts STM32H552xC and STM32H562xC have 256Kb of FLASH + * Parts STM32H552xE and STM32H562xE have 512Kb of FLASH + * + * N.B. Only Single bank mode is supported + */ + +#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32H5_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32H5_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32H5_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32H5_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32H5_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32H5_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32H5_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32H5_FLASH_CONFIG_I) +# define CONFIG_STM32H5_FLASH_OVERRIDE_E +# warning "Flash size not defined defaulting to 512KiB (E)" +#endif + +/* Override of the Flash has been chosen */ + +#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32H5_FLASH_CONFIG_C +# undef CONFIG_STM32H5_FLASH_CONFIG_E +# if defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) +# define CONFIG_STM32H5_FLASH_CONFIG_C +# elif defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) +# define CONFIG_STM32H5_FLASH_CONFIG_E +# endif +#endif + +/* Define the valid configuration */ + +#if defined(CONFIG_STM32H5_FLASH_CONFIG_B) /* 128 kB */ +# define STM32H5_FLASH_NPAGES 32 +# define STM32H5_FLASH_PAGESIZE 4096 +#elif defined(CONFIG_STM32H5_FLASH_CONFIG_C) /* 256 kB */ +# define STM32H5_FLASH_NPAGES 64 +# define STM32H5_FLASH_PAGESIZE 4096 +#elif defined(CONFIG_STM32H5_FLASH_CONFIG_E) /* 512 kB */ +# define STM32H5_FLASH_NPAGES 128 +# define STM32H5_FLASH_PAGESIZE 4096 +#elif defined(CONFIG_STM32H5_FLASH_CONFIG_G) /* 1 MB */ +# define STM32H5_FLASH_NPAGES 256 +# define STM32H5_FLASH_PAGESIZE 4096 +#elif defined(CONFIG_STM32H5_FLASH_CONFIG_I) /* 2 MB */ +# define STM32H5_FLASH_NPAGES 512 +# define STM32H5_FLASH_PAGESIZE 4096 +#else +# error "unknown flash configuration!" +#endif + +#ifdef STM32H5_FLASH_PAGESIZE +# define STM32H5_FLASH_SIZE (STM32H5_FLASH_NPAGES * STM32H5_FLASH_PAGESIZE) +#endif + +/* Register Offsets *********************************************************/ + +#define STM32H5_FLASH_ACR_OFFSET 0x0000 +#define STM32H5_FLASH_NSKEYR_OFFSET 0x0004 +#define STM32H5_FLASH_SECKEYR_OFFSET 0x0008 +#define STM32H5_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32H5_FLASH_NSOBKKEYR_OFFSET 0x0010 +#define STM32H5_FLASH_SECOBKKEYR_OFFSET 0x0014 +#define STM32H5_FLASH_OPSR_OFFSET 0x0018 +#define STM32H5_FLASH_OPTCR_OFFSET 0x001c +#define STM32H5_FLASH_NSSR_OFFSET 0x0020 +#define STM32H5_FLASH_SECSR_OFFSET 0x0024 +#define STM32H5_FLASH_NSCR_OFFSET 0x0028 +#define STM32H5_FLASH_SECCR_OFFSET 0x002c +#define STM32H5_FLASH_NSCCR_OFFSET 0x0030 +#define STM32H5_FLASH_SECCCR_OFFSET 0x0034 +#define STM32H5_FLASH_PRIVCFGR_OFFSET 0x003c +#define STM32H5_FLASH_NSOBKCFGR_OFFSET 0x0040 +#define STM32H5_FLASH_SECOBKCFGR_OFFSET 0x0044 +#define STM32H5_FLASH_HDPEXTR_OFFSET 0x0048 +#define STM32H5_FLASH_OPTSR_CUR_OFFSET 0x0050 +#define STM32H5_FLASH_OPTSR_PRG_OFFSET 0x0054 +#define STM32H5_FLASH_NSEPOCHR_CUR_OFFSET 0x0060 +#define STM32H5_FLASH_NSEPOCHR_PRG_OFFSET 0x0064 +#define STM32H5_FLASH_SECEPOCHR_CUR_OFFSET 0x0068 +#define STM32H5_FLASH_SECEPOCHR_PRG_OFFSET 0x006c +#define STM32H5_FLASH_OPTSR2_CUR_OFFSET 0x0070 +#define STM32H5_FLASH_OPTSR2_PRG_OFFSET 0x0074 +#define STM32H5_FLASH_NSBOOTR_CUR_OFFSET 0x0080 +#define STM32H5_FLASH_NSBOOTR_PRG_OFFSET 0x0084 +#define STM32H5_FLASH_SECBOOTR_CUR_OFFSET 0x0088 +#define STM32H5_FLASH_SECBOOTR_PRG_OFFSET 0x008c +#define STM32H5_FLASH_OTBPBLR_CUR_OFFSET 0x0090 +#define STM32H5_FLASH_OTBPBLR_PRG_OFFSET 0x0094 +#define STM32H5_FLASH_SECBB1R_1_OFFSET 0x00a0 +#define STM32H5_FLASH_SECBB1R_2_OFFSET 0x00a4 +#define STM32H5_FLASH_SECBB1R_3_OFFSET 0x00a8 +#define STM32H5_FLASH_SECBB1R_4_OFFSET 0x00ac +#define STM32H5_FLASH_PRIVBB1R_1_OFFSET 0x00c0 +#define STM32H5_FLASH_PRIVBB1R_2_OFFSET 0x00c4 +#define STM32H5_FLASH_PRIVBB1R_3_OFFSET 0x00c8 +#define STM32H5_FLASH_PRIVBB1R_4_OFFSET 0x00cc +#define STM32H5_FLASH_SECWM1R_CUR_OFFSET 0x00e0 +#define STM32H5_FLASH_SECWM1R_PRG_OFFSET 0x00e4 +#define STM32H5_FLASH_WRP1R_CUR_OFFSET 0x00e8 +#define STM32H5_FLASH_WRP1R_PRG_OFFSET 0x00ec +#define STM32H5_FLASH_EDATA1R_CUR_OFFSET 0x00f0 +#define STM32H5_FLASH_EDATA1R_PRG_OFFSET 0x00f4 +#define STM32H5_FLASH_HDP1R_CUR_OFFSET 0x00f8 +#define STM32H5_FLASH_HDP1R_PRG_OFFSET 0x00fc +#define STM32H5_FLASH_ECCCORR_OFFSET 0x0100 +#define STM32H5_FLASH_ECCDETR_OFFSET 0x0104 +#define STM32H5_FLASH_ECCDR_OFFSET 0x0108 +#define STM32H5_FLASH_SECBB2R_1_OFFSET 0x01a0 +#define STM32H5_FLASH_SECBB2R_2_OFFSET 0x01a4 +#define STM32H5_FLASH_SECBB2R_3_OFFSET 0x01a8 +#define STM32H5_FLASH_SECBB2R_4_OFFSET 0x01ac +#define STM32H5_FLASH_PRIVBB2R_1_OFFSET 0x01c0 +#define STM32H5_FLASH_PRIVBB2R_2_OFFSET 0x01c4 +#define STM32H5_FLASH_PRIVBB2R_3_OFFSET 0x01c8 +#define STM32H5_FLASH_PRIVBB2R_4_OFFSET 0x01cc +#define STM32H5_FLASH_SECWM2R_CUR_OFFSET 0x01e0 +#define STM32H5_FLASH_SECWM2R_PRG_OFFSET 0x01e4 +#define STM32H5_FLASH_WRP2R_CUR_OFFSET 0x01e8 +#define STM32H5_FLASH_WRP2R_PRG_OFFSET 0x01ec +#define STM32H5_FLASH_EDATA2R_CUR_OFFSET 0x01f0 +#define STM32H5_FLASH_EDATA2R_PRG_OFFSET 0x01f4 +#define STM32H5_FLASH_HDP2R_CUR_OFFSET 0x01f8 +#define STM32H5_FLASH_HDP2R_PRG_OFFSET 0x01fc + + + + + +/* Register Addresses *******************************************************/ + +#define STM32H5_FLASH_ACR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_ACR_OFFSET) +#define STM32H5_FLASH_NSKEYR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSKEYR_OFFSET) +#define STM32H5_FLASH_SECKEYR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECKEYR_OFFSET) +#define STM32H5_FLASH_OPTKEYR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OPTKEYR_OFFSET) +#define STM32H5_FLASH_NSOBKKEYR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSOBKKEYR_OFFSET) +#define STM32H5_FLASH_SECOBKKEYR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECOBKKEYR_OFFSET) +#define STM32H5_FLASH_OPSR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OPSR_OFFSET) +#define STM32H5_FLASH_OPTCR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OPTCR_OFFSET) +#define STM32H5_FLASH_NSSR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSSR_OFFSET) +#define STM32H5_FLASH_SECSR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECSR_OFFSET) +#define STM32H5_FLASH_NSCR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSCR_OFFSET) +#define STM32H5_FLASH_SECCR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECCR_OFFSET) +#define STM32H5_FLASH_NSCCR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSCCR_OFFSET) +#define STM32H5_FLASH_SECCCR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECCCR_OFFSET) +#define STM32H5_FLASH_PRIVCFGR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVCFGR_OFFSET) +#define STM32H5_FLASH_NSOBKCFGR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSOBKCFGR_OFFSET) +#define STM32H5_FLASH_SECOBKCFGR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECOBKCFGR_OFFSET) +#define STM32H5_FLASH_HDPEXTR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_HDPEXTR_OFFSET) +#define STM32H5_FLASH_OPTSR_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OPTSR_CUR_OFFSET) +#define STM32H5_FLASH_OPTSR_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OPTSR_PRG_OFFSET) +#define STM32H5_FLASH_NSEPOCHR_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSEPOCHR_CUR_OFFSET) +#define STM32H5_FLASH_NSEPOCHR_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSEPOCHR_PRG_OFFSET) +#define STM32H5_FLASH_SECEPOCHR_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECEPOCHR_CUR_OFFSET) +#define STM32H5_FLASH_SECEPOCHR_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECEPOCHR_PRG_OFFSET) +#define STM32H5_FLASH_OPTSR2_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OPTSR2_CUR_OFFSET) +#define STM32H5_FLASH_OPTSR2_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OPTSR2_PRG_OFFSET) +#define STM32H5_FLASH_NSBOOTR_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSBOOTR_CUR_OFFSET) +#define STM32H5_FLASH_NSBOOTR_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_NSBOOTR_PRG_OFFSET) +#define STM32H5_FLASH_SECBOOTR_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBOOTR_CUR_OFFSET) +#define STM32H5_FLASH_SECBOOTR_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBOOTR_PRG_OFFSET) +#define STM32H5_FLASH_OTBPBLR_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OTBPBLR_CUR_OFFSET) +#define STM32H5_FLASH_OTBPBLR_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_OTBPBLR_PRG_OFFSET) +#define STM32H5_FLASH_SECBB1R_1 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBB1R_1_OFFSET) +#define STM32H5_FLASH_SECBB1R_2 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBB1R_2_OFFSET) +#define STM32H5_FLASH_SECBB1R_3 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBB1R_3_OFFSET) +#define STM32H5_FLASH_SECBB1R_4 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBB1R_4_OFFSET) +#define STM32H5_FLASH_PRIVBB1R_1 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVBB1R_1_OFFSET) +#define STM32H5_FLASH_PRIVBB1R_2 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVBB1R_2_OFFSET) +#define STM32H5_FLASH_PRIVBB1R_3 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVBB1R_3_OFFSET) +#define STM32H5_FLASH_PRIVBB1R_4 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVBB1R_4_OFFSET) +#define STM32H5_FLASH_SECWM1R_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECWM1R_CUR_OFFSET) +#define STM32H5_FLASH_SECWM1R_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECWM1R_PRG_OFFSET) +#define STM32H5_FLASH_WRP1R_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_WRP1R_CUR_OFFSET) +#define STM32H5_FLASH_WRP1R_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_WRP1R_PRG_OFFSET) +#define STM32H5_FLASH_EDATA1R_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_EDATA1R_CUR_OFFSET) +#define STM32H5_FLASH_EDATA1R_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_EDATA1R_PRG_OFFSET) +#define STM32H5_FLASH_HDP1R_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_HDP1R_CUR_OFFSET) +#define STM32H5_FLASH_HDP1R_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_HDP1R_PRG_OFFSET) +#define STM32H5_FLASH_ECCCORR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_ECCCORR_OFFSET) +#define STM32H5_FLASH_ECCDETR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_ECCDETR_OFFSET) +#define STM32H5_FLASH_ECCDR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_ECCDR_OFFSET) +#define STM32H5_FLASH_SECBB2R_1 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBB2R_1_OFFSET) +#define STM32H5_FLASH_SECBB2R_2 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBB2R_2_OFFSET) +#define STM32H5_FLASH_SECBB2R_3 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBB2R_3_OFFSET) +#define STM32H5_FLASH_SECBB2R_4 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECBB2R_4_OFFSET) +#define STM32H5_FLASH_PRIVBB2R_1 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVBB2R_1_OFFSET) +#define STM32H5_FLASH_PRIVBB2R_2 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVBB2R_2_OFFSET) +#define STM32H5_FLASH_PRIVBB2R_3 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVBB2R_3_OFFSET) +#define STM32H5_FLASH_PRIVBB2R_4 (STM32H5_FLASHIF_BASE + STM32H5_FLASH_PRIVBB2R_4_OFFSET) +#define STM32H5_FLASH_SECWM2R_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECWM2R_CUR_OFFSET) +#define STM32H5_FLASH_SECWM2R_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_SECWM2R_PRG_OFFSET) +#define STM32H5_FLASH_WRP2R_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_WRP2R_CUR_OFFSET) +#define STM32H5_FLASH_WRP2R_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_WRP2R_PRG_OFFSET) +#define STM32H5_FLASH_EDATA2R_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_EDATA2R_CUR_OFFSET) +#define STM32H5_FLASH_EDATA2R_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_EDATA2R_PRG_OFFSET) +#define STM32H5_FLASH_HDP2R_CUR (STM32H5_FLASHIF_BASE + STM32H5_FLASH_HDP2R_CUR_OFFSET) +#define STM32H5_FLASH_HDP2R_PRG (STM32H5_FLASHIF_BASE + STM32H5_FLASH_HDP2R_PRG_OFFSET) + + +/* Register Bitfield Definitions ********************************************/ + + +/* TODO: Ended here 9/11/2024 */ +/* Flash Access Control Register (ACR) */ + +#define FLASH_ACR_LATENCY_SHIFT (0) +#define FLASH_ACR_LATENCY_MASK (0xF << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */ +# define FLASH_ACR_LATENCY_0 ( 0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 ( 1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */ +# define FLASH_ACR_LATENCY_2 ( 2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */ +# define FLASH_ACR_LATENCY_3 ( 3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */ +# define FLASH_ACR_LATENCY_4 ( 4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */ +# define FLASH_ACR_LATENCY_5 ( 5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */ +# define FLASH_ACR_LATENCY_6 ( 6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */ +# define FLASH_ACR_LATENCY_7 ( 7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait state */ +# define FLASH_ACR_LATENCY_8 ( 8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */ +# define FLASH_ACR_LATENCY_9 ( 9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait states */ +# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */ +# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */ +# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */ +# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait state */ +# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen states */ +# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */ + +#define FLASH_ACR_RUN_PD (1 << 13) /* Bit 13: Flash mode during Run */ +#define FLASH_ACR_SLEEP_PD (1 << 14) /* Bit 14: Flash mode during Sleep */ +#define FLASH_ACR_LVE (1 << 15) /* Bit 15: Flash low-voltage enable */ + +/* Flash Status Register (SR) */ + +#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ +#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ +#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +#define FLASH_SR_OPTWERR (1 << 13) /* Bit 13: Option write error */ +#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ + +/* Flash Control Register (CR) */ + +#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */ +#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */ +#define FLASH_CR_MER1 (1 << 2) /* Bit 2 : Mass Erase Bank 1 */ + +#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */ +#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT) +#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+128 (if BKER=1), n=0..127 */ + +#define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */ +#define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */ +#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */ +#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */ +#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ +#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ +#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */ +#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */ +#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ + +/* Flash ECC Register (ECCR) */ + +#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-18: ECC fail address */ +#define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT) +#define FLASH_ECCR_BK_ECC (1 << 21) /* Bit 21: ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC (1 << 22) /* Bit 22: System Flash ECC fail */ +#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC2 (1 << 28) /* Bit 28: ECC2 correction */ +#define FLASH_ECCR_ECCD2 (1 << 29) /* Bit 29: ECC2 detection */ +#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */ +#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */ + +/* Flash Option Register (OPTR) */ + +#define FLASH_OPTR_NRST_STOP (1 << 12) /* Bit 12: Generate reset when entering the Stop mode */ +#define FLASH_OPTR_NRST_STDBY (1 << 13) /* Bit 13: Generate reset when entering the Standby mode */ +#define FLASH_OPTR_NRST_SHDW (1 << 14) /* Bit 14: Generate reset when entering the Shutdown mode */ +#define FLASH_OPTR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/ +#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK (1 << 20) /* Bit 20: Swap banks */ +#define FLASH_OPTR_DB256K (1 << 21) /* Bit 21: Dual bank on 256K flash memory devices */ +#define FLASH_OPTR_DBANK (1 << 22) /* Bit 22: Dual bank enable */ +#define FLASH_OPTR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */ +#define FLASH_OPTR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */ +#define FLASH_OPTR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */ +#define FLASH_OPTR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN (1 << 28) /* Bit 28: PA15 pull-up enable */ +#define FLASH_OPTR_TZEN (1 << 31) /* Bit 31: Global TrustZone security enable */ + +#define FLASH_OPTR_BORLEV_SHIFT (8) /* Bits 8-10: BOR reset Level */ +#define FLASH_OPTR_BORLEV_MASK (7 << FLASH_OPTR_BORLEV_SHIFT) +#define FLASH_OPTR_VBOR0 (0 << FLASH_OPTR_BORLEV_SHIFT) /* 000: BOR Level 0 (1.7 V) */ +#define FLASH_OPTR_VBOR1 (1 << FLASH_OPTR_BORLEV_SHIFT) /* 001: BOR Level 1 (2.0 V) */ +#define FLASH_OPTR_VBOR2 (2 << FLASH_OPTR_BORLEV_SHIFT) /* 010: BOR Level 2 (2.2 V) */ +#define FLASH_OPTR_VBOR3 (3 << FLASH_OPTR_BORLEV_SHIFT) /* 011: BOR Level 3 (2.5 V) */ +#define FLASH_OPTR_VBOR4 (4 << FLASH_OPTR_BORLEV_SHIFT) /* 100: BOR Level 4 (2.8 V) */ +#define FLASH_OPTR_RDP_SHIFT (0) /* Bits 0-7: Read Protection Level */ +#define FLASH_OPTR_RDP_MASK (0xFF << FLASH_OPTR_RDP_SHIFT) +#define FLASH_OPTR_RDP_NONE (0xAA << FLASH_OPTR_RDP_SHIFT) +#define FLASH_OPTR_RDP_NSDBG (0x55 << FLASH_OPTR_RDP_SHIFT) +#define FLASH_OPTR_RDP_CHIP (0xCC << FLASH_OPTR_RDP_SHIFT) /* WARNING, CANNOT BE REVERSED !! */ + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_FLASH_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_gpio.h b/arch/arm/src/stm32h5/hardware/stm32h5_gpio.h new file mode 100644 index 0000000000000..3cca8b225ce80 --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_gpio.h @@ -0,0 +1,402 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h5_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_GPIO_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32H5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32H5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32H5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32H5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32H5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32H5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32H5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32H5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32H5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32H5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32H5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32H5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32H5_GPIO_HSLVR_OFFSET 0x002c /* GPIO high-speed low-voltage register */ +#define STM32H5_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ + +/* Register Addresses *******************************************************/ + +#if STM32H5_NPORTS > 0 +# define STM32H5_GPIOA_MODER (STM32H5_GPIOA_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOA_OTYPER (STM32H5_GPIOA_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOA_OSPEED (STM32H5_GPIOA_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOA_PUPDR (STM32H5_GPIOA_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOA_IDR (STM32H5_GPIOA_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOA_ODR (STM32H5_GPIOA_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOA_BSRR (STM32H5_GPIOA_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOA_LCKR (STM32H5_GPIOA_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOA_AFRL (STM32H5_GPIOA_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOA_AFRH (STM32H5_GPIOA_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOA_BRR (STM32H5_GPIOA_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOA_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOA_SECCFGR (STM32H5_GPIOA_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +#if STM32H5_NPORTS > 1 +# define STM32H5_GPIOB_MODER (STM32H5_GPIOB_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOB_OTYPER (STM32H5_GPIOB_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOB_OSPEED (STM32H5_GPIOB_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOB_PUPDR (STM32H5_GPIOB_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOB_IDR (STM32H5_GPIOB_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOB_ODR (STM32H5_GPIOB_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOB_BSRR (STM32H5_GPIOB_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOB_LCKR (STM32H5_GPIOB_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOB_AFRL (STM32H5_GPIOB_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOB_AFRH (STM32H5_GPIOB_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOB_BRR (STM32H5_GPIOB_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOA_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOB_SECCFGR (STM32H5_GPIOB_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +#if STM32H5_NPORTS > 2 +# define STM32H5_GPIOC_MODER (STM32H5_GPIOC_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOC_OTYPER (STM32H5_GPIOC_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOC_OSPEED (STM32H5_GPIOC_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOC_PUPDR (STM32H5_GPIOC_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOC_IDR (STM32H5_GPIOC_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOC_ODR (STM32H5_GPIOC_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOC_BSRR (STM32H5_GPIOC_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOC_LCKR (STM32H5_GPIOC_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOC_AFRL (STM32H5_GPIOC_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOC_AFRH (STM32H5_GPIOC_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOC_BRR (STM32H5_GPIOC_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOA_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOC_SECCFGR (STM32H5_GPIOC_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +#if STM32H5_NPORTS > 3 +# define STM32H5_GPIOD_MODER (STM32H5_GPIOD_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOD_OTYPER (STM32H5_GPIOD_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOD_OSPEED (STM32H5_GPIOD_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOD_PUPDR (STM32H5_GPIOD_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOD_IDR (STM32H5_GPIOD_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOD_ODR (STM32H5_GPIOD_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOD_BSRR (STM32H5_GPIOD_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOD_LCKR (STM32H5_GPIOD_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOD_AFRL (STM32H5_GPIOD_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOD_AFRH (STM32H5_GPIOD_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOD_BRR (STM32H5_GPIOD_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOA_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOD_SECCFGR (STM32H5_GPIOD_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +#if STM32H5_NPORTS > 4 +# define STM32H5_GPIOE_MODER (STM32H5_GPIOE_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOE_OTYPER (STM32H5_GPIOE_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOE_OSPEED (STM32H5_GPIOE_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOE_PUPDR (STM32H5_GPIOE_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOE_IDR (STM32H5_GPIOE_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOE_ODR (STM32H5_GPIOE_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOE_BSRR (STM32H5_GPIOE_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOE_LCKR (STM32H5_GPIOE_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOE_AFRL (STM32H5_GPIOE_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOE_AFRH (STM32H5_GPIOE_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOE_BRR (STM32H5_GPIOE_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOA_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOE_SECCFGR (STM32H5_GPIOE_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +#if STM32H5_NPORTS > 5 +# define STM32H5_GPIOF_MODER (STM32H5_GPIOF_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOF_OTYPER (STM32H5_GPIOF_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOF_OSPEED (STM32H5_GPIOF_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOF_PUPDR (STM32H5_GPIOF_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOF_IDR (STM32H5_GPIOF_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOF_ODR (STM32H5_GPIOF_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOF_BSRR (STM32H5_GPIOF_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOF_LCKR (STM32H5_GPIOF_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOF_AFRL (STM32H5_GPIOF_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOF_AFRH (STM32H5_GPIOF_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOF_BRR (STM32H5_GPIOF_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOA_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOF_SECCFGR (STM32H5_GPIOF_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +#if STM32H5_NPORTS > 6 +# define STM32H5_GPIOG_MODER (STM32H5_GPIOG_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOG_OTYPER (STM32H5_GPIOG_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOG_OSPEED (STM32H5_GPIOG_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOG_PUPDR (STM32H5_GPIOG_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOG_IDR (STM32H5_GPIOG_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOG_ODR (STM32H5_GPIOG_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOG_BSRR (STM32H5_GPIOG_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOG_LCKR (STM32H5_GPIOG_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOG_AFRL (STM32H5_GPIOG_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOG_AFRH (STM32H5_GPIOG_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOG_BRR (STM32H5_GPIOG_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOA_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOG_SECCFGR (STM32H5_GPIOG_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +#if STM32H5_NPORTS > 7 +# define STM32H5_GPIOH_MODER (STM32H5_GPIOH_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOH_OTYPER (STM32H5_GPIOH_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOH_OSPEED (STM32H5_GPIOH_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOH_PUPDR (STM32H5_GPIOH_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOH_IDR (STM32H5_GPIOH_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOH_ODR (STM32H5_GPIOH_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOH_BSRR (STM32H5_GPIOH_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOH_LCKR (STM32H5_GPIOH_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOH_AFRL (STM32H5_GPIOH_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOH_AFRH (STM32H5_GPIOH_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOH_BRR (STM32H5_GPIOH_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOH_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOH_SECCFGR (STM32H5_GPIOH_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +#if STM32H5_NPORTS > 8 +# define STM32H5_GPIOI_MODER (STM32H5_GPIOI_BASE + STM32H5_GPIO_MODER_OFFSET) +# define STM32H5_GPIOI_OTYPER (STM32H5_GPIOI_BASE + STM32H5_GPIO_OTYPER_OFFSET) +# define STM32H5_GPIOI_OSPEED (STM32H5_GPIOI_BASE + STM32H5_GPIO_OSPEED_OFFSET) +# define STM32H5_GPIOI_PUPDR (STM32H5_GPIOI_BASE + STM32H5_GPIO_PUPDR_OFFSET) +# define STM32H5_GPIOI_IDR (STM32H5_GPIOI_BASE + STM32H5_GPIO_IDR_OFFSET) +# define STM32H5_GPIOI_ODR (STM32H5_GPIOI_BASE + STM32H5_GPIO_ODR_OFFSET) +# define STM32H5_GPIOI_BSRR (STM32H5_GPIOI_BASE + STM32H5_GPIO_BSRR_OFFSET) +# define STM32H5_GPIOI_LCKR (STM32H5_GPIOI_BASE + STM32H5_GPIO_LCKR_OFFSET) +# define STM32H5_GPIOI_AFRL (STM32H5_GPIOI_BASE + STM32H5_GPIO_AFRL_OFFSET) +# define STM32H5_GPIOI_AFRH (STM32H5_GPIOI_BASE + STM32H5_GPIO_AFRH_OFFSET) +# define STM32H5_GPIOI_BRR (STM32H5_GPIOI_BASE + STM32H5_GPIO_BRR_OFFSET) +# define STM32H5_GPIOI_HSLVR (STM32H5_GPIOA_BASE + STM32H5_GPIO_HSLVR_OFFSET) +# define STM32H5_GPIOI_SECCFGR (STM32H5_GPIOI_BASE + STM32H5_GPIO_SECCFGR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* GPIO port mode register */ + +#define GPIO_MODER_INPUT (0) /* Input */ +#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */ +#define GPIO_MODER_ALT (2) /* Alternate mode */ +#define GPIO_MODER_ANALOG (3) /* Analog mode */ + +#define GPIO_MODER_SHIFT(n) ((n) << 1) +#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) + +#define GPIO_MODER0_SHIFT (0) +#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT) +#define GPIO_MODER1_SHIFT (2) +#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT) +#define GPIO_MODER2_SHIFT (4) +#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT) +#define GPIO_MODER3_SHIFT (6) +#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT) +#define GPIO_MODER4_SHIFT (8) +#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT) +#define GPIO_MODER5_SHIFT (10) +#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT) +#define GPIO_MODER6_SHIFT (12) +#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT) +#define GPIO_MODER7_SHIFT (14) +#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT) +#define GPIO_MODER8_SHIFT (16) +#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT) +#define GPIO_MODER9_SHIFT (18) +#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT) +#define GPIO_MODER10_SHIFT (20) +#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT) +#define GPIO_MODER11_SHIFT (22) +#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT) +#define GPIO_MODER12_SHIFT (24) +#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT) +#define GPIO_MODER13_SHIFT (26) +#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT) +#define GPIO_MODER14_SHIFT (28) +#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT) +#define GPIO_MODER15_SHIFT (30) +#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT) + +/* GPIO port output type register */ + +#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */ +#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull */ + +/* GPIO port output speed register */ + +#define GPIO_OSPEED_2MHZ (0) /* 2 MHz Low speed */ +#define GPIO_OSPEED_25MHZ (1) /* 25 MHz Medium speed */ +#define GPIO_OSPEED_50MHZ (2) /* 50 MHz High speed */ +#define GPIO_OSPEED_100MHZ (3) /* 100 MHz Very High speed on 30 pF (80 MHz Output max speed on 15 pF) */ + +#define GPIO_OSPEED_SHIFT(n) ((n) << 1) +#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) + +#define GPIO_OSPEED0_SHIFT (0) +#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT) +#define GPIO_OSPEED1_SHIFT (2) +#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT) +#define GPIO_OSPEED2_SHIFT (4) +#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT) +#define GPIO_OSPEED3_SHIFT (6) +#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT) +#define GPIO_OSPEED4_SHIFT (8) +#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT) +#define GPIO_OSPEED5_SHIFT (10) +#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT) +#define GPIO_OSPEED6_SHIFT (12) +#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT) +#define GPIO_OSPEED7_SHIFT (14) +#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT) +#define GPIO_OSPEED8_SHIFT (16) +#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT) +#define GPIO_OSPEED9_SHIFT (18) +#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT) +#define GPIO_OSPEED10_SHIFT (20) +#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT) +#define GPIO_OSPEED11_SHIFT (22) +#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT) +#define GPIO_OSPEED12_SHIFT (24) +#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT) +#define GPIO_OSPEED13_SHIFT (26) +#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT) +#define GPIO_OSPEED14_SHIFT (28) +#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT) +#define GPIO_OSPEED15_SHIFT (30) +#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT) + +/* GPIO port pull-up/pull-down register */ + +#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */ +#define GPIO_PUPDR_PULLUP (1) /* Pull-up */ +#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ + +#define GPIO_PUPDR_SHIFT(n) ((n) << 1) +#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) + +#define GPIO_PUPDR0_SHIFT (0) +#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT) +#define GPIO_PUPDR1_SHIFT (2) +#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT) +#define GPIO_PUPDR2_SHIFT (4) +#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT) +#define GPIO_PUPDR3_SHIFT (6) +#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT) +#define GPIO_PUPDR4_SHIFT (8) +#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT) +#define GPIO_PUPDR5_SHIFT (10) +#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT) +#define GPIO_PUPDR6_SHIFT (12) +#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT) +#define GPIO_PUPDR7_SHIFT (14) +#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT) +#define GPIO_PUPDR8_SHIFT (16) +#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT) +#define GPIO_PUPDR9_SHIFT (18) +#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT) +#define GPIO_PUPDR10_SHIFT (20) +#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT) +#define GPIO_PUPDR11_SHIFT (22) +#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT) +#define GPIO_PUPDR12_SHIFT (24) +#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT) +#define GPIO_PUPDR13_SHIFT (26) +#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT) +#define GPIO_PUPDR14_SHIFT (28) +#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT) +#define GPIO_PUPDR15_SHIFT (30) +#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT) + +/* GPIO port input data register */ + +#define GPIO_IDR(n) (1 << (n)) + +/* GPIO port output data register */ + +#define GPIO_ODR(n) (1 << (n)) + +/* GPIO port bit set/reset register */ + +#define GPIO_BSRR_SET(n) (1 << (n)) +#define GPIO_BSRR_RESET(n) (1 << ((n)+16)) + +/* GPIO port configuration lock register */ + +#define GPIO_LCKR(n) (1 << (n)) +#define GPIO_LCKK (1 << 16) /* Lock key */ + +/* GPIO alternate function low/high register */ + +#define GPIO_AFR_SHIFT(n) ((n) << 2) +#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) + +#define GPIO_AFRL0_SHIFT (0) +#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT) +#define GPIO_AFRL1_SHIFT (4) +#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT) +#define GPIO_AFRL2_SHIFT (8) +#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT) +#define GPIO_AFRL3_SHIFT (12) +#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT) +#define GPIO_AFRL4_SHIFT (16) +#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT) +#define GPIO_AFRL5_SHIFT (20) +#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT) +#define GPIO_AFRL6_SHIFT (24) +#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT) +#define GPIO_AFRL7_SHIFT (28) +#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) + +#define GPIO_AFRH8_SHIFT (0) +#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT) +#define GPIO_AFRH9_SHIFT (4) +#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT) +#define GPIO_AFRH10_SHIFT (8) +#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT) +#define GPIO_AFRH11_SHIFT (12) +#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT) +#define GPIO_AFRH12_SHIFT (16) +#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT) +#define GPIO_AFRH13_SHIFT (20) +#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT) +#define GPIO_AFRH14_SHIFT (24) +#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT) +#define GPIO_AFRH15_SHIFT (28) +#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) + +/* GPIO port bit reset register */ + +#define GPIO_BRR_SET(n) (1 << (n)) + +/* GPIO high-speed low-voltage register */ + +#define GPIO_HSLV_SET(n) (1 << (n)) + +/* GPIO port secure configuration register */ + +#define GPIO_SECCFGR_SET(n) (1 << (n)) + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_GPIO_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_i2c.h b/arch/arm/src/stm32h5/hardware/stm32h5_i2c.h new file mode 100644 index 0000000000000..cd7ed7d9c33bc --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_i2c.h @@ -0,0 +1,250 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/hardware/stm32l4_i2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_I2C_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_I2C_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32H5_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32H5_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32H5_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32H5_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32H5_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32H5_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32H5_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32H5_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32H5_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32H5_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32H5_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ + +/* Register Addresses *******************************************************/ + +#if STM32H5_NI2C > 0 +# define STM32H5_I2C1_CR1 (STM32H5_I2C1_BASE+STM32H5_I2C_CR1_OFFSET) +# define STM32H5_I2C1_CR2 (STM32H5_I2C1_BASE+STM32H5_I2C_CR2_OFFSET) +# define STM32H5_I2C1_OAR1 (STM32H5_I2C1_BASE+STM32H5_I2C_OAR1_OFFSET) +# define STM32H5_I2C1_OAR2 (STM32H5_I2C1_BASE+STM32H5_I2C_OAR2_OFFSET) +# define STM32H5_I2C1_TIMINGR (STM32H5_I2C1_BASE+STM32H5_I2C_TIMINGR_OFFSET) +# define STM32H5_I2C1_TIMEOUTR (STM32H5_I2C1_BASE+STM32H5_I2C_TIMEOUTR_OFFSET) +# define STM32H5_I2C1_ISR (STM32H5_I2C1_BASE+STM32H5_I2C_ISR_OFFSET) +# define STM32H5_I2C1_ICR (STM32H5_I2C1_BASE+STM32H5_I2C_ICR_OFFSET) +# define STM32H5_I2C1_PECR (STM32H5_I2C1_BASE+STM32H5_I2C_PECR_OFFSET) +# define STM32H5_I2C1_RXDR (STM32H5_I2C1_BASE+STM32H5_I2C_RXDR_OFFSET) +# define STM32H5_I2C1_TXDR (STM32H5_I2C1_BASE+STM32H5_I2C_TXDR_OFFSET) +#endif + +#if STM32H5_NI2C > 1 +# define STM32H5_I2C2_CR1 (STM32H5_I2C2_BASE+STM32H5_I2C_CR1_OFFSET) +# define STM32H5_I2C2_CR2 (STM32H5_I2C2_BASE+STM32H5_I2C_CR2_OFFSET) +# define STM32H5_I2C2_OAR1 (STM32H5_I2C2_BASE+STM32H5_I2C_OAR1_OFFSET) +# define STM32H5_I2C2_OAR2 (STM32H5_I2C2_BASE+STM32H5_I2C_OAR2_OFFSET) +# define STM32H5_I2C2_TIMINGR (STM32H5_I2C2_BASE+STM32H5_I2C_TIMINGR_OFFSET) +# define STM32H5_I2C2_TIMEOUTR (STM32H5_I2C2_BASE+STM32H5_I2C_TIMEOUTR_OFFSET) +# define STM32H5_I2C2_ISR (STM32H5_I2C2_BASE+STM32H5_I2C_ISR_OFFSET) +# define STM32H5_I2C2_ICR (STM32H5_I2C2_BASE+STM32H5_I2C_ICR_OFFSET) +# define STM32H5_I2C2_PECR (STM32H5_I2C2_BASE+STM32H5_I2C_PECR_OFFSET) +# define STM32H5_I2C2_RXDR (STM32H5_I2C2_BASE+STM32H5_I2C_RXDR_OFFSET) +# define STM32H5_I2C2_TXDR (STM32H5_I2C2_BASE+STM32H5_I2C_TXDR_OFFSET) +#endif + +#if STM32H5_NI2C > 2 +# define STM32H5_I2C3_CR1 (STM32H5_I2C3_BASE+STM32H5_I2C_CR1_OFFSET) +# define STM32H5_I2C3_CR2 (STM32H5_I2C3_BASE+STM32H5_I2C_CR2_OFFSET) +# define STM32H5_I2C3_OAR1 (STM32H5_I2C3_BASE+STM32H5_I2C_OAR1_OFFSET) +# define STM32H5_I2C3_OAR2 (STM32H5_I2C3_BASE+STM32H5_I2C_OAR2_OFFSET) +# define STM32H5_I2C3_TIMINGR (STM32H5_I2C3_BASE+STM32H5_I2C_TIMINGR_OFFSET) +# define STM32H5_I2C3_TIMEOUTR (STM32H5_I2C3_BASE+STM32H5_I2C_TIMEOUTR_OFFSET) +# define STM32H5_I2C3_ISR (STM32H5_I2C3_BASE+STM32H5_I2C_ISR_OFFSET) +# define STM32H5_I2C3_ICR (STM32H5_I2C3_BASE+STM32H5_I2C_ICR_OFFSET) +# define STM32H5_I2C3_PECR (STM32H5_I2C3_BASE+STM32H5_I2C_PECR_OFFSET) +# define STM32H5_I2C3_RXDR (STM32H5_I2C3_BASE+STM32H5_I2C_RXDR_OFFSET) +# define STM32H5_I2C3_TXDR (STM32H5_I2C3_BASE+STM32H5_I2C_TXDR_OFFSET) +#endif + +#if STM32H5_NI2C > 3 +# define STM32H5_I2C4_CR1 (STM32H5_I2C4_BASE+STM32H5_I2C_CR1_OFFSET) +# define STM32H5_I2C4_CR2 (STM32H5_I2C4_BASE+STM32H5_I2C_CR2_OFFSET) +# define STM32H5_I2C4_OAR1 (STM32H5_I2C4_BASE+STM32H5_I2C_OAR1_OFFSET) +# define STM32H5_I2C4_OAR2 (STM32H5_I2C4_BASE+STM32H5_I2C_OAR2_OFFSET) +# define STM32H5_I2C4_TIMINGR (STM32H5_I2C4_BASE+STM32H5_I2C_TIMINGR_OFFSET) +# define STM32H5_I2C4_TIMEOUTR (STM32H5_I2C4_BASE+STM32H5_I2C_TIMEOUTR_OFFSET) +# define STM32H5_I2C4_ISR (STM32H5_I2C4_BASE+STM32H5_I2C_ISR_OFFSET) +# define STM32H5_I2C4_ICR (STM32H5_I2C4_BASE+STM32H5_I2C_ICR_OFFSET) +# define STM32H5_I2C4_PECR (STM32H5_I2C4_BASE+STM32H5_I2C_PECR_OFFSET) +# define STM32H5_I2C4_RXDR (STM32H5_I2C4_BASE+STM32H5_I2C_RXDR_OFFSET) +# define STM32H5_I2C4_TXDR (STM32H5_I2C4_BASE+STM32H5_I2C_TXDR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ +#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */ +#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */ +#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */ +#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */ +#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */ +#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ +#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ +#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ +#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT) +# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) +# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ + +#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ +#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ +#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ +#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */ +#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ +#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ +#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ +#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ +#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ + +/* Control register 2 */ + +#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */ +#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT) +#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */ +#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT) +#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */ +#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */ +#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */ +#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */ +#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */ +#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */ +#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */ +#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT) +#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */ +#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */ +#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */ + +/* Own address register 1 */ + +#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */ +#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT) +#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */ +#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT) +#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */ +#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */ + +/* Own address register 2 */ + +#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */ +#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT) +#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */ +#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT) +# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */ +# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */ +# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */ +# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */ +# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */ +# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ +# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ +# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ + +#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ + +/* Timing register */ + +#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */ +#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT) +# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */ + +#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */ +#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT) +# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ + +#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ +#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT) +# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ + +#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ +#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT) +# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ + +#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ +#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT) +# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ + +/* Timeout register */ + +#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */ +#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT) +# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT) +#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */ +#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */ +#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT) +# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) +#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ + +/* Interrupt and Status register and interrupt clear register */ + +/* Common interrupt bits */ + +#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ +#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ +#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ +#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ +#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ +#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ +#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ +#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ +#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ + +/* Fields unique to the Interrupt and Status register */ + +#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ +#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */ +#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */ +#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */ +#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */ +#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */ +#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */ +#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ +#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) + +#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT) + +#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \ + | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT) + +/* Packet error checking register */ + +#define I2C_PECR_MASK (0xff) + +/* Receive data register */ + +#define I2C_RXDR_MASK (0xff) + +/* Transmit data register */ + +#define I2C_TXDR_MASK (0xff) + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_I2C_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_memorymap.h b/arch/arm/src/stm32h5/hardware/stm32h5_memorymap.h new file mode 100644 index 0000000000000..b9d1d847b68a7 --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_memorymap.h @@ -0,0 +1,194 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h5_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* STM32H5XXX Address Blocks ************************************************/ + +#define STM32H5_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32H5_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32H5_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32H5_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +#define STM32H5_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +#define STM32H5_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +#define STM32H5_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +#define STM32H5_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32H5_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32H5_REGION_MASK 0xF0000000 +#define STM32H5_IS_SRAM(a) ((((uint32_t)(a)) & STM32H5_REGION_MASK) == STM32H5_SRAM_BASE) +#define STM32H5_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32H5_REGION_MASK) == STM32H5_FMC_BANK1) + +/* Code Base Addresses ******************************************************/ + +#define STM32H5_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32H5_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ +#define STM32H5_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ +#define STM32H5_SRAM2_BASE 0x20040000 /* 0x20040000-0x2004ffff: 64k SRAM2 */ +#define STM32H5_SRAM3_BASE 0x20050000 /* 0x20050000-0x2008ffff: 320k SRAM3 */ + /* 0x20090000-0x2009ffff: Reserved for ECC */ + +/* System Memory Addresses **************************************************/ + +#define STM32H5_SYSMEM_UID 0x08FFF800 /* The 96-bit unique device identifier */ +#define STM32H5_SYSMEM_FSIZE 0x08FFF80C /* Size of Flash memory in Kbytes. */ +#define STM32H5_SYSMEM_PACKAGE 0x08FFF80E /* Indicates the device's package type. */ + +/* Peripheral Base Addresses ************************************************/ + +#define STM32H5_APB1_BASE 0x40000000 /* 0x40000000-0x4000fbff: APB1 */ +#define STM32H5_APB2_BASE 0x40012C00 /* 0x40012c00-0x40016bff: APB2 */ +#define STM32H5_AHB1_BASE 0x40020000 /* 0x40020000-0x400373ff: AHB1 */ +#define STM32H5_AHB2_BASE 0x42020000 /* 0x42020000-0x420c3fff: AHB2 */ +#define STM32H5_APB3_BASE 0x44000400 /* 0x44000400-0x44007fff: APB3 */ +#define STM32H5_AHB3_BASE 0x44020800 /* 0x44020800-0x440243ff: AHB3 */ +#define STM32H5_AHB4_BASE 0x46005000 /* 0x46005000-0x470017ff: AHB4 */ + +/* APB1 Base Addresses ******************************************************/ + +#define STM32H5_UCPD1_BASE 0x4000dc00 +#define STM32H5_FDCAN_SRAM_BASE 0x4000ac00 +#define STM32H5_FDCAN2_BASE 0x4000a800 +#define STM32H5_FDCAN1_BASE 0x4000a400 +#define STM32H5_LPTIM2 0x40009400 +#define STM32H5_DTS_BASE 0x40008c00 +#define STM32H5_UART12_BASE 0x40008400 +#define STM32H5_UART9_BASE 0x40008000 +#define STM32H5_UART8_BASE 0x40007c00 +#define STM32H5_UART7_BASE 0x40007800 +#define STM32H5_HDMICEC_BASE 0x40007000 +#define STM32H5_USART11_BASE 0x40006c00 +#define STM32H5_USART10_BASE 0x40006800 +#define STM32H5_USART6_BASE 0x40006400 +#define STM32H5_CRS_BASE 0x40006000 +#define STM32H5_I3C1_BASE 0x40005c00 +#define STM32H5_I2C2_BASE 0x40005800 +#define STM32H5_I2C1_BASE 0x40005400 +#define STM32H5_UART5_BASE 0x40005000 +#define STM32H5_UART4_BASE 0x40004c00 +#define STM32H5_USART3_BASE 0x40004800 +#define STM32H5_USART2_BASE 0x40004400 +#define STM32H5_SPI3_BASE 0x40003c00 +#define STM32H5_SPI2_BASE 0x40003800 +#define STM32H5_IWDG_BASE 0x40003000 +#define STM32H5_WWDG_BASE 0x40002c00 +#define STM32H5_TIM14_BASE 0x40002000 +#define STM32H5_TIM13_BASE 0x40001c00 +#define STM32H5_TIM12_BASE 0x40001800 +#define STM32H5_TIM7_BASE 0x40001400 +#define STM32H5_TIM6_BASE 0x40001000 +#define STM32H5_TIM5_BASE 0x40000c00 +#define STM32H5_TIM4_BASE 0x40000800 +#define STM32H5_TIM3_BASE 0x40000400 +#define STM32H5_TIM2_BASE 0x40000000 + +/* APB2 Base Addresses ******************************************************/ + +#define STM32H5_USB_FS_RAM_BASE 0x40016400 +#define STM32H5_USB_FS_BASE 0x40016000 +#define STM32H5_SAI2_BASE 0x40015800 +#define STM32H5_SAI1_BASE 0x40015400 +#define STM32H5_SPI6_BASE 0x40015000 +#define STM32H5_SPI4_BASE 0x40014c00 +#define STM32H5_TIM17_BASE 0x40014800 +#define STM32H5_TIM16_BASE 0x40014400 +#define STM32H5_TIM15_BASE 0x40014000 +#define STM32H5_USART1_BASE 0x40013800 +#define STM32H5_TIM8_BASE 0x40013400 +#define STM32H5_SPI1_BASE 0x40013000 +#define STM32H5_TIM1_BASE 0x40012C00 + +/* AHB1 Base Addresses ******************************************************/ + +#define STM32H5_MPC_WM_BKPRAM_BASE 0x40036400 +#define STM32H5_GTZC1_BASE 0x40032400 +#define STM32H5_DCACHE_BASE 0x40030400 +#define STM32H5_ICACHE_BASE 0x40031400 +#define STM32H5_EMAC_BASE 0x40030400 +#define STM32H5_RAMCFG_BASE 0x40026000 +#define STM32H5_FMAC_BASE 0x40023c00 +#define STM32H5_CORDIC_BASE 0x40023800 +#define STM32H5_CRC_BASE 0x40023000 +#define STM32H5_FLASHIF_BASE 0x40022000 +#define STM32H5_DMA2_BASE 0x40021000 +#define STM32H5_DMA1_BASE 0x40020000 + +/* AHB2 Base Addresses ******************************************************/ + +#define STM32H5_PKA_BASE 0x420c2000 +#define STM32H5_SAES_BASE 0x420c0C00 +#define STM32H5_RNG_BASE 0x420c0800 +#define STM32H5_HASH_BASE 0x420c0400 +#define STM32H5_AES_BASE 0x420c0000 +#define STM32H5_PSSI_BASE 0x4202c400 +#define STM32H5_DCMI_BASE 0x4202c000 +#define STM32H5_DAC1_BASE 0x42028400 +#define STM32H5_ADC12_BASE 0x42028000 +#define STM32H5_GPIOI_BASE 0x42022000 +#define STM32H5_GPIOH_BASE 0x42021c00 +#define STM32H5_GPIOG_BASE 0x42021800 +#define STM32H5_GPIOF_BASE 0x42021400 +#define STM32H5_GPIOE_BASE 0x42021000 +#define STM32H5_GPIOD_BASE 0x42020c00 +#define STM32H5_GPIOC_BASE 0x42020800 +#define STM32H5_GPIOB_BASE 0x42020400 +#define STM32H5_GPIOA_BASE 0x42020000 + +/* APB3 Base Addresses ******************************************************/ + +#define STM32H5_TAMP_BASE 0x44007c00 +#define STM32H5_RTC_BASE 0x44007800 +#define STM32H5_VREFBUF_BASE 0x44007400 +#define STM32H5_LPTIM6_BASE 0x44005400 +#define STM32H5_LPTIM5_BASE 0x44005000 +#define STM32H5_LPTIM4_BASE 0x44004c00 +#define STM32H5_LPTIM3_BASE 0x44004800 +#define STM32H5_LPTIM1_BASE 0x44004400 +#define STM32H5_I2C4_BASE 0x44002c00 +#define STM32H5_I2C3_BASE 0x44002800 +#define STM32H5_LPUART1_BASE 0x44002400 +#define STM32H5_SPI5_BASE 0x44002000 +#define STM32H5_SBS_BASE 0x44000400 + +/* AHB3 Base Addresses ******************************************************/ + +#define STM32H5_DEBUG_BASE 0x44024000 +#define STM32H5_EXTI_BASE 0x44022000 +#define STM32H5_RCC_BASE 0x44020C00 +#define STM32H5_PWR_BASE 0x44020800 + +/* AHB4 Base Addresses ******************************************************/ + +#define STM32H5_OCTOSPI1_BASE 0x47001400 +#define STM32H5_FMC_BASE 0x47000400 +#define STM32H5_DLYBOS1_BASE 0x4600f000 +#define STM32H5_SDMMC2_BASE 0x46008c00 +#define STM32H5_DLYBSD2_BASE 0x46008800 +#define STM32H5_DLYBSD1_BASE 0x46008400 +#define STM32H5_SDMMC1_BASE 0x46008000 +#define STM32H5_OTFDEC1_BASE 0x46005000 + + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32h5_pinmap.h new file mode 100644 index 0000000000000..37263329b2a7c --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_pinmap.h @@ -0,0 +1,37 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h5_pinmap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_PINMAP_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32H5_STM32H56XXX) +# include "hardware/stm32h56xxx_pinmap.h" +#else +# error "Unsupported STM32 H5 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_PINMAP_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_pwr.h b/arch/arm/src/stm32h5/hardware/stm32h5_pwr.h new file mode 100644 index 0000000000000..e0e0dcb6fa493 --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_pwr.h @@ -0,0 +1,250 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h5_pwr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_PWR_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32H5_PWR_PMCR_OFFSET 0x0000 /* Power Mode Control */ +#define STM32H5_PWR_PMSR_OFFSET 0x0004 /* Power Mode Status */ +#define STM32H5_PWR_VOSCR_OFFSET 0x0010 /* Voltage Scaling Control */ +#define STM32H5_PWR_VOSSR_OFFSET 0x0014 /* Voltage Scaling Status */ +#define STM32H5_PWR_BDCR_OFFSET 0x0020 /* Backup Domain Control */ +#define STM32H5_PWR_DBPCR_OFFSET 0x0024 /* Backup Domain Protection Control */ +#define STM32H5_PWR_BDSR_OFFSET 0x0028 /* Backup Domain Status */ +#define STM32H5_PWR_UCPDR_OFFSET 0x002c /* USB-C Power Delivery */ +#define STM32H5_PWR_SCCR_OFFSET 0x0030 /* Supply Configuration Control */ +#define STM32H5_PWR_VMCR_OFFSET 0x0034 /* Voltage Monitor Control */ +#define STM32H5_PWR_USBSCR_OFFSET 0x0038 /* USB Supply Control */ +#define STM32H5_PWR_VMSR_OFFSET 0x003c /* Voltage Monitor Status */ +#define STM32H5_PWR_WUSCR_OFFSET 0x0040 /* Wake-Up Status Clear */ +#define STM32H5_PWR_WUSR_OFFSET 0x0044 /* Wake-Up Status */ +#define STM32H5_PWR_WUCR_OFFSET 0x0048 /* Wake-Up Configuration */ +#define STM32H5_PWR_IORETR_OFFSET 0x0050 /* I/O Retention */ +#define STM32H5_PWR_SECCFGR_OFFSET 0x0100 /* Power secure configuration register */ +#define STM32H5_PWR_PRIVCFGR_OFFSET 0x0104 /* Power privilege configuration register */ + +/* Register Addresses *******************************************************/ + +#define STM32H5_PWR_PMCR (STM32H5_PWR_BASE + STM32H5_PWR_PMCR_OFFSET) +#define STM32H5_PWR_PMSR (STM32H5_PWR_BASE + STM32H5_PWR_PMSR_OFFSET) +#define STM32H5_PWR_VOSCR (STM32H5_PWR_BASE + STM32H5_PWR_VOSCR_OFFSET) +#define STM32H5_PWR_VOSSR (STM32H5_PWR_BASE + STM32H5_PWR_VOSSR_OFFSET) +#define STM32H5_PWR_BDCR (STM32H5_PWR_BASE + STM32H5_PWR_BDCR_OFFSET) +#define STM32H5_PWR_DBPCR (STM32H5_PWR_BASE + STM32H5_PWR_DBPCR_OFFSET) +#define STM32H5_PWR_BDSR (STM32H5_PWR_BASE + STM32H5_PWR_BDSR_OFFSET) +#define STM32H5_PWR_UCPDR (STM32H5_PWR_BASE + STM32H5_PWR_UCPDR_OFFSET) +#define STM32H5_PWR_SCCR (STM32H5_PWR_BASE + STM32H5_PWR_SCCR_OFFSET) +#define STM32H5_PWR_VMCR (STM32H5_PWR_BASE + STM32H5_PWR_VMCR_OFFSET) +#define STM32H5_PWR_USBSCR (STM32H5_PWR_BASE + STM32H5_PWR_USBSCR_OFFSET) +#define STM32H5_PWR_VMSR (STM32H5_PWR_BASE + STM32H5_PWR_VMSR_OFFSET) +#define STM32H5_PWR_WUSCR (STM32H5_PWR_BASE + STM32H5_PWR_WUSCR_OFFSET) +#define STM32H5_PWR_WUSR (STM32H5_PWR_BASE + STM32H5_PWR_WUSR_OFFSET) +#define STM32H5_PWR_WUCR (STM32H5_PWR_BASE + STM32H5_PWR_WUCR_OFFSET) +#define STM32H5_PWR_IORETR (STM32H5_PWR_BASE + STM32H5_PWR_IORETR_OFFSET) +#define STM32H5_PWR_SECCFGR (STM32H5_PWR_BASE + STM32H5_PWR_SECCFGR_OFFSET) +#define STM32H5_PWR_PRIVCFGR (STM32H5_PWR_BASE + STM32H5_PWR_PRIVCFGR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Power Mode Control Register */ + +#define PWR_PMCR_LPMS (1 << 0) /* Low-Power Mode */ +#define PWR_PMCR_SVOS_SHIFT (2) /* System Stop Mode Voltage Scaling */ +#define PWR_PMCR_SVOS_MASK (0x3 << PWR_PMCR_SVOS_SHIFT) +# define PWR_PMCR_SVOS_SVOS5 (1 << PWR_PMCR_SVOS_SHIFT) +# define PWR_PMCR_SVOS_SVOS4 (2 << PWR_PMCR_SVOS_SHIFT) +# define PWR_PMCR_SVOS_SVOS3 (3 << PWR_PMCR_SVOS_SHIFT) +#define PWR_PMCR_CSSF (1 << 7) /* Clear Standby and Stop Flags */ +#define PWR_PMCR_FLPS (1 << 9) /* Flash Memory Low-Power Mode in Stop Mode */ +#define PWR_PMCR_BOOSTE (1 << 12) /* Analog Switch Vboost Control */ +#define PWR_PMCR_AVD_READY (1 << 13) /* Analog Voltage Ready */ +#define PWR_PMCR_ETHERNETSO (1 << 16) /* Ethernet RAM shut-off in Stop Mode */ +#define PWR_PMCR_SRAM3SO (1 << 23) /* AHB SRAM3 shut-off in Stop mode */ + +#if defined(CONFIG_STM32H5_STM32H56X) || defined(CONFIG_STM32H5_STM32H7X) + +#define PWR_PMCR_SRAM2_16SO (1 << 24) /* AHB SRAM3 16-Kbyte shut-off in Stop mode **/ +#define PWR_PMCR_SRAM2_48SO (1 << 25) /* AHB SRAM2 48-Kbyte shut-off in Stop mode **/ +#define PWR_PMCR_SRAM1SO (1 << 26) /* AHB SRAM1 shut-off in Stop mode * */ + +#elif defined(CONFIG_STM32H5_STM32H2X) || defined(CONFIG_STM32H5_STM32H3X) + +#define PWR_PMCR_SRAM2_16LSO (1 << 24) /* AHB SRAM3 16-Kbyte Low shut-off in Stop mode **/ +#define PWR_PMCR_SRAM2_16HSO (1 << 25) /* AHB SRAM3 16-Kbyte High shut-off in Stop mode **/ +#define PWR_PMCR_SRAM2_48SO (1 << 26) /* AHB SRAM2 48-Kbyte shut-off in Stop mode **/ +#define PWR_PMCR_SRAM1SO (1 << 27) /* AHB SRAM1 shut-off in Stop mode */ + +#endif + +/* Status Register */ + +#define PWR_PMSR_STOPF (1 << 5) /* Stop Flag */ +#define PWR_PMSR_SBF (1 << 6) /* System Standby Flag */ + +/* Voltage Scaling Control Register */ + +#define PWR_VOSCR_VOS_SHIFT (4) +#define PWR_VOSCR_VOS_MASK (3 << PWR_VOSCR_VOS_SHIFT) +# define PWR_VOSCR_VOS_RANGE3 (0 << PWR_VOSCR_VOS_SHIFT) +# define PWR_VOSCR_VOS_RANGE2 (1 << PWR_VOSCR_VOS_SHIFT) +# define PWR_VOSCR_VOS_RANGE1 (2 << PWR_VOSCR_VOS_SHIFT) +# define PWR_VOSCR_VOS_RANGE0 (3 << PWR_VOSCR_VOS_SHIFT) + +/* Voltage Scaling Status Register */ + +#define PWR_VOSSR_VOSRDY (1 << 3) +#define PWR_VOSSR_ACTVOSRDY (1 << 13) +#define PWR_VOSSR_ACTVOS_SHIFT (14) +#define PWR_VOSSR_ACTVOS_MASK (3 << PWR_VOSSR_ACTVOS_SHIFT) +# define PWR_VOSSR_ACTVOS_VOS3 (0 << PWR_VOSSR_ACTVOS_SHIFT) +# define PWR_VOSSR_ACTVOS_VOS2 (1 << PWR_VOSSR_ACTVOS_SHIFT) +# define PWR_VOSSR_ACTVOS_VOS1 (2 << PWR_VOSSR_ACTVOS_SHIFT) +# define PWR_VOSSR_ACTVOS_VOS0 (3 << PWR_VOSSR_ACTVOS_SHIFT) + +/* Backup Domain Control Register */ + +#define PWR_BDCR_BREN (1 << 0) /* Backup RAM Retention in Sby and VBAT modes */ +#define PWR_BDCR_MONEN (1 << 1) /* Backup Domain Voltage and Temperature Monitoring Enable */ +#define PWR_BDCR_VBE (1 << 8) /* Vbat Charging Enable */ +#define PWR_BDCR_VBRS (1 << 9) /* Vbat Charging Resistor Selection: 0=5k, 1=1.5k */ + +/* Backup Domain Protected Control Register */ + +#define PWR_DBPCR_DBP (1 << 0) + +/* Backup Domain Status Register */ + +#define PWR_BDSR_BRRDY (1 << 16) /* Backup Regulator Ready */ +#define PWR_BDSR_VBATL (1 << 20) /* Vbat Level Monitoring vs Low Threshold */ +#define PWR_BDSR_VBATH (1 << 21) /* Vbat Level Monitoring vs High Threshold */ +#define PWR_BDSR_TEMPL (1 << 22) /* Temperature Level Monitoring vs Low Threshold */ +#define PWR_BDSR_TEMPH (1 << 23) /* Temperature Level Monitoring vs High Threshold */ + +/* USB Type-C Power Delivery Register */ + +#define PWR_UCPDR_UCPD_DBDIS (1 << 0) /* USB-C Power Delivery and Dead Battery Disable */ +#define PWR_UCPDR_UCPD_STBY (1 << 1) /* USB-C and Power Delivery Standby Mode */ + +/* Supply Configuration Control Register */ + +#define PWR_SCCR_BYPASS (1 << 0) /* Power Management Unit Bypass + * 0: Normal Operation: Use Internal Regulator + * 1: Bypassed: Use External Power (Monitoring still active) + */ +#define PWR_SCCR_LDOEN (1 << 8) /* Low Dropout Regulator Enable */ +#define PWR_SCCR_SMPSEN (1 << 9) /* Switch-Mode Power Supply Enable */ + +/* Voltage Monitor Control Register */ + +#define PWR_VMCR_PVDE (1 << 0) /* Programmable Voltage Detector (PVD) Enable */ +#define PWR_VMCR_PLS_SHIFT (1) +#define PWR_VMCR_PLS_MASK (3 << PWR_VMCR_PLS_SHIFT) +# define PWR_VMCR_PLS_PVD0 (0 << PWR_VMCR_PLS_SHIFT) +# define PWR_VMCR_PLS_PVD1 (1 << PWR_VMCR_PLS_SHIFT) +# define PWR_VMCR_PLS_PVD2 (2 << PWR_VMCR_PLS_SHIFT) +# define PWR_VMCR_PLS_PVD3 (3 << PWR_VMCR_PLS_SHIFT) +# define PWR_VMCR_PLS_PVD4 (4 << PWR_VMCR_PLS_SHIFT) +# define PWR_VMCR_PLS_PVD5 (5 << PWR_VMCR_PLS_SHIFT) +# define PWR_VMCR_PLS_PVD6 (6 << PWR_VMCR_PLS_SHIFT) +# define PWR_VMCR_PLS_PVDIN (7 << PWR_VMCR_PLS_SHIFT) +#define PWR_VMCR_AVDEN (1 << 8) /* Peripheral Voltage Monitor on Vdda enable */ +#define PWR_VMCR_ALS_SHIFT (9) +#define PWR_VMCR_ALS_MASK (3 << PWR_VMCR_ALS_SHIFT) +# define PWR_VMCR_ALS_AVD0 (0 << PWR_VMCR_ALS_SHIFT) +# define PWR_VMCR_ALS_AVD1 (1 << PWR_VMCR_ALS_SHIFT) +# define PWR_VMCR_ALS_AVD2 (2 << PWR_VMCR_ALS_SHIFT) +# define PWR_VMCR_ALS_AVD3 (3 << PWR_VMCR_ALS_SHIFT) + +/* USB Supply Control Register */ + +#define PWR_USBSCR_USB33DEN (1 << 24) /* Vddusb voltage level detector enable */ +#define PWR_USBSCR_USB33SV (1 << 25) /* Independent USB Supply Valid */ + +/* Voltage Monitor Status Register */ + +#define PWR_VMSR_AVDO (1 << 19) /* Analog Voltage Detector Output on Vdda */ +#define PWR_VMSR_VDDIO2RDY (1 << 20) /* Voltage Detector Output on Vddio2 */ +#define PWR_VMSR_PVDO (1 << 22) /* Programmable Voltage Detect Output */ +#define PWR_VMSR_USB33RDY (1 << 24) /* Vddusb Ready */ + +/* Wake-up Status Clear Register */ + +#define PWR_WUSCR_CWUF1 (1 << 0) /* Clear wake-up pin flag for WUF1 */ +#define PWR_WUSCR_CWUF2 (1 << 1) /* Clear wake-up pin flag for WUF2 */ +#define PWR_WUSCR_CWUF3 (1 << 2) /* Clear wake-up pin flag for WUF3 */ +#define PWR_WUSCR_CWUF4 (1 << 3) /* Clear wake-up pin flag for WUF4 */ +#define PWR_WUSCR_CWUF5 (1 << 4) /* Clear wake-up pin flag for WUF5 */ +#define PWR_WUSCR_CWUF6 (1 << 5) /* Clear wake-up pin flag for WUF6 */ +#define PWR_WUSCR_CWUF7 (1 << 6) /* Clear wake-up pin flag for WUF7 */ +#define PWR_WUSCR_CWUF8 (1 << 7) /* Clear wake-up pin flag for WUF8 */ + +/* Wake-up Status Register */ + +#define PWR_WUSR_WUF1 (1 << 0) /* Wake-up event received for WUF1 */ +#define PWR_WUSR_WUF2 (1 << 1) /* Wake-up event received for WUF2 */ +#define PWR_WUSR_WUF3 (1 << 2) /* Wake-up event received for WUF3 */ +#define PWR_WUSR_WUF4 (1 << 3) /* Wake-up event received for WUF4 */ +#define PWR_WUSR_WUF5 (1 << 4) /* Wake-up event received for WUF5 */ +#define PWR_WUSR_WUF6 (1 << 5) /* Wake-up event received for WUF6 */ +#define PWR_WUSR_WUF7 (1 << 6) /* Wake-up event received for WUF7 */ +#define PWR_WUSR_WUF8 (1 << 7) /* Wake-up event received for WUF8 */ + +/* Wake-up Configuration Register */ + +#define PWR_WUCR_WUPEN(n) (1 << (n-1)) /* Enable wake-up pin WUPn. n = 1..8 */ +#define PWR_WUCR_WUPP(n) (1 << (n+7)) /* Wake-up Pin Polarity bit for WUPn */ +#define PWR_WUCR_MASK_WUPPUPD(n) (3 << (((n-1) * 2) + 16)) /* Wake-up pin pull configuration */ +#define PWR_WUCR_NOPU_WUPPUPD(n) (0 << (((n-1) * 2) + 16)) +#define PWR_WUCR_PU_WUPPUPD(n) (1 << (((n-1) * 2) + 16)) +#define PWR_WUCR_PD_WUPPUPD(n) (2 << (((n-1) * 2) + 16)) + +/* IO Retention Register */ + +#define PWR_IORETR_IORETEN (1 << 0) /* IO Retention Enable */ +#define PWR_IORETR_JTAGIORETEN (1 << 16) /* IO Retention Enable for JTAG IOs */ + +/* Power secure configuration register */ + +#define PWR_SECCFGR_WUP(n)SEC (1 << (n-1)) /* WUP(n) Secure Protection */ +#define PWR_SECCFGR_RETSEC (1 << 11) /* Retention Secure Protection */ +#define PWR_SECCFGR_LPMSEC (1 << 12) /* Low-power Modes Secure Protection */ +#define PWR_SECCFGR_SCMSEC (1 << 13) /* Supply Configuration and Monitoring Secure Protection */ +#define PWR_SECCFGR_VBSEC (1 << 14) /* Backup Domain Secure Protection */ +#define PWR_SECCFGR_VUSBSEC (1 << 15) /* Voltage USB Secure Protection */ + +/* Power privilege configuration register */ + +#define PWR_PRIVCFGR_SPRIV (1 << 0) /* Bit 0: Power Secure Privilege protection */ +#define PWR_PRIVCFGR_NSPRIV (1 << 1) /* Bit 0: Power Non-secure Privilege protection */ + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_PWR_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_rcc.h b/arch/arm/src/stm32h5/hardware/stm32h5_rcc.h new file mode 100644 index 0000000000000..032ed9f5f0375 --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_rcc.h @@ -0,0 +1,1232 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h562xx_rcc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XX_RCC_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XX_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32H5_STM32H5XXXX) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32H5_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32H5_RCC_HSICFGR_OFFSET 0x0010 /* HSI Calibration Register */ +#define STM32H5_RCC_CRRCR_OFFSET 0x0014 /* RCC clock recovery RC register */ +#define STM32H5_RCC_CFGR1_OFFSET 0x001c /* RCC clock configuration register 1 */ +#define STM32H5_RCC_CFGR2_OFFSET 0x0020 /* RCC clock configuration register 2 */ +#define STM32H5_RCC_PLL1CFGR_OFFSET 0x0028 /* RCC PLL1 configuration register */ +#define STM32H5_RCC_PLL2CFGR_OFFSET 0x002c /* RCC PLL2 configuration register */ +#define STM32H5_RCC_PLL3CFGR_OFFSET 0x0030 /* RCC PLL3 configuration register */ +#define STM32H5_RCC_PLL1DIVR_OFFSET 0x0034 /* RCC PLL1 dividers register */ +#define STM32H5_RCC_PLL1FRACR_OFFSET 0x0038 /* RCC PLL1 fractional divider register */ +#define STM32H5_RCC_PLL2DIVR_OFFSET 0x003c /* RCC PLL2 dividers register */ +#define STM32H5_RCC_PLL2FRACR_OFFSET 0x0040 /* RCC PLL2 fractional divider register */ +#define STM32H5_RCC_PLL3DIVR_OFFSET 0x0044 /* RCC PLL3 dividers register */ +#define STM32H5_RCC_PLL3FRACR_OFFSET 0x0048 /* RCC PLL3 fractional divider register */ +#define STM32H5_RCC_CIER_OFFSET 0x0050 /* RCC clock interrupt enable register */ +#define STM32H5_RCC_CIFR_OFFSET 0x0054 /* RCC clock interrupt flag register */ +#define STM32H5_RCC_CICR_OFFSET 0x0058 /* RCC clock interrupt clear register */ +#define STM32H5_RCC_AHB1RSTR_OFFSET 0x0060 /* RCC AHB1 peripheral reset register */ +#define STM32H5_RCC_AHB2RSTR_OFFSET 0x0064 /* RCC AHB2 peripheral reset register 1 */ +#define STM32H5_RCC_AHB4RSTR_OFFSET 0x006c /* RCC AHB4 peripheral reset register*/ +#define STM32H5_RCC_APB1LRSTR_OFFSET 0x0074 /* RCC APB1 peripheral reset register 1 */ +#define STM32H5_RCC_APB1HRSTR_OFFSET 0x0078 /* RCC APB1 peripheral reset register 2 */ +#define STM32H5_RCC_APB2RSTR_OFFSET 0x007c /* RCC APB2 peripheral reset register */ +#define STM32H5_RCC_APB3RSTR_OFFSET 0x0080 /* RCC APB3 peripheral reset register */ +#define STM32H5_RCC_AHB1ENR_OFFSET 0x0088 /* RCC AHB1 peripheral clock enable register */ +#define STM32H5_RCC_AHB2ENR_OFFSET 0x008c /* RCC AHB2 peripheral clock enable register */ +#define STM32H5_RCC_AHB4ENR_OFFSET 0x0094 /* RCC AHB4 peripheral clock enable register */ +#define STM32H5_RCC_APB1LENR_OFFSET 0x009c /* RCC APB1 peripheral clock enable register 1 */ +#define STM32H5_RCC_APB1HENR_OFFSET 0x00a0 /* RCC APB1 peripheral clock enable register 2 */ +#define STM32H5_RCC_APB2ENR_OFFSET 0x00a4 /* RCC APB2 peripheral clock enable register */ +#define STM32H5_RCC_APB3ENR_OFFSET 0x00a8 /* RCC APB3 peripheral clock enable register */ +#define STM32H5_RCC_AHB1LPENR_OFFSET 0x00b0 /* RCC AHB1 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32H5_RCC_AHB2LPENR_OFFSET 0x00b4 /* RCC AHB2 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32H5_RCC_AHB4LPENR_OFFSET 0x00bc /* RCC AHB3 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32H5_RCC_APB1LPENR1_OFFSET 0x00c4 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 */ +#define STM32H5_RCC_APB1LPENR2_OFFSET 0x00c8 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 */ +#define STM32H5_RCC_APB2LPENR_OFFSET 0x00cc /* RCC APB2 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32H5_RCC_APB3LPENR_OFFSET 0x00d0 /* RCC APB3 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32H5_RCC_CCIPR1_OFFSET 0x00d8 /* RCC peripherals independent clock configuration register 1 */ +#define STM32H5_RCC_CCIPR2_OFFSET 0x00dc /* RCC peripherals independent clock configuration register 2 */ +#define STM32H5_RCC_CCIPR3_OFFSET 0x00e0 /* RCC peripherals independent clock configuration register 3 */ +#define STM32H5_RCC_CCIPR4_OFFSET 0x00e4 /* RCC peripherals independent clock configuration register 5 */ +#define STM32H5_RCC_CCIPR5_OFFSET 0x00e8 /* RCC peripherals independent clock configuration register 5 */ +#define STM32H5_RCC_BDCR_OFFSET 0x00f0 /* RCC Backup domain control register */ +#define STM32H5_RCC_RSR_OFFSET 0x00f4 /* RCC control/status register */ /* TODO: CSR in U5 */ +#define STM32H5_RCC_SECCFGR_OFFSET 0x0110 /* RCC secure configuration register */ +#define STM32H5_RCC_PRIVCFGR_OFFSET 0x0114 /* RCC privilege configuration register */ + +/* Register Addresses *******************************************************/ + +#define STM32H5_RCC_CR (STM32H5_RCC_BASE + STM32H5_RCC_CR_OFFSET) +#define STM32H5_RCC_HSICFGR (STM32H5_RCC_BASE + STM32H5_RCC_HSICFGR_OFFSET) +#define STM32H5_RCC_CRRCR (STM32H5_RCC_BASE + STM32H5_RCC_CRRCR_OFFSET) +#define STM32H5_RCC_CFGR1 (STM32H5_RCC_BASE + STM32H5_RCC_CFGR1_OFFSET) +#define STM32H5_RCC_CFGR2 (STM32H5_RCC_BASE + STM32H5_RCC_CFGR2_OFFSET) +#define STM32H5_RCC_PLL1CFGR (STM32H5_RCC_BASE + STM32H5_RCC_PLL1CFGR_OFFSET) +#define STM32H5_RCC_PLL2CFGR (STM32H5_RCC_BASE + STM32H5_RCC_PLL2CFGR_OFFSET) +#define STM32H5_RCC_PLL3CFGR (STM32H5_RCC_BASE + STM32H5_RCC_PLL3CFGR_OFFSET) +#define STM32H5_RCC_PLL1DIVR (STM32H5_RCC_BASE + STM32H5_RCC_PLL1DIVR_OFFSET) +#define STM32H5_RCC_PLL1FRACR (STM32H5_RCC_BASE + STM32H5_RCC_PLL1FRACR_OFFSET) +#define STM32H5_RCC_PLL2DIVR (STM32H5_RCC_BASE + STM32H5_RCC_PLL2DIVR_OFFSET) +#define STM32H5_RCC_PLL2FRACR (STM32H5_RCC_BASE + STM32H5_RCC_PLL2FRACR_OFFSET) +#define STM32H5_RCC_PLL3DIVR (STM32H5_RCC_BASE + STM32H5_RCC_PLL3DIVR_OFFSET) +#define STM32H5_RCC_PLL3FRACR (STM32H5_RCC_BASE + STM32H5_RCC_PLL3FRACR_OFFSET) +#define STM32H5_RCC_CIER (STM32H5_RCC_BASE + STM32H5_RCC_CIER_OFFSET) +#define STM32H5_RCC_CIFR (STM32H5_RCC_BASE + STM32H5_RCC_CIFR_OFFSET) +#define STM32H5_RCC_CICR (STM32H5_RCC_BASE + STM32H5_RCC_CICR_OFFSET) +#define STM32H5_RCC_AHB1RSTR (STM32H5_RCC_BASE + STM32H5_RCC_AHB1RSTR_OFFSET) +#define STM32H5_RCC_AHB2RSTR (STM32H5_RCC_BASE + STM32H5_RCC_AHB2RSTR_OFFSET) +#define STM32H5_RCC_AHB4RSTR (STM32H5_RCC_BASE + STM32H5_RCC_AHB4RSTR_OFFSET) +#define STM32H5_RCC_APB1LRSTR (STM32H5_RCC_BASE + STM32H5_RCC_APB1LRSTR_OFFSET) +#define STM32H5_RCC_APB1HRSTR (STM32H5_RCC_BASE + STM32H5_RCC_APB1HRSTR_OFFSET) +#define STM32H5_RCC_APB2RSTR (STM32H5_RCC_BASE + STM32H5_RCC_APB2RSTR_OFFSET) +#define STM32H5_RCC_APB3RSTR (STM32H5_RCC_BASE + STM32H5_RCC_APB3RSTR_OFFSET) +#define STM32H5_RCC_AHB1ENR (STM32H5_RCC_BASE + STM32H5_RCC_AHB1ENR_OFFSET) +#define STM32H5_RCC_AHB2ENR (STM32H5_RCC_BASE + STM32H5_RCC_AHB2ENR_OFFSET) +#define STM32H5_RCC_AHB4ENR (STM32H5_RCC_BASE + STM32H5_RCC_AHB4ENR_OFFSET) +#define STM32H5_RCC_APB1LENR (STM32H5_RCC_BASE + STM32H5_RCC_APB1LENR_OFFSET) +#define STM32H5_RCC_APB1HENR (STM32H5_RCC_BASE + STM32H5_RCC_APB1HENR_OFFSET) +#define STM32H5_RCC_APB2ENR (STM32H5_RCC_BASE + STM32H5_RCC_APB2ENR_OFFSET) +#define STM32H5_RCC_APB3ENR (STM32H5_RCC_BASE + STM32H5_RCC_APB3ENR_OFFSET) +#define STM32H5_RCC_AHB1LPENR (STM32H5_RCC_BASE + STM32H5_RCC_AHB1LPENR_OFFSET) +#define STM32H5_RCC_AHB2LPENR (STM32H5_RCC_BASE + STM32H5_RCC_AHB2LPENR_OFFSET) +#define STM32H5_RCC_AHB4LPENR (STM32H5_RCC_BASE + STM32H5_RCC_AHB4LPENR_OFFSET) +#define STM32H5_RCC_APB1LPENR (STM32H5_RCC_BASE + STM32H5_RCC_APB1LPENR1_OFFSET) +#define STM32H5_RCC_APB1HPENR (STM32H5_RCC_BASE + STM32H5_RCC_APB1LPENR2_OFFSET) +#define STM32H5_RCC_APB2LPENR (STM32H5_RCC_BASE + STM32H5_RCC_APB2LPENR_OFFSET) +#define STM32H5_RCC_APB3LPENR (STM32H5_RCC_BASE + STM32H5_RCC_APB3LPENR_OFFSET) +#define STM32H5_RCC_CCIPR1 (STM32H5_RCC_BASE + STM32H5_RCC_CCIPR1_OFFSET) +#define STM32H5_RCC_CCIPR2 (STM32H5_RCC_BASE + STM32H5_RCC_CCIPR2_OFFSET) +#define STM32H5_RCC_CCIPR3 (STM32H5_RCC_BASE + STM32H5_RCC_CCIPR3_OFFSET) +#define STM32H5_RCC_CCIPR4 (STM32H5_RCC_BASE + STM32H5_RCC_CCIPR4_OFFSET) +#define STM32H5_RCC_CCIPR5 (STM32H5_RCC_BASE + STM32H5_RCC_CCIPR5_OFFSET) +#define STM32H5_RCC_BDCR (STM32H5_RCC_BASE + STM32H5_RCC_BDCR_OFFSET) +#define STM32H5_RCC_RSR (STM32H5_RCC_BASE + STM32H5_RCC_RSR_OFFSET) +#define STM32H5_RCC_SECCFGR (STM32H5_RCC_BASE + STM32H5_RCC_SECCFGR_OFFSET) +#define STM32H5_RCC_PRIVCFGR (STM32H5_RCC_BASE + STM32H5_RCC_PRIVCFGR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Clock control register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ +#define RCC_CR_HSIKERON (1 << 2) /* Bit 2: HSI clock enable in Stop mode */ +#define RCC_CR_HSIDIV_SHIFT (3) /* Bit [4:3] HSI Divider */ +#define RCC_CR_HSIDIV_MASK (0x3 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV(n) (((n) << RCC_CR_HSIDIV_SHIFT & RCC_CR_HSIDIV_MASK)) /* m = 0 to 3 */ +#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI divider flag */ + +#define RCC_CR_CSION (1 << 8) /* Bit 8: CSI clock enable */ +#define RCC_CR_CSIRDY (1 << 9) /* Bit 9: CSI clock ready flag */ +#define RCC_CR_CSIKERON (1 << 10) /* Bit 10: CSI clock enable in Stop mode */ + +#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable */ +#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready flag */ + +#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE clock bypass */ +#define RCC_CR_HSECSSON (1 << 19) /* Bit 19: HSE clock security system enable */ +#define RCC_CR_HSEEXT (1 << 20) /* Bit 20: HSE external high speed clock + type in bypass mode */ +#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: PLL1 enable */ +#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: PLL1 clock ready flag */ +#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: PLL2 enable */ +#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: PLL2 clock ready flag */ +#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: PLL3 enable */ +#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: PLL3 clock ready flag */ + +/* HSI Calibration register */ + +#define RCC_HSICFGR_HSITRIM_SHIFT (16) /* Bits 22-16: Internal High Speed clock trimming */ +#define RCC_HSICFGR_HSITRIM_MASK (0x7f << RCC_HSICFGR_HSITRIM_SHIFT) +#define RCC_HSICFGR_HSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ +#define RCC_HSICFGR_HSICAL_MASK (0xfff << RCC_HSICFGR_HSICAL_SHIFT) + +/* Clock Recovery RC register */ + +#define RCC_CRRCR_HSI48CAL_SHIFT (0) /* Bits 9-0: Internal RC 48MHz Clock Calibration */ +#define RCC_CRRCR_HSI48CAL_MASK (0x3ff << RCC_CRRCR_HSI48CAL_SHIFT) + +/* CSI Calibration register */ + +#define RCC_CSICFGR_CSITRIM_SHIFT (16) /* Bits 21-16: Internal High Speed clock trimming */ +#define RCC_CSICFGR_CSITRIM_MASK (0x3f << RCC_CSICFGR_CSITRIM_SHIFT) +#define RCC_CSICFGR_CSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ +#define RCC_CSICFGR_CSICAL_MASK (0xff << RCC_CSICFGR_CSICAL_SHIFT) + +/* Clock configuration register 1 */ + +#define RCC_CFGR1_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ +#define RCC_CFGR1_SW_MASK (3 << RCC_CFGR1_SW_SHIFT) +# define RCC_CFGR1_SW_MSI (0 << RCC_CFGR1_SW_SHIFT) /* 00: MSI selected as system clock */ +# define RCC_CFGR1_SW_HSI16 (1 << RCC_CFGR1_SW_SHIFT) /* 00: HSI16 selected as system clock */ +# define RCC_CFGR1_SW_HSE (2 << RCC_CFGR1_SW_SHIFT) /* 01: HSE selected as system clock */ +# define RCC_CFGR1_SW_PLL (3 << RCC_CFGR1_SW_SHIFT) /* 10: PLL selected as system clock */ + +#define RCC_CFGR1_SWS_SHIFT (3) /* Bits 3-4: System Clock Switch Status */ +#define RCC_CFGR1_SWS_MASK (3 << RCC_CFGR1_SWS_SHIFT) +# define RCC_CFGR1_SWS_MSI (0 << RCC_CFGR1_SWS_SHIFT) /* 00: MSI oscillator used as system clock */ +# define RCC_CFGR1_SWS_HSI16 (1 << RCC_CFGR1_SWS_SHIFT) /* 00: HSI16 oscillator used as system clock */ +# define RCC_CFGR1_SWS_HSE (2 << RCC_CFGR1_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ +# define RCC_CFGR1_SWS_PLL (3 << RCC_CFGR1_SWS_SHIFT) /* 10: PLL used as system clock */ + +#define RCC_CFGR1_STOPWUCK (1 << 6) /* System clock selection after a wakeup from system stop */ +#define RCC_CFGR1_STOPKERWUCK (1 << 7) /* Kernel clock selection after a wakeup from system stop */ + + +#define RCC_CFGR1_RTCPRE_SHIFT (8) /* Bits 13-8: RTC prescaler */ +#define RCC_CFGR1_RTCPRE_MASK (0x3f << RCC_CFGR1_RTCPRE_SHIFT) +# define RCC_CFGR1_RTCPRE_HSE (0 << RCC_CFGR1_RTCPRE_SHIFT) /* 0xxx: HSE not divided */ +# define RCC_CFGR1_RTCPRE_HSEd2 (2 << RCC_CFGR1_RTCPRE_SHIFT) /* 10: HSE divided by 2 */ +# define RCC_CFGR1_RTCPRE_HSEd4 (4 << RCC_CFGR1_RTCPRE_SHIFT) /* 100: HSE divided by 4 */ +# define RCC_CFGR1_RTCPRE_HSEd8 (8 << RCC_CFGR1_RTCPRE_SHIFT) /* 1000: HSE divided by 8 */ +# define RCC_CFGR1_RTCPRE_HSEd16 (16 << RCC_CFGR1_RTCPRE_SHIFT) /* 10000: HSE divided by 16 */ +# define RCC_CFGR1_RTCPRE_HSEd32 (32 << RCC_CFGR1_RTCPRE_SHIFT) /* 100000: HSE divided by 32 */ +# define RCC_CFGR1_RTCPRE_HSEd63 (63 << RCC_CFGR1_RTCPRE_SHIFT) /* 111111: HSE divided by 63 */ + +#define RCC_CFGR1_TIMPRE (1 << 15) /* timers clocks prescaler selection */ + +#define RCC_CFGR1_MCO1PRE_SHIFT (18) /* Bits 21-18: MCO1 Prescaler */ +#define RCC_CFGR1_MCO1PRE_MASK (0xf << RCC_CFGR1_MCO1PRE_SHIFT) +# define RCC_CFGR1_MCO1PRE_MCO1 (0 << RCC_CFGR1_MCO1PRE_SHIFT) /* 0xx: MCO1 not divided */ +# define RCC_CFGR1_MCO1PRE_MCO1d2 (2 << RCC_CFGR1_MCO1PRE_SHIFT) /* 10: MCO1 divided by 2 */ +# define RCC_CFGR1_MCO1PRE_MCO1d4 (4 << RCC_CFGR1_MCO1PRE_SHIFT) /* 100: MCO1 divided by 4 */ +# define RCC_CFGR1_MCO1PRE_MCO1d8 (8 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1000: MCO1 divided by 8 */ +# define RCC_CFGR1_MCO1PRE_MCO1d15 (15 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1111: MCO1 divided by 15 */ + +#define RCC_CFGR1_MCO1SEL_SHIFT (22) /* Bits 24-22: Microcontroller Clock Output1 */ +#define RCC_CFGR1_MCO1SEL_MASK (0x7 << RCC_CFGR1_MCO1SEL_SHIFT) +# define RCC_CFGR1_MCO1SEL_HSI (0 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0000: HSI clock selected */ +# define RCC_CFGR1_MCO1SEL_LSE (1 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0001: LSE clock selected */ +# define RCC_CFGR1_MCO1SEL_HSE (2 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0010: HSE clock selected */ +# define RCC_CFGR1_MCO1SEL_PLL1 (3 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0011: Main PLL1 selected */ +# define RCC_CFGR1_MCO1SEL_HSI48 (4 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0100: HSI48 clock selected */ + +#define RCC_CFGR1_MCO2PRE_SHIFT (25) /* Bits 28-25: MCO2 Prescaler */ +#define RCC_CFGR1_MCO2PRE_MASK (0xf << RCC_CFGR1_MCO2PRE_SHIFT) +# define RCC_CFGR1_MCO2PRE_MCO2 (0 << RCC_CFGR1_MCO2PRE_SHIFT) /* 0xx: MCO2 not divided */ +# define RCC_CFGR1_MCO2PRE_MCO2d2 (2 << RCC_CFGR1_MCO2PRE_SHIFT) /* 10: MCO2 divided by 2 */ +# define RCC_CFGR1_MCO2PRE_MCO2d4 (4 << RCC_CFGR1_MCO2PRE_SHIFT) /* 100: MCO2 divided by 4 */ +# define RCC_CFGR1_MCO2PRE_MCO2d8 (8 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1000: MCO2 divided by 8 */ +# define RCC_CFGR1_MCO2PRE_MCO2d15 (15 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1111: MCO2 divided by 15 */ + +#define RCC_CFGR1_MCO2SEL_SHIFT (29) /* Bits 31-29: Microcontroller Clock Output1 */ +#define RCC_CFGR1_MCO2SEL_MASK (0x7 << RCC_CFGR1_MCO2SEL_SHIFT) +# define RCC_CFGR1_MCO2SEL_SYSCLLK (0 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0000: Main SYSCLLK selected */ +# define RCC_CFGR1_MCO2SEL_PLL2 (1 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0001: Main PLL2 selected */ +# define RCC_CFGR1_MCO2SEL_HSE (2 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0010: HSE clock selected */ +# define RCC_CFGR1_MCO2SEL_PLL1 (3 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0011: Main PLL1 selected */ +# define RCC_CFGR1_MCO2SEL_CSI (4 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0100: CSI clock selected */ +# define RCC_CFGR1_MCO2SEL_LSI (5 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0101: LSI clock selected */ + +/* Clock configuration register 2 */ + +#define RCC_CFGR2_HPRE_SHIFT (0) /* Bits 3-0: HPRE Prescaler */ +#define RCC_CFGR2_HPRE_MASK (0xf << RCC_CFGR2_HPRE_SHIFT) +# define RCC_CFGR2_HPRE_SYSCLK (0 << RCC_CFGR2_HPRE_SHIFT) /* 0xx: SYSCLK not divided */ +# define RCC_CFGR2_HPRE_SYSCLKd2 (8 << RCC_CFGR2_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR2_HPRE_SYSCLKd4 (9 << RCC_CFGR2_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR2_HPRE_SYSCLKd8 (10 << RCC_CFGR2_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR2_HPRE_SYSCLKd16 (11 << RCC_CFGR2_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR2_HPRE_SYSCLKd64 (12 << RCC_CFGR2_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR2_HPRE_SYSCLKd128 (13 << RCC_CFGR2_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR2_HPRE_SYSCLKd256 (14 << RCC_CFGR2_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR2_HPRE_SYSCLKd512 (15 << RCC_CFGR2_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ + +#define RCC_CFGR2_PPRE1_SHIFT (0) /* Bits 6-4: PPRE1 Prescaler */ +#define RCC_CFGR2_PPRE1_MASK (0x7 << RCC_CFGR2_PPRE1_SHIFT) +# define RCC_CFGR2_PPRE1_HCLK1 (0 << RCC_CFGR2_PPRE1_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE1_HCLK1d2 (4 << RCC_CFGR2_PPRE1_SHIFT) /* 1000: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE1_HCLK1d4 (5 << RCC_CFGR2_PPRE1_SHIFT) /* 1001: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE1_HCLK1d8 (6 << RCC_CFGR2_PPRE1_SHIFT) /* 1010: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE1_HCLK1d16 (7 << RCC_CFGR2_PPRE1_SHIFT) /* 1011: HCLK1 divided by 16 */ + +#define RCC_CFGR2_PPRE2_SHIFT (8) /* Bits 10-8: PPRE2 Prescaler */ +#define RCC_CFGR2_PPRE2_MASK (0x7 << RCC_CFGR2_PPRE2_SHIFT) +# define RCC_CFGR2_PPRE2_HCLK1 (0 << RCC_CFGR2_PPRE2_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE2_HCLK1d2 (4 << RCC_CFGR2_PPRE2_SHIFT) /* 1000: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE2_HCLK1d4 (5 << RCC_CFGR2_PPRE2_SHIFT) /* 1001: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE2_HCLK1d8 (6 << RCC_CFGR2_PPRE2_SHIFT) /* 1010: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE2_HCLK1d16 (7 << RCC_CFGR2_PPRE2_SHIFT) /* 1011: HCLK1 divided by 16 */ + +#define RCC_CFGR2_PPRE3_SHIFT (12) /* Bits 14-12: PPRE3 Prescaler */ +#define RCC_CFGR2_PPRE3_MASK (0x7 << RCC_CFGR2_PPRE3_SHIFT) +# define RCC_CFGR2_PPRE3_HCLK1 (0 << RCC_CFGR2_PPRE3_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE3_HCLK1d2 (4 << RCC_CFGR2_PPRE3_SHIFT) /* 1000: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE3_HCLK1d4 (5 << RCC_CFGR2_PPRE3_SHIFT) /* 1001: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE3_HCLK1d8 (6 << RCC_CFGR2_PPRE3_SHIFT) /* 1010: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE3_HCLK1d16 (7 << RCC_CFGR2_PPRE3_SHIFT) /* 1011: HCLK1 divided by 16 */ + +#define RCC_CFGR2_AHB1DIS (1 << 16) /* AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS (1 << 17) /* AHB2 clock disable */ +#define RCC_CFGR2_AHB4DIS (1 << 19) /* AHB4 clock disable */ +#define RCC_CFGR2_APB1DIS (1 << 20) /* APB1 clock disable */ +#define RCC_CFGR2_APB2DIS (1 << 21) /* APB2 clock disable */ +#define RCC_CFGR2_APB3DIS (1 << 22) /* APB3 clock disable */ + +/* PLL1 configuration register */ + +#define RCC_PLL1CFGR_PLL1SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL1CFGR_PLL1SRC_MASK (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) +# define RCC_PLL1CFGR_PLL1SRC_NONE (0 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL1CFGR_PLL1SRC_HSI (1 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL1CFGR_PLL1SRC_CSI (2 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL1CFGR_PLL1SRC_HSE (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL1CFGR_PLL1RGE_MASK (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) +# define RCC_PLL1CFGR_PLL1RGE_1_2M (0 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL1CFGR_PLL1RGE_2_4M (1 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL1CFGR_PLL1RGE_4_8M (2 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ +# define RCC_PLL1CFGR_PLL1RGE_8_16M (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ + +#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) /* PLL1 Fractional Latch Enable */ +#define RCC_PLL1CFGR_PLL1VCOSEL (1 << 5) /* PLL1 VCO Selection */ + +#define RCC_PLL1CFGR_PLL1M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL1CFGR_PLL1M_MASK (0x3f << RCC_PLL1CFGR_PLL1M_SHIFT) +# define RCC_PLL1CFGR_PLL1M(n) ((n) << RCC_PLL1CFGR_PLL1M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL1CFGR_PLL1PEN (1 << 16) /* PLL1 DIVP divder output enable */ +#define RCC_PLL1CFGR_PLL1QEN (1 << 17) /* PLL1 DIVQ divder output enable */ +#define RCC_PLL1CFGR_PLL1REN (1 << 18) /* PLL1 DIVR divder output enable */ + +/* PLL2 configuration register */ + +#define RCC_PLL2CFGR_PLL2SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL2CFGR_PLL2SRC_MASK (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) +# define RCC_PLL2CFGR_PLL2SRC_NONE (0 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL2CFGR_PLL2SRC_HSI (1 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL2CFGR_PLL2SRC_CSI (2 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL2CFGR_PLL2SRC_HSE (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL2CFGR_PLL2RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL2CFGR_PLL2RGE_MASK (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) +# define RCC_PLL2CFGR_PLL2RGE_1_2M (0 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL2CFGR_PLL2RGE_2_4M (1 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL2CFGR_PLL2RGE_4_8M (2 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ +# define RCC_PLL2CFGR_PLL2RGE_8_16M (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ + +#define RCC_PLL2CFGR_PLL2FRACEN (1 << 4) /* PLL2 Fractional Latch Enable */ +#define RCC_PLL2CFGR_PLL2VCOSEL (1 << 5) /* PLL2 VCO Selection */ + +#define RCC_PLL2CFGR_PLL2M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL2CFGR_PLL2M_MASK (0x3f << RCC_PLL2CFGR_PLL2M_SHIFT) +# define RCC_PLL2CFGR_PLL2M(n) ((n) << RCC_PLL2CFGR_PLL2M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL2CFGR_PLL2PEN (1 << 16) /* PLL2 DIVP divder output enable */ +#define RCC_PLL2CFGR_PLL2QEN (1 << 17) /* PLL2 DIVQ divder output enable */ +#define RCC_PLL2CFGR_PLL2REN (1 << 18) /* PLL2 DIVR divder output enable */ + +/* PLL3 configuration register */ + +#define RCC_PLL3CFGR_PLL3SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL3CFGR_PLL3SRC_MASK (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) +# define RCC_PLL3CFGR_PLL3SRC_NONE (0 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL3CFGR_PLL3SRC_HSI (1 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL3CFGR_PLL3SRC_CSI (2 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL3CFGR_PLL3SRC_HSE (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL3CFGR_PLL3RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL3CFGR_PLL3RGE_MASK (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) +# define RCC_PLL3CFGR_PLL3RGE_1_2M (0 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL3CFGR_PLL3RGE_2_4M (1 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL3CFGR_PLL3RGE_4_8M (2 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ +# define RCC_PLL3CFGR_PLL3RGE_8_16M (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ + +#define RCC_PLL3CFGR_PLL3FRACEN (1 << 4) /* PLL3 Fractional Latch Enable */ +#define RCC_PLL3CFGR_PLL3VCOSEL (1 << 5) /* PLL3 VCO Selection */ + +#define RCC_PLL3CFGR_PLL3M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL3CFGR_PLL3M_MASK (0x3f << RCC_PLL3CFGR_PLL3M_SHIFT) +# define RCC_PLL3CFGR_PLL3M(n) ((n) << RCC_PLL3CFGR_PLL3M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL3CFGR_PLL3PEN (1 << 16) /* PLL3 DIVP divder output enable */ +#define RCC_PLL3CFGR_PLL3QEN (1 << 17) /* PLL3 DIVQ divder output enable */ +#define RCC_PLL3CFGR_PLL3REN (1 << 18) /* PLL3 DIVR divder output enable */ + +/* PLL1 dividers register */ + +#define RCC_PLL1DIVR_PLL1N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL1DIVR_PLL1N_MASK (0x1ff << RCC_PLL1DIVR_PLL1N_SHIFT) +# define RCC_PLL1DIVR_PLL1N(n) ((n-1) << RCC_PLL1DIVR_PLL1N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL1DIVR_PLL1P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL1DIVR_PLL1P_MASK (0x7f << RCC_PLL1DIVR_PLL1P_SHIFT) +# define RCC_PLL1DIVR_PLL1P(n) ((n-1) << RCC_PLL1DIVR_PLL1P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL1DIVR_PLL1Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL1DIVR_PLL1Q_MASK (0x7f << RCC_PLL1DIVR_PLL1Q_SHIFT) +# define RCC_PLL1DIVR_PLL1Q(n) ((n-1) << RCC_PLL1DIVR_PLL1Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL1DIVR_PLL1R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL1DIVR_PLL1R_MASK (0x7f << RCC_PLL1DIVR_PLL1R_SHIFT) +# define RCC_PLL1DIVR_PLL1R(n) ((n-1) << RCC_PLL1DIVR_PLL1R_SHIFT) /* m = 1..128 */ + +/* PLL2 dividers register */ + +#define RCC_PLL2DIVR_PLL2N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL2DIVR_PLL2N_MASK (0x1ff << RCC_PLL2DIVR_PLL2N_SHIFT) +# define RCC_PLL2DIVR_PLL2N(n) ((n-1) << RCC_PLL2DIVR_PLL2N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL2DIVR_PLL2P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL2DIVR_PLL2P_MASK (0x7f << RCC_PLL2DIVR_PLL2P_SHIFT) +# define RCC_PLL2DIVR_PLL2P(n) ((n-1) << RCC_PLL2DIVR_PLL2P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL2DIVR_PLL2Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL2DIVR_PLL2Q_MASK (0x7f << RCC_PLL2DIVR_PLL2Q_SHIFT) +# define RCC_PLL2DIVR_PLL2Q(n) ((n-1) << RCC_PLL2DIVR_PLL2Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL2DIVR_PLL2R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL2DIVR_PLL2R_MASK (0x7f << RCC_PLL2DIVR_PLL2R_SHIFT) +# define RCC_PLL2DIVR_PLL2R(n) ((n-1) << RCC_PLL2DIVR_PLL2R_SHIFT) /* m = 1..128 */ + +/* PLL3 dividers register */ + +#define RCC_PLL3DIVR_PLL3N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL3DIVR_PLL3N_MASK (0x1ff << RCC_PLL3DIVR_PLL3N_SHIFT) +# define RCC_PLL3DIVR_PLL3N(n) ((n-1) << RCC_PLL3DIVR_PLL3N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL3DIVR_PLL3P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL3DIVR_PLL3P_MASK (0x7f << RCC_PLL3DIVR_PLL3P_SHIFT) +# define RCC_PLL3DIVR_PLL3P(n) ((n-1) << RCC_PLL3DIVR_PLL3P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL3DIVR_PLL3Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL3DIVR_PLL3Q_MASK (0x7f << RCC_PLL3DIVR_PLL3Q_SHIFT) +# define RCC_PLL3DIVR_PLL3Q(n) ((n-1) << RCC_PLL3DIVR_PLL3Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL3DIVR_PLL3R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL3DIVR_PLL3R_MASK (0x7f << RCC_PLL3DIVR_PLL3R_SHIFT) +# define RCC_PLL3DIVR_PLL3R(n) ((n-1) << RCC_PLL3DIVR_PLL3R_SHIFT) /* m = 1..128 */ + + +/* Clock interrupt enable register */ + +#define RCC_CIER_LSIRDYIE (1 << 0) /* Bit 0: LSI Ready Interrupt Enable */ +#define RCC_CIER_LSERDYIE (1 << 1) /* Bit 1: LSE Ready Interrupt Enable */ +#define RCC_CIER_CSIRDYIE (1 << 2) /* Bit 2: CSI Ready Interrupt Enable */ +#define RCC_CIER_HSIRDYIE (1 << 3) /* Bit 3: HSI Ready Interrupt Enable */ +#define RCC_CIER_HSERDYIE (1 << 4) /* Bit 4: HSE Ready Interrupt Enable */ +#define RCC_CIER_HSI48RDYIE (1 << 5) /* Bit 5: HSI48 Ready Interrupt Enable */ +#define RCC_CIER_PLL1RDYIE (1 << 6) /* Bit 6: PLL1 Ready Interrupt Enable */ +#define RCC_CIER_PLL2RDYIE (1 << 7) /* Bit 7: PLL2 Ready Interrupt Enable */ +#define RCC_CIER_PLL3RDYIE (1 << 8) /* Bit 8: PLL3 Ready Interrupt Enable */ + +/* Clock interrupt flag register */ + +#define RCC_CIFR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ +#define RCC_CIFR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ +#define RCC_CIFR_CSIRDYF (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ +#define RCC_CIFR_HSIRDYF (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ +#define RCC_CIFR_HSERDYF (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ +#define RCC_CIFR_HSI48RDYF (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ +#define RCC_CIFR_PLL1RDYF (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ +#define RCC_CIFR_PLL2RDYF (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ +#define RCC_CIFR_PLL3RDYF (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ +#define RCC_CIFR_HSECSSF (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ + +/* Clock interrupt clear register */ + +#define RCC_CICR_LSIRDYC (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ +#define RCC_CICR_LSERDYC (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ +#define RCC_CICR_CSIRDYC (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ +#define RCC_CICR_HSIRDYC (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ +#define RCC_CICR_HSERDYC (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ +#define RCC_CICR_HSI48RDYC (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ +#define RCC_CICR_PLL1RDYC (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ +#define RCC_CICR_PLL2RDYC (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ +#define RCC_CICR_PLL3RDYC (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ +#define RCC_CICR_HSECSSC (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_GPDMA1RST (1 << 0) /* Bit 0: GPDMA1 reset */ +#define RCC_AHB1RSTR_GPDMA2RST (1 << 1) /* Bit 1: GPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */ +#define RCC_AHB1RSTR_CORDICRST (1 << 14) /* Bit 14: CORDIC reset */ +#define RCC_AHB1RSTR_FMACRST (1 << 15) /* Bit 15: FMAC reset */ +#define RCC_AHB1RSTR_RAMCFGRST (1 << 17) /* Bit 17: RAMCFG reset */ +#define RCC_AHB1RSTR_ETHRST (1 << 19) /* Bit 19: ETH reset */ + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_GPIORST(n) (1 << (n)) +#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ +#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ +#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ +#define RCC_AHB2RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */ +#define RCC_AHB2RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */ +#define RCC_AHB2RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */ +#define RCC_AHB2RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ +#define RCC_AHB2RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ +#define RCC_AHB2RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */ +#define RCC_AHB2RSTR_ADCRST (1 << 10) /* Bit 10: ADC interface reset (common to all ADCs) */ +#define RCC_AHB2RSTR_DACRST (1 << 11) /* Bit 11: DAC Block reset */ +#define RCC_AHB2RSTR_DCMI_PSSIRST (1 << 12) /* Bit 12: Digital Camera Interface block reset */ +#define RCC_AHB2RSTR_AESRST (1 << 16) /* Bit 16: AES Cryptographic module reset */ +#define RCC_AHB2RSTR_HASHRST (1 << 17) /* Bit 17: HASH block reset */ +#define RCC_AHB2RSTR_RNGRST (1 << 18) /* Bit 18: Random number generator module reset */ +#define RCC_AHB2RSTR_PKARST (1 << 19) /* Bit 19: Public Key Accelerator module reset */ +#define RCC_AHB2RSTR_SAESRST (1 << 20) /* Bit 20: SAES block reset */ + +/* AHB4 peripheral reset register */ + +#define RCC_AHB4RSTR_OTFDEC1RST (1 << 7) /* Bit 0: OTFDEC1 block reset */ +#define RCC_AHB4RSTR_SDMMC1RST (1 << 11) /* Bit 11: SDMMC1RST blocks reset */ +#define RCC_AHB4RSTR_SDMMC2RST (1 << 12) /* Bit 12: SDMMC2RST blocks reset */ +#define RCC_AHB4RSTR_FMCRST (1 << 16) /* Bit 16: FMC block reset */ +#define RCC_AHB4RSTR_OSPI1RST (1 << 20) /* Bit 20: OCTOSPI1 block reset */ + +/* APB1 Peripheral reset register 1 */ + +#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ +#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ +#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ +#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* Bit 5: TIM12 reset */ +#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* Bit 5: TIM13 reset */ +#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* Bit 5: TIM14 reset */ +#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* Bit 15: SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST (1 << 17) /* Bit 17: USART2 reset */ +#define RCC_APB1LRSTR_USART3RST (1 << 18) /* Bit 18: USART3 reset */ +#define RCC_APB1LRSTR_UART4RST (1 << 19) /* Bit 19: UART4 reset */ +#define RCC_APB1LRSTR_UART5RST (1 << 20) /* Bit 20: UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* Bit 22: I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST (1 << 23) /* Bit 23: I3C1 reset */ +#define RCC_APB1LRSTR_CRSRST (1 << 24) /* Bit 24: CRS reset */ +#define RCC_APB1LRSTR_USART6RST (1 << 25) /* Bit 25: USART6 reset */ +#define RCC_APB1LRSTR_USART10RST (1 << 26) /* Bit 26: USART10 reset */ +#define RCC_APB1LRSTR_USART11RST (1 << 27) /* Bit 27: USART11 reset */ +#define RCC_APB1LRSTR_CECRST (1 << 28) /* Bit 28: CEC reset */ +#define RCC_APB1LRSTR_UART7RST (1 << 30) /* Bit 30: UART7 reset */ +#define RCC_APB1LRSTR_UART8RST (1 << 31) /* Bit 31: UART8 reset */ + +/* APB1 Peripheral reset register 2 */ + +#define RCC_APB1HRSTR_UART9RST (1 << 0) /* Bit 0: UART9 reset */ +#define RCC_APB1HRSTR_UART12RST (1 << 1) /* Bit 1: UART12 reset */ +#define RCC_APB1HRSTR_DTSRST (1 << 3) /* Bit 3: DTS reset */ +#define RCC_APB1HRSTR_LPTIM2RST (1 << 5) /* Bit 5: Low-power Timer 2 reset */ +#define RCC_APB1HRSTR_FDCANRST (1 << 9) /* Bit 9: FDCAN reset */ +#define RCC_APB1HRSTR_UCPD1RST (1 << 23) /* Bit 23: UCPD1 reset */ + +/* APB2 Peripheral reset register */ + +#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 reset */ +#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */ +#define RCC_APB2RSTR_SPI4RST (1 << 19) /* Bit 19: SPI4 reset */ +#define RCC_APB2RSTR_SPI67RST (1 << 20) /* Bit 20: SPI6 reset */ +#define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */ +#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 22: SAI2 reset */ +#define RCC_APB2RSTR_USBRST (1 << 24) /* Bit 24: USB reset */ + +/* APB3 Peripheral reset register */ + +#define RCC_APB3RSTR_SPI5RST (1 << 5) /* Bit 5: SPI5 reset */ +#define RCC_APB3RSTR_LPUART1RST (1 << 6) /* Bit 6: LPUART1 reset */ +#define RCC_APB3RSTR_I2C3RST (1 << 7) /* Bit 7: I2C3 reset */ +#define RCC_APB3RSTR_I2C4RST (1 << 8) /* Bit 8: I2C4 reset */ +#define RCC_APB3RSTR_I3C2RST (1 << 9) /* Bit 9: I3C2 reset */ +#define RCC_APB3RSTR_LPTIM1RST (1 << 11) /* Bit 11: LPTIM1 reset */ +#define RCC_APB3RSTR_LPTIM3RST (1 << 12) /* Bit 12: LPTIM3 reset */ +#define RCC_APB3RSTR_LPTIM4RST (1 << 13) /* Bit 13: LPTIM4 reset */ +#define RCC_APB3RSTR_LPTIM5RST (1 << 14) /* Bit 14: LPTIM5 reset */ +#define RCC_APB3RSTR_LPTIM6RST (1 << 15) /* Bit 15: LPTIM6 reset */ +#define RCC_APB3RSTR_VREFRST (1 << 20) /* Bit 20: VREF reset */ + +/* AHB1 Peripheral Clock enable register */ + +#define RCC_AHB1ENR_GPDMA1EN (1 << 0) /* Bit 0: GPDMA1 clock enable */ +#define RCC_AHB1ENR_GPDMA2EN (1 << 1) /* Bit 1: GPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash Interace clock enable */ +#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN (1 << 14) /* Bit 14: CORDIC clock enable */ +#define RCC_AHB1ENR_FMACEN (1 << 15) /* Bit 15: FMAC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN (1 << 17) /* Bit 17: RAMCFG clock enable */ +#define RCC_AHB1ENR_ETHEN (1 << 19) /* Bit 19: ETH clock enable */ +#define RCC_AHB1ENR_ETHTXEN (1 << 20) /* Bit 20: ETH TX clock enable */ +#define RCC_AHB1ENR_ETHRXEN (1 << 21) /* Bit 21: ETH RX clock enable */ +#define RCC_AHB1ENR_TZSC1EN (1 << 24) /* Bit 24: TZSC1 clock enable */ +#define RCC_AHB1ENR_BKPRAMEN (1 << 28) /* Bit 28: BKPRAM clock enable */ +#define RCC_AHB1ENR_DCACHEEN (1 << 30) /* Bit 25: DCACHE clock enable */ +#define RCC_AHB1ENR_SRAM1EN (1 << 31) /* Bit 25: SRAM1 clock enable */ + + +/* AHB2 Peripheral Clock enable register */ + +#define RCC_AHB2ENR_GPIOEN(n) (1 << (n)) +#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */ +#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */ +#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */ +#define RCC_AHB2ENR_GPIODEN (1 << 3) /* Bit 3: IO port D enable */ +#define RCC_AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E enable */ +#define RCC_AHB2ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F enable */ +#define RCC_AHB2ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G enable */ +#define RCC_AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H enable */ +#define RCC_AHB2ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I enable */ +#define RCC_AHB2ENR_ADCEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ +#define RCC_AHB2ENR_DAC1EN (1 << 11) /* Bit 11: DAC clock enable */ +#define RCC_AHB2ENR_DCMI_PSSIEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ +#define RCC_AHB2ENR_AESEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ +#define RCC_AHB2ENR_HASHEN (1 << 17) /* Bit 17: HASH module enable */ +#define RCC_AHB2ENR_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */ +#define RCC_AHB2ENR_PKAEN (1 << 19) /* Bit 19: PKA clock enable */ +#define RCC_AHB2ENR_SAESEN (1 << 20) /* Bit 20: SAES clock enable */ +#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* Bit 30: SRAM2 clock enable */ +#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* Bit 30: SRAM2 clock enable */ + +/* AHB4 Peripheral Clock enable register */ + +#define RCC_AHB4ENR_OTFDEC1EN (1 << 7) /* Bit 7: On-the-fly decryption module clock enable */ +#define RCC_AHB4ENR_SDMMC1EN (1 << 11) /* Bit 11: SDMMC1 clock enable */ +#define RCC_AHB4ENR_SDMMC2EN (1 << 12) /* Bit 12: SDMMC2 clock enable */ +#define RCC_AHB4ENR_FMCEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ +#define RCC_AHB4ENR_OSPI1EN (1 << 20) /* Bit 20: OCTOSPI1 module enable */ + +/* APB1 Peripheral clock enable register 1 */ + +#define RCC_APB1LENR_TIM2EN (1 << 0) /* Bit 0: TIM2 clock enable */ +#define RCC_APB1LENR_TIM3EN (1 << 1) /* Bit 1: TIM3 clock enable */ +#define RCC_APB1LENR_TIM4EN (1 << 2) /* Bit 2: TIM4 clock enable */ +#define RCC_APB1LENR_TIM5EN (1 << 3) /* Bit 3: TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN (1 << 4) /* Bit 4: TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN (1 << 5) /* Bit 5: TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN (1 << 6) /* Bit 5: TIM12 clock enable */ +#define RCC_APB1LENR_TIM13EN (1 << 7) /* Bit 5: TIM13 clock enable */ +#define RCC_APB1LENR_TIM14EN (1 << 8) /* Bit 5: TIM14 clock enable */ +#define RCC_APB1LENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN (1 << 17) /* Bit 17: USART2 clock enable */ +#define RCC_APB1LENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */ +#define RCC_APB1LENR_UART4EN (1 << 19) /* Bit 19: UART4 clock enable */ +#define RCC_APB1LENR_UART5EN (1 << 20) /* Bit 20: UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN (1 << 23) /* Bit 23: I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN (1 << 24) /* Bit 24: CRS clock enable */ +#define RCC_APB1LENR_USART6EN (1 << 25) /* Bit 25: USART6 clock enable */ +#define RCC_APB1LENR_USART10EN (1 << 26) /* Bit 26: USART10 clock enable */ +#define RCC_APB1LENR_USART11EN (1 << 27) /* Bit 27: USART11 clock enable */ +#define RCC_APB1LENR_CECEN (1 << 28) /* Bit 28: CEC clock enable */ +#define RCC_APB1LENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */ +#define RCC_APB1LENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */ + +/* APB1 Peripheral clock enable register 2 */ + +#define RCC_APB1HENR_UART9EN (1 << 0) /* Bit 0: UART9 clock enable */ +#define RCC_APB1HENR_UART12EN (1 << 1) /* Bit 1: UART12 clock enable */ +#define RCC_APB1HENR_DTSEN (1 << 3) /* Bit 3: DTS clock enable */ +#define RCC_APB1HENR_LPTIM2EN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable */ +#define RCC_APB1HENR_FDCANEN (1 << 9) /* Bit 9: FDCAN clock enable */ +#define RCC_APB1HENR_UCPD1EN (1 << 23) /* Bit 23: UCPD1 clock enable */ + +/* APB2 Peripheral clock enable register */ + +#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 clock enable */ +#define RCC_APB2ENR_SPI4EN (1 << 19) /* Bit 19: SPI4 clock enable */ +#define RCC_APB2ENR_SPI67EN (1 << 20) /* Bit 20: SPI6 clock enable */ +#define RCC_APB2ENR_SAI1EN (1 << 21) /* Bit 21: SAI1 clock enable */ +#define RCC_APB2ENR_SAI2EN (1 << 22) /* Bit 22: SAI2 clock enable */ +#define RCC_APB2ENR_USBEN (1 << 24) /* Bit 24: USB clock enable */ + +/* APB3 Peripheral clock enable register */ + +#define RCC_APB3ENR_SBSEN (1 << 1) /* Bit 1: SBS clock enable */ +#define RCC_APB3ENR_SPI5EN (1 << 5) /* Bit 5: SPI5 clock enable */ +#define RCC_APB3ENR_LPUART1EN (1 << 6) /* Bit 6: LPUART1 clock enable */ +#define RCC_APB3ENR_I2C3EN (1 << 7) /* Bit 7: I2C3 clock enable */ +#define RCC_APB3ENR_I2C4EN (1 << 8) /* Bit 8: I2C4 clock enable */ +#define RCC_APB3ENR_I3C2EN (1 << 9) /* Bit 9: I3C2 clock enable */ +#define RCC_APB3ENR_LPTIM1EN (1 << 11) /* Bit 11: LPTIM1 clock enable */ +#define RCC_APB3ENR_LPTIM3EN (1 << 12) /* Bit 12: LPTIM3 clock enable */ +#define RCC_APB3ENR_LPTIM4EN (1 << 13) /* Bit 13: LPTIM4 clock enable */ +#define RCC_APB3ENR_LPTIM5EN (1 << 14) /* Bit 14: LPTIM5 clock enable */ +#define RCC_APB3ENR_LPTIM6EN (1 << 15) /* Bit 15: LPTIM6 clock enable */ +#define RCC_APB3ENR_VREFEN (1 << 20) /* Bit 20: VREF clock enable */ +#define RCC_APB3ENR_RTCAPBEN (1 << 21) /* Bit 21: RTCABP clock enable */ + +/* RCC AHB1 Sleep and Stop modes peripheral clock enable register */ + +#define RCC_AHB1LPENR_GPDMA1LPEN (1 << 0) /* Bit 0: GPDMA1 clock enable during sleep mode */ +#define RCC_AHB1LPENR_GPDMA2LPEN (1 << 1) /* Bit 1: GPDMA2 clock enable during sleep mode */ +#define RCC_AHB1LPENR_FLITFLPEN (1 << 8) /* Bit 8: Flash Interace clock enable during sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during sleep mode */ +#define RCC_AHB1LPENR_CORDICLPEN (1 << 14) /* Bit 14: CORDIC clock enable during sleep mode */ +#define RCC_AHB1LPENR_FMACLPEN (1 << 15) /* Bit 15: FMAC clock enable during sleep mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN (1 << 17) /* Bit 17: RAMCFG clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHLPEN (1 << 19) /* Bit 19: ETH clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHTXLPEN (1 << 20) /* Bit 20: ETH TX clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHRXLPEN (1 << 21) /* Bit 21: ETH RX clock enable during sleep mode */ +#define RCC_AHB1LPENR_TZSC1LPEN (1 << 24) /* Bit 24: TZSC1 clock enable during sleep mode */ +#define RCC_AHB1LPENR_BKPRAMLPEN (1 << 28) /* Bit 28: BKPRAM clock enable during sleep mode */ +#define RCC_AHB1LPENR_DCACHELPEN (1 << 30) /* Bit 25: DCACHE clock enable during sleep mode */ +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 31) /* Bit 25: SRAM1 clock enable during sleep mode */ + + +/* RCC AHB2 low power mode peripheral clock enable register */ + +#define RCC_AHB2LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during sleep mode */ +#define RCC_AHB2LPENR_ADCLPEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ +#define RCC_AHB2LPENR_DAC1LPEN (1 << 11) /* Bit 11: DAC clock enable during sleep mode */ +#define RCC_AHB2LPENR_DCMI_PSSILPEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ +#define RCC_AHB2LPENR_AESLPEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ +#define RCC_AHB2LPENR_HASHLPEN (1 << 17) /* Bit 17: HASH module enable */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 18) /* Bit 18: Random number generator module enable */ +#define RCC_AHB2LPENR_PKALPEN (1 << 19) /* Bit 19: PKA clock enable during sleep mode */ +#define RCC_AHB2LPENR_SAESLPEN (1 << 20) /* Bit 20: SAES clock enable during sleep mode */ +#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* Bit 30: SRAM2 clock enable during sleep mode */ +#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* Bit 30: SRAM2 clock enable during sleep mode */ + + +/* RCC AHB4 low power mode peripheral clock enable register */ + +#define RCC_AHB4LPENR_OTFDEC1LPEN (1 << 7) /* Bit 7: OTFDEC1 clock enable during sleep mode */ +#define RCC_AHB4LPENR_SDMMC1LPEN (1 << 11) /* Bit 11: SDMMC1 clock enable during sleep mode */ +#define RCC_AHB4LPENR_SDMMC2LPEN (1 << 12) /* Bit 12: SDMMC2 clock enable during sleep mode */ +#define RCC_AHB4LPENR_FMCLPEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ +#define RCC_AHB4LPENR_OSPI1LPEN (1 << 20) /* Bit 20: OCTOSPI1 module clock enable during sleep mode */ + +/* APB1 Peripheral clock enable register 1 */ + +#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM4 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM5 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM6 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM7 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 clock enable during sleep mode */ +#define RCC_APB1LLPENR_WWDGLPEN (1 << 11) /* Bit 11: WWDG clock enable during sleep mode */ +#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* Bit 17: USART2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* Bit 18: USART3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* Bit 19: UART4 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* Bit 20: UART5 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I3C1LPEN (1 << 23) /* Bit 23: I3C1 clock enable during sleep mode */ +#define RCC_APB1LLPENR_CRSLPEN (1 << 24) /* Bit 24: CRS clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART6LPEN (1 << 25) /* Bit 25: USART6 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART10LPEN (1 << 26) /* Bit 26: USART10 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART11LPEN (1 << 27) /* Bit 27: USART11 clock enable during sleep mode */ +#define RCC_APB1LLPENR_CECLPEN (1 << 28) /* Bit 28: CEC clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during sleep mode */ + +/* APB1 Peripheral clock enable register 2 */ + +#define RCC_APB1HLPENR_UART9LPEN (1 << 0) /* Bit 0: UART9 clock enable during sleep mode */ +#define RCC_APB1HLPENR_UART12LPEN (1 << 1) /* Bit 1: UART12 clock enable during sleep mode */ +#define RCC_APB1HLPENR_DTSLPEN (1 << 3) /* Bit 3: DTS clock enable during sleep mode */ +#define RCC_APB1HLPENR_LPTIM2LPEN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable during sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN (1 << 9) /* Bit 9: FDCAN clock enable during sleep mode */ +#define RCC_APB1HLPENR_UCPD1LPEN (1 << 23) /* Bit 23: UCPD1 clock enable during sleep mode */ + +/* APB2 Peripheral clock enable register */ + +#define RCC_APB2LPENR_TIM1LPEN (1 << 11) /* Bit 11: TIM1 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 13) /* Bit 13: TIM8 clock enable during sleep mode */ +#define RCC_APB2LPENR_USART1LPEN (1 << 14) /* Bit 14: USART1 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* Bit 16: TIM15 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* Bit 17: TIM16 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* Bit 18: TIM17 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 19) /* Bit 19: SPI4 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI67LPEN (1 << 20) /* Bit 20: SPI6 clock enable during sleep mode */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 21) /* Bit 21: SAI1 clock enable during sleep mode */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 22) /* Bit 22: SAI2 clock enable during sleep mode */ +#define RCC_APB2LPENR_USBLPEN (1 << 24) /* Bit 24: USB clock enable during sleep mode */ + +/* APB3 Peripheral clock enable register */ + +#define RCC_APB3LPENR_SBSLPEN (1 << 1) /* Bit 1: SBS clock enable during sleep mode */ +#define RCC_APB3LPENR_SPI5LPEN (1 << 5) /* Bit 5: SPI5 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPUART1LPEN (1 << 6) /* Bit 6: LPUART1 clock enable during sleep mode */ +#define RCC_APB3LPENR_I2C3LPEN (1 << 7) /* Bit 7: I2C3 clock enable during sleep mode */ +#define RCC_APB3LPENR_I2C4LPEN (1 << 8) /* Bit 8: I2C4 clock enable during sleep mode */ +#define RCC_APB3LPENR_I3C2LPEN (1 << 9) /* Bit 9: I3C2 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM1LPEN (1 << 11) /* Bit 11: LPTIM1 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM3LPEN (1 << 12) /* Bit 12: LPTIM3 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM4LPEN (1 << 13) /* Bit 13: LPTIM4 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM5LPEN (1 << 14) /* Bit 14: LPTIM5 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM6LPEN (1 << 15) /* Bit 15: LPTIM6 clock enable during sleep mode */ +#define RCC_APB3LPENR_VREFLPEN (1 << 20) /* Bit 20: VREF clock enable during sleep mode */ +#define RCC_APB3LPENR_RTCAPBLPEN (1 << 21) /* Bit 21: RTCABP clock enable during sleep mode */ + + +/* Kernel Clock Configuration register 1 */ + +#define RCC_CCIPR1_USART1SEL_SHIFT (0) +#define RCC_CCIPR1_USART1SEL_MASK (7 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_PLL2QCK (1 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_PLL3QCK (2 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_HSIKERCK (3 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_CSIKERCK (4 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_LSECK (5 << RCC_CCIPR1_USART1SEL_SHIFT) + +#define RCC_CCIPR1_USART2SEL_SHIFT (3) +#define RCC_CCIPR1_USART2SEL_MASK (7 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_PLL2QCK (1 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_PLL3QCK (2 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_HSIKERCK (3 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_CSIKERCK (4 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_LSECK (5 << RCC_CCIPR1_USART2SEL_SHIFT) + +#define RCC_CCIPR1_USART3SEL_SHIFT (6) +#define RCC_CCIPR1_USART3SEL_MASK (7 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_PLL2QCK (1 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_PLL3QCK (2 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_HSIKERCK (3 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_CSIKERCK (4 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_LSECK (5 << RCC_CCIPR1_USART3SEL_SHIFT) + +#define RCC_CCIPR1_UART4SEL_SHIFT (9) +#define RCC_CCIPR1_UART4SEL_MASK (7 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_PLL2QCK (1 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_PLL3QCK (2 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_HSIKERCK (3 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_CSIKERCK (4 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_LSECK (5 << RCC_CCIPR1_UART4SEL_SHIFT) + +#define RCC_CCIPR1_UART5SEL_SHIFT (12) +#define RCC_CCIPR1_UART5SEL_MASK (7 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_PLL2QCK (1 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_PLL3QCK (2 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_HSIKERCK (3 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_CSIKERCK (4 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_LSECK (5 << RCC_CCIPR1_UART5SEL_SHIFT) + +#define RCC_CCIPR1_UART6SEL_SHIFT (15) +#define RCC_CCIPR1_UART6SEL_MASK (7 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_PLL2QCK (1 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_PLL3QCK (2 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_HSIKERCK (3 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_CSIKERCK (4 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_LSECK (5 << RCC_CCIPR1_UART6SEL_SHIFT) + +#define RCC_CCIPR1_UART7SEL_SHIFT (18) +#define RCC_CCIPR1_UART7SEL_MASK (7 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_PLL2QCK (1 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_PLL3QCK (2 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_HSIKERCK (3 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_CSIKERCK (4 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_LSECK (5 << RCC_CCIPR1_UART7SEL_SHIFT) + +#define RCC_CCIPR1_UART8SEL_SHIFT (21) +#define RCC_CCIPR1_UART8SEL_MASK (7 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_PLL2QCK (1 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_PLL3QCK (2 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_HSIKERCK (3 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_CSIKERCK (4 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_LSECK (5 << RCC_CCIPR1_UART8SEL_SHIFT) + +#define RCC_CCIPR1_UART9SEL_SHIFT (24) +#define RCC_CCIPR1_UART9SEL_MASK (7 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_PLL2QCK (1 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_PLL3QCK (2 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_HSIKERCK (3 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_CSIKERCK (4 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_LSECK (5 << RCC_CCIPR1_UART9SEL_SHIFT) + +#define RCC_CCIPR1_USART10SEL_SHIFT (27) +#define RCC_CCIPR1_USART10SEL_MASK (7 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_PLL2QCK (1 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_PLL3QCK (2 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_HSIKERCK (3 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_CSIKERCK (4 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_LSECK (5 << RCC_CCIPR1_USART10SEL_SHIFT) + +#define RCC_CCIPR1_TIMICSEL (1 << 31) + +/* Kernel Clock Configuration register 2 */ + +#define RCC_CCIPR2_USART11SEL_SHIFT (0) +#define RCC_CCIPR2_USART11SEL_MASK (7 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_PLL2QCK (1 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_PLL3QCK (2 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_HSIKERCK (3 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_CSIKERCK (4 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_LSECK (5 << RCC_CCIPR2_USART11SEL_SHIFT) + +#define RCC_CCIPR2_USART12SEL_SHIFT (4) +#define RCC_CCIPR2_USART12SEL_MASK (7 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_PLL2QCK (1 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_PLL3QCK (2 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_HSIKERCK (3 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_CSIKERCK (4 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_LSECK (5 << RCC_CCIPR2_USART12SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM1SEL_SHIFT (8) +#define RCC_CCIPR2_LPTIM1SEL_MASK (7 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_LSECK (5 << RCC_CCIPR2_LPTIM1SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM2SEL_SHIFT (12) +#define RCC_CCIPR2_LPTIM2SEL_MASK (7 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_RCCPCLK1 (0 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_LSECK (5 << RCC_CCIPR2_LPTIM2SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM3SEL_SHIFT (16) +#define RCC_CCIPR2_LPTIM3SEL_MASK (7 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_LSECK (5 << RCC_CCIPR2_LPTIM3SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM4SEL_SHIFT (20) +#define RCC_CCIPR2_LPTIM4SEL_MASK (7 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_LSECK (5 << RCC_CCIPR2_LPTIM4SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM5SEL_SHIFT (24) +#define RCC_CCIPR2_LPTIM5SEL_MASK (7 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_LSECK (5 << RCC_CCIPR2_LPTIM5SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM6SEL_SHIFT (28) +#define RCC_CCIPR2_LPTIM6SEL_MASK (7 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_LSECK (5 << RCC_CCIPR2_LPTIM6SEL_SHIFT) + +/* Kernel Clock Configuration register 3 */ + +#define RCC_CCIPR3_SPI1SEL_SHIFT (0) +#define RCC_CCIPR3_SPI1SEL_MASK (7 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL1QCK (0 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL2PCK (1 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL3PCK (2 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_AUDIOCK (3 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PERCKv (4 << RCC_CCIPR3_SPI1SEL_SHIFT) + +#define RCC_CCIPR3_SPI2SEL_SHIFT (3) +#define RCC_CCIPR3_SPI2SEL_MASK (7 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL1QCK (0 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL2PCK (1 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL3PCK (2 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_AUDIOCK (3 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PERCKv (4 << RCC_CCIPR3_SPI2SEL_SHIFT) + +#define RCC_CCIPR3_SPI3SEL_SHIFT (6) +#define RCC_CCIPR3_SPI3SEL_MASK (7 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL1QCK (0 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL2PCK (1 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL3PCK (2 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_AUDIOCK (3 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PERCKv (4 << RCC_CCIPR3_SPI3SEL_SHIFT) + +#define RCC_CCIPR3_SPI4SEL_SHIFT (9) +#define RCC_CCIPR3_SPI4SEL_MASK (7 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_RCCPCLK1 (0 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_PLL2QCK (1 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_PLL3QCK (2 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_HSIKERCK (3 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_CSIKERCK (4 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_HSECK (5 << RCC_CCIPR3_SPI4SEL_SHIFT) + +#define RCC_CCIPR3_SPI5SEL_SHIFT (12) +#define RCC_CCIPR3_SPI5SEL_MASK (7 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_RCCPCLK3 (0 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_PLL2QCK (1 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_PLL3QCK (2 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_HSIKERCK (3 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_CSIKERCK (4 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_HSECK (5 << RCC_CCIPR3_SPI5SEL_SHIFT) + +#define RCC_CCIPR3_SPI6SEL_SHIFT (15) +#define RCC_CCIPR3_SPI6SEL_MASK (7 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_PLL2QCK (1 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_PLL3QCK (2 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_HSIKERCK (3 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_CSIKERCK (4 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_HSECK (5 << RCC_CCIPR3_SPI6SEL_SHIFT) + +#define RCC_CCIPR3_LPUART1SEL_SHIFT (24) +#define RCC_CCIPR3_LPUART1SEL_MASK (7 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_RCCPCLK3 (0 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_PLL2QCK (1 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_PLL3QCK (2 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_HSIKERCK (3 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_CSIKERCK (4 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_LSECK (5 << RCC_CCIPR3_LPUART1SEL_SHIFT) + +/* Kernel Clock Configuration register 4 */ + +#define RCC_CCIPR4_OCTOSPI1SEL_SHIFT (0) +#define RCC_CCIPR4_OCTOSPI1SEL_MASK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_RCCHCLK4 (0 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PLL1QCK (1 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PLL2RCK (2 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PERCK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) + +#define RCC_CCIPR4_SYSTICKSEL_SHIFT (2) +#define RCC_CCIPR4_SYSTICKSEL_MASK (3 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_RCCHCLKd8 (0 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_LSIKERCK1 (1 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_LSICK1 (2 << RCC_CCIPR4_SYSTICKSEL_SHIFT) + +#define RCC_CCIPR4_USBSEL_SHIFT (4) +#define RCC_CCIPR4_USBSEL_MASK (3 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_NOCK (0 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_PLL1QCK (1 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_PLL3QCK (2 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_HSI48KERCK (3 << RCC_CCIPR4_USBSEL_SHIFT) + +#define RCC_CCIPR4_SDMMC1SEL (1 << 6) +#define RCC_CCIPR4_SDMMC2SEL (1 << 7) + +#define RCC_CCIPR4_I2C1SEL_SHIFT (16) +#define RCC_CCIPR4_I2C1SEL_MASK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_PLL3RCK (1 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_HSIKERCK (2 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_CSIKERCK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) + +#define RCC_CCIPR4_I2C2SEL_SHIFT (18) +#define RCC_CCIPR4_I2C2SEL_MASK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_PLL3RCK (1 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_HSIKERCK (2 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_CSIKERCK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) + +#define RCC_CCIPR4_I2C3SEL_SHIFT (20) +#define RCC_CCIPR4_I2C3SEL_MASK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_PLL3RCK (1 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_HSIKERCK (2 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_CSIKERCK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) + +#define RCC_CCIPR4_I2C4SEL_SHIFT (22) +#define RCC_CCIPR4_I2C4SEL_MASK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_PLL3RCK (1 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_HSIKERCK (2 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_CSIKERCK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) + +#define RCC_CCIPR4_I3C1SEL_SHIFT (24) +#define RCC_CCIPR4_I3C1SEL_MASK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_PLL3RCK (1 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_HSIKERCK (2 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_NOCK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) + +#define RCC_CCIPR4_I3C2SEL_SHIFT (24) +#define RCC_CCIPR4_I3C2SEL_MASK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_PLL3RCK (1 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_HSIKERCK (2 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_NOCK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) + +/* Kernel Clock Configuration register 5 */ + +#define RCC_CCIPR5_ADCDACSEL_SHIFT (0) +#define RCC_CCIPR5_ADCDACSEL_MASK (7 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_RCCHCLK (0 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_SYSCK (1 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_PLL2RCK (2 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_HSECK (3 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_HSEKERCK (4 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_CSIKERCK (4 << RCC_CCIPR5_ADCDACSEL_SHIFT) + +#define RCC_CCIPR5_DACSEL (1 << 3) + +#define RCC_CCIPR5_RNGSEL_SHIFT (4) +#define RCC_CCIPR5_RNGSEL_MASK (3 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_HSI48KERCK (0 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_PLL1QCK (1 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_LSECK (2 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_LSIKERCK (3 << RCC_CCIPR5_RNGSEL_SHIFT) + +#define RCC_CCIPR5_CECSEL_SHIFT (6) +#define RCC_CCIPR5_CECSEL_MASK (3 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_LSECK (0 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_LSIKERCK (1 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_CSIKERCKd122 (2 << RCC_CCIPR5_CECSEL_SHIFT) + +#define RCC_CCIPR5_FDCANSEL_SHIFT (8) +#define RCC_CCIPR5_FDCANSEL_MASK (3 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_HSECK (0 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_PLL1QCK (1 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_PLL2QCK (2 << RCC_CCIPR5_FDCANSEL_SHIFT) + +#define RCC_CCIPR5_SAI1SEL_SHIFT (16) +#define RCC_CCIPR5_SAI1SEL_MASK (7 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL1QCK (0 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL2PCK (1 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL3PCK (2 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PERCK (4 << RCC_CCIPR5_SAI1SEL_SHIFT) + +#define RCC_CCIPR5_SAI2SEL_SHIFT (19) +#define RCC_CCIPR5_SAI2SEL_MASK (7 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL1QCK (0 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL2PCK (1 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL3PCK (2 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PERCK (4 << RCC_CCIPR5_SAI2SEL_SHIFT) + +#define RCC_CCIPR5_CKPERSEL_SHIFT (30) +#define RCC_CCIPR5_CKPERSEL_MASK (3 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_HSIKERCK (0 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_CSIKERCK (1 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_HSECK (2 << RCC_CCIPR5_CKPERSEL_SHIFT) + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ + +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */ +# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */ +# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */ + +#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */ +#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */ +#define RCC_BDCR_LSEEXT (1 << 7) /* Bit 7: LSE external clock type in bypass mode */ + +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */ + +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_VSWRST (1 << 16) /* Bit 16: VSwitch domain software reset */ +#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */ +#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */ +# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ +# define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */ + +#define RCC_BDCR_LSION (1 << 26) /* Bit 26: LSI Oscillator Enable */ +#define RCC_BDCR_LSIRDY (1 << 27) /* Bit 27: LSI Oscillator Ready */ + +/* Reset status register */ + +#define RCC_RSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */ +#define RCC_RSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_RSR_BORRSTF (1 << 27) /* Bit 27: BOR reset flag */ +#define RCC_RSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ +#define RCC_RSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ +#define RCC_RSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ + +/* Secure Configuration Register */ + +#define RCC_SECCFGR_HSISEC (1 << 0) /* HSI clock configuration and status bits security */ +#define RCC_SECCFGR_HSESEC (1 << 1) /* HSE clock configuration and status bits security */ +#define RCC_SECCFGR_CSISEC (1 << 2) /* CSI clock configuration and status bits security */ +#define RCC_SECCFGR_LSISEC (1 << 3) /* LSI clock configuration and status bits security */ +#define RCC_SECCFGR_LSESEC (1 << 4) /* LSE clock configuration and status bits security */ +#define RCC_SECCFGR_SYSCLKSEC (1 << 5) /* SYSCLK configuration and status bits security */ +#define RCC_SECCFGR_PRESCSEC (1 << 6) /* PRESC configuration and status bits security */ +#define RCC_SECCFGR_PLL1SEC (1 << 7) /* PLL1 configuration and status bits security */ +#define RCC_SECCFGR_PLL2SEC (1 << 8) /* PLL2 configuration and status bits security */ +#define RCC_SECCFGR_PLL3SEC (1 << 9) /* PLL3 configuration and status bits security */ +#define RCC_SECCFGR_HSI48SEC (1 << 11) /* HSI48 configuration and status bits security */ +#define RCC_SECCFGR_RMVRST (1 << 12) /* Remove Reset flag security */ +#define RCC_SECCFGR_CKPERSELSEC (1 << 13) /* PER_CK selection security */ + +/* Privilege Configuration Register */ + +#define RCC_PRIVCFGR_SPRIV (1 << 0) /* Secure functions privilege configuration */ +#define RCC_PRIVCFGR_NSPRIV (1 << 1) /* Non-secure functions privilege configuration */ + +#endif /* CONFIG_STM32H5_STM32H562XX */ +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H562XX_RCC_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5_uart.h b/arch/arm/src/stm32h5/hardware/stm32h5_uart.h new file mode 100644 index 0000000000000..e8660659bed2b --- /dev/null +++ b/arch/arm/src/stm32h5/hardware/stm32h5_uart.h @@ -0,0 +1,431 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/hardware/stm32h5_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_UART_H +#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32H5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32H5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32H5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32H5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32H5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32H5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32H5_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32H5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32H5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32H5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32H5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32H5_USART_PRESC_OFFSET 0x002c /* Prescaler register */ + +/* Register Addresses *******************************************************/ + +#if STM32H5_NLPUART > 0 +# define STM32H5_LPUART1_CR1 (STM32H5_LPUART1_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_LPUART1_CR2 (STM32H5_LPUART1_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_LPUART1_CR3 (STM32H5_LPUART1_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_LPUART1_BRR (STM32H5_LPUART1_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_LPUART1_GTPR (STM32H5_LPUART1_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_LPUART1_RTOR (STM32H5_LPUART1_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_LPUART1_RQR (STM32H5_LPUART1_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_LPUART1_ISR (STM32H5_LPUART1_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_LPUART1_ICR (STM32H5_LPUART1_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_LPUART1_RDR (STM32H5_LPUART1_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_LPUART1_TDR (STM32H5_LPUART1_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_LPUART1_PRESC (STM32H5_LPUART1_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUSART > 0 +# define STM32H5_USART1_CR1 (STM32H5_USART1_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_USART1_CR2 (STM32H5_USART1_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_USART1_CR3 (STM32H5_USART1_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_USART1_BRR (STM32H5_USART1_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_USART1_GTPR (STM32H5_USART1_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_USART1_RTOR (STM32H5_USART1_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_USART1_RQR (STM32H5_USART1_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_USART1_ISR (STM32H5_USART1_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_USART1_ICR (STM32H5_USART1_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_USART1_RDR (STM32H5_USART1_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_USART1_TDR (STM32H5_USART1_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_USART1_PRESC (STM32H5_USART1_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUSART > 1 +# define STM32H5_USART2_CR1 (STM32H5_USART2_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_USART2_CR2 (STM32H5_USART2_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_USART2_CR3 (STM32H5_USART2_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_USART2_BRR (STM32H5_USART2_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_USART2_GTPR (STM32H5_USART2_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_USART2_RTOR (STM32H5_USART2_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_USART2_RQR (STM32H5_USART2_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_USART2_ISR (STM32H5_USART2_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_USART2_ICR (STM32H5_USART2_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_USART2_RDR (STM32H5_USART2_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_USART2_TDR (STM32H5_USART2_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_USART2_PRESC (STM32H5_USART2_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUSART > 2 +# define STM32H5_USART3_CR1 (STM32H5_USART3_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_USART3_CR2 (STM32H5_USART3_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_USART3_CR3 (STM32H5_USART3_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_USART3_BRR (STM32H5_USART3_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_USART3_GTPR (STM32H5_USART3_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_USART3_RTOR (STM32H5_USART3_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_USART3_RQR (STM32H5_USART3_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_USART3_ISR (STM32H5_USART3_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_USART3_ICR (STM32H5_USART3_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_USART3_RDR (STM32H5_USART3_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_USART3_TDR (STM32H5_USART3_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_USART3_PRESC (STM32H5_USART3_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUSART > 4 +# define STM32H5_USART6_CR1 (STM32H5_USART6_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_USART6_CR2 (STM32H5_USART6_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_USART6_CR3 (STM32H5_USART6_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_USART6_BRR (STM32H5_USART6_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_USART6_GTPR (STM32H5_USART6_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_USART6_RTOR (STM32H5_USART6_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_USART6_RQR (STM32H5_USART6_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_USART6_ISR (STM32H5_USART6_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_USART6_ICR (STM32H5_USART6_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_USART6_RDR (STM32H5_USART6_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_USART6_TDR (STM32H5_USART6_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_USART6_PRESC (STM32H5_USART6_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUSART > 5 +# define STM32H5_USART10_CR1 (STM32H5_USART10_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_USART10_CR2 (STM32H5_USART10_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_USART10_CR3 (STM32H5_USART10_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_USART10_BRR (STM32H5_USART10_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_USART10_GTPR (STM32H5_USART10_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_USART10_RTOR (STM32H5_USART10_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_USART10_RQR (STM32H5_USART10_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_USART10_ISR (STM32H5_USART10_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_USART10_ICR (STM32H5_USART10_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_USART10_RDR (STM32H5_USART10_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_USART10_TDR (STM32H5_USART10_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_USART10_PRESC (STM32H5_USART10_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUSART > 6 +# define STM32H5_USART11_CR1 (STM32H5_USART11_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_USART11_CR2 (STM32H5_USART11_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_USART11_CR3 (STM32H5_USART11_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_USART11_BRR (STM32H5_USART11_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_USART11_GTPR (STM32H5_USART11_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_USART11_RTOR (STM32H5_USART11_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_USART11_RQR (STM32H5_USART11_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_USART11_ISR (STM32H5_USART11_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_USART11_ICR (STM32H5_USART11_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_USART11_RDR (STM32H5_USART11_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_USART11_TDR (STM32H5_USART11_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_USART11_PRESC (STM32H5_USART11_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUART > 0 +# define STM32H5_UART4_CR1 (STM32H5_UART4_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_UART4_CR2 (STM32H5_UART4_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_UART4_CR3 (STM32H5_UART4_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_UART4_BRR (STM32H5_UART4_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_UART4_GTPR (STM32H5_UART4_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_UART4_RTOR (STM32H5_UART4_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_UART4_RQR (STM32H5_UART4_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_UART4_ISR (STM32H5_UART4_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_UART4_ICR (STM32H5_UART4_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_UART4_RDR (STM32H5_UART4_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_UART4_TDR (STM32H5_UART4_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_UART4_PRESC (STM32H5_UART4_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUART > 1 +# define STM32H5_UART5_CR1 (STM32H5_UART5_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_UART5_CR2 (STM32H5_UART5_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_UART5_CR3 (STM32H5_UART5_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_UART5_BRR (STM32H5_UART5_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_UART5_GTPR (STM32H5_UART5_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_UART5_RTOR (STM32H5_UART5_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_UART5_RQR (STM32H5_UART5_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_UART5_ISR (STM32H5_UART5_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_UART5_ICR (STM32H5_UART5_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_UART5_RDR (STM32H5_UART5_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_UART5_TDR (STM32H5_UART5_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_UART5_PRESC (STM32H5_UART5_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUART > 2 +# define STM32H5_UART7_CR1 (STM32H5_UART7_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_UART7_CR2 (STM32H5_UART7_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_UART7_CR3 (STM32H5_UART7_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_UART7_BRR (STM32H5_UART7_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_UART7_GTPR (STM32H5_UART7_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_UART7_RTOR (STM32H5_UART7_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_UART7_RQR (STM32H5_UART7_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_UART7_ISR (STM32H5_UART7_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_UART7_ICR (STM32H5_UART7_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_UART7_RDR (STM32H5_UART7_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_UART7_TDR (STM32H5_UART7_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_UART7_PRESC (STM32H5_UART7_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUART > 3 +# define STM32H5_UART8_CR1 (STM32H5_UART8_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_UART8_CR2 (STM32H5_UART8_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_UART8_CR3 (STM32H5_UART8_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_UART8_BRR (STM32H5_UART8_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_UART8_GTPR (STM32H5_UART8_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_UART8_RTOR (STM32H5_UART8_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_UART8_RQR (STM32H5_UART8_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_UART8_ISR (STM32H5_UART8_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_UART8_ICR (STM32H5_UART8_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_UART8_RDR (STM32H5_UART8_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_UART8_TDR (STM32H5_UART8_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_UART8_PRESC (STM32H5_UART8_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUART > 4 +# define STM32H5_UART9_CR1 (STM32H5_UART9_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_UART9_CR2 (STM32H5_UART9_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_UART9_CR3 (STM32H5_UART9_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_UART9_BRR (STM32H5_UART9_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_UART9_GTPR (STM32H5_UART9_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_UART9_RTOR (STM32H5_UART9_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_UART9_RQR (STM32H5_UART9_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_UART9_ISR (STM32H5_UART9_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_UART9_ICR (STM32H5_UART9_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_UART9_RDR (STM32H5_UART9_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_UART9_TDR (STM32H5_UART9_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_UART9_PRESC (STM32H5_UART9_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +#if STM32H5_NUART > 5 +# define STM32H5_UART12_CR1 (STM32H5_UART12_BASE + STM32H5_USART_CR1_OFFSET) +# define STM32H5_UART12_CR2 (STM32H5_UART12_BASE + STM32H5_USART_CR2_OFFSET) +# define STM32H5_UART12_CR3 (STM32H5_UART12_BASE + STM32H5_USART_CR3_OFFSET) +# define STM32H5_UART12_BRR (STM32H5_UART12_BASE + STM32H5_USART_BRR_OFFSET) +# define STM32H5_UART12_GTPR (STM32H5_UART12_BASE + STM32H5_USART_GTPR_OFFSET) +# define STM32H5_UART12_RTOR (STM32H5_UART12_BASE + STM32H5_USART_RTOR_OFFSET) +# define STM32H5_UART12_RQR (STM32H5_UART12_BASE + STM32H5_USART_RQR_OFFSET) +# define STM32H5_UART12_ISR (STM32H5_UART12_BASE + STM32H5_USART_ISR_OFFSET) +# define STM32H5_UART12_ICR (STM32H5_UART12_BASE + STM32H5_USART_ICR_OFFSET) +# define STM32H5_UART12_RDR (STM32H5_UART12_BASE + STM32H5_USART_RDR_OFFSET) +# define STM32H5_UART12_TDR (STM32H5_UART12_BASE + STM32H5_USART_TDR_OFFSET) +# define STM32H5_UART12_PRESC (STM32H5_UART12_BASE + STM32H5_USART_PRESC_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */ +#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */ +#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ +#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ + +#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */ +#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) + +#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */ +#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) + +#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ +#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */ +#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \ + USART_CR1_TCIE|USART_CR1_TXEIE| \ + USART_CR1_PEIE|USART_CR1_CMIE| \ + USART_CR1_RTOIE|USART_CR1_EOBIE) +#define LPUART_CR1_ALLINTS \ + (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ + USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \ + USART_CR1_TXFEIE | USART_CR1_RXFFIE) + +/* Control register 2 */ + +#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-bit/4-bit Address Detection */ +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ + +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ +#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ +#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ +#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ +#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ +#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ +#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */ + +#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/ +#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) +#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */ +#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */ +#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */ +#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */ + +#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ + +#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */ +#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT) + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */ +#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ +#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */ +#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */ +#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */ +#define USART_CR3_SCARCNT2_SHIFT (17) /* Bits 17-19: Smart card auto retry count */ +#define USART_CR3_SCARCNT2_MASK (7 << USART_CR3_SCARCNT2_SHIFT) +#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */ +#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */ +#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */ +#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */ +#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Receiver timeout register */ + +/* Request Register */ + +#define USART_CR1_SBRKQ (1 << 1) /* Bit 1: Send Break */ + +/* Interrupt and Status register */ + +#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt Flag */ +#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS Flag */ +#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout Flag */ +#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block Flag */ +#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */ +#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate Error */ +#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate Flag */ +#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy Flag */ +#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match Flag */ +#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break Flag */ +#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ +#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode Flag */ +#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge Flag */ +#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge Flag */ + +/* ICR */ + +#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ +#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ +#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */ +#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ +#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ +#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */ +#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ +#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */ +#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ +#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ +#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ +#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ + +/* Receive Data register */ + +#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_RDR_MASK (0xff << USART_RDR_SHIFT) + +/* Transmit Data register */ + +#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_TDR_MASK (0xff << USART_TDR_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5_UART_H */ diff --git a/arch/arm/src/stm32h5/stm32h5.h b/arch/arm/src/stm32h5/stm32h5.h new file mode 100644 index 0000000000000..1df6cd9424fa2 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32h5_dbgmcu.h" +/* #include "stm32h5_flash.h" */ +#include "stm32h5_gpio.h" +#include "stm32h5_pwr.h" +#include "stm32h5_rcc.h" +/* #include "stm32h5_spi.h" */ +/* #include "stm32h5_tim.h" */ +#include "stm32h5_uart.h" +#include "stm32h5_lowputc.h" + +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_H */ diff --git a/arch/arm/src/stm32h5/stm32h52x_3x_rcc.c b/arch/arm/src/stm32h5/stm32h52x_3x_rcc.c new file mode 100644 index 0000000000000..f9337b4a82cb4 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h52x_3x_rcc.c @@ -0,0 +1,1093 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h562xx_rcc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "stm32h5_pwr.h" +#include "stm32h5_flash.h" +#include "stm32h5_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. Normally this is very fast, but I have seen at least one + * board that required this long, long timeout for the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/* Same for HSI and CSI */ + +#define HSIRDY_TIMEOUT HSERDY_TIMEOUT +#define LSIRDY_TIMEOUT HSERDY_TIMEOUT + +/* HSE divisor to yield ~1MHz RTC clock */ + +#define HSE_DIVISOR (STM32H5_HSE_FREQUENCY + 500000) / 1000000 + +/* Determine if board wants to use HSI48 as 48 MHz oscillator. */ + +#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48) +# if STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK +# define STM32H5_USE_HSI48 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_enableahb1 + * + * Description: + * Enable selected AHB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB1ENR register to enabled the + * selected AHB1 peripherals. + */ + + regval = getreg32(STM32H5_RCC_AHB1ENR); + +#ifdef CONFIG_STM32H5_GPDMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHB1ENR_GPDMA1EN; +#endif + +#ifdef CONFIG_STM32H5_GPDMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHB1ENR_GPDMA2EN; +#endif + +#ifdef CONFIG_STM32H5_FLASHEN + /* Flash memory interface clock enable */ + + regval |= RCC_AHB1ENR_FLASHEN; +#endif + +#ifdef CONFIG_STM32H5_CRC + /* CRC clock enable */ + + regval |= RCC_AHB1ENR_CRCEN; +#endif + +#ifdef CONFIG_STM32H5_RAMCFG + /* RAMCFG clock enable */ + + regval |= RCC_AHB1ENR_RAMCFGEN; +#endif + +#ifdef CONFIG_STM32H5_TZSC1 + + + regval |= RCC_AHB1ENR_TZSC1EN; +#endif + +#ifdef CONFIG_STM32H5_BKPRAM + /* BKPRAM clock enable */ + + regval |= RCC_AHB1ENR_BKPRAMEN; +#endif + +#ifdef CONFIG_STM32H5_DCACHE + /* DCACHE clock enable */ + + regval |= RCC_AHB1ENR_DCACHEEN; +#endif + +#ifdef CONFIG_STM32H5_SRAM1 + /* SRAM1 clock enable */ + + regval |= RCC_AHB1ENR_SRAM1EN; +#endif + + putreg32(regval, STM32H5_RCC_AHB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb2 + * + * Description: + * Enable selected AHB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB2ENR register to enable the + * selected AHB2 peripherals. + */ + + regval = getreg32(STM32H5_RCC_AHB2ENR); + + /* Enable GPIOA, GPIOB, .... GPIOH */ + +#if STM32H5_NPORTS > 0 + regval |= (RCC_AHB2ENR_GPIOAEN +#if STM32H5_NPORTS > 1 + | RCC_AHB2ENR_GPIOBEN +#endif +#if STM32H5_NPORTS > 2 + | RCC_AHB2ENR_GPIOCEN +#endif +#if STM32H5_NPORTS > 3 + | RCC_AHB2ENR_GPIODEN +#endif +#if STM32H5_NPORTS > 4 + | RCC_AHB2ENR_GPIOEEN +#endif +#if STM32H5_NPORTS > 5 + | RCC_AHB2ENR_GPIOFEN +#endif +#if STM32H5_NPORTS > 6 + | RCC_AHB2ENR_GPIOGEN +#endif +#if STM32H5_NPORTS > 7 + | RCC_AHB2ENR_GPIOHEN +#endif +#if STM32H5_NPORTS > 7 + | RCC_AHB2ENR_GPIOIEN +#endif + + ); +#endif + +#if defined(CONFIG_STM32H5_ADC) + /* ADC clock enable */ + + regval |= RCC_AHB2ENR_ADCEN; +#endif + +#ifdef CONFIG_STM32H5_DAC1 + /* DAC1 clock enable */ + + regval |= RCC_AHB2ENR_DAC1EN; +#endif + +#ifdef CONFIG_STM32H5_DCMI_PSSI + /* Digital Camera Interface clock enable */ + + regval |= RCC_AHB2ENR_DCMI_PSSIEN; +#endif + +#ifdef CONFIG_STM32H5_AES + /* Cryptographic modules clock enable */ + + regval |= RCC_AHB2ENR_AESEN; +#endif + +#ifdef CONFIG_STM32H5_HASH + /* Hash module enable */ + + regval |= RCC_AHB2ENR_HASHEN +#endif + +#ifdef CONFIG_STM32H5_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHB2ENR_RNGEN; +#endif + +#ifdef CONFIG_STM32H5_PKA + /* Public Key Accelerator clock enable */ + + regval |= RCC_AHB2ENR_PKAEN; +#endif + +#ifdef CONFIG_STM32H5_SAES + /* Secure AES coprocessor clock enable */ + + regval |= RCC_AHB2ENR_SAESEN; +#endif + +#ifdef CONFIG_STM32H5_SRAM2 + /* SRAM2 clock enable */ + + regval |= RCC_AHB2ENR_SRAM2EN; +#endif + +#ifdef CONFIG_STM32H5_SRAM3 + /* SRAM2 clock enable */ + + regval |= RCC_AHB2ENR_SRAM3EN; +#endif + + putreg32(regval, STM32H5_RCC_AHB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb4 + * + * Description: + * Enable selected AHB4 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb4(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB4ENR register to enabled the + * selected AHB4 peripherals. + */ + + regval = getreg32(STM32H5_RCC_AHB4ENR); + +#ifdef CONFIG_STM32H5_OTFDEC1EN + /* On-the-fly-decryption module clock enable */ + + regval |= RCC_AHB4ENR_OTFDEC1EN; +#endif + +#ifdef CONFIG_STM32H5_SDMMC1 + /* SDMMC1 clock enable */ + + regval |= RCC_AHB4ENR_SDMMC1EN; +#endif + +#ifdef CONFIG_STM32H5_SDMMC2 + /* SDMMC1 clock enable */ + + regval |= RCC_AHB4ENR_SDMMC2EN; +#endif + + +#ifdef CONFIG_STM32H5_FMC + /* Flexible memory controller clock enable */ + + regval |= RCC_AHB4ENR_FMCEN; +#endif + +#ifdef CONFIG_STM32H5_OCTOSPI1 + /* OCTOSPI1 module clock enable */ + + regval |= RCC_AHB4ENR_OSPI1EN; +#endif + + putreg32(regval, STM32H5_RCC_AHB4ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1l + * + * Description: + * Enable selected APB1L peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1l(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1LENR register to enabled the + * selected APB1L peripherals. + */ + + regval = getreg32(STM32H5_RCC_APB1LENR); + +#ifdef CONFIG_STM32H5_TIM2 + /* Bit 0: TIM2 clock enable */ + + regval |= RCC_APB1LENR_TIM2EN; +#endif + +#ifdef CONFIG_STM32H5_TIM3 + /* Bit 1: TIM3 clock enable */ + + regval |= RCC_APB1LENR_TIM3EN; +#endif + +#ifdef CONFIG_STM32H5_TIM4 + /* Bit 2: TIM4 clock enable */ + + regval |= RCC_APB1LENR_TIM4EN; +#endif + +#ifdef CONFIG_STM32H5_TIM5 + /* Bit 3: TIM5 clock enable */ + + regval |= RCC_APB1LENR_TIM5EN; +#endif + +#ifdef CONFIG_STM32H5_TIM6 + /* Bit 4: TIM6 clock enable */ + + regval |= RCC_APB1LENR_TIM6EN; +#endif + +#ifdef CONFIG_STM32H5_TIM7 + /* Bit 5: TIM7 clock enable */ + + regval |= RCC_APB1LENR_TIM7EN; +#endif + +#ifdef CONFIG_STM32H5_TIM12 + /* Bit 5: TIM12 clock enable */ + + regval |= RCC_APB1LENR_TIM12EN; +#endif + +#ifdef CONFIG_STM32H5_SPI2 + /* Bit 14: SPI2 clock enable */ + + regval |= RCC_APB1LENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32H5_SPI3 + /* Bit 15: SPI3 clock enable */ + + regval |= RCC_APB1LENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32H5_USART2 + /* Bit 17: USART2 clock enable */ + + regval |= RCC_APB1LENR_USART2EN; +#endif + +#ifdef CONFIG_STM32H5_USART3 + /* Bit 18: USART3 clock enable */ + + regval |= RCC_APB1LENR_USART3EN; +#endif + +#ifdef CONFIG_STM32H5_UART4 + /* Bit 19: UART4 clock enable */ + + regval |= RCC_APB1LENR_UART4EN; +#endif + +#ifdef CONFIG_STM32H5_UART5 + /* Bit 20: UART5 clock enable */ + + regval |= RCC_APB1LENR_UART5EN; +#endif + +#ifdef CONFIG_STM32H5_I2C1 + /* Bit 21: I2C1 clock enable */ + + regval |= RCC_APB1LENR_I2C1EN; +#endif + +#ifdef CONFIG_STM32H5_I2C2 + /* Bit 22: I2C2 clock enable */ + + regval |= RCC_APB1LENR_I2C2EN; +#endif + +#ifdef CONFIG_STM32H5_I3C1 + /* Bit 23: I3C1 clock enable */ + + regval |= RCC_APB1LENR_I3C1EN; +#endif + +#ifdef STM32H5_USE_HSI48 + if (STM32H5_HSI48_SYNCSRC != SYNCSRC_NONE) + { + /* Bit 24: CRS clock enable */ + + regval |= RCC_APB1LENR_CRSEN; + } +#endif + +#ifdef CONFIG_STM32H5_USART6 + /* Bit 25: USART6 clock enable */ + + regval |= RCC_APB1LENR_USART6EN; +#endif + + +#ifdef CONFIG_STM32H5_CEC + /* Bit 28: CEC clock enable */ + + regval |= RCC_APB1LENR_CECEN; +#endif + + putreg32(regval, STM32H5_RCC_APB1LENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1h + * + * Description: + * Enable selected APB1H peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1h(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1HENR register to enabled the + * selected APB1H peripherals. + */ + + regval = getreg32(STM32H5_RCC_APB1HENR); + +#ifdef CONFIG_STM32H5_DTS + /* Bit 3: DTS clock enable */ + + regval |= RCC_APB1HENR_DTSEN; +#endif + +#ifdef CONFIG_STM32H5_LPTIM2 + /* Bit 5: Low-power Timer 2 clock enable */ + + regval |= RCC_APB1HENR_LPTIM2EN; +#endif + +#ifdef CONFIG_STM32H5_FDCAN + /* Bit 9: FDCAN clock enable */ + + regval |= RCC_APB1HENR_FDCANEN; +#endif + +#ifdef CONFIG_STM32H5_UCPD1 + /* Bit 23: UCPD1 clock enable */ + + regval |= RCC_APB1HENR_UCPD1EN; +#endif + + /* Enable APB1H peripherals */ + + putreg32(regval, STM32H5_RCC_APB1HENR); + +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32H5_RCC_APB2ENR); + + +#ifdef CONFIG_STM32H5_TIM1 + /* TIM1 clock enable */ + + regval |= RCC_APB2ENR_TIM1EN; +#endif + +#ifdef CONFIG_STM32H5_SPI1 + /* SPI1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32H5_TIM8 + /* TIM8 clock enable */ + + regval |= RCC_APB2ENR_TIM8EN; +#endif + +#ifdef CONFIG_STM32H5_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32H5_TIM15 + /* TIM15 clock enable */ + + regval |= RCC_APB2ENR_TIM15EN; +#endif + +#ifdef CONFIG_STM32H5_SPI4 + /* SPI4 clock enable */ + + regval |= RCC_APB2ENR_SPI4EN; +#endif + +#ifdef CONFIG_STM32H5_USB + /* USB clock enable */ + + regval |= RCC_APB2ENR_USBEN; +#endif + + putreg32(regval, STM32H5_RCC_APB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb3 + * + * Description: + * Enable selected APB3 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb3(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32H5_RCC_APB3ENR); + + +#ifdef CONFIG_STM32H5_SBS + /* Bit 1: SBS clock enable */ + + regval |= RCC_APB3ENR_SBSEN; +#endif + +#ifdef CONFIG_STM32H5_LPUART1 + /* Bit 6: LPUART1 clock enable */ + + regval |= RCC_APB3ENR_LPUART1EN; +#endif + +#ifdef CONFIG_STM32H5_I2C3 + /* Bit 7: I2C3 clock enable */ + + regval |= RCC_APB3ENR_I2C3EN; +#endif + +#ifdef CONFIG_STM32H5_I3C2 + /* Bit 9: I3C2 clock enable */ + + regval |= RCC_APB3ENR_I3C2EN; +#endif + +#ifdef CONFIG_STM32H5_LPTIM1 + /* Bit 11: LPTIM1 clock enable */ + + regval |= RCC_APB3ENR_LPTIM1EN; +#endif + +#ifdef CONFIG_STM32H5_VREF + /* Bit 20: VREF clock enable */ + + regval |= RCC_APB3ENR_VREFEN; +#endif + +#ifdef CONFIG_STM32H5_RTCAPB + /* Bit 21: RTCABP clock enable */ + + regval |= RCC_APB3ENR_RTCAPBEN; +#endif + + + /* Enable peripherals */ + + putreg32(regval, STM32H5_RCC_APB3ENR); + +} +/**************************************************************************** + * Name: rcc_enableccip + * + * Description: + * Set peripherals independent clock configuration. + * + ****************************************************************************/ + +static inline void rcc_enableccip(void) +{ + +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_rcc_enableperipherals + ****************************************************************************/ + +void stm32h5_rcc_enableperipherals(void) +{ + rcc_enableccip(); + rcc_enableahb1(); + rcc_enableahb2(); + rcc_enableahb4(); + rcc_enableapb1l(); + rcc_enableapb1h(); + rcc_enableapb2(); + rcc_enableapb3(); + +#ifdef STM32H5_USE_HSI48 + /* Enable HSI48 clocking to support USB transfers or RNG */ + + stm32h5_enable_hsi48(STM32L4_HSI48_SYNCSRC); +#endif + +} + +/**************************************************************************** + * Name: stm32h5_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +void stm32h5_stdclockconfig(void) +{ + uint32_t regval; + volatile int32_t timeout; + +#if defined(STM32H5_BOARD_USEHSI) + /* Enable Internal High-Speed Clock (HSI) */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_HSION; /* Enable HSI */ + +#if defined(STMT32H5_CR_HSIDIV) + regval |= STM32H5_CR_HSIDIV; +#else + /* Use default (32 MHz) */ + +#endif + + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until the HSI is ready (or until a timeout elapsed) */ + + for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSIRDY flag is the set in the CR */ + + if ((getreg32(STM32H5_RCC_CR) & RCC_CR_HSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + + /* Make sure HSIDIVF is also not 0 */ + + for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSIRDY flag is the set in the CR */ + + if ((getreg32(STM32H5_RCC_CR) & RCC_CR_HSIDIVF) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } +#endif + +#if defined(STM32H5_BOARD_USEHSI) + /* Already set above */ + +#elif defined(STM32H5_BOARD_USECSI) + /* Enable Internal Low Power Internal Clock (CSI) */ + + /* Wait until the CSI is either off or ready (or until a timeout elapsed) */ + + for (timeout = CSIRDY_TIMEOUT; timeout > 0; timeout--) + { + if ((regval = getreg32(STM32H5_RCC_CR)), + (regval & RCC_CR_CSIRDY) || ~(regval & RCC_CR_CSION)) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_CSION; /* Enable CSI */ + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until the CSI is ready (or until a timeout elapsed) */ + + for (timeout = CSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the CSIRDY flag is the set in the CR */ + + if ((getreg32(STM32H5_RCC_CR) & RCC_CR_CSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + +#elif defined(STM32H5_BOARD_USEHSE) + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32H5_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } +#else + +# error stm32h5_stdclockconfig(), must have one of STM32H5_BOARD_USEHSI, STM32H5_BOARD_USECSI, STM32H5_BOARD_USEHSE defined + +#endif + + /* Check for a timeout. If this timeout occurs, then we are hosed. We + * have no real back-up plan, although the following logic makes it look + * as though we do. + */ + + if (timeout > 0) + { + /* Select main regulator voltage range according to system clock + * frequency. + */ + + stm32h5_pwr_adjustvcore(STM32H5_SYSCLK_FREQUENCY); + + regval = getreg32(STM32H5_RCC_CFGR2); + /* Set the HCLK source/divider */ + + regval &= ~RCC_CFGR2_HPRE_MASK; + regval |= STM32H5_RCC_CFGR2_HPRE; + + /* Set the PCLK1 divider */ + + regval &= ~RCC_CFGR2_PPRE1_MASK; + regval |= STM32H5_RCC_CFGR2_PPRE1; + + /* Set the PCLK2 divider */ + + regval &= ~RCC_CFGR2_PPRE2_MASK; + regval |= STM32H5_RCC_CFGR2_PPRE2; + + /* Set the PCLK3 divider */ + + regval &= ~RCC_CFGR2_PPRE3_MASK; + regval |= STM32H5_RCC_CFGR2_PPRE3; + + putreg32(regval, STM32H5_RCC_CFGR2); + + +#ifdef CONFIG_STM32H5_RTC_HSECLOCK + /* Set the RTC clock divisor */ + + regval = getreg32(STM32H5_RCC_CFGR1); + regval &= ~RCC_CFGR1_RTCPRE_MASK; + regval |= RCC_CFGR1_RTCPRE(HSE_DIVISOR); + putreg32(regval, STM32H5_RCC_CFGR1); +#endif + + /* Configure PLL1 */ + + /* PLL1CFGR */ + + regval = getreg32(STM32H5_RCC_PLL1CFGR); + + /* Set the PLL1 source and main divider */ + +/* Can keep below ifdefs and add ifdefs on top for board.h definitions */ + +#ifdef STM32H5_PLL1SRC_HSI + regval |= RCC_PLL1CFGR_PLL1SRC_HSI; +#elif defined(STM32H5_PLL1SRC_CSI) + regval |= RCC_PLL1CFGR_PLL1SRC_CSI; +#elif defined(STM32H5_PLL1SRC_HSE) + regval |= RCC_PLL1CFGR_PLL1SRC_HSE; +#elif defined(STM32H5_BOARD_USEHSI) + regval |= RCC_PLL1CFGR_PLL1SRC_HSI; +#elif defined(STM32H5_BOARD_USECSI) + regval |= RCC_PLL1CFGR_PLL1SRC_CSI; +#else /* if STM32H5_BOARD_USEHSE */ + regval |= RCC_PLL1CFGR_PLL1SRC_HSE; +#endif + + /* Set RGE, FRACEN, VCOSEL, and M from board.h */ + + regval |= (STM32H5_PLL1CFGR_PLL1RGE | STM32H5_PLL1CFGR_PLL1FRACEN | + STM32H5_PLL1CFGR_PLL1VCOSEL | STM32H5_PLL1CFGR_PLL1M); + +#ifdef STM32H5_PLL1CFG_PLL1P_ENABLED + regval |= RCC_PLL1CFGR_PLL1PEN; +#endif +#ifdef STM32H5_PLL1CFG_PLL1Q_ENABLED + regval |= RCC_PLL1CFGR_PLL1QEN; +#endif +#ifdef STM32H5_PLL1CFG_PLL1R_ENABLED + regval |= RCC_PLL1CFGR_PLL1REN; +#endif + + putreg32(regval, STM32H5_RCC_PLL1CFGR); + + /* PLL1DIVR and PLL1FRACR */ + + /* Get settings from board.h */ + + /* PLL1DIVR */ + + regval = getreg32(STM32H5_RCC_PLL1DIVR); + regval = (STM32H5_PLL1DIVR_PLL1N | STM32H5_PLL1DIVR_PLL1P | + STM32H5_PLL1DIVR_PLL1Q | STM32H5_PLL1DIVR_PLL1R); + putreg32(regval, STM32H5_RCC_PLL1DIVR); + + /* PLL1FRACR */ + + regval = getreg32(STM32H5_RCC_PLL1FRACR); + regval |= STM32H5_PLL1FRACR_PLL1FRACN; + putreg32(regval, STM32H5_RCC_PLL1FRACR); + + /* Enable PLL1 */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_PLL1ON; + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until PLL1 is ready */ + + while ((getreg32(STM32H5_RCC_CR) & RCC_CR_PLL1RDY) == 0) + { + } + + /* Configure PLL2 */ + + /* PLL2CFGR */ + + regval = getreg32(STM32H5_RCC_PLL2CFGR); + + /* Set the PLL2 source and main divider */ + +#ifdef STM32H5_PLL2SRC_HSI + regval |= RCC_PLL2CFGR_PLL2SRC_HSI; +#elif defined(STM32H5_PLL2SRC_CSI) + regval |= RCC_PLL2CFGR_PLL2SRC_CSI; +#elif defined(STM32H5_PLL2SRC_HSE) + regval |= RCC_PLL2CFGR_PLL2SRC_HSE; +#elif defined(STM32H5_BOARD_USEHSI) + regval |= RCC_PLL2CFGR_PLL2SRC_HSI; +#elif defined(STM32H5_BOARD_USECSI) + regval |= RCC_PLL2CFGR_PLL2SRC_CSI; +#else /* if STM32H5_BOARD_USEHSE */ + regval |= RCC_PLL2CFGR_PLL2SRC_HSE; +#endif + + /* Set RGE, FRACEN, VCOSEL, and M from board.h */ + + regval |= (STM32H5_PLL2CFGR_PLL2RGE | STM32H5_PLL2CFGR_PLL2FRACEN | + STM32H5_PLL2CFGR_PLL2VCOSEL | STM32H5_PLL2CFGR_PLL2M); + +#ifdef STM32H5_PLL2CFG_PLL2P_ENABLED + regval |= RCC_PLL2CFGR_PLL2PEN; +#endif +#ifdef STM32H5_PLL2CFG_PLL2Q_ENABLED + regval |= RCC_PLL2CFGR_PLL2QEN; +#endif +#ifdef STM32H5_PLL2CFG_PLL2R_ENABLED + regval |= RCC_PLL2CFGR_PLL2REN; +#endif + + putreg32(regval, STM32H5_RCC_PLL2CFGR); + + /* PLL2DIVR and PLL2FRACR */ + + /* Get settings from board.h */ + + /* PLL2DIVR */ + + regval = getreg32(STM32H5_RCC_PLL2DIVR); + regval = (STM32H5_PLL2DIVR_PLL2N | STM32H5_PLL2DIVR_PLL2P | + STM32H5_PLL2DIVR_PLL2Q | STM32H5_PLL2DIVR_PLL2R); + putreg32(regval, STM32H5_RCC_PLL2DIVR); + + /* PLL2FRACR */ + + regval = getreg32(STM32H5_RCC_PLL2FRACR); + regval |= STM32H5_PLL2FRACR_PLL2FRACN; + putreg32(regval, STM32H5_RCC_PLL2FRACR); + + /* Enable PLL2 */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_PLL2ON; + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until PLL2 is ready */ + + while ((getreg32(STM32H5_RCC_CR) & RCC_CR_PLL2RDY) == 0) + { + } + + /* Configure PLL3 */ + + /* PLL3CFGR */ + + regval = getreg32(STM32H5_RCC_PLL3CFGR); + + /* Set the PLL3 source and main divider */ + +#ifdef STM32H5_PLL3SRC_HSI + regval |= RCC_PLL3CFGR_PLL3SRC_HSI; +#elif defined(STM32H5_PLL3SRC_CSI) + regval |= RCC_PLL3CFGR_PLL3SRC_CSI; +#elif defined(STM32H5_PLL3SRC_HSE) + regval |= RCC_PLL3CFGR_PLL3SRC_HSE; +#elif defined(STM32H5_BOARD_USEHSI) + regval |= RCC_PLL3CFGR_PLL3SRC_HSI; +#elif defined(STM32H5_BOARD_USECSI) + regval |= RCC_PLL3CFGR_PLL3SRC_CSI; +#else /* if STM32H5_BOARD_USEHSE */ + regval |= RCC_PLL3CFGR_PLL3SRC_HSE; +#endif + + /* Set RGE, FRACEN, VCOSEL, and M from board.h */ + + regval |= (STM32H5_PLL3CFGR_PLL3RGE | STM32H5_PLL3CFGR_PLL3FRACEN | + STM32H5_PLL3CFGR_PLL3VCOSEL | STM32H5_PLL3CFGR_PLL3M); + +#ifdef STM32H5_PLL3CFG_PLL3P_ENABLED + regval |= RCC_PLL3CFGR_PLL3PEN; +#endif +#ifdef STM32H5_PLL3CFG_PLL3Q_ENABLED + regval |= RCC_PLL3CFGR_PLL3QEN; +#endif +#ifdef STM32H5_PLL3CFG_PLL3R_ENABLED + regval |= RCC_PLL3CFGR_PLL3REN; +#endif + + putreg32(regval, STM32H5_RCC_PLL3CFGR); + + /* PLL3DIVR and PLL3FRACR */ + + /* Get settings from board.h */ + + /* PLL3DIVR */ + + regval = getreg32(STM32H5_RCC_PLL3DIVR); + regval = (STM32H5_PLL3DIVR_PLL3N | STM32H5_PLL3DIVR_PLL3P | + STM32H5_PLL3DIVR_PLL3Q | STM32H5_PLL3DIVR_PLL3R); + putreg32(regval, STM32H5_RCC_PLL3DIVR); + + /* PLL3FRACR */ + + regval = getreg32(STM32H5_RCC_PLL3FRACR); + regval |= STM32H5_PLL3FRACR_PLL3FRACN; + putreg32(regval, STM32H5_RCC_PLL3FRACR); + + /* Enable PLL3 */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_PLL3ON; + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until PLL3 is ready */ + + while ((getreg32(STM32H5_RCC_CR) & RCC_CR_PLL3RDY) == 0) + { + } + + /* 250 MHz SYSCLK. VOS0 = 1.30V to 1.40V + * Enable FLASH 5 wait states + * See Table 44. in Reference Manual + */ + + regval = FLASH_ACR_LATENCY_5; + putreg32(regval, STM32H5_FLASH_ACR); + + /* Select the main PLL as system clock source */ + + regval = getreg32(STM32H5_RCC_CFGR1); + regval &= ~RCC_CFGR1_SW_MASK; + regval |= RCC_CFGR1_SW_PLL; + putreg32(regval, STM32H5_RCC_CFGR1); + + /* Wait until the PLL source is used as the system clock source */ + + while ((getreg32(STM32H5_RCC_CFGR1) & RCC_CFGR1_SWS_MASK) != + RCC_CFGR1_SWS_PLL) + { + } + +#if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \ + defined(STM32H5_USE_LSCO_LSI) + + /* Low speed internal clock source LSI */ + + stm32h5_rcc_enablelsi(); +#endif + +#if defined(STM32H5_USE_LSE) || defined(STM32H5_USE_LSCO_LSE) + /* Low speed external clock source LSE */ + + stm32h5_rcc_enablelse(); +#else + /* + * There is another case where the LSE needs to + * be enabled: if the MCO1 pin selects LSE as source. + * Other cases can be handled by peripheral drivers. + */ + + if ((getreg32(STM32_RCC_CFGR1) & RCC_CFGR1_MCO1SEL_MASK) == + RCC_CFGR1_MCO1SEL_LSE) + { + stm32h5_rcc_enablelse(); + } + +#endif /* STM32H5_USE_LSE */ + } +} +#endif diff --git a/arch/arm/src/stm32h5/stm32h56x_7x_rcc.c b/arch/arm/src/stm32h5/stm32h56x_7x_rcc.c new file mode 100644 index 0000000000000..c27596316db39 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h56x_7x_rcc.c @@ -0,0 +1,1235 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h562xx_rcc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "stm32h5_pwr.h" +#include "stm32h5_flash.h" +#include "stm32h5_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. Normally this is very fast, but I have seen at least one + * board that required this long, long timeout for the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/* Same for HSI and CSI */ + +#define HSIRDY_TIMEOUT HSERDY_TIMEOUT +#define LSIRDY_TIMEOUT HSERDY_TIMEOUT + +/* HSE divisor to yield ~1MHz RTC clock */ + +#define HSE_DIVISOR (STM32H5_HSE_FREQUENCY + 500000) / 1000000 + +/* Determine if board wants to use HSI48 as 48 MHz oscillator. */ + +#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48) +# if STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK +# define STM32H5_USE_HSI48 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_enableahb1 + * + * Description: + * Enable selected AHB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB1ENR register to enabled the + * selected AHB1 peripherals. + */ + + regval = getreg32(STM32H5_RCC_AHB1ENR); + +#ifdef CONFIG_STM32H5_GPDMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHB1ENR_GPDMA1EN; +#endif + +#ifdef CONFIG_STM32H5_GPDMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHB1ENR_GPDMA2EN; +#endif + +#ifdef CONFIG_STM32H5_FLASHEN + /* Flash memory interface clock enable */ + + regval |= RCC_AHB1ENR_FLASHEN; +#endif + +#ifdef CONFIG_STM32H5_CRC + /* CRC clock enable */ + + regval |= RCC_AHB1ENR_CRCEN; +#endif + +#ifdef CONFIG_STM32H5_CORDIC + /* CORDIC clock enable */ + + regval |= RCC_AHB1ENR_CORDICEN; +#endif + +#ifdef CONFIG_STM32H5_FMAC + /* FMAC clock enable */ + + regval |= RCC_AHB1ENR_FMACEN; +#endif + +#ifdef CONFIG_STM32H5_RAMCFG + /* RAMCFG clock enable */ + + regval |= RCC_AHB1ENR_RAMCFGEN; +#endif + +#ifdef CONFIG_STM32H5_ETH + /* ETH clock enable */ + + regval |= RCC_AHB1ENR_ETHEN; +#endif +#ifdef CONFIG_STM32H5_ETHTX + /* ETH TX clock enable */ + + regval |= RCC_AHB1ENR_ETHTXEN; +#endif + +#ifdef CONFIG_STM32H5_ETHRX + /* ETH RX clock enable */ + + regval |= RCC_AHB1ENR_ETHRXEN; +#endif + +#ifdef CONFIG_STM32H5_TZSC1 + + + regval |= RCC_AHB1ENR_TZSC1EN; +#endif + +#ifdef CONFIG_STM32H5_BKPRAM + /* BKPRAM clock enable */ + + regval |= RCC_AHB1ENR_BKPRAMEN; +#endif + +#ifdef CONFIG_STM32H5_DCACHE + /* DCACHE clock enable */ + + regval |= RCC_AHB1ENR_DCACHEEN; +#endif + +#ifdef CONFIG_STM32H5_SRAM1 + /* ETH clock enable */ + + regval |= RCC_AHB1ENR_SRAM1EN; +#endif + + putreg32(regval, STM32H5_RCC_AHB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb2 + * + * Description: + * Enable selected AHB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB2ENR register to enable the + * selected AHB2 peripherals. + */ + + regval = getreg32(STM32H5_RCC_AHB2ENR); + + /* Enable GPIOA, GPIOB, .... GPIOH */ + +#if STM32H5_NPORTS > 0 + regval |= (RCC_AHB2ENR_GPIOAEN +#if STM32H5_NPORTS > 1 + | RCC_AHB2ENR_GPIOBEN +#endif +#if STM32H5_NPORTS > 2 + | RCC_AHB2ENR_GPIOCEN +#endif +#if STM32H5_NPORTS > 3 + | RCC_AHB2ENR_GPIODEN +#endif +#if STM32H5_NPORTS > 4 + | RCC_AHB2ENR_GPIOEEN +#endif +#if STM32H5_NPORTS > 5 + | RCC_AHB2ENR_GPIOFEN +#endif +#if STM32H5_NPORTS > 6 + | RCC_AHB2ENR_GPIOGEN +#endif +#if STM32H5_NPORTS > 7 + | RCC_AHB2ENR_GPIOHEN +#endif +#if STM32H5_NPORTS > 7 + | RCC_AHB2ENR_GPIOIEN +#endif + + ); +#endif + +#if defined(CONFIG_STM32H5_ADC) + /* ADC clock enable */ + + regval |= RCC_AHB2ENR_ADCEN; +#endif + +#ifdef CONFIG_STM32H5_DAC1 + /* DAC1 clock enable */ + + regval |= RCC_AHB2ENR_DAC1EN; +#endif + +#ifdef CONFIG_STM32H5_DCMI_PSSI + /* Digital Camera Interface clock enable */ + + regval |= RCC_AHB2ENR_DCMI_PSSIEN; +#endif + +#ifdef CONFIG_STM32H5_AES + /* Cryptographic modules clock enable */ + + regval |= RCC_AHB2ENR_AESEN; +#endif + +#ifdef CONFIG_STM32H5_HASH + /* Hash module enable */ + + regval |= RCC_AHB2ENR_HASHEN +#endif + +#ifdef CONFIG_STM32H5_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHB2ENR_RNGEN; +#endif + +#ifdef CONFIG_STM32H5_PKA + /* Public Key Accelerator clock enable */ + + regval |= RCC_AHB2ENR_PKAEN; +#endif + +#ifdef CONFIG_STM32H5_SAES + /* Secure AES coprocessor clock enable */ + + regval |= RCC_AHB2ENR_SAESEN; +#endif + +#ifdef CONFIG_STM32H5_SRAM2 + /* SRAM2 clock enable */ + + regval |= RCC_AHB2ENR_SRAM2EN; +#endif + +#ifdef CONFIG_STM32H5_SRAM3 + /* SRAM2 clock enable */ + + regval |= RCC_AHB2ENR_SRAM3EN; +#endif + + putreg32(regval, STM32H5_RCC_AHB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb4 + * + * Description: + * Enable selected AHB4 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb4(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB4ENR register to enabled the + * selected AHB4 peripherals. + */ + + regval = getreg32(STM32H5_RCC_AHB4ENR); + +#ifdef CONFIG_STM32H5_OTFDEC1EN + /* On-the-fly-decryption module clock enable */ + + regval |= RCC_AHB4ENR_OTFDEC1EN; +#endif + +#ifdef CONFIG_STM32H5_SDMMC1 + /* SDMMC1 clock enable */ + + regval |= RCC_AHB4ENR_SDMMC1EN; +#endif + +#ifdef CONFIG_STM32H5_SDMMC2 + /* SDMMC1 clock enable */ + + regval |= RCC_AHB4ENR_SDMMC2EN; +#endif + + +#ifdef CONFIG_STM32H5_FMC + /* Flexible memory controller clock enable */ + + regval |= RCC_AHB4ENR_FMCEN; +#endif + +#ifdef CONFIG_STM32H5_OCTOSPI1 + /* OCTOSPI1 module clock enable */ + + regval |= RCC_AHB4ENR_OSPI1EN; +#endif + + putreg32(regval, STM32H5_RCC_AHB4ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1l + * + * Description: + * Enable selected APB1L peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1l(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1LENR register to enabled the + * selected APB1L peripherals. + */ + + regval = getreg32(STM32H5_RCC_APB1LENR); + +#ifdef CONFIG_STM32H5_TIM2 + /* Bit 0: TIM2 clock enable */ + + regval |= RCC_APB1LENR_TIM2EN; +#endif + +#ifdef CONFIG_STM32H5_TIM3 + /* Bit 1: TIM3 clock enable */ + + regval |= RCC_APB1LENR_TIM3EN; +#endif + +#ifdef CONFIG_STM32H5_TIM4 + /* Bit 2: TIM4 clock enable */ + + regval |= RCC_APB1LENR_TIM4EN; +#endif + +#ifdef CONFIG_STM32H5_TIM5 + /* Bit 3: TIM5 clock enable */ + + regval |= RCC_APB1LENR_TIM5EN; +#endif + +#ifdef CONFIG_STM32H5_TIM6 + /* Bit 4: TIM6 clock enable */ + + regval |= RCC_APB1LENR_TIM6EN; +#endif + +#ifdef CONFIG_STM32H5_TIM7 + /* Bit 5: TIM7 clock enable */ + + regval |= RCC_APB1LENR_TIM7EN; +#endif + +#ifdef CONFIG_STM32H5_TIM12 + /* Bit 5: TIM12 clock enable */ + + regval |= RCC_APB1LENR_TIM12EN; +#endif + +#ifdef CONFIG_STM32H5_TIM13 + /* Bit 5: TIM13 clock enable */ + + regval |= RCC_APB1LENR_TIM13EN; +#endif + +#ifdef CONFIG_STM32H5_TIM14 + /* Bit 5: TIM14 clock enable */ + + regval |= RCC_APB1LENR_TIM14EN; +#endif + +#ifdef CONFIG_STM32H5_SPI2 + /* Bit 14: SPI2 clock enable */ + + regval |= RCC_APB1LENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32H5_SPI3 + /* Bit 15: SPI3 clock enable */ + + regval |= RCC_APB1LENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32H5_USART2 + /* Bit 17: USART2 clock enable */ + + regval |= RCC_APB1LENR_USART2EN; +#endif + +#ifdef CONFIG_STM32H5_USART3 + /* Bit 18: USART3 clock enable */ + + regval |= RCC_APB1LENR_USART3EN; +#endif + +#ifdef CONFIG_STM32H5_UART4 + /* Bit 19: UART4 clock enable */ + + regval |= RCC_APB1LENR_UART4EN; +#endif + +#ifdef CONFIG_STM32H5_UART5 + /* Bit 20: UART5 clock enable */ + + regval |= RCC_APB1LENR_UART5EN; +#endif + +#ifdef CONFIG_STM32H5_I2C1 + /* Bit 21: I2C1 clock enable */ + + regval |= RCC_APB1LENR_I2C1EN; +#endif + +#ifdef CONFIG_STM32H5_I2C2 + /* Bit 22: I2C2 clock enable */ + + regval |= RCC_APB1LENR_I2C2EN; +#endif + +#ifdef CONFIG_STM32H5_I3C1 + /* Bit 23: I3C1 clock enable */ + + regval |= RCC_APB1LENR_I3C1EN; +#endif + +#ifdef STM32H5_USE_HSI48 + if (STM32H5_HSI48_SYNCSRC != SYNCSRC_NONE) + { + /* Bit 24: CRS clock enable */ + + regval |= RCC_APB1LENR_CRSEN; + } +#endif + +#ifdef CONFIG_STM32H5_USART6 + /* Bit 25: USART6 clock enable */ + + regval |= RCC_APB1LENR_USART6EN; +#endif + +#ifdef CONFIG_STM32H5_USART10 + /* Bit 26: USART10 clock enable */ + + regval |= RCC_APB1LENR_USART10EN; +#endif + +#ifdef CONFIG_STM32H5_USART11 + /* Bit 27: USART11 clock enable */ + + regval |= RCC_APB1LENR_USART11EN; +#endif + +#ifdef CONFIG_STM32H5_CEC + /* Bit 28: CEC clock enable */ + + regval |= RCC_APB1LENR_CECEN; +#endif + +#ifdef CONFIG_STM32H5_UART7 + /* Bit 30: UART7 clock enable */ + + regval |= RCC_APB1LENR_UART7EN; +#endif + +#ifdef CONFIG_STM32H5_UART8 + /* Bit 31: UART8 clock enable */ + + regval |= RCC_APB1LENR_UART8EN; +#endif + + putreg32(regval, STM32H5_RCC_APB1LENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1h + * + * Description: + * Enable selected APB1H peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1h(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1HENR register to enabled the + * selected APB1H peripherals. + */ + + regval = getreg32(STM32H5_RCC_APB1HENR); + +#ifdef CONFIG_STM32H5_UART9 + /* Bit 0: UART9 clock enable */ + + regval |= RCC_APB1HENR_UART9EN; +#endif + +#ifdef CONFIG_STM32H5_UART12 + /* Bit 1: UART12 clock enable */ + + regval |= RCC_APB1HENR_UART12EN; +#endif + +#ifdef CONFIG_STM32H5_DTS + /* Bit 3: DTS clock enable */ + + regval |= RCC_APB1HENR_DTSEN; +#endif + +#ifdef CONFIG_STM32H5_LPTIM2 + /* Bit 5: Low-power Timer 2 clock enable */ + + regval |= RCC_APB1HENR_LPTIM2EN; +#endif + +#ifdef CONFIG_STM32H5_FDCAN + /* Bit 9: FDCAN clock enable */ + + regval |= RCC_APB1HENR_FDCANEN; +#endif + +#ifdef CONFIG_STM32H5_UCPD1 + /* Bit 23: UCPD1 clock enable */ + + regval |= RCC_APB1HENR_UCPD1EN; +#endif + + /* Enable APB1H peripherals */ + + putreg32(regval, STM32H5_RCC_APB1HENR); + +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32H5_RCC_APB2ENR); + + +#ifdef CONFIG_STM32H5_TIM1 + /* TIM1 clock enable */ + + regval |= RCC_APB2ENR_TIM1EN; +#endif + +#ifdef CONFIG_STM32H5_SPI1 + /* SPI1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32H5_TIM8 + /* TIM8 clock enable */ + + regval |= RCC_APB2ENR_TIM8EN; +#endif + +#ifdef CONFIG_STM32H5_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32H5_TIM15 + /* TIM15 clock enable */ + + regval |= RCC_APB2ENR_TIM15EN; +#endif + +#ifdef CONFIG_STM32H5_TIM16 + /* TIM16 clock enable */ + + regval |= RCC_APB2ENR_TIM16EN; +#endif + +#ifdef CONFIG_STM32H5_TIM17 + /* TIM17 clock enable */ + + regval |= RCC_APB2ENR_TIM17EN; +#endif + +#ifdef CONFIG_STM32H5_SPI4 + /* SPI4 clock enable */ + + regval |= RCC_APB2ENR_SPI4EN; +#endif + +#ifdef CONFIG_STM32H5_SPI6 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SPI6EN; +#endif + +#ifdef CONFIG_STM32H5_SAI1 + /* SAI1 clock enable */ + + regval |= RCC_APB2ENR_SAI1EN; +#endif + +#ifdef CONFIG_STM32H5_SAI2 + /* SAI2 clock enable */ + + regval |= RCC_APB2ENR_SAI2EN; +#endif + +#ifdef CONFIG_STM32H5_USB + /* USB clock enable */ + + regval |= RCC_APB2ENR_USBEN; +#endif + + putreg32(regval, STM32H5_RCC_APB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb3 + * + * Description: + * Enable selected APB3 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb3(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32H5_RCC_APB3ENR); + + +#ifdef CONFIG_STM32H5_SBS + /* Bit 1: SBS clock enable */ + + regval |= RCC_APB3ENR_SBSEN; +#endif + +#ifdef CONFIG_STM32H5_SPI5 + /* Bit 5: SPI5 clock enable */ + + regval |= RCC_APB3ENR_SPI5EN; +#endif + +#ifdef CONFIG_STM32H5_LPUART1 + /* Bit 6: LPUART1 clock enable */ + + regval |= RCC_APB3ENR_LPUART1EN; +#endif + +#ifdef CONFIG_STM32H5_I2C3 + /* Bit 7: I2C3 clock enable */ + + regval |= RCC_APB3ENR_I2C3EN; +#endif + +#ifdef CONFIG_STM32H5_I2C4 + /* Bit 8: I2C4 clock enable */ + + regval |= RCC_APB3ENR_I2C4EN; +#endif + +#ifdef CONFIG_STM32H5_I3C2 + /* Bit 9: I3C2 clock enable */ + + regval |= RCC_APB3ENR_I3C2EN; +#endif + +#ifdef CONFIG_STM32H5_LPTIM1 + /* Bit 11: LPTIM1 clock enable */ + + regval |= RCC_APB3ENR_LPTIM1EN; +#endif + +#ifdef CONFIG_STM32H5_LPTIM3 + /* Bit 12: LPTIM3 clock enable */ + + regval |= RCC_APB3ENR_LPTIM3EN; +#endif + +#ifdef CONFIG_STM32H5_LPTIM4 + /* Bit 13: LPTIM4 clock enable */ + + regval |= RCC_APB3ENR_LPTIM4EN; +#endif + +#ifdef CONFIG_STM32H5_LPTIM5 + /* Bit 14: LPTIM5 clock enable */ + + regval |= RCC_APB3ENR_LPTIM5EN; +#endif + +#ifdef CONFIG_STM32H5_LPTIM6 + /* Bit 15: LPTIM6 clock enable */ + + regval |= RCC_APB3ENR_LPTIM6EN; +#endif + +#ifdef CONFIG_STM32H5_VREF + /* Bit 20: VREF clock enable */ + + regval |= RCC_APB3ENR_VREFEN; +#endif + +#ifdef CONFIG_STM32H5_RTCAPB + /* Bit 21: RTCABP clock enable */ + + regval |= RCC_APB3ENR_RTCAPBEN; +#endif + + + /* Enable peripherals */ + + putreg32(regval, STM32H5_RCC_APB3ENR); + +} +/**************************************************************************** + * Name: rcc_enableccip + * + * Description: + * Set peripherals independent clock configuration. + * + ****************************************************************************/ + +static inline void rcc_enableccip(void) +{ + +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_rcc_enableperipherals + ****************************************************************************/ + +void stm32h5_rcc_enableperipherals(void) +{ + rcc_enableccip(); + rcc_enableahb1(); + rcc_enableahb2(); + rcc_enableahb4(); + rcc_enableapb1l(); + rcc_enableapb1h(); + rcc_enableapb2(); + rcc_enableapb3(); + +#ifdef STM32H5_USE_HSI48 + /* Enable HSI48 clocking to support USB transfers or RNG */ + + stm32h5_enable_hsi48(STM32L4_HSI48_SYNCSRC); +#endif + +} + +/**************************************************************************** + * Name: stm32h5_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +void stm32h5_stdclockconfig(void) +{ + uint32_t regval; + volatile int32_t timeout; + +#if defined(STM32H5_BOARD_USEHSI) + /* Enable Internal High-Speed Clock (HSI) */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_HSION; /* Enable HSI */ + +#if defined(STMT32H5_CR_HSIDIV) + regval |= STM32H5_CR_HSIDIV; +#else + /* Use default (32 MHz) */ + +#endif + + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until the HSI is ready (or until a timeout elapsed) */ + + for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSIRDY flag is the set in the CR */ + + if ((getreg32(STM32H5_RCC_CR) & RCC_CR_HSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + + /* Make sure HSIDIVF is also not 0 */ + + for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSIRDY flag is the set in the CR */ + + if ((getreg32(STM32H5_RCC_CR) & RCC_CR_HSIDIVF) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } +#endif + +#if defined(STM32H5_BOARD_USEHSI) + /* Already set above */ + +#elif defined(STM32H5_BOARD_USECSI) + /* Enable Internal Low Power Internal Clock (CSI) */ + + /* Wait until the CSI is either off or ready (or until a timeout elapsed) */ + + for (timeout = CSIRDY_TIMEOUT; timeout > 0; timeout--) + { + if ((regval = getreg32(STM32H5_RCC_CR)), + (regval & RCC_CR_CSIRDY) || ~(regval & RCC_CR_CSION)) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_CSION; /* Enable CSI */ + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until the CSI is ready (or until a timeout elapsed) */ + + for (timeout = CSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the CSIRDY flag is the set in the CR */ + + if ((getreg32(STM32H5_RCC_CR) & RCC_CR_CSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + +#elif defined(STM32H5_BOARD_USEHSE) + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32H5_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } +#else + +# error stm32h5_stdclockconfig(), must have one of STM32H5_BOARD_USEHSI, STM32H5_BOARD_USECSI, STM32H5_BOARD_USEHSE defined + +#endif + + /* Check for a timeout. If this timeout occurs, then we are hosed. We + * have no real back-up plan, although the following logic makes it look + * as though we do. + */ + + if (timeout > 0) + { + /* Select main regulator voltage range according to system clock + * frequency. + */ + + stm32h5_pwr_adjustvcore(STM32H5_SYSCLK_FREQUENCY); + + regval = getreg32(STM32H5_RCC_CFGR2); + /* Set the HCLK source/divider */ + + regval &= ~RCC_CFGR2_HPRE_MASK; + regval |= STM32H5_RCC_CFGR2_HPRE; + + /* Set the PCLK1 divider */ + + regval &= ~RCC_CFGR2_PPRE1_MASK; + regval |= STM32H5_RCC_CFGR2_PPRE1; + + /* Set the PCLK2 divider */ + + regval &= ~RCC_CFGR2_PPRE2_MASK; + regval |= STM32H5_RCC_CFGR2_PPRE2; + + /* Set the PCLK3 divider */ + + regval &= ~RCC_CFGR2_PPRE3_MASK; + regval |= STM32H5_RCC_CFGR2_PPRE3; + + putreg32(regval, STM32H5_RCC_CFGR2); + + +#ifdef CONFIG_STM32H5_RTC_HSECLOCK + /* Set the RTC clock divisor */ + + regval = getreg32(STM32H5_RCC_CFGR1); + regval &= ~RCC_CFGR1_RTCPRE_MASK; + regval |= RCC_CFGR1_RTCPRE(HSE_DIVISOR); + putreg32(regval, STM32H5_RCC_CFGR1); +#endif + + /* Configure PLL1 */ + + /* PLL1CFGR */ + + regval = getreg32(STM32H5_RCC_PLL1CFGR); + + /* Set the PLL1 source and main divider */ + +/* Can keep below ifdefs and add ifdefs on top for board.h definitions */ + +#ifdef STM32H5_PLL1SRC_HSI + regval |= RCC_PLL1CFGR_PLL1SRC_HSI; +#elif defined(STM32H5_PLL1SRC_CSI) + regval |= RCC_PLL1CFGR_PLL1SRC_CSI; +#elif defined(STM32H5_PLL1SRC_HSE) + regval |= RCC_PLL1CFGR_PLL1SRC_HSE; +#elif defined(STM32H5_BOARD_USEHSI) + regval |= RCC_PLL1CFGR_PLL1SRC_HSI; +#elif defined(STM32H5_BOARD_USECSI) + regval |= RCC_PLL1CFGR_PLL1SRC_CSI; +#else /* if STM32H5_BOARD_USEHSE */ + regval |= RCC_PLL1CFGR_PLL1SRC_HSE; +#endif + + /* Set RGE, FRACEN, VCOSEL, and M from board.h */ + + regval |= (STM32H5_PLL1CFGR_PLL1RGE | STM32H5_PLL1CFGR_PLL1FRACEN | + STM32H5_PLL1CFGR_PLL1VCOSEL | STM32H5_PLL1CFGR_PLL1M); + +#ifdef STM32H5_PLL1CFGR_PLL1P_ENABLED + regval |= RCC_PLL1CFGR_PLL1PEN; +#endif +#ifdef STM32H5_PLL1CFGR_PLL1Q_ENABLED + regval |= RCC_PLL1CFGR_PLL1QEN; +#endif +#ifdef STM32H5_PLL1CFGR_PLL1R_ENABLED + regval |= RCC_PLL1CFGR_PLL1REN; +#endif + + putreg32(regval, STM32H5_RCC_PLL1CFGR); + + /* PLL1DIVR and PLL1FRACR */ + + /* Get settings from board.h */ + + /* PLL1DIVR */ + + regval = getreg32(STM32H5_RCC_PLL1DIVR); + regval = (STM32H5_PLL1DIVR_PLL1N | STM32H5_PLL1DIVR_PLL1P | + STM32H5_PLL1DIVR_PLL1Q | STM32H5_PLL1DIVR_PLL1R); + putreg32(regval, STM32H5_RCC_PLL1DIVR); + + /* PLL1FRACR */ + + regval = getreg32(STM32H5_RCC_PLL1FRACR); + regval |= STM32H5_PLL1FRACR_PLL1FRACN; + putreg32(regval, STM32H5_RCC_PLL1FRACR); + + /* Enable PLL1 */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_PLL1ON; + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until PLL1 is ready */ + + while ((getreg32(STM32H5_RCC_CR) & RCC_CR_PLL1RDY) == 0) + { + } + + /* Configure PLL2 */ + + /* PLL2CFGR */ + + regval = getreg32(STM32H5_RCC_PLL2CFGR); + + /* Set the PLL2 source and main divider */ + +#ifdef STM32H5_PLL2SRC_HSI + regval |= RCC_PLL2CFGR_PLL2SRC_HSI; +#elif defined(STM32H5_PLL2SRC_CSI) + regval |= RCC_PLL2CFGR_PLL2SRC_CSI; +#elif defined(STM32H5_PLL2SRC_HSE) + regval |= RCC_PLL2CFGR_PLL2SRC_HSE; +#elif defined(STM32H5_BOARD_USEHSI) + regval |= RCC_PLL2CFGR_PLL2SRC_HSI; +#elif defined(STM32H5_BOARD_USECSI) + regval |= RCC_PLL2CFGR_PLL2SRC_CSI; +#else /* if STM32H5_BOARD_USEHSE */ + regval |= RCC_PLL2CFGR_PLL2SRC_HSE; +#endif + + /* Set RGE, FRACEN, VCOSEL, and M from board.h */ + + regval |= (STM32H5_PLL2CFGR_PLL2RGE | STM32H5_PLL2CFGR_PLL2FRACEN | + STM32H5_PLL2CFGR_PLL2VCOSEL | STM32H5_PLL2CFGR_PLL2M); + +#ifdef STM32H5_PLL2CFGR_PLL2P_ENABLED + regval |= RCC_PLL2CFGR_PLL2PEN; +#endif +#ifdef STM32H5_PLL2CFGR_PLL2Q_ENABLED + regval |= RCC_PLL2CFGR_PLL2QEN; +#endif +#ifdef STM32H5_PLL2CFGR_PLL2R_ENABLED + regval |= RCC_PLL2CFGR_PLL2REN; +#endif + + putreg32(regval, STM32H5_RCC_PLL2CFGR); + + /* PLL2DIVR and PLL2FRACR */ + + /* Get settings from board.h */ + + /* PLL2DIVR */ + + regval = getreg32(STM32H5_RCC_PLL2DIVR); + regval = (STM32H5_PLL2DIVR_PLL2N | STM32H5_PLL2DIVR_PLL2P | + STM32H5_PLL2DIVR_PLL2Q | STM32H5_PLL2DIVR_PLL2R); + putreg32(regval, STM32H5_RCC_PLL2DIVR); + + /* PLL2FRACR */ + + regval = getreg32(STM32H5_RCC_PLL2FRACR); + regval |= STM32H5_PLL2FRACR_PLL2FRACN; + putreg32(regval, STM32H5_RCC_PLL2FRACR); + + /* Enable PLL2 */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_PLL2ON; + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until PLL2 is ready */ + + while ((getreg32(STM32H5_RCC_CR) & RCC_CR_PLL2RDY) == 0) + { + } + + /* Configure PLL3 */ + + /* PLL3CFGR */ + + regval = getreg32(STM32H5_RCC_PLL3CFGR); + + /* Set the PLL3 source and main divider */ + +#ifdef STM32H5_PLL3SRC_HSI + regval |= RCC_PLL3CFGR_PLL3SRC_HSI; +#elif defined(STM32H5_PLL3SRC_CSI) + regval |= RCC_PLL3CFGR_PLL3SRC_CSI; +#elif defined(STM32H5_PLL3SRC_HSE) + regval |= RCC_PLL3CFGR_PLL3SRC_HSE; +#elif defined(STM32H5_BOARD_USEHSI) + regval |= RCC_PLL3CFGR_PLL3SRC_HSI; +#elif defined(STM32H5_BOARD_USECSI) + regval |= RCC_PLL3CFGR_PLL3SRC_CSI; +#else /* if STM32H5_BOARD_USEHSE */ + regval |= RCC_PLL3CFGR_PLL3SRC_HSE; +#endif + + /* Set RGE, FRACEN, VCOSEL, and M from board.h */ + + regval |= (STM32H5_PLL3CFGR_PLL3RGE | STM32H5_PLL3CFGR_PLL3FRACEN | + STM32H5_PLL3CFGR_PLL3VCOSEL | STM32H5_PLL3CFGR_PLL3M); + +#ifdef STM32H5_PLL3CFGR_PLL3P_ENABLED + regval |= RCC_PLL3CFGR_PLL3PEN; +#endif +#ifdef STM32H5_PLL3CFGR_PLL3Q_ENABLED + regval |= RCC_PLL3CFGR_PLL3QEN; +#endif +#ifdef STM32H5_PLL3CFGR_PLL3R_ENABLED + regval |= RCC_PLL3CFGR_PLL3REN; +#endif + + putreg32(regval, STM32H5_RCC_PLL3CFGR); + + /* PLL3DIVR and PLL3FRACR */ + + /* Get settings from board.h */ + + /* PLL3DIVR */ + + regval = getreg32(STM32H5_RCC_PLL3DIVR); + regval = (STM32H5_PLL3DIVR_PLL3N | STM32H5_PLL3DIVR_PLL3P | + STM32H5_PLL3DIVR_PLL3Q | STM32H5_PLL3DIVR_PLL3R); + putreg32(regval, STM32H5_RCC_PLL3DIVR); + + /* PLL3FRACR */ + + regval = getreg32(STM32H5_RCC_PLL3FRACR); + regval |= STM32H5_PLL3FRACR_PLL3FRACN; + putreg32(regval, STM32H5_RCC_PLL3FRACR); + + /* Enable PLL3 */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_PLL3ON; + putreg32(regval, STM32H5_RCC_CR); + + /* Wait until PLL3 is ready */ + + while ((getreg32(STM32H5_RCC_CR) & RCC_CR_PLL3RDY) == 0) + { + } + + /* 250 MHz SYSCLK. VOS0 = 1.30V to 1.40V + * Enable FLASH 5 wait states + * See Table 44. in Reference Manual + */ + + regval = FLASH_ACR_LATENCY_5; + putreg32(regval, STM32H5_FLASH_ACR); + + /* Select the main PLL as system clock source */ + + regval = getreg32(STM32H5_RCC_CFGR1); + regval &= ~RCC_CFGR1_SW_MASK; + regval |= RCC_CFGR1_SW_PLL; + putreg32(regval, STM32H5_RCC_CFGR1); + + /* Wait until the PLL source is used as the system clock source */ + + while ((getreg32(STM32H5_RCC_CFGR1) & RCC_CFGR1_SWS_MASK) != + RCC_CFGR1_SWS_PLL) + { + } + +#if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \ + defined(STM32H5_USE_LSCO_LSI) + + /* Low speed internal clock source LSI */ + + stm32h5_rcc_enablelsi(); +#endif + +#if defined(STM32H5_USE_LSE) || defined(STM32H5_USE_LSCO_LSE) + /* Low speed external clock source LSE */ + + stm32h5_rcc_enablelse(); +#else + /* + * There is another case where the LSE needs to + * be enabled: if the MCO1 pin selects LSE as source. + * Other cases can be handled by peripheral drivers. + */ + + if ((getreg32(STM32_RCC_CFGR1) & RCC_CFGR1_MCO1SEL_MASK) == + RCC_CFGR1_MCO1SEL_LSE) + { + stm32h5_rcc_enablelse(); + } + +#endif /* STM32H5_USE_LSE */ + } +} +#endif diff --git a/arch/arm/src/stm32h5/stm32h5_allocateheap.c b/arch/arm/src/stm32h5/stm32h5_allocateheap.c new file mode 100644 index 0000000000000..017051ddcbfa5 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_allocateheap.c @@ -0,0 +1,371 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "mpu.h" +#include "arm_internal.h" +#include "stm32h5_mpuinit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Internal SRAM is available in all members of the STM32H5 family. The + * following definitions must be provided to specify the size and + * location of internal (system) SRAM1 and SRAM2: + * + * SRAM1_START 0x20000000 + * SRAM1_END + * SRAM2_START 0x10000000 + * SRAM2_END + * + * In addition to internal SRAM, memory may also be available through the + * FSMC. In order to use FSMC SRAM, the following additional things need to + * be present in the NuttX configuration file: + * + * CONFIG_STM32H5_FSMC=y : Enables the FSMC + * CONFIG_STM32H5_FSMC_SRAM=y : Indicates that SRAM is available via the + * FSMC (as opposed to an LCD or FLASH). + * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC + * address space + * CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC + * address space + * CONFIG_MM_REGIONS : Must be set to a large enough value to + * include the additional regions. + */ + +#ifndef CONFIG_STM32H5_FSMC +# undef CONFIG_STM32H5_FSMC_SRAM +#endif + +/* STM32H5[7,8]6xx have 128 Kib in two banks, both accessible to DMA: + * + * 1) 96 KiB of System SRAM beginning at address 0x2000:0000 - 0x2001:8000 + * 2) 32 KiB of System SRAM beginning at address 0x1000:0000 - 0x1000:8000 + * + * STM32H596xx have 320 Kib in two banks, both accessible to DMA: + * + * 1) 256 KiB of System SRAM beginning at address 0x2000:0000 - 0x2004:0000 + * 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000 + * + * STM32H5Rxxx have 640 Kib in three banks: + * + * 1) 192 KiB of System SRAM beginning at address 0x2000:0000 - 0x2003:0000 + * 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000 + * 3) 384 KiB of System SRAM beginning at address 0x2004:0000 - 0x200A:0000 + * + * In addition, external FSMC SRAM may be available. + */ + +/* Set the range of system SRAM */ + +#define SRAM1_START STM32H5_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32H5_SRAM1_SIZE) + +/* Set the range of SRAM2 as well, requires a second memory region */ + +#define SRAM2_START STM32H5_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32H5_SRAM2_SIZE) + +/* Set the range of SRAM3, requiring a third memory region */ + +#ifdef STM32H5_SRAM3_SIZE +# define SRAM3_START STM32H5_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32H5_SRAM3_SIZE) +#endif + +/* Some sanity checking. If multiple memory regions are defined, verify + * that CONFIG_MM_REGIONS is set to match the number of memory regions + * that we have been asked to add to the heap. + */ + +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32H5_SRAM2_HEAP) + \ + defined(CONFIG_STM32H5_SRAM3_HEAP) + \ + defined(CONFIG_STM32H5_FSMC_SRAM_HEAP) + 1 +# error "You need more memory manager regions to support selected heap components" +#endif + +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32H5_SRAM2_HEAP) + \ + defined(CONFIG_STM32H5_SRAM3_HEAP) + \ + defined(CONFIG_STM32H5_FSMC_SRAM_HEAP) + 1 +# warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" +#endif + +/* If FSMC SRAM is going to be used as heap, then verify that the starting + * address and size of the external SRAM region has been provided in the + * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). + */ + +#ifdef CONFIG_STM32H5_FSMC_SRAM +# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) +# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" +# undef CONFIG_STM32H5_FSMC_SRAM +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_heap_color + * + * Description: + * Set heap memory to a known, non-zero state to checking heap usage. + * + ****************************************************************************/ + +#ifdef CONFIG_HEAP_COLORATION +static inline void up_heap_color(void *start, size_t size) +{ + memset(start, HEAP_COLOR, size); +} +#else +# define up_heap_color(start,size) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size given by CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +void up_allocate_heap(void **heap_start, size_t *heap_size) +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = SRAM1_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)SRAM1_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the SRAM1_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = SRAM1_END - usize; + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)ubase; + *heap_size = usize; + + /* Colorize the heap for debug */ + + up_heap_color((void *)ubase, usize); + + /* Allow user-mode access to the user heap memory */ + + stm32h5_mpu_uheap((uintptr_t)ubase, usize); +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)g_idle_topstack; + *heap_size = SRAM1_END - g_idle_topstack; + + /* Colorize the heap for debug */ + + up_heap_color(*heap_start, *heap_size); +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * (and protects) the kernel-space heap. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = SRAM1_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)SRAM1_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the SRAM1_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = SRAM1_END - usize; + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif + +/**************************************************************************** + * Name: arm_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void arm_addregion(void) +{ +#ifdef CONFIG_STM32H5_SRAM2_HEAP + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + + /* Allow user-mode access to the SRAM2 heap */ + + stm32h5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + +#endif + + /* Colorize the heap for debug */ + + up_heap_color((void *)SRAM2_START, SRAM2_END - SRAM2_START); + + /* Add the SRAM2 user heap region. */ + + kumm_addregion((void *)SRAM2_START, SRAM2_END - SRAM2_START); + +#endif /* SRAM2 */ + +#ifdef CONFIG_STM32H5_SRAM3_HEAP + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + + /* Allow user-mode access to the SRAM3 heap */ + + stm32h5_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); + +#endif + + /* Colorize the heap for debug */ + + up_heap_color((void *)SRAM3_START, SRAM3_END - SRAM3_START); + + /* Add the SRAM3 user heap region. */ + + kumm_addregion((void *)SRAM3_START, SRAM3_END - SRAM3_START); + +#endif /* SRAM3 */ + +#ifdef CONFIG_STM32H5_FSMC_SRAM_HEAP +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + + /* Allow user-mode access to the FSMC SRAM user heap memory */ + + stm32h5_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + +#endif + + /* Colorize the heap for debug */ + + up_heap_color((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + + /* Add the external FSMC SRAM user heap region. */ + + kumm_addregion((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); +#endif +} +#endif diff --git a/arch/arm/src/stm32h5/stm32h5_dbgmcu.h b/arch/arm/src/stm32h5/stm32h5_dbgmcu.h new file mode 100644 index 0000000000000..67e7b79a5a848 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_dbgmcu.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_dbgmcu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_DBGMCU_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#if defined(CONFIG_STM32H5_STM32H5XXXX) +# include "hardware/stm32h562xx_dbgmcu.h" +#else +# error "Unsupported STM32H5 chip" +#endif + +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_DBGMCU_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_flash.h b/arch/arm/src/stm32h5/stm32h5_flash.h new file mode 100644 index 0000000000000..718f1bed92465 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_flash.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm/src/stm32l5/stm32l5_flash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H +#define __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/stm32h5_flash.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void stm32l5_flash_lock(void); +void stm32l5_flash_unlock(void); + +/**************************************************************************** + * Name: stm32l5_flash_user_optbytes + * + * Description: + * Modify the contents of the user option bytes (USR OPT) on the flash. + * This does not set OBL_LAUNCH so new options take effect only after + * next power reset. + * + * Input Parameters: + * clrbits - Bits in the option bytes to be cleared + * setbits - Bits in the option bytes to be set + * + * Returned Value: + * Option bytes after operation is completed + * + ****************************************************************************/ + +uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); + +#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_gpio.c b/arch/arm/src/stm32h5/stm32h5_gpio.c new file mode 100644 index 0000000000000..ddbd773a4e772 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_gpio.c @@ -0,0 +1,402 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32h5_gpio.h" + + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#if defined(CONFIG_STM32H5_USE_LEGACY_PINMAP) +# pragma message "CONFIG_STM32H5_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py" +#endif + +/* Base addresses for each GPIO block */ + +const uint32_t g_gpiobase[STM32H5_NPORTS] = +{ +#if STM32H5_NPORTS > 0 + STM32H5_GPIOA_BASE, +#endif +#if STM32H5_NPORTS > 1 + STM32H5_GPIOB_BASE, +#endif +#if STM32H5_NPORTS > 2 + STM32H5_GPIOC_BASE, +#endif +#if STM32H5_NPORTS > 3 + STM32H5_GPIOD_BASE, +#endif +#if STM32H5_NPORTS > 4 + STM32H5_GPIOE_BASE, +#endif +#if STM32H5_NPORTS > 5 + STM32H5_GPIOF_BASE, +#endif +#if STM32H5_NPORTS > 6 + STM32H5_GPIOG_BASE, +#endif +#if STM32H5_NPORTS > 7 + STM32H5_GPIOH_BASE, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32h5_gpioinit + * + * Description: + * Based on configuration within the .config file, it does: + * - Remaps positions of alternative functions. + * + * Typically called from stm32h5_start(). + * + * Assumptions: + * This function is called early in the initialization sequence so that + * no mutual exclusion is necessary. + * + ****************************************************************************/ + +void stm32h5_gpioinit(void) +{ +} + +/**************************************************************************** + * Name: stm32h5_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) + * function, it must be unconfigured with stm32h5_unconfiggpio() with + * the same cfgset first before it can be set to non-alternative function. + * + * Returned Value: + * OK on success + * A negated errno value on invalid port, or when pin is locked as ALT + * function. + * + * To-Do: Auto Power Enable + ****************************************************************************/ + +int stm32h5_configgpio(uint32_t cfgset) +{ + uintptr_t base; + uint32_t regval; + uint32_t setting; + unsigned int regoffset; + unsigned int port; + unsigned int pin; + unsigned int pos; + unsigned int pinmode; + irqstate_t flags; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= STM32H5_NPORTS) + { + return -EINVAL; + } + + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number and select the port configuration register for that + * pin + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set up the mode register (and remember whether the pin mode) */ + + switch (cfgset & GPIO_MODE_MASK) + { + default: + case GPIO_INPUT: /* Input mode */ + pinmode = GPIO_MODER_INPUT; + break; + + case GPIO_OUTPUT: /* General purpose output mode */ + + /* Set the initial output value */ + + stm32h5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + pinmode = GPIO_MODER_OUTPUT; + break; + + case GPIO_ALT: /* Alternate function mode */ + pinmode = GPIO_MODER_ALT; + break; + + case GPIO_ANALOG: /* Analog mode */ + pinmode = GPIO_MODER_ANALOG; + break; + } + + /* Interrupts must be disabled from here on out so that we have mutually + * exclusive access to all of the GPIO configuration registers. + */ + + flags = enter_critical_section(); + + /* Now apply the configuration to the mode register */ + + regval = getreg32(base + STM32H5_GPIO_MODER_OFFSET); + regval &= ~GPIO_MODER_MASK(pin); + regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); + putreg32(regval, base + STM32H5_GPIO_MODER_OFFSET); + + /* Set up the pull-up/pull-down configuration (all but analog pins) */ + + setting = GPIO_PUPDR_NONE; + if (pinmode != GPIO_MODER_ANALOG) + { + switch (cfgset & GPIO_PUPD_MASK) + { + default: + case GPIO_FLOAT: /* No pull-up, pull-down */ + break; + + case GPIO_PULLUP: /* Pull-up */ + setting = GPIO_PUPDR_PULLUP; + break; + + case GPIO_PULLDOWN: /* Pull-down */ + setting = GPIO_PUPDR_PULLDOWN; + break; + } + } + + regval = getreg32(base + STM32H5_GPIO_PUPDR_OFFSET); + regval &= ~GPIO_PUPDR_MASK(pin); + regval |= (setting << GPIO_PUPDR_SHIFT(pin)); + putreg32(regval, base + STM32H5_GPIO_PUPDR_OFFSET); + + /* Set the alternate function (Only alternate function pins) */ + + if (pinmode == GPIO_MODER_ALT) + { + setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT; + } + else + { + setting = 0; + } + + if (pin < 8) + { + regoffset = STM32H5_GPIO_AFRL_OFFSET; + pos = pin; + } + else + { + regoffset = STM32H5_GPIO_AFRH_OFFSET; + pos = pin - 8; + } + + regval = getreg32(base + regoffset); + regval &= ~GPIO_AFR_MASK(pos); + regval |= (setting << GPIO_AFR_SHIFT(pos)); + putreg32(regval, base + regoffset); + + /* Set speed (Only outputs and alternate function pins) */ + + if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) + { + switch (cfgset & GPIO_SPEED_MASK) + { + default: + case GPIO_SPEED_2MHZ: /* 2 MHz Low speed output */ + setting = GPIO_OSPEED_2MHZ; + break; + + case GPIO_SPEED_25MHZ: /* 25 MHz Medium speed output */ + setting = GPIO_OSPEED_25MHZ; + break; + + case GPIO_SPEED_50MHZ: /* 50 MHz High speed output */ + setting = GPIO_OSPEED_50MHZ; + break; + + case GPIO_SPEED_100MHZ: /* 100 MHz Very High speed output */ + setting = GPIO_OSPEED_100MHZ; + break; + } + } + else + { + setting = 0; + } + + regval = getreg32(base + STM32H5_GPIO_OSPEED_OFFSET); + regval &= ~GPIO_OSPEED_MASK(pin); + regval |= (setting << GPIO_OSPEED_SHIFT(pin)); + putreg32(regval, base + STM32H5_GPIO_OSPEED_OFFSET); + + /* Set push-pull/open-drain (Only outputs and alternate function pins) */ + + regval = getreg32(base + STM32H5_GPIO_OTYPER_OFFSET); + setting = GPIO_OTYPER_OD(pin); + + if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && + (cfgset & GPIO_OPENDRAIN) != 0) + { + regval |= setting; + } + else + { + regval &= ~setting; + } + + putreg32(regval, base + STM32H5_GPIO_OTYPER_OFFSET); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32h5_unconfiggpio + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin, set + * it into default HiZ state (and possibly mark it's unused) and unlock it + * whether it was previously selected as alternative function + * (GPIO_ALT|GPIO_CNF_AFPP|...). + * + * This is a safety function and prevents hardware from shocks, as + * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' + * while it should operate in PWM mode could produce excessive on-board + * currents and trigger over-current/alarm function. + * + * Returned Value: + * OK on success + * A negated errno value on invalid port + * + * To-Do: Auto Power Disable + ****************************************************************************/ + +int stm32h5_unconfiggpio(uint32_t cfgset) +{ + /* Reuse port and pin number and set it to default HiZ INPUT */ + + cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK; + cfgset |= GPIO_INPUT | GPIO_FLOAT; + + /* To-Do: Mark its unuse for automatic power saving options */ + + return stm32h5_configgpio(cfgset); +} + +/**************************************************************************** + * Name: stm32h5_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void stm32h5_gpiowrite(uint32_t pinset, bool value) +{ + uint32_t base; + uint32_t bit; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < STM32H5_NPORTS) + { + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set or clear the output on the pin */ + + if (value) + { + bit = GPIO_BSRR_SET(pin); + } + else + { + bit = GPIO_BSRR_RESET(pin); + } + + putreg32(bit, base + STM32H5_GPIO_BSRR_OFFSET); + } +} + +/**************************************************************************** + * Name: stm32h5_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool stm32h5_gpioread(uint32_t pinset) +{ + uint32_t base; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < STM32H5_NPORTS) + { + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number and return the input state of that pin */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + return ((getreg32(base + STM32H5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + } + + return 0; +} diff --git a/arch/arm/src/stm32h5/stm32h5_gpio.h b/arch/arm/src/stm32h5/stm32h5_gpio.h new file mode 100644 index 0000000000000..02c2befdadd3b --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_gpio.h @@ -0,0 +1,363 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_GPIO_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include +#include + +#include "chip.h" + +#if defined(CONFIG_STM32H5_STM32H5XXXX) +# include "hardware/stm32h5_gpio.h" +#else +# error "Unsupported STM32H5 chip" +#endif + +/**************************************************************************** + * Pre-Processor Declarations + ****************************************************************************/ + +/* Bit-encoded input to stm32h5_configgpio() */ + +/* Each port bit of the general-purpose I/O (GPIO) ports can be individually + * configured by software in several modes: + * + * - Input floating + * - Input pull-up + * - Input-pull-down + * - Output open-drain with pull-up or pull-down capability + * - Output push-pull with pull-up or pull-down capability + * - Alternate function push-pull with pull-up or pull-down capability + * - Alternate function open-drain with pull-up or pull-down capability + * - Analog + * + * 20-bit Encoding: 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * Inputs: MMUU .... ...X PPPP BBBB + * Outputs: MMUU .... FFOV PPPP BBBB + * Alternate Functions: MMUU AAAA FFO. PPPP BBBB + * Analog: MM.. .... .... PPPP BBBB + */ + +/* Mode: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * MM.. .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ +# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ +# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ + +/* Input/output pull-ups/downs (not used with analog): + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * ..UU .... .... .... .... + */ + +#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */ +#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT) +# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */ +# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */ +# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */ + +/* Alternate Functions: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... AAAA .... .... .... + */ + +#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */ +#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT) +# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) +# define GPIO_AF0 (0 << GPIO_AF_SHIFT) +# define GPIO_AF1 (1 << GPIO_AF_SHIFT) +# define GPIO_AF2 (2 << GPIO_AF_SHIFT) +# define GPIO_AF3 (3 << GPIO_AF_SHIFT) +# define GPIO_AF4 (4 << GPIO_AF_SHIFT) +# define GPIO_AF5 (5 << GPIO_AF_SHIFT) +# define GPIO_AF6 (6 << GPIO_AF_SHIFT) +# define GPIO_AF7 (7 << GPIO_AF_SHIFT) +# define GPIO_AF8 (8 << GPIO_AF_SHIFT) +# define GPIO_AF9 (9 << GPIO_AF_SHIFT) +# define GPIO_AF10 (10 << GPIO_AF_SHIFT) +# define GPIO_AF11 (11 << GPIO_AF_SHIFT) +# define GPIO_AF12 (12 << GPIO_AF_SHIFT) +# define GPIO_AF13 (13 << GPIO_AF_SHIFT) +# define GPIO_AF14 (14 << GPIO_AF_SHIFT) +# define GPIO_AF15 (15 << GPIO_AF_SHIFT) + +/* Output/Alt function frequency selection: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... FF.. .... .... + */ + +#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ +#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) +# define GPIO_SPEED_2MHZ (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ +# define GPIO_SPEED_25MHZ (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */ +# define GPIO_SPEED_50MHZ (2 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */ +# define GPIO_SPEED_100MHZ (3 << GPIO_SPEED_SHIFT) /* 100 MHz Very High speed output */ + +/* Output/Alt function type selection: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ..O. .... .... + */ + +#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */ +#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */ + +/* If the pin is a GPIO digital output, then this identifies the initial + * output value. If the pin is an input, this bit is overloaded to provide + * the qualifier to distinguish input pull-up and -down: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ...V .... .... + */ + +#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */ +#define GPIO_OUTPUT_CLEAR (0) + +/* External interrupt selection (GPIO inputs only): + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ...X .... .... + */ + +#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */ + +/* This identifies the GPIO port: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .... PPPP .... + */ + +#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ +#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) +# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ +# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ +# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ +# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ +# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ +# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ +# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ +# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ + +/* This identifies the bit in the port: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .... .... BBBB + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */ +#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Base addresses for each GPIO block */ + +EXTERN const uint32_t g_gpiobase[STM32H5_NPORTS]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) + * function, it must be unconfigured with stm32h5_unconfiggpio() with + * the same cfgset first before it can be set to non-alternative function. + * + * Returned Value: + * OK on success + * ERROR on invalid port, or when pin is locked as ALT function. + * + ****************************************************************************/ + +int stm32h5_configgpio(uint32_t cfgset); + +/**************************************************************************** + * Name: stm32h5_unconfiggpio + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin, set + * it into default HiZ state (and possibly mark it's unused) and unlock it + * whether it was previously selected as alternative function + * (GPIO_ALT|GPIO_CNF_AFPP|...). + * + * This is a safety function and prevents hardware from shocks, as + * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' + * while it should operate in PWM mode could produce excessive on-board + * currents and trigger over-current/alarm function. + * + * Returned Value: + * OK on success + * ERROR on invalid port + * + ****************************************************************************/ + +int stm32h5_unconfiggpio(uint32_t cfgset); + +/**************************************************************************** + * Name: stm32h5_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void stm32h5_gpiowrite(uint32_t pinset, bool value); + +/**************************************************************************** + * Name: stm32h5_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool stm32h5_gpioread(uint32_t pinset); + +/**************************************************************************** + * Name: stm32h5_gpiosetevent + * + * Description: + * Sets/clears GPIO based event and interrupt triggers. + * + * Input Parameters: + * pinset - GPIO pin configuration + * risingedge - Enables interrupt on rising edges + * fallingedge - Enables interrupt on falling edges + * event - Generate event when set + * func - When non-NULL, generate interrupt + * arg - Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) is returned on success, otherwise a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32h5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, + bool event, xcpt_t func, void *arg); + +/**************************************************************************** + * Function: stm32h5_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +int stm32h5_dumpgpio(uint32_t pinset, const char *msg); +#else +# define stm32h5_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Function: stm32h5_gpioinit + * + * Description: + * Based on configuration within the .config file, it does: + * - Remaps positions of alternative functions. + * + * Typically called from stm32h5_start(). + * + ****************************************************************************/ + +void stm32h5_gpioinit(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_GPIO_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_hsi48.c b/arch/arm/src/stm32h5/stm32h5_hsi48.c new file mode 100644 index 0000000000000..6b6e096e1aae2 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_hsi48.c @@ -0,0 +1,168 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_hsi48.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32h5_rcc.h" +#include "hardware/stm32h5_crs.h" + +#include "stm32h5_hsi48.h" + +#ifdef CONFIG_STM32H5_HAVE_HSI48 +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_enable_hsi48 + * + * Description: + * The HSI48 + * clock signal is generated from an internal 48 MHz RC oscillator and can + * be used directly as a system clock or divided and be used as PLL input. + * + * The internal 48MHz RC oscillator is mainly dedicated to provide a high + * precision clock to the USB peripheral by means of a special Clock + * Recovery System (CRS) circuitry, which could use the USB SOF signal or + * the LSE or an external signal to automatically adjust the oscillator + * frequency on-fly, in a very small steps. This oscillator can also be + * used as a system clock source when the system is in run mode; it will + * be disabled as soon as the system enters in Stop or Standby mode. When + * the CRS is not used, the HSI48 RC oscillator runs on its default + * frequency which is subject to manufacturing process variations. + * + * Input Parameters: + * Identifies the syncrhonization source for the HSI48. When used as the + * USB source clock, this must be set to SYNCSRC_USB. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) +{ + uint32_t regval; + + /* Enable the HSI48 clock. + * + * The HSI48 RC can be switched on and off using the HSI48ON bit in the + * Clock control register (RCC_CRRCR). + * + * The USB clock may be derived from either the PLL clock or from the + * HSI48 clock. This oscillator will be also automatically enabled (by + * hardware forcing HSI48ON bit to one) as soon as it is chosen as a clock + * source for the USB and the peripheral is + * enabled. + */ + + regval = getreg32(STM32H5_RCC_CR); + regval |= RCC_CR_HSI48ON; + putreg32(regval, STM32H5_RCC_CR); + + /* Wait for the HSI48 clock to stabilize */ + + while ((getreg32(STM32H5_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + + /* Return if no synchronization */ + + if (syncsrc == SYNCSRC_NONE) + { + return; + } + + /* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR + * register, can be the signal from the external CRS_SYNC pin, the LSE + * clock or the USB SOF signal. + */ + + regval = getreg32(STM32H5_CRS_CFGR); + regval &= ~CRS_CFGR_SYNCSRC_MASK; + + switch (syncsrc) + { + default: + case SYNCSRC_GPIO: /* GPIO selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_GPIO; + break; + + case SYNCSRC_LSE: /* LSE selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_LSE; + break; + + case SYNCSRC_USB: /* USB SOF selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_USBSOF; + break; + } + + putreg32(regval, STM32H5_CRS_CFGR); + + /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic + * hardware adjustment of TRIM bits according to the measured frequency + * error between the selected SYNC event. Also enable CEN bit to enable + * frequency error counter and SYNC events. + */ + + regval = getreg32(STM32H5_CRS_CR); + regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; + putreg32(regval, STM32H5_CRS_CR); +} + +/**************************************************************************** + * Name: stm32h5_disable_hsi48 + * + * Description: + * Disable the HSI48 clock. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32h5_disable_hsi48(void) +{ + uint32_t regval; + + /* Disable the HSI48 clock */ + + regval = getreg32(STM32H5_RCC_CR); + regval &= ~RCC_CR_HSI48ON; + putreg32(regval, STM32H5_RCC_CR); + + /* Set other registers to the default settings. */ + + regval = getreg32(STM32H5_CRS_CFGR); + regval &= ~CRS_CFGR_SYNCSRC_MASK; + putreg32(regval, STM32H5_CRS_CFGR); + + regval = getreg32(STM32H5_CRS_CR); + regval &= ~CRS_CR_AUTOTRIMEN; + putreg32(regval, STM32H5_CRS_CR); +} +#endif /* CONFIG_STM32H5_HAVE_HSI48 */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/stm32h5_hsi48.h b/arch/arm/src/stm32h5/stm32h5_hsi48.h new file mode 100644 index 0000000000000..cc109e05d0783 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_hsi48.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_hsi48.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_HSI48_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_HSI48_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32H5_HAVE_HSI48 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum syncsrc_e +{ + SYNCSRC_NONE = 0, /* No SYNC signal */ + SYNCSRC_GPIO, /* GPIO selected as SYNC signal source */ + SYNCSRC_LSE, /* LSE selected as SYNC signal source */ + SYNCSRC_USB, /* USB SOF selected as SYNC signal source */ +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_enable_hsi48 + * + * Description: + * On STM32H5X3, STM32H596xx/4A6xx and STM32H5XR devices only, the HSI48 + * clock signal is generated from an internal 48 MHz RC oscillator and can + * be used directly as a system clock or divided and be used as PLL input. + * + * The internal 48MHz RC oscillator is mainly dedicated to provide a high + * precision clock to the USB peripheral by means of a special Clock + * Recovery System (CRS) circuitry, which could use the USB SOF signal or + * the LSE or an external signal to automatically adjust the oscillator + * frequency on-fly, in a very small steps. This oscillator can also be + * used as a system clock source when the system is in run mode; it will + * be disabled as soon as the system enters in Stop or Standby mode. When + * the CRS is not used, the HSI48 RC oscillator runs on its default + * frequency which is subject to manufacturing process variations. + * + * Input Parameters: + * Identifies the syncrhonization source for the HSI48. When used as the + * USB source clock, this must be set to SYNCSRC_USB. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32h5_enable_hsi48(enum syncsrc_e syncsrc); + +/**************************************************************************** + * Name: stm32h5_disable_hsi48 + * + * Description: + * Disable the HSI48 clock. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32h5_disable_hsi48(void); + +#endif /* CONFIG_STM32H5_HAVE_HSI48 */ +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_HSI48_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_idle.c b/arch/arm/src/stm32h5/stm32h5_idle.c new file mode 100644 index 0000000000000..d5e6874e5bd86 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_idle.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include + +#include "chip.h" +#include "stm32h5_rcc.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#define up_idlepm() + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + up_idlepm(); + + /* Sleep until an interrupt occurs to save power. */ + +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif + +#endif +} diff --git a/arch/arm/src/stm32h5/stm32h5_irq.c b/arch/arm/src/stm32h5/stm32h5_irq.c new file mode 100644 index 0000000000000..63d6d64451653 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_irq.c @@ -0,0 +1,474 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "nvic.h" +#include "ram_vectors.h" +#include "arm_internal.h" +#include "stm32h5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void stm32h5_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); + irqinfo(" IRQ ENABLE: %08x %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE), + getreg32(NVIC_IRQ64_95_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), + getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), + getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY), + getreg32(NVIC_IRQ60_63_PRIORITY)); + irqinfo(" %08x\n", + getreg32(NVIC_IRQ64_67_PRIORITY)); + + leave_critical_section(flags); +} +#else +# define stm32h5_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: stm32h5_nmi, stm32h5_pendsv, stm32h5_pendsv, stm32h5_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provide over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int stm32h5_nmi(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int stm32h5_pendsv(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int stm32h5_reserved(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32h5_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV8M_USEBASEPRI +static inline void stm32h5_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Name: stm32h5_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int stm32h5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + int n; + + DEBUGASSERT(irq >= STM32H5_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= STM32H5_IRQ_FIRST) + { + n = irq - STM32H5_IRQ_FIRST; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + *bit = (uint32_t)1 << (n & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == STM32H5_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == STM32H5_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == STM32H5_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == STM32H5_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; + int num_priority_registers; + int i; + + /* Disable all interrupts */ + + for (i = 0; i < NR_IRQS - STM32H5_IRQ_FIRST; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + /* The standard location for the vector table is at the beginning of FLASH + * at address 0x0800:0000. If we are using the STMicro DFU bootloader, + * then the vector table will be offset to a different location in FLASH + * and we will need to set the NVIC vector location to this alternative + * location. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + up_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(STM32H5_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32H5_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + + /* up_prioritize_irq(STM32H5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + +#endif +#ifdef CONFIG_ARMV8M_USEBASEPRI + stm32h5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARM_MPU + irq_attach(STM32H5_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32H5_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(STM32H5_IRQ_NMI, stm32h5_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(STM32H5_IRQ_MEMFAULT, arm_memfault, NULL); +#endif + irq_attach(STM32H5_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32H5_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32H5_IRQ_PENDSV, stm32h5_pendsv, NULL); + arm_enable_dbgmonitor(); + irq_attach(STM32H5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32H5_IRQ_RESERVED, stm32h5_reserved, NULL); +#endif + + stm32h5_dumpnvic("initial", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (stm32h5_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= STM32H5_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (stm32h5_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= STM32H5_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= STM32H5_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < STM32H5_IRQ_FIRST) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= STM32H5_IRQ_FIRST; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32h5_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/stm32h5/stm32h5_lowputc.c b/arch/arm/src/stm32h5/stm32h5_lowputc.c new file mode 100644 index 0000000000000..d2190d39a6890 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_lowputc.c @@ -0,0 +1,550 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" +#include "chip.h" + +#include "stm32h5.h" +#include "stm32h5_rcc.h" +#include "stm32h5_gpio.h" +#include "stm32h5_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select USART parameters for the selected console */ + +#ifdef HAVE_CONSOLE +# if defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_LPUART1_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB3ENR +# define STM32H5_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN +# define STM32H5_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32H5_CONSOLE_TX GPIO_LPUART1_TX +# define STM32H5_CONSOLE_RX GPIO_LPUART1_RX +# ifdef CONFIG_LPUART1_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART1_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_USART1_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK2_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB2ENR +# define STM32H5_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32H5_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32H5_CONSOLE_TX GPIO_USART1_TX +# define STM32H5_CONSOLE_RX GPIO_USART1_RX +# ifdef CONFIG_USART1_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_USART2_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART2EN +# define STM32H5_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32H5_CONSOLE_TX GPIO_USART2_TX +# define STM32H5_CONSOLE_RX GPIO_USART2_RX +# ifdef CONFIG_USART2_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_USART3_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART3EN +# define STM32H5_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32H5_CONSOLE_TX GPIO_USART3_TX +# define STM32H5_CONSOLE_RX GPIO_USART3_RX +# ifdef CONFIG_USART3_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_UART4_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART4EN +# define STM32H5_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32H5_CONSOLE_TX GPIO_UART4_TX +# define STM32H5_CONSOLE_RX GPIO_UART4_RX +# ifdef CONFIG_UART4_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_UART5_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART5EN +# define STM32H5_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32H5_CONSOLE_TX GPIO_UART5_TX +# define STM32H5_CONSOLE_RX GPIO_UART5_RX +# ifdef CONFIG_UART5_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART6_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_USART6_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART6EN +# define STM32H5_CONSOLE_BAUD CONFIG_USART6_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_USART6_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_USART6_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_USART6_2STOP +# define STM32H5_CONSOLE_TX GPIO_USART6_TX +# define STM32H5_CONSOLE_RX GPIO_USART6_RX +# ifdef CONFIG_USART6_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR +# if (CONFIG_USART6_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART7_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_UART7_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART7EN +# define STM32H5_CONSOLE_BAUD CONFIG_UART7_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_UART7_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_UART7_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_UART7_2STOP +# define STM32H5_CONSOLE_TX GPIO_UART7_TX +# define STM32H5_CONSOLE_RX GPIO_UART7_RX +# ifdef CONFIG_UART7_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR +# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART8_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_UART8_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART8EN +# define STM32H5_CONSOLE_BAUD CONFIG_UART8_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_UART8_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_UART8_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_UART8_2STOP +# define STM32H5_CONSOLE_TX GPIO_UART8_TX +# define STM32H5_CONSOLE_RX GPIO_UART8_RX +# ifdef CONFIG_UART8_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR +# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART9_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_UART9_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART9EN +# define STM32H5_CONSOLE_BAUD CONFIG_UART9_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_UART9_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_UART9_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_UART9_2STOP +# define STM32H5_CONSOLE_TX GPIO_UART9_TX +# define STM32H5_CONSOLE_RX GPIO_UART9_RX +# ifdef CONFIG_UART9_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR +# if (CONFIG_UART9_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART10_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_USART10_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART10EN +# define STM32H5_CONSOLE_BAUD CONFIG_USART10_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_USART10_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_USART10_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_USART10_2STOP +# define STM32H5_CONSOLE_TX GPIO_USART10_TX +# define STM32H5_CONSOLE_RX GPIO_USART10_RX +# ifdef CONFIG_USART10_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR +# if (CONFIG_USART10_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART11_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_USART11_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART11EN +# define STM32H5_CONSOLE_BAUD CONFIG_USART11_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_USART11_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_USART11_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_USART11_2STOP +# define STM32H5_CONSOLE_TX GPIO_USART11_TX +# define STM32H5_CONSOLE_RX GPIO_USART11_RX +# ifdef CONFIG_USART11_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR +# if (CONFIG_USART11_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART12_SERIAL_CONSOLE) +# define STM32H5_CONSOLE_BASE STM32H5_UART12_BASE +# define STM32H5_APBCLOCK STM32H5_PCLK1_FREQUENCY +# define STM32H5_CONSOLE_APBREG STM32H5_RCC_APB1LENR +# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART12EN +# define STM32H5_CONSOLE_BAUD CONFIG_UART12_BAUD +# define STM32H5_CONSOLE_BITS CONFIG_UART12_BITS +# define STM32H5_CONSOLE_PARITY CONFIG_UART12_PARITY +# define STM32H5_CONSOLE_2STOP CONFIG_UART12_2STOP +# define STM32H5_CONSOLE_TX GPIO_UART12_TX +# define STM32H5_CONSOLE_RX GPIO_UART12_RX +# ifdef CONFIG_UART12_RS485 +# define STM32H5_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR +# if (CONFIG_UART12_RS485_DIR_POLARITY == 0) +# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# endif + + /* CR1 settings */ + +# if STM32H5_CONSOLE_BITS == 9 +# define USART_CR1_M0_VALUE USART_CR1_M0 +# define USART_CR1_M1_VALUE 0 +# elif STM32H5_CONSOLE_BITS == 7 +# define USART_CR1_M0_VALUE 0 +# define USART_CR1_M1_VALUE USART_CR1_M1 +# else /* 8 bits */ +# define USART_CR1_M0_VALUE 0 +# define USART_CR1_M1_VALUE 0 +# endif + +# if STM32H5_CONSOLE_PARITY == 1 /* odd parity */ +# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) +# elif STM32H5_CONSOLE_PARITY == 2 /* even parity */ +# define USART_CR1_PARITY_VALUE USART_CR1_PCE +# else /* no parity */ +# define USART_CR1_PARITY_VALUE 0 +# endif + +# if STM32H5_CONSOLE_BASE == STM32H5_LPUART1_BASE +# define USART_CR1_CLRBITS \ + (USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ + USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \ + USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \ + USART_CR1_DEAT_MASK | LPUART_CR1_ALLINTS) +# else +# define USART_CR1_CLRBITS \ + (USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ + USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \ + USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \ + USART_CR1_DEAT_MASK | USART_CR1_ALLINTS) +# endif + +# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE) + + /* CR2 settings */ + +# if STM32H5_CONSOLE_2STOP != 0 +# define USART_CR2_STOP2_VALUE USART_CR2_STOP2 +# else +# define USART_CR2_STOP2_VALUE 0 +# endif + +# define USART_CR2_CLRBITS \ + (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ + USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ + USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \ + USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \ + USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK) + +# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE + + /* CR3 settings */ + +# define USART_CR3_CLRBITS \ + (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ + USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \ + USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ + USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \ + USART_CR3_SCARCNT2_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE) + +# define USART_CR3_SETBITS 0 + +# undef USE_OVER8 + + /* Calculate USART BAUD rate divider */ +# if STM32H5_CONSOLE_BASE == STM32H5_LPUART1_BASE + + /* BRR = (256 * (APBCLOCK / Prescaler)) / (Baud rate) + * With Prescaler == 16, BRR = (16 * APBCLOCK / (Baud rate) + * Set Prescaler to 16 to support wide range of standard baud rates + */ + +# define STM32_BRR_VALUE \ + (((STM32_APBCLOCK & 0xf0000000) / STM32_CONSOLE_BAUD) << 4) + \ + (((STM32_APBCLOCK & 0x0fffffff) << 4) / STM32_CONSOLE_BAUD) +# define STM32_PRESC_VALUE 0x7 + +# else + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / UARTDIV + * UARTDIV = fCK / baud + * + * In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / UARTDIV + * UARTDIV = 2 * fCK / baud + */ + +# define STM32H5_USARTDIV8 \ + (((STM32H5_APBCLOCK << 1) + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) +# define STM32H5_USARTDIV16 \ + ((STM32H5_APBCLOCK + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) + + /* Use oversamply by 8 only if the divisor is small. But what is small? */ + +# if STM32H5_USARTDIV8 > 2000 +# define STM32H5_BRR_VALUE STM32H5_USARTDIV16 +# else +# define USE_OVER8 1 +# define STM32H5_BRR_VALUE \ + ((STM32H5_USARTDIV8 & 0xfff0) | ((STM32H5_USARTDIV8 & 0x000f) >> 1)) +# endif +# endif +#endif /* HAVE_CONSOLE */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + /* Wait until the TX data register is empty */ + + while ((getreg32(STM32H5_CONSOLE_BASE + STM32H5_USART_ISR_OFFSET) & + USART_ISR_TXE) == 0); +#ifdef STM32H5_CONSOLE_RS485_DIR + stm32h5_gpiowrite(STM32H5_CONSOLE_RS485_DIR, + STM32H5_CONSOLE_RS485_DIR_POLARITY); +#endif + + /* Then send the character */ + + putreg32((uint32_t)ch, STM32H5_CONSOLE_BASE + STM32H5_USART_TDR_OFFSET); + +#ifdef STM32H5_CONSOLE_RS485_DIR + while ((getreg32(STM32H5_CONSOLE_BASE + STM32H5_USART_ISR_OFFSET) & + USART_ISR_TC) == 0); + stm32h5_gpiowrite(STM32H5_CONSOLE_RS485_DIR, + !STM32H5_CONSOLE_RS485_DIR_POLARITY); +#endif + +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: stm32h5_lowsetup + * + * Description: + * This performs basic initialization of the USART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void stm32h5_lowsetup(void) +{ +#if defined(HAVE_UART) +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t cr; +#endif + +#if defined(HAVE_CONSOLE) + /* Enable USART APB clock */ + + modifyreg32(STM32H5_CONSOLE_APBREG, 0, STM32H5_CONSOLE_APBEN); +#endif + + /* Enable the console USART and configure GPIO pins needed for rx/tx. + * + * NOTE: Clocking for selected U[S]ARTs was already provided in + * stm32h5_rcc.c + */ + +#ifdef STM32H5_CONSOLE_TX + stm32h5_configgpio(STM32H5_CONSOLE_TX); +#endif +#ifdef STM32H5_CONSOLE_RX + stm32h5_configgpio(STM32H5_CONSOLE_RX); +#endif + +#ifdef STM32H5_CONSOLE_RS485_DIR + stm32h5_configgpio(STM32H5_CONSOLE_RS485_DIR); + stm32h5_gpiowrite(STM32H5_CONSOLE_RS485_DIR, + !STM32H5_CONSOLE_RS485_DIR_POLARITY); +#endif + + /* Enable and configure the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Configure CR2 */ + + cr = getreg32(STM32H5_CONSOLE_BASE + STM32H5_USART_CR2_OFFSET); + cr &= ~USART_CR2_CLRBITS; + cr |= USART_CR2_SETBITS; + putreg32(cr, STM32H5_CONSOLE_BASE + STM32H5_USART_CR2_OFFSET); + + /* Configure CR1 */ + + cr = getreg32(STM32H5_CONSOLE_BASE + STM32H5_USART_CR1_OFFSET); + cr &= ~USART_CR1_CLRBITS; + cr |= USART_CR1_SETBITS; + putreg32(cr, STM32H5_CONSOLE_BASE + STM32H5_USART_CR1_OFFSET); + + /* Configure CR3 */ + + cr = getreg32(STM32H5_CONSOLE_BASE + STM32H5_USART_CR3_OFFSET); + cr &= ~USART_CR3_CLRBITS; + cr |= USART_CR3_SETBITS; + putreg32(cr, STM32H5_CONSOLE_BASE + STM32H5_USART_CR3_OFFSET); + + /* Configure the USART Baud Rate */ + + putreg32(STM32H5_BRR_VALUE, + STM32H5_CONSOLE_BASE + STM32H5_USART_BRR_OFFSET); + + /* Select oversampling by 8 */ + + cr = getreg32(STM32H5_CONSOLE_BASE + STM32H5_USART_CR1_OFFSET); +#ifdef USE_OVER8 + cr |= USART_CR1_OVER8; + putreg32(cr, STM32H5_CONSOLE_BASE + STM32H5_USART_CR1_OFFSET); +#endif + + /* Enable Rx, Tx, and the USART */ + + cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + putreg32(cr, STM32H5_CONSOLE_BASE + STM32H5_USART_CR1_OFFSET); + +#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_UART */ +} diff --git a/arch/arm/src/stm32h5/stm32h5_lowputc.h b/arch/arm/src/stm32h5/stm32h5_lowputc.h new file mode 100644 index 0000000000000..a126da670cc84 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_lowputc.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32h5_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization of serial console. + * + ****************************************************************************/ + +void stm32h5_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_LOWPUTC_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_lse.c b/arch/arm/src/stm32h5/stm32h5_lse.c new file mode 100644 index 0000000000000..aff1cec92f298 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_lse.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_lse.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "stm32h5_pwr.h" +#include "stm32h5_rcc.h" +#include "stm32h5_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) + +#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +static const uint32_t drives[4] = +{ + RCC_BDCR_LSEDRV_LOW, + RCC_BDCR_LSEDRV_MEDLO, + RCC_BDCR_LSEDRV_MEDHI, + RCC_BDCR_LSEDRV_HIGH +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_rcc_enablelse + * + * Description: + * Enable the External Low-Speed (LSE) oscillator and the LSE system clock. + * + ****************************************************************************/ + +void stm32h5_rcc_enablelse(void) +{ + bool writable; + uint32_t regval; + volatile int32_t timeout; +#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + volatile int32_t drive = 0; +#endif + + /* Check if both the External Low-Speed (LSE) oscillator and the LSE system + * clock are already running. + */ + + regval = getreg32(STM32H5_RCC_BDCR); + + if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != + (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) + { + /* The LSE is in the RTC domain and write access is denied to this + * domain after reset, you have to enable write access using DBP bit in + * the PWR CR register before to configuring the LSE. + */ + + writable = stm32h5_pwr_enablebkp(true); + + /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON + * bit the RCC BDCR register. + */ + + regval |= RCC_BDCR_LSEON; + +#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY + /* Set start-up drive capability for LSE oscillator. LSE must be OFF + * to change drive strength. + */ + + regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); + regval |= CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY << + RCC_BDCR_LSEDRV_SHIFT; + putreg32(regval, STM32H5_RCC_BDCR); + regval |= RCC_BDCR_LSEON; +#endif + +#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + do + { + regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); + regval |= drives[drive++]; + putreg32(regval, STM32H5_RCC_BDCR); + regval |= RCC_BDCR_LSEON; +#endif + + putreg32(regval, STM32H5_RCC_BDCR); + + /* Wait for the LSE clock to be ready (or until a timeout elapsed) + */ + + for (timeout = LSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the LSERDY flag is the set in the BDCR */ + + regval = getreg32(STM32H5_RCC_BDCR); + + if (regval & RCC_BDCR_LSERDY) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + +#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + if (timeout != 0) + { + break; + } + } + while (drive < sizeof(drives) / sizeof(drives[0])); +#endif + +#ifdef CONFIG_STM32H5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + + /* Set running drive capability for LSE oscillator. */ + + regval &= ~RCC_BDCR_LSEDRV_MASK; + regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; + putreg32(regval, STM32H5_RCC_BDCR); +#endif + + /* Disable backup domain access if it was disabled on entry */ + + stm32h5_pwr_enablebkp(writable); + } +} diff --git a/arch/arm/src/stm32h5/stm32h5_lsi.c b/arch/arm/src/stm32h5/stm32h5_lsi.c new file mode 100644 index 0000000000000..8e12e1a99e788 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_lsi.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_lsi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "arm_internal.h" +#include "stm32h5_rcc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_rcc_enablelsi + * + * Description: + * Enable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32h5_rcc_enablelsi(void) +{ + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit the RCC CSR register. + */ + + modifyreg32(STM32H5_RCC_BDCR, 0, RCC_BDCR_LSION); + + /* Wait for the internal LSI oscillator to be stable. */ + + while ((getreg32(STM32H5_RCC_BDCR) & RCC_BDCR_LSIRDY) == 0); +} + +/**************************************************************************** + * Name: stm32h5_rcc_disablelsi + * + * Description: + * Disable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32h5_rcc_disablelsi(void) +{ + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit the RCC CSR register. + */ + + modifyreg32(STM32H5_RCC_BDCR, RCC_BDCR_LSION, 0); + + /* LSIRDY should go low after 3 LSI clock cycles */ +} diff --git a/arch/arm/src/stm32h5/stm32h5_mpuinit.c b/arch/arm/src/stm32h5/stm32h5_mpuinit.c new file mode 100644 index 0000000000000..fb29c2e548974 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_mpuinit.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_mpuinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "mpu.h" +#include "stm32h5_mpuinit.h" + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted SAM3U + * resources. + * + ****************************************************************************/ + +void stm32h5_mpuinitialize(void) +{ + uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && + dataend >= datastart); + + /* Show MPU information */ + + mpu_showtype(); + + /* Configure user flash and SRAM space */ + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + mpu_user_intsram(datastart, dataend - datastart); + + /* Then enable the MPU */ + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: stm32h5_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +void stm32h5_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} + +#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */ diff --git a/arch/arm/src/stm32h5/stm32h5_mpuinit.h b/arch/arm/src/stm32h5/stm32h5_mpuinit.h new file mode 100644 index 0000000000000..7230d9cc945d0 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_mpuinit.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_mpuinit.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_MPUINIT_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_MPUINIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only unrestricted MCU + * resources. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void stm32h5_mpuinitialize(void); +#else +# define stm32h5_mpuinitialize() +#endif + +/**************************************************************************** + * Name: stm32h5_mpu_uheap + * + * Description: + * Map the user heap region. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void stm32h5_mpu_uheap(uintptr_t start, size_t size); +#else +# define stm32h5_mpu_uheap(start,size) +#endif + +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_MPUINIT_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_pwr.c b/arch/arm/src/stm32h5/stm32h5_pwr.c new file mode 100644 index 0000000000000..4e279c7e61d7a --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_pwr.c @@ -0,0 +1,309 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_pwr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32h5_pwr.h" +#include "stm32h5_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PWR_TIMEOUT (10 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline uint32_t stm32h5_pwr_getreg(uint16_t offset) +{ + return getreg32(STM32H5_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32h5_pwr_putreg(uint16_t offset, uint16_t value) +{ + putreg32(value, STM32H5_PWR_BASE + (uint32_t)offset); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_pwr_enablebkp + * + * Description: + * Enables access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * + * Input Parameters: + * writable True: enable ability to write to backup domain registers + * + * Returned Value: + * True: The backup domain was previously writable. + * + ****************************************************************************/ + +bool stm32h5_pwr_enablebkp(bool writable) +{ + uint16_t regval; + bool waswritable; + + /* Get the current state of the PWR disable Backup domain register */ + + regval = stm32h5_pwr_getreg(STM32H5_PWR_DBPCR_OFFSET); + waswritable = ((regval & PWR_DBPCR_DBP) != 0); + + /* Enable or disable the ability to write */ + + if (waswritable && !writable) + { + /* Disable backup domain access */ + + regval &= ~PWR_DBPCR_DBP; + stm32h5_pwr_putreg(STM32H5_PWR_DBPCR_OFFSET, regval); + } + else if (!waswritable && writable) + { + /* Enable backup domain access */ + + regval |= PWR_DBPCR_DBP; + stm32h5_pwr_putreg(STM32H5_PWR_DBPCR_OFFSET, regval); + + /* Enable does not happen right away */ + + up_udelay(4); + } + + return waswritable; +} + +/**************************************************************************** + * Name stm32h5_pwr_adjustvcore + * + * Description: + * Adjusts the voltage used for digital peripherals (V_CORE) before + * raising or after decreasing the system clock frequency. Compare + * [RM0481], section 10.7 Dynamic voltage scaling management. + * + * Note: Use only for VCore supplied with internal LDO or SMPS. + * For supplying VCore externally, use stm32h5_pwr_adjustvos_ext. + * + * Input Parameters: + * sysclock - The frequency in Hertz the system clock will or has been set + * to. + * + ****************************************************************************/ + +void stm32h5_pwr_adjustvcore(unsigned sysclock) +{ + volatile int timeout; + uint32_t vos_range; + uint32_t actvos; + + /* Select the applicable V_CORE voltage range depending on the new system + * clock frequency. + */ + + DEBUGASSERT(sysclock <= 250000000); + + if (sysclock > 200000000) + { + vos_range = PWR_VOSCR_VOS_RANGE0; + } + else if (sysclock > 150000000) + { + vos_range = PWR_VOSCR_VOS_RANGE1; + } + else if (sysclock > 100000000) + { + vos_range = PWR_VOSCR_VOS_RANGE2; + } + else + { + vos_range = PWR_VOSCR_VOS_RANGE3; + } + + actvos = (getreg32(STM32H5_PWR_VOSSR) & PWR_VOSSR_ACTVOS_MASK); + modreg32(vos_range, PWR_VOSCR_VOS_MASK, STM32H5_PWR_VOSCR); + + if (vos_range > actvos) + { + /* Wait until the new V_CORE voltage range has been applied. */ + + for (timeout = PWR_TIMEOUT; timeout; timeout--) + { + if (getreg32(STM32H5_PWR_VOSSR) & PWR_VOSSR_VOSRDY) + { + break; + } + } + + DEBUGASSERT(timeout > 0); + } + else if (vos_range < actvos) + { + /* Wait until the voltage level for the currently used VOS is ready. */ + + for (timeout = PWR_TIMEOUT; timeout; timeout--) + { + if (getreg32(STM32H5_PWR_VOSSR) & PWR_VOSSR_ACTVOSRDY) + { + break; + } + } + + DEBUGASSERT(timeout > 0); + } + else + { + /* actvos == vos_range. Do nothing. */ + + return; + } +} + +/**************************************************************************** + * Name stm32h5_pwr_adjustvos_ext + * + * Description: + * When changing VCore with an external supply, VOS must + * incrementally select intermediate levels. + * + * When increasing the performance: + * 1. First, voltage scaling must be incremented (for example when + * changing from VOS3 to VOS0, lower levels must be selected in the + * VOS[1:0] bits: VOS2, VOS1, and then VOS0). + * 2. The external voltage can be increased. + * 3. The system frequency can be increased. + * + * When decreasing the performance: + * 1. The system frequency MUST be decreased. + * 2. The external voltage MUST be decreased. + * 3. The voltage scaling can be decremented (for example when changing + * from VOS1 to VOS3, lower levels must be selected in the VOS[1:0] + * bits: VOS2, and then VOS3) + * + * Input Parameters: + * sysclock - The frequency in Hertz the system clock will or has been set + * to. + * + ****************************************************************************/ + +void stm32h5_pwr_adjustvos_ext(unsigned sysclock) +{ + uint32_t vos_range; + uint32_t vos_range_val; + uint32_t vos_range_set; + uint32_t actvos_val; + + /* Select the applicable V_CORE voltage range depending on the new system + * clock frequency. + */ + + DEBUGASSERT(sysclock <= 250000000); + + if (sysclock > 200000000) + { + vos_range = PWR_VOSCR_VOS_RANGE0; + } + else if (sysclock > 150000000) + { + vos_range = PWR_VOSCR_VOS_RANGE1; + } + else if (sysclock > 100000000) + { + vos_range = PWR_VOSCR_VOS_RANGE2; + } + else + { + vos_range = PWR_VOSCR_VOS_RANGE3; + } + + vos_range_val = (vos_range & PWR_VOSCR_VOS_MASK) >> PWR_VOSCR_VOS_SHIFT; + + actvos_val = ((getreg32(STM32H5_PWR_VOSSR) & PWR_VOSSR_ACTVOS_MASK) >> + PWR_VOSSR_ACTVOS_SHIFT); + + if (vos_range_val > actvos_val) + { + /* Gradually Increase VOS Scale */ + + for (int i = actvos_val; i < vos_range_val; ++i) + { + if (i == 0) + { + vos_range_set = PWR_VOSCR_VOS_RANGE2; + } + else if (i == 1) + { + vos_range_set = PWR_VOSCR_VOS_RANGE1; + } + else /* (i == 2) */ + { + vos_range_set = PWR_VOSCR_VOS_RANGE0; + } + + modreg32(vos_range_set, PWR_VOSCR_VOS_MASK, STM32H5_PWR_VOSCR); + up_udelay(1); + } + } + else if (vos_range_val < actvos_val) + { + /* Gradually Decrease VOS Scale */ + + for (int i = actvos_val; i > vos_range_val; --i) + { + if (i == 1) + { + vos_range_set = PWR_VOSCR_VOS_RANGE3; + } + else if (i == 2) + { + vos_range_set = PWR_VOSCR_VOS_RANGE2; + } + else /* (i == 3) */ + { + vos_range_set = PWR_VOSCR_VOS_RANGE1; + } + + modreg32(vos_range_set, PWR_VOSCR_VOS_MASK, STM32H5_PWR_VOSCR); + up_udelay(1); + } + } + else + { + /* actvos == new vos. Do nothing. */ + + return; + } +} diff --git a/arch/arm/src/stm32h5/stm32h5_pwr.h b/arch/arm/src/stm32h5/stm32h5_pwr.h new file mode 100644 index 0000000000000..125b22b8ea5df --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_pwr.h @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/arm/src/stm32u5/stm32_pwr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U5_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32U5_STM32_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip.h" +#include "hardware/stm32h5_pwr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwr_enablebkp + * + * Description: + * Enables write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). Compare [RM0456], section 10.4.7 + * Battery Backup domain, Backup domain access. + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * True: The backup domain was previously writable. + * + ****************************************************************************/ + +bool stm32h5_pwr_enablebkp(bool writable); + +/**************************************************************************** + * Name stm32_pwr_adjustvcore + * + * Description: + * Adjusts the voltage used for digital peripherals (V_CORE) before + * raising or after decreasing the system clock frequency. Compare + * [RM0456], section 10.5.4 Dynamic voltage scaling management. + * + * Input Parameters: + * sysclock - The frequency in Hertz the system clock will be raised to. + * + ****************************************************************************/ + +void stm32h5_pwr_adjustvcore(unsigned sysclock); + +void stm32h5_pwr_adjustvos_ext(unsigned sysclock); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32U5_STM32_PWR_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_rcc.c b/arch/arm/src/stm32h5/stm32h5_rcc.c new file mode 100644 index 0000000000000..cb8c350c98dbb --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_rcc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32h5_rcc.h" +#include "stm32h5_flash.h" +#include "stm32h5.h" +#include "stm32h5_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name + * + * Description + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. In + * order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters + * None + * + * Returned Value + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32H5_PWR) && defined(CONFIG_STM32H5_RTC) +static inline void rcc_resetbkp(void) +{ + bool init_stat; + + /* Check if the RTC is already configured */ + + init_stat = stm32h5_rtc_is_initialized(); + if (!init_stat) + { + uint32_t bkregs[STM32H5_RTC_BKCOUNT]; + int i; + + /* Backup backup-registers before RTC reset. */ + + for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + { + bkregs[i] = getreg32(STM32H5_RTC_BKR(i)); + } + + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32h5_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32H5_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32H5_RCC_BDCR, RCC_BDCR_BDRST, 0); + + /* Restore backup-registers, except RTC related. */ + + for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + { + if (RTC_MAGIC_REG == STM32H5_RTC_BKR(i)) + { + continue; + } + + putreg32(bkregs[i], STM32H5_RTC_BKR(i)); + } + + stm32h5_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name + * + * Description + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32h5_board_clockconfig(). + * + * Input Parameters + * None + * + * Returned Value + * None + * + ****************************************************************************/ + +void stm32h5_clockconfig(void) +{ +#if 0 + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); +#endif +#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32h5_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions in + * board.h + */ + + stm32h5_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + stm32h5_rcc_enableperipherals(); +} + +/**************************************************************************** + * Name + * + * Description + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation + * re-enable/re-start the PLL + * + * This function performs a subset of the operations performed by + * stm32h5_clockconfig() + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32h5_board_clockconfig(). + * + * Input Parameters + * None + * + * Returned Value + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32h5_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32h5_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions in + * board.h + */ + + stm32h5_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32h5/stm32h5_rcc.h b/arch/arm/src/stm32h5/stm32h5_rcc.h new file mode 100644 index 0000000000000..60ea9b34ea87f --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_rcc.h @@ -0,0 +1,251 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_rcc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_RCC_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "chip.h" + +#if defined(CONFIG_STM32H5_STM32H5XXXX) +# include "hardware/stm32h5_rcc.h" +#else +# error "Unsupported STM32H5 chip" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_mco1config + * + * Description: + * + * Input Parameters: + * source - One of the definitions for the RCC_CFGR_MCO definitions from + * chip/stm32h5_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK, + * RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK, + * RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK} + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32h5_mco1config(uint32_t source) +{ + uint32_t regval; + + /* Set MCO source */ + + regval = getreg32(STM32H5_RCC_CFGR1); + regval &= ~(RCC_CFGR1_MCO1SEL_MASK); + regval |= (source & RCC_CFGR1_MCO1SEL_MASK); + putreg32(regval, STM32H5_RCC_CFGR1); +} + +/**************************************************************************** + * Name: stm32h5_mco2config + * + * Description: + * + * Input Parameters: + * source - One of the definitions for the RCC_CFGR_MCO definitions from + * chip/stm32h5_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK, + * RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK, + * RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK} + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32h5_mco2config(uint32_t source) +{ + uint32_t regval; + + /* Set MCO source */ + + regval = getreg32(STM32H5_RCC_CFGR1); + regval &= ~(RCC_CFGR1_MCO2SEL_MASK); + regval |= (source & RCC_CFGR1_MCO2SEL_MASK); + putreg32(regval, STM32H5_RCC_CFGR1); +} + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all periperipherals enabled in the + * NuttX configuration file. + * + * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32h5_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32h5_clockconfig(void); + +/**************************************************************************** + * Name: stm32h5_board_clockconfig + * + * Description: + * Any STM32H5 board may replace the "standard" board clock configuration + * logic with its own, custom clock configuration logic. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +void stm32h5_board_clockconfig(void); +#endif + +/**************************************************************************** + * Name: stm32h5_stdclockconfig + * + * Description: + * The standard logic to configure the clocks based on settings in board.h. + * Applicable if no custom clock config is provided. This function is + * chip type specific and implemented in corresponding modules such as e.g. + * stm32h562xx_rcc.c + * + ****************************************************************************/ + +#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +void stm32h5_stdclockconfig(void); +#endif + +/**************************************************************************** + * Name: stm32h5_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This function performs a subset of the operations performed by + * stm32h5_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32h5_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32h5_clockenable(void); +#endif + +/**************************************************************************** + * Name: stm32h5_rcc_enablelse + * + * Description: + * Enable the External Low-Speed (LSE) Oscillator. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32h5_rcc_enablelse(void); + +/**************************************************************************** + * Name: stm32h5_rcc_enablelsi + * + * Description: + * Enable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32h5_rcc_enablelsi(void); + +/**************************************************************************** + * Name: stm32h5_rcc_disablelsi + * + * Description: + * Disable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32h5_rcc_disablelsi(void); + +/**************************************************************************** + * Name: stm32h5_rcc_enableperipherals + * + * Description: + * Enable all the chip peripherals according to configuration. This is + * chip type specific and thus implemented in corresponding modules such as + * e.g. stm32h562xx_rcc.c + * + ****************************************************************************/ + +void stm32h5_rcc_enableperipherals(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_RCC_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_serial.c b/arch/arm/src/stm32h5/stm32h5_serial.c new file mode 100644 index 0000000000000..a592e394bfc68 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_serial.c @@ -0,0 +1,3858 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include + +#include "chip.h" +#include "stm32h5_gpio.h" +#include "stm32h5_uart.h" +#ifdef SERIAL_HAVE_DMA +# include "stm32h5_dma.h" +#endif +#include "stm32h5_rcc.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +/* DMA configuration */ + +/* If DMA is enabled on any USART, then very that other pre-requisites + * have also been selected. + * UART DMA1 DMA2 + * 1 X X + * 2 X + * 3 X + * 4 X + * 5 X + */ + +#ifdef SERIAL_HAVE_DMA + +/* Verify that DMA has been enabled and the DMA channel has been defined. + */ + +# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) +# if !defined(CONFIG_STM32H5_DMA1) && !defined(CONFIG_STM32H5_DMAMUX) +# error STM32H5 USART2/3 receive DMA requires CONFIG_STM32H5_DMA1 +# endif +# endif + +# if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) +# if !defined(CONFIG_STM32H5_DMA2) && !defined(CONFIG_STM32H5_DMAMUX) +# error STM32H5 UART4/5 receive DMA requires CONFIG_STM32H5_DMA2 +# endif +# endif + +/* Currently RS-485 support cannot be enabled when RXDMA is in use due to + * lack of testing - RS-485 support was developed on STM32F1x + */ + +# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \ + (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \ + (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \ + (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \ + (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) +# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART" +# endif + +/* For the L4, there are alternate DMA channels for USART1. + * Logic in the board.h file make the DMA channel selection by defining + * the following in the board.h file. + */ + +# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) +# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" +# endif + +/* UART2-5 have no alternate channels without DMAMUX */ + +# ifndef CONFIG_STM32H5_HAVE_DMAMUX +# define DMAMAP_USART2_RX DMACHAN_USART2_RX +# define DMAMAP_USART3_RX DMACHAN_USART3_RX +# define DMAMAP_UART4_RX DMACHAN_UART4_RX +# define DMAMAP_UART5_RX DMACHAN_UART5_RX +# endif + +# if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX) +# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" +# endif + +# if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX) +# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" +# endif + +# if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX) +# error "UART4 DMA channel not defined (DMAMAP_UART4_RX)" +# endif + +# if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX) +# error "UART5 DMA channel not defined (DMAMAP_UART5_RX)" +# endif + +/* The DMA buffer size when using RX DMA to emulate a FIFO. + * + * When streaming data, the generic serial layer will be called + * every time the FIFO receives half this number of bytes. + * + * If there ever is a STM32H5 with D-cache, the buffer size + * should be an even multiple of ARMV7M_DCACHE_LINESIZE, so that it + * can be individually invalidated. + */ + +# if !defined(CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# define RXDMA_BUFFER_SIZE 32 +# else +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# endif + +/* DMA priority */ + +# ifndef CONFIG_USART_DMAPRIO +# define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED +# endif +# if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_USART_DMAPRIO" +# endif + +/* DMA control words */ + +# define SERIAL_DMA_CONTROL_WORD \ + (DMA_CCR_CIRC | \ + DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_USART_DMAPRIO) +# ifdef CONFIG_SERIAL_IFLOWCONTROL +# define SERIAL_DMA_IFLOW_CONTROL_WORD \ + (DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_USART_DMAPRIO) +# endif + +#endif + +/* Power management definitions */ + +#if defined(CONFIG_PM) && !defined(CONFIG_STM32H5_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32H5_PM_SERIAL_ACTIVITY 10 +#endif + +/* Keep track if a Break was set + * + * Note: + * + * 1) This value is set in the priv->ie but never written to the control + * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE + * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. + * + * See stm32h5serial_restoreusartint where the masking is done. + */ + +#ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 +# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) +#endif + +#ifdef USE_SERIALDRIVER +#ifdef HAVE_UART + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32h5_serial_s +{ + struct uart_dev_s dev; /* Generic UART device */ + uint16_t ie; /* Saved interrupt mask bits value */ + uint16_t sr; /* Saved status bits */ + + /* Has been initialized and HW is setup. */ + + bool initialized; + +#ifdef CONFIG_PM + bool suspended; /* UART device has been suspended. */ + + /* Interrupt mask value stored before suspending for stop mode. */ + + uint16_t suspended_ie; +#endif + + /* If termios are supported, then the following fields may vary at + * runtime. + */ + +#ifdef CONFIG_SERIAL_TERMIOS + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* output flow control (CTS) enabled */ +#endif + uint32_t baud; /* Configured baud */ +#else + const uint8_t parity; /* 0=none, 1=odd, 2=even */ + const uint8_t bits; /* Number of bits (7 or 8) */ + const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + const bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const bool oflow; /* output flow control (CTS) enabled */ +#endif + const uint32_t baud; /* Configured baud */ +#endif + + const uint8_t irq; /* IRQ associated with this USART */ + const uint32_t apbclock; /* PCLK 1 or 2 frequency */ + const uint32_t usartbase; /* Base address of USART registers */ + const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ + const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ +#endif + +#ifdef SERIAL_HAVE_DMA + const unsigned int rxdma_channel; /* DMA channel assigned */ +#endif + + /* RX DMA state */ + +#ifdef SERIAL_HAVE_DMA + DMA_HANDLE rxdma; /* currently-open receive DMA stream */ + bool rxenable; /* DMA-based reception en/disable */ +#ifdef CONFIG_PM + bool rxdmasusp; /* Rx DMA suspended */ +#endif + uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ + char *const rxfifo; /* Receive DMA buffer */ +#endif + +#ifdef HAVE_RS485 + const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ + const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ +#endif + const bool islpuart; /* Is this device a Low Power UART? */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifndef CONFIG_SUPPRESS_UART_CONFIG +static void stm32h5serial_setformat(struct uart_dev_s *dev); +#endif +static int stm32h5serial_setup(struct uart_dev_s *dev); +static void stm32h5serial_shutdown(struct uart_dev_s *dev); +static int stm32h5serial_attach(struct uart_dev_s *dev); +static void stm32h5serial_detach(struct uart_dev_s *dev); +static int stm32h5serial_interrupt(int irq, void *context, + void *arg); +static int stm32h5serial_ioctl(struct file *filep, int cmd, + unsigned long arg); +#ifndef SERIAL_HAVE_ONLY_DMA +static int stm32h5serial_receive(struct uart_dev_s *dev, + unsigned int *status); +static void stm32h5serial_rxint(struct uart_dev_s *dev, bool enable); +static bool stm32h5serial_rxavailable(struct uart_dev_s *dev); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool stm32h5serial_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif +static void stm32h5serial_send(struct uart_dev_s *dev, int ch); +static void stm32h5serial_txint(struct uart_dev_s *dev, bool enable); +static bool stm32h5serial_txready(struct uart_dev_s *dev); + +#ifdef SERIAL_HAVE_DMA +static int stm32h5serial_dmasetup(struct uart_dev_s *dev); +static void stm32h5serial_dmashutdown(struct uart_dev_s *dev); +static int stm32h5serial_dmareceive(struct uart_dev_s *dev, + unsigned int *status); +static void stm32h5serial_dmareenable(struct stm32h5_serial_s *priv); +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool stm32h5serial_dmaiflowrestart(struct stm32h5_serial_s *priv); +#endif +static void stm32h5serial_dmarxint(struct uart_dev_s *dev, bool enable); +static bool stm32h5serial_dmarxavailable(struct uart_dev_s *dev); + +static void stm32h5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, + void *arg); +#endif + +#ifdef CONFIG_PM +static void stm32h5serial_setsuspend(struct uart_dev_s *dev, bool suspend); +static void stm32h5serial_pm_setsuspend(bool suspend); +static void stm32h5serial_pmnotify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int stm32h5serial_pmprepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_DMA +static const struct uart_ops_s g_uart_ops = +{ + .setup = stm32h5serial_setup, + .shutdown = stm32h5serial_shutdown, + .attach = stm32h5serial_attach, + .detach = stm32h5serial_detach, + .ioctl = stm32h5serial_ioctl, + .receive = stm32h5serial_receive, + .rxint = stm32h5serial_rxint, + .rxavailable = stm32h5serial_rxavailable, +# ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = stm32h5serial_rxflowcontrol, +# endif + .send = stm32h5serial_send, + .txint = stm32h5serial_txint, + .txready = stm32h5serial_txready, + .txempty = stm32h5serial_txready, +}; +#endif + +#ifdef SERIAL_HAVE_DMA +static const struct uart_ops_s g_uart_dma_ops = +{ + .setup = stm32h5serial_dmasetup, + .shutdown = stm32h5serial_dmashutdown, + .attach = stm32h5serial_attach, + .detach = stm32h5serial_detach, + .ioctl = stm32h5serial_ioctl, + .receive = stm32h5serial_dmareceive, + .rxint = stm32h5serial_dmarxint, + .rxavailable = stm32h5serial_dmarxavailable, +# ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = stm32h5serial_rxflowcontrol, +# endif + .send = stm32h5serial_send, + .txint = stm32h5serial_txint, + .txready = stm32h5serial_txready, + .txempty = stm32h5serial_txready, +}; +#endif + +/* I/O buffers */ + +#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; +# ifdef CONFIG_LPUART1_RXDMA +static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; +static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; +# ifdef CONFIG_USART1_RXDMA +static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; +static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; +# ifdef CONFIG_USART2_RXDMA +static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; +static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; +# ifdef CONFIG_USART3_RXDMA +static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +# ifdef CONFIG_UART4_RXDMA +static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; +# ifdef CONFIG_UART5_RXDMA +static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +/* This describes the state of the STM32 USART1 ports. */ + +#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +static struct stm32h5_serial_s g_lpuart1priv = +{ + .dev = + { +# if CONSOLE_UART == 1 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_lpuart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_lpuart1txbuffer, + }, +# ifdef CONFIG_LPUART1_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_lpuart1priv, + }, + + .islpuart = true, + .irq = STM32H5_IRQ_LPUART1, + .parity = CONFIG_LPUART1_PARITY, + .bits = CONFIG_LPUART1_BITS, + .stopbits2 = CONFIG_LPUART1_2STOP, + .baud = CONFIG_LPUART1_BAUD, + .apbclock = STM32H5_PCLK2_FREQUENCY, + .usartbase = STM32H5_LPUART1_BASE, + .tx_gpio = GPIO_LPUART1_TX, + .rx_gpio = GPIO_LPUART1_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_LPUART1_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_LPUART1_RTS, +# endif +# ifdef CONFIG_LPUART1_RXDMA + .rxdma_channel = DMAMAP_LPUSART_RX, + .rxfifo = g_lpuart1rxfifo, +# endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +static struct stm32h5_serial_s g_usart1priv = +{ + .dev = + { +# if CONSOLE_UART == 2 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART1_RXBUFSIZE, + .buffer = g_usart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART1_TXBUFSIZE, + .buffer = g_usart1txbuffer, + }, +# ifdef CONFIG_USART1_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart1priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_USART1, + .parity = CONFIG_USART1_PARITY, + .bits = CONFIG_USART1_BITS, + .stopbits2 = CONFIG_USART1_2STOP, + .baud = CONFIG_USART1_BAUD, + .apbclock = STM32H5_PCLK2_FREQUENCY, + .usartbase = STM32H5_USART1_BASE, + .tx_gpio = GPIO_USART1_TX, + .rx_gpio = GPIO_USART1_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART1_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART1_RTS, +# endif +# ifdef CONFIG_USART1_RXDMA + .rxdma_channel = DMAMAP_USART1_RX, + .rxfifo = g_usart1rxfifo, +# endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 USART2 port. */ + +#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +static struct stm32h5_serial_s g_usart2priv = +{ + .dev = + { +# if CONSOLE_UART == 3 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART2_RXBUFSIZE, + .buffer = g_usart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART2_TXBUFSIZE, + .buffer = g_usart2txbuffer, + }, +# ifdef CONFIG_USART2_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart2priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_USART2, + .parity = CONFIG_USART2_PARITY, + .bits = CONFIG_USART2_BITS, + .stopbits2 = CONFIG_USART2_2STOP, + .baud = CONFIG_USART2_BAUD, + .apbclock = STM32H5_PCLK1_FREQUENCY, + .usartbase = STM32H5_USART2_BASE, + .tx_gpio = GPIO_USART2_TX, + .rx_gpio = GPIO_USART2_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART2_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART2_RTS, +# endif +# ifdef CONFIG_USART2_RXDMA + .rxdma_channel = DMAMAP_USART2_RX, + .rxfifo = g_usart2rxfifo, +# endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 USART3 port. */ + +#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +static struct stm32h5_serial_s g_usart3priv = +{ + .dev = + { +# if CONSOLE_UART == 4 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART3_RXBUFSIZE, + .buffer = g_usart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART3_TXBUFSIZE, + .buffer = g_usart3txbuffer, + }, +# ifdef CONFIG_USART3_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart3priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_USART3, + .parity = CONFIG_USART3_PARITY, + .bits = CONFIG_USART3_BITS, + .stopbits2 = CONFIG_USART3_2STOP, + .baud = CONFIG_USART3_BAUD, + .apbclock = STM32H5_PCLK1_FREQUENCY, + .usartbase = STM32H5_USART3_BASE, + .tx_gpio = GPIO_USART3_TX, + .rx_gpio = GPIO_USART3_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART3_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART3_RTS, +# endif +# ifdef CONFIG_USART3_RXDMA + .rxdma_channel = DMAMAP_USART3_RX, + .rxfifo = g_usart3rxfifo, +# endif + +# ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 UART4 port. */ + +#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +static struct stm32h5_serial_s g_uart4priv = +{ + .dev = + { +# if CONSOLE_UART == 5 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, +# ifdef CONFIG_UART4_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart4priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_UART4, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stopbits2 = CONFIG_UART4_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART4_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART4_RTS, +# endif + .baud = CONFIG_UART4_BAUD, + .apbclock = STM32H5_PCLK1_FREQUENCY, + .usartbase = STM32H5_UART4_BASE, + .tx_gpio = GPIO_UART4_TX, + .rx_gpio = GPIO_UART4_RX, +# ifdef CONFIG_UART4_RXDMA + .rxdma_channel = DMAMAP_UART4_RX, + .rxfifo = g_uart4rxfifo, +# endif + +# ifdef CONFIG_UART4_RS485 + .rs485_dir_gpio = GPIO_UART4_RS485_DIR, +# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 UART5 port. */ + +#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +static struct stm32h5_serial_s g_uart5priv = +{ + .dev = + { +# if CONSOLE_UART == 6 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART5_RXBUFSIZE, + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART5_TXBUFSIZE, + .buffer = g_uart5txbuffer, + }, +# ifdef CONFIG_UART5_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart5priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_UART5, + .parity = CONFIG_UART5_PARITY, + .bits = CONFIG_UART5_BITS, + .stopbits2 = CONFIG_UART5_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART5_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART5_RTS, +# endif + .baud = CONFIG_UART5_BAUD, + .apbclock = STM32H5_PCLK1_FREQUENCY, + .usartbase = STM32H5_UART5_BASE, + .tx_gpio = GPIO_UART5_TX, + .rx_gpio = GPIO_UART5_RX, +# ifdef CONFIG_UART5_RXDMA + .rxdma_channel = DMAMAP_UART5_RX, + .rxfifo = g_uart5rxfifo, +# endif + +# ifdef CONFIG_UART5_RS485 + .rs485_dir_gpio = GPIO_UART5_RS485_DIR, +# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 USART6 port. */ + +#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +static struct stm32h5_serial_s g_usart6priv = +{ + .dev = + { +# if CONSOLE_UART == 7 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART6_RXBUFSIZE, + .buffer = g_usart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART6_TXBUFSIZE, + .buffer = g_usart6txbuffer, + }, +# ifdef CONFIG_USART6_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart6priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_USART6, + .parity = CONFIG_USART6_PARITY, + .bits = CONFIG_USART6_BITS, + .stopbits2 = CONFIG_USART6_2STOP, + .baud = CONFIG_USART6_BAUD, + .apbclock = STM32H5_PCLK2_FREQUENCY, + .usartbase = STM32H5_USART6_BASE, + .tx_gpio = GPIO_USART6_TX, + .rx_gpio = GPIO_USART6_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART6_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART6_RTS, +# endif +# ifdef CONFIG_USART6_RXDMA + .rxdma_channel = DMAMAP_USART6_RX, + .rxfifo = g_usart6rxfifo, +# endif + +# ifdef CONFIG_USART6_RS485 + .rs485_dir_gpio = GPIO_USART6_RS485_DIR, +# if (CONFIG_USART6_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 UART7 port. */ + +#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +static struct stm32h5_serial_s g_uart7priv = +{ + .dev = + { +# if CONSOLE_UART == 8 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART7_RXBUFSIZE, + .buffer = g_uart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART7_TXBUFSIZE, + .buffer = g_uart7txbuffer, + }, +# ifdef CONFIG_UART7_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart7priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_UART7, + .parity = CONFIG_UART7_PARITY, + .bits = CONFIG_UART7_BITS, + .stopbits2 = CONFIG_UART7_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART7_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART7_RTS, +# endif + .baud = CONFIG_UART7_BAUD, + .apbclock = STM32H5_PCLK1_FREQUENCY, + .usartbase = STM32H5_UART7_BASE, + .tx_gpio = GPIO_UART7_TX, + .rx_gpio = GPIO_UART7_RX, +# ifdef CONFIG_UART7_RXDMA + .rxdma_channel = DMAMAP_UART7_RX, + .rxfifo = g_uart7rxfifo, +# endif + +# ifdef CONFIG_UART7_RS485 + .rs485_dir_gpio = GPIO_UART7_RS485_DIR, +# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 UART8 port. */ + +#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +static struct stm32h5_serial_s g_uart8priv = +{ + .dev = + { +# if CONSOLE_UART == 9 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART8_RXBUFSIZE, + .buffer = g_uart8rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART8_TXBUFSIZE, + .buffer = g_uart8txbuffer, + }, +# ifdef CONFIG_UART8_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart8priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_UART8, + .parity = CONFIG_UART8_PARITY, + .bits = CONFIG_UART8_BITS, + .stopbits2 = CONFIG_UART8_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART8_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART8_RTS, +# endif + .baud = CONFIG_UART8_BAUD, + .apbclock = STM32H5_PCLK1_FREQUENCY, + .usartbase = STM32H5_UART8_BASE, + .tx_gpio = GPIO_UART8_TX, + .rx_gpio = GPIO_UART8_RX, +# ifdef CONFIG_UART8_RXDMA + .rxdma_channel = DMAMAP_UART8_RX, + .rxfifo = g_uart8rxfifo, +# endif + +# ifdef CONFIG_UART8_RS485 + .rs485_dir_gpio = GPIO_UART8_RS485_DIR, +# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 UART9 port. */ + +#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +static struct stm32h5_serial_s g_uart9priv = +{ + .dev = + { +# if CONSOLE_UART == 10 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART9_RXBUFSIZE, + .buffer = g_uart9rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART9_TXBUFSIZE, + .buffer = g_uart9txbuffer, + }, +# ifdef CONFIG_UART9_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart9priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_UART9, + .parity = CONFIG_UART9_PARITY, + .bits = CONFIG_UART9_BITS, + .stopbits2 = CONFIG_UART9_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART9_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART9_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART9_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART9_RTS, +# endif + .baud = CONFIG_UART9_BAUD, + .apbclock = STM32H5_PCLK1_FREQUENCY, + .usartbase = STM32H5_UART9_BASE, + .tx_gpio = GPIO_UART9_TX, + .rx_gpio = GPIO_UART9_RX, +# ifdef CONFIG_UART9_RXDMA + .rxdma_channel = DMAMAP_UART9_RX, + .rxfifo = g_uart9rxfifo, +# endif + +# ifdef CONFIG_UART9_RS485 + .rs485_dir_gpio = GPIO_UART9_RS485_DIR, +# if (CONFIG_UART9_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 USART10 port. */ + +#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +static struct stm32h5_serial_s g_usart10priv = +{ + .dev = + { +# if CONSOLE_UART == 11 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART10_RXBUFSIZE, + .buffer = g_usart10rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART10_TXBUFSIZE, + .buffer = g_usart10txbuffer, + }, +# ifdef CONFIG_USART10_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart10priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_USART10, + .parity = CONFIG_USART10_PARITY, + .bits = CONFIG_USART10_BITS, + .stopbits2 = CONFIG_USART10_2STOP, + .baud = CONFIG_USART10_BAUD, + .apbclock = STM32H5_PCLK2_FREQUENCY, + .usartbase = STM32H5_USART10_BASE, + .tx_gpio = GPIO_USART10_TX, + .rx_gpio = GPIO_USART10_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART10_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART10_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART10_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART10_RTS, +# endif +# ifdef CONFIG_USART10_RXDMA + .rxdma_channel = DMAMAP_USART10_RX, + .rxfifo = g_usart10rxfifo, +# endif + +# ifdef CONFIG_USART10_RS485 + .rs485_dir_gpio = GPIO_USART10_RS485_DIR, +# if (CONFIG_USART10_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 USART11 port. */ + +#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +static struct stm32h5_serial_s g_usart11priv = +{ + .dev = + { +# if CONSOLE_UART == 12 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART11_RXBUFSIZE, + .buffer = g_usart11rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART11_TXBUFSIZE, + .buffer = g_usart11txbuffer, + }, +# ifdef CONFIG_USART11_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart11priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_USART11, + .parity = CONFIG_USART11_PARITY, + .bits = CONFIG_USART11_BITS, + .stopbits2 = CONFIG_USART11_2STOP, + .baud = CONFIG_USART11_BAUD, + .apbclock = STM32H5_PCLK2_FREQUENCY, + .usartbase = STM32H5_USART11_BASE, + .tx_gpio = GPIO_USART11_TX, + .rx_gpio = GPIO_USART11_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART11_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART11_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART11_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART11_RTS, +# endif +# ifdef CONFIG_USART11_RXDMA + .rxdma_channel = DMAMAP_USART11_RX, + .rxfifo = g_usart11rxfifo, +# endif + +# ifdef CONFIG_USART11_RS485 + .rs485_dir_gpio = GPIO_USART11_RS485_DIR, +# if (CONFIG_USART11_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This describes the state of the STM32 UART12 port. */ + +#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +static struct stm32h5_serial_s g_uart12priv = +{ + .dev = + { +# if CONSOLE_UART == 13 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART12_RXBUFSIZE, + .buffer = g_uart12rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART12_TXBUFSIZE, + .buffer = g_uart12txbuffer, + }, +# ifdef CONFIG_UART12_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart12priv, + }, + + .islpuart = false, + .irq = STM32H5_IRQ_UART12, + .parity = CONFIG_UART12_PARITY, + .bits = CONFIG_UART12_BITS, + .stopbits2 = CONFIG_UART12_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART12_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART12_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART12_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART12_RTS, +# endif + .baud = CONFIG_UART12_BAUD, + .apbclock = STM32H5_PCLK1_FREQUENCY, + .usartbase = STM32H5_UART12_BASE, + .tx_gpio = GPIO_UART12_TX, + .rx_gpio = GPIO_UART12_RX, +# ifdef CONFIG_UART12_RXDMA + .rxdma_channel = DMAMAP_UART12_RX, + .rxfifo = g_uart12rxfifo, +# endif + +# ifdef CONFIG_UART12_RS485 + .rs485_dir_gpio = GPIO_UART12_RS485_DIR, +# if (CONFIG_UART12_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif +}; +#endif + +/* This table lets us iterate over the configured USARTs */ + +static struct stm32h5_serial_s * const + g_uart_devs[STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART] = +{ +#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER + [0] = &g_lpuart1priv, +#endif +#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER + [1] = &g_usart1priv, +#endif +#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER + [2] = &g_usart2priv, +#endif +#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER + [3] = &g_usart3priv, +#endif +#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER + [4] = &g_uart4priv, +#endif +#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER + [5] = &g_uart5priv, +#endif +#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER + [6] = &g_usart6priv, +#endif +#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER + [7] = &g_uart7priv, +#endif +#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER + [8] = &g_uart8priv, +#endif +#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER + [9] = &g_uart9priv, +#endif +#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER + [10] = &g_usart10priv, +#endif +#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER + [11] = &g_usart11priv, +#endif +#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER + [12] = &g_uart12priv, +#endif +}; + +#ifdef CONFIG_PM +struct serialpm_s +{ + struct pm_callback_s pm_cb; + bool serial_suspended; +}; + +static struct serialpm_s g_serialpm = +{ + .pm_cb.notify = stm32h5serial_pmnotify, + .pm_cb.prepare = stm32h5serial_pmprepare, + .serial_suspended = false +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5serial_getreg + ****************************************************************************/ + +static inline +uint32_t stm32h5serial_getreg(struct stm32h5_serial_s *priv, int offset) +{ + return getreg32(priv->usartbase + offset); +} + +/**************************************************************************** + * Name: stm32h5serial_putreg + ****************************************************************************/ + +static inline +void stm32h5serial_putreg(struct stm32h5_serial_s *priv, + int offset, uint32_t value) +{ + putreg32(value, priv->usartbase + offset); +} + +/**************************************************************************** + * Name: stm32h5serial_setusartint + ****************************************************************************/ + +static inline +void stm32h5serial_setusartint(struct stm32h5_serial_s *priv, + uint16_t ie) +{ + uint32_t cr; + + /* Save the interrupt mask */ + + priv->ie = ie; + + /* And restore the interrupt state (see the interrupt enable/usage table + * above) + */ + + cr = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + cr &= ~(USART_CR1_USED_INTS); + cr |= (ie & (USART_CR1_USED_INTS)); + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, cr); + + cr = stm32h5serial_getreg(priv, STM32H5_USART_CR3_OFFSET); + cr &= ~USART_CR3_EIE; + cr |= (ie & USART_CR3_EIE); + stm32h5serial_putreg(priv, STM32H5_USART_CR3_OFFSET, cr); +} + +/**************************************************************************** + * Name: up_restoreusartint + ****************************************************************************/ + +static void stm32h5serial_restoreusartint(struct stm32h5_serial_s *priv, + uint16_t ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(NULL); + + stm32h5serial_setusartint(priv, ie); + + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: stm32h5serial_disableusartint + ****************************************************************************/ + +static void stm32h5serial_disableusartint(struct stm32h5_serial_s *priv, + uint16_t *ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(NULL); + + if (ie) + { + uint32_t cr1; + uint32_t cr3; + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ---------------------- ------------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready to + * be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_ISR_TC Transmission Complete (only RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register + * Empty + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NF Noise Flag + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + */ + + cr1 = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + cr3 = stm32h5serial_getreg(priv, STM32H5_USART_CR3_OFFSET); + + /* Return the current interrupt mask value for the used interrupts. + * Notice that this depends on the fact that none of the used interrupt + * enable bits overlap. This logic would fail if we needed the break + * interrupt! + */ + + *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE); + } + + /* Disable all interrupts */ + + stm32h5serial_setusartint(priv, 0); + + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: stm32h5serial_dmanextrx + * + * Description: + * Returns the index into the RX FIFO where the DMA will place the next + * byte that it receives. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +static int stm32h5serial_dmanextrx(struct stm32h5_serial_s *priv) +{ + size_t dmaresidual; + + dmaresidual = stm32h5_dmaresidual(priv->rxdma); + + return (RXDMA_BUFFER_SIZE - (int)dmaresidual); +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_setformat + * + * Description: + * Set the serial line format and speed. + * + ****************************************************************************/ + +#ifndef CONFIG_SUPPRESS_UART_CONFIG +static void stm32h5serial_setformat(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + uint32_t regval; + uint32_t brr; + uint32_t cr1; + + /* This first implementation is for U[S]ARTs that support oversampling + * by 8 in additional to the standard oversampling by 16. + */ +#ifdef CONFIG_STM32H5_LPUART1 + if (priv->islpuart == true) + { + /* LPUART BRR (19:00) = (256*apbclock_hz/baud_rate) */ + + uint32_t apbclock_whole = priv->apbclock; + uint32_t clock_baud_ratio = apbclock_whole / priv->baud; + uint32_t presc_reg = 0x0; + + /* LPUART PRESC (3:0) + * Divide the apbclock if necessary for low baud rates + * 3 * baud_rate <= apbclock_whole <= 4096 * baud_rate + */ + + if (clock_baud_ratio <= 4096) + { + presc_reg = 0x0; + } + else if (clock_baud_ratio > 4096 && clock_baud_ratio <= 8192) + { + presc_reg = 0x1; + apbclock_whole >>= 1; + } + else if (clock_baud_ratio > 8192 && clock_baud_ratio <= 16384) + {arch/arm/src/stm32h5/.stm32h5_serial.c.swo + presc_reg = 0x2; + apbclock_whole >>= 2; + } + else if (clock_baud_ratio > 16384 && clock_baud_ratio <= 24576) + { + presc_reg = 0x3; + apbclock_whole /= 6; + } + else if (clock_baud_ratio > 24576 && clock_baud_ratio <= 32768) + { + presc_reg = 0x4; + apbclock_whole >>= 3; + } + else if (clock_baud_ratio > 32768 && clock_baud_ratio <= 40960) + { + presc_reg = 0x5; + apbclock_whole /= 10; + } + else if (clock_baud_ratio > 40960 && clock_baud_ratio <= 49152) + { + presc_reg = 0x6; + apbclock_whole /= 12; + } + else if (clock_baud_ratio > 32768 && clock_baud_ratio <= 65536) + { + presc_reg = 0x7; + apbclock_whole >>= 4; + } + else if (clock_baud_ratio > 65536 && clock_baud_ratio <= 131072) + { + presc_reg = 0x8; + apbclock_whole >>= 5; + } + else if (clock_baud_ratio > 131072 && clock_baud_ratio <= 262144) + { + presc_reg = 0x9; + apbclock_whole >>= 6; + } + else if (clock_baud_ratio > 262144 && clock_baud_ratio <= 524288) + { + presc_reg = 0xa; + apbclock_whole >>= 7; + } + else + { + presc_reg = 0xb; + apbclock_whole >>= 8; + } + + /* Write the PRESC register */ + + up_serialout(priv, STM32_USART_PRESC_OFFSET, presc_reg); + + /* Set the LPUART BRR value after setting Prescaler + * BRR = ( (256 * apbclock_whole) + baud_rate / 2 ) / baud_rate + */ + + brr = (((uint64_t)apbclock_whole << 8) + (priv->baud >> 1)) / \ + priv->baud; + } + else +#endif /* CONFIG_STM32H5_LPUART1 */ + { + + uint32_t usartdiv8; + + /* In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / usartdiv8 + * usartdiv8 = 2 * fCK / baud + */ + + usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / usartdiv16 + * usartdiv16 = fCK / baud + * = 2 * usartdiv8 + */ + + /* Use oversamply by 8 only if the divisor is small. But what is small? */ + + cr1 = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + if (usartdiv8 > 2000) + { + /* Use usartdiv16 */ + + brr = (usartdiv8 + 1) >> 1; + + /* Clear oversampling by 8 to enable oversampling by 16 */ + + cr1 &= ~USART_CR1_OVER8; + } + else + { + DEBUGASSERT(usartdiv8 >= 8); + + /* Perform mysterious operations on bits 0-3 */ + + brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); + + /* Set oversampling by 8 */ + + cr1 |= USART_CR1_OVER8; + } + } + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, cr1); + stm32h5serial_putreg(priv, STM32H5_USART_BRR_OFFSET, brr); + + /* Configure parity mode */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); + + if (priv->parity == 1) /* Odd parity */ + { + regval |= (USART_CR1_PCE | USART_CR1_PS); + } + else if (priv->parity == 2) /* Even parity */ + { + regval |= USART_CR1_PCE; + } + + /* Configure word length (parity uses one of configured bits) + * + * Default: 1 start, 8 data (no parity), n stop, OR + * 1 start, 7 data + parity, n stop + */ + + if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0)) + { + /* Select: 1 start, 8 data + parity, n stop, OR + * 1 start, 9 data (no parity), n stop. + */ + + regval |= USART_CR1_M0; + } + else if (priv->bits == 7 && priv->parity == 0) + { + /* Select: 1 start, 7 data (no parity), n stop, OR + */ + + regval |= USART_CR1_M1; + } + + /* Else Select: 1 start, 7 data + parity, n stop, OR + * 1 start, 8 data (no parity), n stop. + */ + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, regval); + + /* Configure STOP bits */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK); + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + + stm32h5serial_putreg(priv, STM32H5_USART_CR2_OFFSET, regval); + + /* Configure hardware flow control */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN) + if (priv->iflow && (priv->rts_gpio != 0)) + { + regval |= USART_CR3_RTSE; + } +#endif + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->oflow && (priv->cts_gpio != 0)) + { + regval |= USART_CR3_CTSE; + } +#endif + + stm32h5serial_putreg(priv, STM32H5_USART_CR3_OFFSET, regval); +} +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + +/**************************************************************************** + * Name: stm32h5serial_setsuspend + * + * Description: + * Suspend or resume serial peripheral. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32h5serial_setsuspend(struct uart_dev_s *dev, bool suspend) +{ + struct stm32h5_serial_s *priv = (struct stm32h5_serial_s *)dev->priv; +#ifdef SERIAL_HAVE_DMA + bool dmarestored = false; +#endif + + if (priv->suspended == suspend) + { + return; + } + + priv->suspended = suspend; + + if (suspend) + { +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Force RTS high to prevent further Rx. */ + + stm32h5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); + } +#endif + + /* Disable interrupts to prevent Tx. */ + + stm32h5serial_disableusartint(priv, &priv->suspended_ie); + + /* Wait last Tx to complete. */ + + while ((stm32h5serial_getreg(priv, STM32H5_USART_ISR_OFFSET) & + USART_ISR_TC) == 0); + +#ifdef SERIAL_HAVE_DMA + if (priv->dev.ops == &g_uart_dma_ops && !priv->rxdmasusp) + { +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow && priv->rxdmanext == RXDMA_BUFFER_SIZE) + { + /* Rx DMA in non-circular iflow mode and already stopped + * at end of DMA buffer. No need to suspend. + */ + } + else +#endif + { + /* Suspend Rx DMA. */ + + stm32h5_dmastop(priv->rxdma); + priv->rxdmasusp = true; + } + } +#endif + } + else + { +#ifdef SERIAL_HAVE_DMA + if (priv->dev.ops == &g_uart_dma_ops && priv->rxdmasusp) + { +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + stm32h5serial_dmaiflowrestart(priv); + } + else +#endif + { + /* This USART does not have HW flow-control. Unconditionally + * re-enable DMA (might loss unprocessed bytes received + * to DMA buffer before suspending). + */ + + stm32h5serial_dmareenable(priv); + priv->rxdmasusp = false; + } + + dmarestored = true; + } +#endif + + /* Re-enable interrupts to resume Tx. */ + + stm32h5serial_restoreusartint(priv, priv->suspended_ie); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Restore peripheral RTS control. */ + + stm32h5_configgpio(priv->rts_gpio); + } +#endif + } + +#ifdef SERIAL_HAVE_DMA + if (dmarestored) + { + irqstate_t flags; + + flags = enter_critical_section(); + + /* Perform initial Rx DMA buffer fetch to wake-up serial device + * activity. + */ + + if (priv->rxdma != NULL) + { + stm32h5serial_dmarxcallback(priv->rxdma, 0, priv); + } + + leave_critical_section(flags); + } +#endif +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_pm_setsuspend + * + * Description: + * Suspend or resume serial peripherals for/from deep-sleep/stop modes. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32h5serial_pm_setsuspend(bool suspend) +{ + int n; + + /* Already in desired state? */ + + if (suspend == g_serialpm.serial_suspended) + return; + + g_serialpm.serial_suspended = suspend; + + for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + { + struct stm32h5_serial_s *priv = g_uart_devs[n]; + + if (!priv || !priv->initialized) + { + continue; + } + + stm32h5serial_setsuspend(&priv->dev, suspend); + } +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_setapbclock + * + * Description: + * Enable or disable APB clock for the USART peripheral + * + * Input Parameters: + * dev - A reference to the UART driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static void stm32h5serial_setapbclock(struct uart_dev_s *dev, bool on) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + uint32_t rcc_en; + uint32_t regaddr; + + /* Determine which USART to configure */ + + switch (priv->usartbase) + { + default: + return; +#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER + case STM32H5_LPUART1_BASE: + rcc_en = RCC_APB3ENR_LPUART1EN ; + regaddr = STM32H5_RCC_APB3ENR; + break; +#endif +#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER + case STM32H5_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN ; + regaddr = STM32H5_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER + case STM32H5_USART2_BASE: + rcc_en = RCC_APB1LENR_USART2EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER + case STM32H5_USART3_BASE: + rcc_en = RCC_APB1LENR_USART3EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER + case STM32H5_UART4_BASE: + rcc_en = RCC_APB1LENR_UART4EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER + case STM32H5_UART5_BASE: + rcc_en = RCC_APB1LENR_UART5EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER + case STM32H5_USART6_BASE: + rcc_en = RCC_APB1LENR_USART6EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER + case STM32H5_UART7_BASE: + rcc_en = RCC_APB1LENR_UART7EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER + case STM32H5_UART8_BASE: + rcc_en = RCC_APB1LENR_UART8EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER + case STM32H5_UART9_BASE: + rcc_en = RCC_APB1HENR_UART9EN; + regaddr = STM32H5_RCC_APB1HENR; + break; +#endif + +#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER + case STM32H5_USART10_BASE: + rcc_en = RCC_APB1LENR_USART10EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER + case STM32H5_USART11_BASE: + rcc_en = RCC_APB1LENR_USART11EN; + regaddr = STM32H5_RCC_APB1LENR; + break; +#endif +#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER + case STM32H5_UART12_BASE: + rcc_en = RCC_APB1HENR_UART12EN; + regaddr = STM32H5_RCC_APB1HENR; + break; +#endif + } + + /* Enable/disable APB 1/2 clock for USART */ + + if (on) + { + modifyreg32(regaddr, 0, rcc_en); + } + else + { + modifyreg32(regaddr, rcc_en, 0); + } +} + +/**************************************************************************** + * Name: stm32h5serial_setup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int stm32h5serial_setup(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t regval; + + /* Note: The logic here depends on the fact that that the USART module + * was enabled in stm32h5_lowsetup(). + */ + + /* Enable USART APB1/2 clock */ + + stm32h5serial_setapbclock(dev, true); + + /* Configure pins for USART use */ + + stm32h5_configgpio(priv->tx_gpio); + stm32h5_configgpio(priv->rx_gpio); + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->cts_gpio != 0) + { + stm32h5_configgpio(priv->cts_gpio); + } +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->rts_gpio != 0) + { + uint32_t config = priv->rts_gpio; + +#ifdef CONFIG_STM32H5_FLOWCONTROL_BROKEN + /* Instead of letting hw manage this pin, we will bitbang */ + + config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; +#endif + stm32h5_configgpio(config); + } +#endif + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32h5_configgpio(priv->rs485_dir_gpio); + stm32h5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + } +#endif + + /* Configure CR2 */ + + /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR2_OFFSET); + if (priv->islpuart == true) + { + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN); + } + else + { + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | + USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); + } + + /* Configure STOP bits */ + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + + stm32h5serial_putreg(priv, STM32H5_USART_CR2_OFFSET, regval); + + /* Configure CR1 */ + + /* Clear TE, REm and all interrupt enable bits */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + +#ifdef CONFIG_STM32_LPUART1 + if (priv->islpuart == true) + { + regval &= ~(USART_CR1_TE | USART_CR1_RE | LPUART_CR1_ALLINTS); + } + else +#endif + { + regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); + } + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, regval); + + /* Configure CR3 */ + + /* Clear CTSE, RTSE, and all interrupt enable bits */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | + USART_CR3_EIE); + + stm32h5serial_putreg(priv, STM32H5_USART_CR3_OFFSET, regval); + + /* Configure the USART line format and speed. */ + + stm32h5serial_setformat(dev); + + /* Enable Rx, Tx, and the USART */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, regval); + +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + + /* Set up the cached interrupt enables value */ + + priv->ie = 0; + + /* Mark device as initialized. */ + + priv->initialized = true; + + return OK; +} + +/**************************************************************************** + * Name: stm32h5serial_dmasetup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +static int stm32h5serial_dmasetup(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + int result; + uint32_t regval; + + /* Do the basic UART setup first, unless we are the console */ + + if (!dev->isconsole) + { + result = stm32h5serial_setup(dev); + if (result != OK) + { + return result; + } + } + + /* Acquire the DMA channel. This should always succeed. */ + + priv->rxdma = stm32h5_dmachannel(priv->rxdma_channel); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Configure for non-circular DMA reception into the RX FIFO */ + + stm32h5_dmasetup(priv->rxdma, + priv->usartbase + STM32H5_USART_RDR_OFFSET, + (uint32_t)priv->rxfifo, + RXDMA_BUFFER_SIZE, + SERIAL_DMA_IFLOW_CONTROL_WORD); + } + else +#endif + { + /* Configure for circular DMA reception into the RX FIFO */ + + stm32h5_dmasetup(priv->rxdma, + priv->usartbase + STM32H5_USART_RDR_OFFSET, + (uint32_t)priv->rxfifo, + RXDMA_BUFFER_SIZE, + SERIAL_DMA_CONTROL_WORD); + } + + /* Reset our DMA shadow pointer to match the address just + * programmed above. + */ + + priv->rxdmanext = 0; + + /* Enable receive DMA for the UART */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR3_OFFSET); + regval |= USART_CR3_DMAR; + stm32h5serial_putreg(priv, STM32H5_USART_CR3_OFFSET, regval); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Start the DMA channel, and arrange for callbacks at the full point + * in the FIFO. After buffer gets full, hardware flow-control kicks + * in and DMA transfer is stopped. + */ + + stm32h5_dmastart(priv->rxdma, stm32h5serial_dmarxcallback, + (void *)priv, false); + } + else +#endif + { + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + stm32h5_dmastart(priv->rxdma, stm32h5serial_dmarxcallback, + (void *)priv, true); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_shutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void stm32h5serial_shutdown(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + uint32_t regval; + + /* Mark device as uninitialized. */ + + priv->initialized = false; + + /* Disable all interrupts */ + + stm32h5serial_disableusartint(priv, NULL); + + /* Disable USART APB1/2 clock */ + + stm32h5serial_setapbclock(dev, false); + + /* Disable Rx, Tx, and the UART */ + + regval = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, regval); + + /* Release pins. "If the serial-attached device is powered down, the TX + * pin causes back-powering, potentially confusing the device to the point + * of complete lock-up." + * + * REVISIT: Is unconfiguring the pins appropriate for all device? If not, + * then this may need to be a configuration option. + */ + + stm32h5_unconfiggpio(priv->tx_gpio); + stm32h5_unconfiggpio(priv->rx_gpio); + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->cts_gpio != 0) + { + stm32h5_unconfiggpio(priv->cts_gpio); + } +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->rts_gpio != 0) + { + stm32h5_unconfiggpio(priv->rts_gpio); + } +#endif + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32h5_unconfiggpio(priv->rs485_dir_gpio); + } +#endif +} + +/**************************************************************************** + * Name: stm32h5serial_dmashutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +static void stm32h5serial_dmashutdown(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + + /* Perform the normal UART shutdown */ + + stm32h5serial_shutdown(dev); + + /* Stop the DMA channel */ + + stm32h5_dmastop(priv->rxdma); + + /* Release the DMA channel */ + + stm32h5_dmafree(priv->rxdma); + priv->rxdma = NULL; +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_attach + * + * Description: + * Configure the USART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int stm32h5serial_attach(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, stm32h5serial_interrupt, priv); + + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32h5serial_detach + * + * Description: + * Detach USART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void stm32h5serial_detach(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: stm32h5serial_interrupt + * + * Description: + * This is the USART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int stm32h5serial_interrupt(int irq, void *context, void *arg) +{ + struct stm32h5_serial_s *priv = (struct stm32h5_serial_s *)arg; + int passes; + bool handled; + + DEBUGASSERT(priv != NULL); + + /* Report serial activity to the power management logic */ + +#if defined(CONFIG_PM) && CONFIG_STM32H5_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H5_PM_SERIAL_ACTIVITY); +#endif + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the masked USART status word. */ + + priv->sr = stm32h5serial_getreg(priv, STM32H5_USART_ISR_OFFSET); + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ---------------------- ------------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready to + * be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_ISR_TC Transmission Complete (only RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register + * Empty + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NE Noise Error + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + * + * NOTE: Some of these status bits must be cleared by explicitly + * writing one to the ICR register: USART_ICR_CTSCF, USART_ICR_LBDCF. + * None of those are currently being used. + */ + +#ifdef HAVE_RS485 + /* Transmission of whole buffer is over - TC is set, TXEIE is cleared. + * Note - this should be first, to have the most recent TC bit value + * from SR register - sending data affects TC, but without refresh we + * will not know that... + */ + + if ((priv->sr & USART_ISR_TC) != 0 && + (priv->ie & USART_CR1_TCIE) != 0 && + (priv->ie & USART_CR1_TXEIE) == 0) + { + stm32h5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32h5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + } +#endif + + /* Handle incoming, receive bytes. */ + + if ((priv->sr & USART_ISR_RXNE) != 0 && + (priv->ie & USART_CR1_RXNEIE) != 0) + { + /* Received data ready... process incoming bytes. NOTE the check + * for RXNEIE: We cannot call uart_recvchards of RX interrupts are + * disabled. + */ + + uart_recvchars(&priv->dev); + handled = true; + } + + /* We may still have to read from the DR register to clear any pending + * error conditions. + */ + + else if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) + != 0) + { + /* These errors are cleared by writing the corresponding bit to the + * interrupt clear register (ICR). + */ + + stm32h5serial_putreg(priv, STM32H5_USART_ICR_OFFSET, + (USART_ICR_NCF | USART_ICR_ORECF | + USART_ICR_FECF)); + } + + /* Handle outgoing, transmit bytes */ + + if ((priv->sr & USART_ISR_TXE) != 0 && + (priv->ie & USART_CR1_TXEIE) != 0) + { + /* Transmit data register empty ... process outgoing bytes */ + + uart_xmitchars(&priv->dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32h5serial_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int stm32h5serial_ioctl(struct file *filep, int cmd, + unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif +#if defined(CONFIG_SERIAL_TERMIOS) + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct stm32h5_serial_s *user; + + user = (struct stm32h5_serial_s *)arg; + + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct stm32h5_serial_s)); + } + } + break; +#endif + +#ifdef CONFIG_STM32H5_USART_SINGLEWIRE + case TIOCSSINGLEWIRE: + { + uint32_t cr1; + uint32_t cr1_ue; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Get the original state of UE */ + + cr1 = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + cr1_ue = cr1 & USART_CR1_UE; + cr1 &= ~USART_CR1_UE; + + /* Disable UE, HDSEL can only be written when UE=0 */ + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, cr1); + + /* Change the TX port to be open-drain/push-pull and enable/disable + * half-duplex mode. + */ + + uint32_t cr = stm32h5serial_getreg(priv, STM32H5_USART_CR3_OFFSET); + + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + uint32_t gpio_val = GPIO_OPENDRAIN; + + if ((arg & SER_SINGLEWIRE_PULL_MASK) == SER_SINGLEWIRE_PULLUP) + { + gpio_val |= GPIO_PULLUP; + } + else + { + gpio_val |= GPIO_FLOAT; + } + + if ((arg & SER_SINGLEWIRE_PULL_MASK) == SER_SINGLEWIRE_PULLDOWN) + { + gpio_val |= GPIO_PULLDOWN; + } + else + { + gpio_val |= GPIO_FLOAT; + } + + stm32h5_configgpio((priv->tx_gpio & + ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | + gpio_val); + + cr |= USART_CR3_HDSEL; + } + else + { + stm32h5_configgpio((priv->tx_gpio & + ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | + GPIO_PUSHPULL); + cr &= ~USART_CR3_HDSEL; + } + + stm32h5serial_putreg(priv, STM32H5_USART_CR3_OFFSET, cr); + + /* Re-enable UE if appropriate */ + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, cr1 | cr1_ue); + leave_critical_section(flags); + } + break; +#endif + +#ifdef CONFIG_STM32H5_USART_INVERT + case TIOCSINVERT: + { + uint32_t cr1; + uint32_t cr1_ue; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Get the original state of UE */ + + cr1 = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + cr1_ue = cr1 & USART_CR1_UE; + cr1 &= ~USART_CR1_UE; + + /* Disable UE, {R,T}XINV can only be written when UE=0 */ + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, cr1); + + /* Enable/disable signal inversion. */ + + uint32_t cr = stm32h5serial_getreg(priv, STM32H5_USART_CR2_OFFSET); + + if (arg & SER_INVERT_ENABLED_RX) + { + cr |= USART_CR2_RXINV; + } + else + { + cr &= ~USART_CR2_RXINV; + } + + if (arg & SER_INVERT_ENABLED_TX) + { + cr |= USART_CR2_TXINV; + } + else + { + cr &= ~USART_CR2_TXINV; + } + + stm32h5serial_putreg(priv, STM32H5_USART_CR2_OFFSET, cr); + + /* Re-enable UE if appropriate */ + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, cr1 | cr1_ue); + leave_critical_section(flags); + } + break; +#endif + +#ifdef CONFIG_STM32H5_USART_SWAP + case TIOCSSWAP: + { + uint32_t cr1; + uint32_t cr1_ue; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Get the original state of UE */ + + cr1 = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + cr1_ue = cr1 & USART_CR1_UE; + cr1 &= ~USART_CR1_UE; + + /* Disable UE, SWAP can only be written when UE=0 */ + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, cr1); + + /* Enable/disable Swap mode. */ + + uint32_t cr = stm32h5serial_getreg(priv, STM32H5_USART_CR2_OFFSET); + + if (arg == SER_SWAP_ENABLED) + { + cr |= USART_CR2_SWAP; + } + else + { + cr &= ~USART_CR2_SWAP; + } + + stm32h5serial_putreg(priv, STM32H5_USART_CR2_OFFSET, cr); + + /* Re-enable UE if appropriate */ + + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, cr1 | cr1_ue); + leave_critical_section(flags); + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + cfsetispeed(termiosp, priv->baud); + + /* Note that since we only support 8/9 bit modes and + * there is no way to report 9-bit mode, we always claim 8. + */ + + termiosp->c_cflag = + ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0) | + ((priv->stopbits2) ? CSTOPB : 0) | +#ifdef CONFIG_SERIAL_OFLOWCONTROL + ((priv->oflow) ? CCTS_OFLOW : 0) | +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + ((priv->iflow) ? CRTS_IFLOW : 0) | +#endif + CS8; + + /* TODO: CRTS_IFLOW, CCTS_OFLOW */ + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Perform some sanity checks before accepting any changes */ + + if (((termiosp->c_cflag & CSIZE) != CS8) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + if (termiosp->c_cflag & PARENB) + { + priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + priv->parity = 0; + } + + priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + + /* Note that since there is no way to request 9-bit mode + * and no way to support 5/6/7-bit modes, we ignore them + * all here. + */ + + /* Note that only cfgetispeed is used because we have knowledge + * that only one speed is supported. + */ + + priv->baud = cfgetispeed(termiosp); + + /* Effect the changes immediately - note that we do not implement + * TCSADRAIN / TCSAFLUSH + */ + + stm32h5serial_setformat(dev); + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + +#ifdef CONFIG_STM32H5_USART_BREAKS +# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + { + irqstate_t flags; + uint32_t tx_break; + + flags = enter_critical_section(); + + /* Disable any further tx activity */ + + priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; + + stm32h5serial_txint(dev, false); + + /* Configure TX as a GPIO output pin and Send a break signal */ + + tx_break = GPIO_OUTPUT | + (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); + stm32h5_configgpio(tx_break); + + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + { + irqstate_t flags; + + flags = enter_critical_section(); + + /* Configure TX back to U(S)ART */ + + stm32h5_configgpio(priv->tx_gpio); + + priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; + + /* Enable further tx activity */ + + stm32h5serial_txint(dev, true); + + leave_critical_section(flags); + } + break; +# else + case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ + { + uint32_t cr1; + irqstate_t flags; + + flags = enter_critical_section(); + cr1 = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, + cr1 | USART_CR1_SBK); + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */ + { + uint32_t cr1; + irqstate_t flags; + + flags = enter_critical_section(); + cr1 = stm32h5serial_getreg(priv, STM32H5_USART_CR1_OFFSET); + stm32h5serial_putreg(priv, STM32H5_USART_CR1_OFFSET, + cr1 & ~USART_CR1_SBK); + leave_critical_section(flags); + } + break; +# endif +#endif + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32h5serial_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_DMA +static int stm32h5serial_receive(struct uart_dev_s *dev, + unsigned int *status) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + uint32_t rdr; + + /* Get the Rx byte */ + + rdr = stm32h5serial_getreg(priv, STM32H5_USART_RDR_OFFSET); + + /* Get the Rx byte plux error information. Return those in status */ + + *status = priv->sr << 16 | rdr; + priv->sr = 0; + + /* Then return the actual received byte */ + + return rdr & 0xff; +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_DMA +static void stm32h5serial_rxint(struct uart_dev_s *dev, bool enable) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + irqstate_t flags; + uint16_t ie; + + /* USART receive interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ---------------------- ---------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready + * to be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NF Noise Flag + * " " USART_ISR_ORE Overrun Error Detected + */ + + flags = enter_critical_section(); + ie = priv->ie; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data + * register (or an Rx timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS +#ifdef CONFIG_USART_ERRINTS + ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); +#else + ie |= USART_CR1_RXNEIE; +#endif +#endif + } + else + { + ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); + } + + /* Then set the new interrupt state */ + + stm32h5serial_restoreusartint(priv, ie); + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_DMA +static bool stm32h5serial_rxavailable(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + + return ((stm32h5serial_getreg(priv, STM32H5_USART_ISR_OFFSET) & + USART_ISR_RXNE) != 0); +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_rxflowcontrol + * + * Description: + * Called when Rx buffer is full (or exceeds configured watermark levels + * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if UART activated RX flow control to block more incoming + * data + * + * Input Parameters: + * dev - UART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool stm32h5serial_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + +#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ + defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN) + if (priv->iflow && (priv->rts_gpio != 0)) + { + /* Assert/de-assert nRTS set it high resume/stop sending */ + + stm32h5_gpiowrite(priv->rts_gpio, upper); + + if (upper) + { + /* With heavy Rx traffic, RXNE might be set and data pending. + * Returning 'true' in such case would cause RXNE left unhandled + * and causing interrupt storm. Sending end might be also be slow + * to react on nRTS, and returning 'true' here would prevent + * processing that data. + * + * Therefore, return 'false' so input data is still being processed + * until sending end reacts on nRTS signal and stops sending more. + */ + + return false; + } + + return upper; + } + +#else + if (priv->iflow) + { + /* Is the RX buffer full? */ + + if (upper) + { + /* Disable Rx interrupt to prevent more data being from + * peripheral. When hardware RTS is enabled, this will + * prevent more data from coming in. + * + * This function is only called when UART recv buffer is full, + * that is: "dev->recv.head + 1 == dev->recv.tail". + * + * Logic in "uart_read" will automatically toggle Rx interrupts + * when buffer is read empty and thus we do not have to re- + * enable Rx interrupts. + */ + + uart_disablerxint(dev); + return true; + } + + /* No.. The RX buffer is empty */ + + else + { + /* We might leave Rx interrupt disabled if full recv buffer was + * read empty. Enable Rx interrupt to make sure that more input is + * received. + */ + + uart_enablerxint(dev); + } + } +#endif + + return false; +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_dmareceive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +static int stm32h5serial_dmareceive(struct uart_dev_s *dev, + unsigned int *status) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + int c = 0; + + if (stm32h5serial_dmanextrx(priv) != priv->rxdmanext) + { + c = priv->rxfifo[priv->rxdmanext]; + + priv->rxdmanext++; + if (priv->rxdmanext == RXDMA_BUFFER_SIZE) + { +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* RX DMA buffer full. RX paused, RTS line pulled up to prevent + * more input data from other end. + */ + } + else +#endif + { + priv->rxdmanext = 0; + } + } + } + + return c; +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_dmareenable + * + * Description: + * Call to re-enable RX DMA. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_DMA) +static void stm32h5serial_dmareenable(struct stm32h5_serial_s *priv) +{ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Configure for non-circular DMA reception into the RX FIFO */ + + stm32h5_dmasetup(priv->rxdma, + priv->usartbase + STM32H5_USART_RDR_OFFSET, + (uint32_t)priv->rxfifo, + RXDMA_BUFFER_SIZE, + SERIAL_DMA_IFLOW_CONTROL_WORD); + } + else +#endif + { + /* Configure for circular DMA reception into the RX FIFO */ + + stm32h5_dmasetup(priv->rxdma, + priv->usartbase + STM32H5_USART_RDR_OFFSET, + (uint32_t)priv->rxfifo, + RXDMA_BUFFER_SIZE, + SERIAL_DMA_CONTROL_WORD); + } + + /* Reset our DMA shadow pointer to match the address just + * programmed above. + */ + + priv->rxdmanext = 0; + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Start the DMA channel, and arrange for callbacks at the full point + * in the FIFO. After buffer gets full, hardware flow-control kicks + * in and DMA transfer is stopped. + */ + + stm32h5_dmastart(priv->rxdma, stm32h5serial_dmarxcallback, + (void *)priv, false); + } + else +#endif + { + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + stm32h5_dmastart(priv->rxdma, stm32h5serial_dmarxcallback, + (void *)priv, true); + } + +#ifdef CONFIG_PM + /* Clear DMA suspended flag. */ + + priv->rxdmasusp = false; +#endif +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_dmaiflowrestart + * + * Description: + * Call to restart RX DMA for input flow-controlled USART + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) +static bool stm32h5serial_dmaiflowrestart(struct stm32h5_serial_s *priv) +{ + if (!priv->rxenable) + { + /* Rx not enabled by upper layer. */ + + return false; + } + + if (priv->rxdmanext != RXDMA_BUFFER_SIZE) + { +#ifdef CONFIG_PM + if (priv->rxdmasusp) + { + /* Rx DMA in suspended state. */ + + if (stm32h5serial_dmarxavailable(&priv->dev)) + { + /* DMA buffer has unprocessed data, do not re-enable yet. */ + + return false; + } + } + else +#endif + { + return false; + } + } + + /* DMA is stopped or suspended and DMA buffer does not have pending data, + * re-enabling without data loss is now safe. + */ + + stm32h5serial_dmareenable(priv); + + return true; +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_dmarxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +static void stm32h5serial_dmarxint(struct uart_dev_s *dev, bool enable) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + + /* En/disable DMA reception. + * + * Note that it is not safe to check for available bytes and immediately + * pass them to uart_recvchars as that could potentially recurse back + * to us again. Instead, bytes must wait until the next up_dma_poll or + * DMA event. + */ + + priv->rxenable = enable; + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Re-enable RX DMA. */ + + stm32h5serial_dmaiflowrestart(priv); + } +#endif +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_dmarxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +static bool stm32h5serial_dmarxavailable(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + + /* Compare our receive pointer to the current DMA pointer, if they + * do not match, then there are bytes to be received. + */ + + return (stm32h5serial_dmanextrx(priv) != priv->rxdmanext); +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_send + * + * Description: + * This method will send one byte on the USART + * + ****************************************************************************/ + +static void stm32h5serial_send(struct uart_dev_s *dev, int ch) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32h5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + } +#endif + + stm32h5serial_putreg(priv, STM32H5_USART_TDR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: stm32h5serial_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void stm32h5serial_txint(struct uart_dev_s *dev, bool enable) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + irqstate_t flags; + + /* USART transmit interrupts: + * + * Enable Status Meaning Usage + * --------------- ------------- ---------------------------- ------------- + * USART_CR1_TCIE USART_ISR_TC Transmission Complete (only RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register Empty + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + */ + + flags = enter_critical_section(); + if (enable) + { + /* Set to receive an interrupt when the TX data register is empty */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + uint16_t ie = priv->ie | USART_CR1_TXEIE; + + /* If RS-485 is supported on this U[S]ART, then also enable the + * transmission complete interrupt. + */ + +# ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + ie |= USART_CR1_TCIE; + } +# endif + +# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT + if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) + { + leave_critical_section(flags); + return; + } +# endif + + stm32h5serial_restoreusartint(priv, ie); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + stm32h5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32h5serial_txready + * + * Description: + * Return true if the transmit data register is empty + * + ****************************************************************************/ + +static bool stm32h5serial_txready(struct uart_dev_s *dev) +{ + struct stm32h5_serial_s *priv = + (struct stm32h5_serial_s *)dev->priv; + + return ((stm32h5serial_getreg(priv, STM32H5_USART_ISR_OFFSET) & + USART_ISR_TXE) != 0); +} + +/**************************************************************************** + * Name: stm32h5serial_dmarxcallback + * + * Description: + * This function checks the current DMA state and calls the generic + * serial stack when bytes appear to be available. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +static void stm32h5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, + void *arg) +{ + struct stm32h5_serial_s *priv = (struct stm32h5_serial_s *)arg; + + if (priv->rxenable && stm32h5serial_dmarxavailable(&priv->dev)) + { + uart_recvchars(&priv->dev); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Re-enable RX DMA. */ + + stm32h5serial_dmaiflowrestart(priv); + } +#endif + } + + /* Get the masked USART status word to check and clear error flags. + * + * When wake-up from low power mode was not fast enough, UART is resumed + * too late and sometimes exactly when character was coming over UART, + * resulting to frame error. + * If error flag is not cleared, Rx DMA will be stuck. Clearing errors + * will release Rx DMA. + */ + + priv->sr = stm32h5serial_getreg(priv, STM32H5_USART_ISR_OFFSET); + + if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) + { + stm32h5serial_putreg(priv, STM32H5_USART_ICR_OFFSET, + (USART_ICR_NCF | USART_ICR_ORECF | + USART_ICR_FECF)); + } +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_pmnotify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32h5serial_pmnotify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + stm32h5serial_pm_setsuspend(false); + } + break; + + case PM_IDLE: + { + stm32h5serial_pm_setsuspend(false); + } + break; + + case PM_STANDBY: + { + /* TODO: Alternative configuration and logic for enabling serial in + * Stop 1 mode with HSI16 missing. Current logic allows + * suspending serial peripherals for Stop 0/1/2 when serial + * Rx/Tx buffers are empty (checked in pmprepare). + */ + + stm32h5serial_pm_setsuspend(true); + } + break; + + case PM_SLEEP: + { + stm32h5serial_pm_setsuspend(true); + } + break; + + default: + + /* Should not get here */ + + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32h5serial_pmprepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int stm32h5serial_pmprepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + int n; + + /* Logic to prepare for a reduced power state goes here. */ + + switch (pmstate) + { + case PM_NORMAL: + case PM_IDLE: + break; + + case PM_STANDBY: + case PM_SLEEP: + +#ifdef SERIAL_HAVE_DMA + /* Flush Rx DMA buffers before checking state of serial device + * buffers. + */ + + stm32h5_serial_dma_poll(); +#endif + + /* Check if any of the active ports have data pending on Tx/Rx + * buffers. + */ + + for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + { + struct stm32h5_serial_s *priv = g_uart_devs[n]; + + if (!priv || !priv->initialized) + { + /* Not active, skip. */ + + continue; + } + + if (priv->suspended) + { + /* Port already suspended, skip. */ + + continue; + } + + /* Check if port has data pending (Rx & Tx). */ + + if (priv->dev.xmit.head != priv->dev.xmit.tail) + { + return ERROR; + } + + if (priv->dev.recv.head != priv->dev.recv.tail) + { + return ERROR; + } + } + break; + + default: + + /* Should not get here */ + + break; + } + + return OK; +} +#endif + +#endif /* HAVE_UART */ +#endif /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level USART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before arm_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void arm_earlyserialinit(void) +{ +#ifdef HAVE_UART + unsigned i; + + /* Disable all USART interrupts */ + + for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + { + if (g_uart_devs[i]) + { + stm32h5serial_disableusartint(g_uart_devs[i], NULL); + } + } + + /* Configure whichever one is the console */ + +#if CONSOLE_UART > 0 + stm32h5serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); +#endif +#endif /* HAVE UART */ +} +#endif /* USE_EARLYSERIALINIT */ + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that arm_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ +#ifdef HAVE_UART + char devname[16]; + unsigned i; + unsigned minor = 0; +#ifdef CONFIG_PM + int ret; +#endif + + /* Register to receive power management callbacks */ + +#ifdef CONFIG_PM + ret = pm_register(&g_serialpm.pm_cb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + + /* Register the console */ + +#if CONSOLE_UART > 0 + uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); + +#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING + /* If not disabled, register the console UART to ttyS0 and exclude + * it from initializing it further down + */ + + uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev); + minor = 1; +#endif + +#ifdef SERIAL_HAVE_CONSOLE_DMA + /* If we need to re-initialise the console to enable DMA do that here. */ + + stm32h5serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); +#endif +#endif /* CONSOLE_UART > 0 */ + + /* Register all remaining USARTs */ + + strlcpy(devname, "/dev/ttySx", sizeof(devname)); + + for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + { + /* Don't create a device for non-configured ports. */ + + if (g_uart_devs[i] == 0) + { + continue; + } + +#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING + /* Don't create a device for the console - we did that above */ + + if (g_uart_devs[i]->dev.isconsole) + { + continue; + } +#endif + + /* Register USARTs as devices in increasing order */ + + devname[9] = '0' + minor++; + uart_register(devname, &g_uart_devs[i]->dev); + } +#endif /* HAVE UART */ +} + +/**************************************************************************** + * Name: stm32h5_serial_dma_poll + * + * Description: + * Checks receive DMA buffers for received bytes that have not accumulated + * to the point where the DMA half/full interrupt has triggered. + * + * This function should be called from a timer or other periodic context. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +void stm32h5_serial_dma_poll(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + +#ifdef CONFIG_LPUART1_RXDMA + if (g_lpuart1priv.rxdma != NULL) + { + stm32h5serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); + } +#endif + +#ifdef CONFIG_USART1_RXDMA + if (g_usart1priv.rxdma != NULL) + { + stm32h5serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); + } +#endif + +#ifdef CONFIG_USART2_RXDMA + if (g_usart2priv.rxdma != NULL) + { + stm32h5serial_dmarxcallback(g_usart2priv.rxdma, 0, &g_usart2priv); + } +#endif + +#ifdef CONFIG_USART3_RXDMA + if (g_usart3priv.rxdma != NULL) + { + stm32h5serial_dmarxcallback(g_usart3priv.rxdma, 0, &g_usart3priv); + } +#endif + +#ifdef CONFIG_UART4_RXDMA + if (g_uart4priv.rxdma != NULL) + { + stm32h5serial_dmarxcallback(g_uart4priv.rxdma, 0, &g_uart4priv); + } +#endif + +#ifdef CONFIG_UART5_RXDMA + if (g_uart5priv.rxdma != NULL) + { + stm32h5serial_dmarxcallback(g_uart5priv.rxdma, 0, &g_uart5priv); + } +#endif + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#if CONSOLE_UART > 0 + struct stm32h5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + uint16_t ie; + + stm32h5serial_disableusartint(priv, &ie); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + arm_lowputc('\r'); + } + + arm_lowputc(ch); + stm32h5serial_restoreusartint(priv, ie); +#endif + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#if CONSOLE_UART > 0 + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + arm_lowputc('\r'); + } + + arm_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/stm32h5/stm32h5_start.c b/arch/arm/src/stm32h5/stm32h5_start.c new file mode 100644 index 0000000000000..e20fcb7870226 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_start.c @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "nvic.h" + +#include "stm32h5.h" +#include "stm32h5_gpio.h" +#include "stm32h5_userspace.h" +#include "stm32h5_start.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory Map ***************************************************************/ + +/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors. + * Mapped as boot memory address 0x0000:0000 at reset. + * 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH). + * 0x2000:0000 - Start of internal SRAM1 and start of .data (_sdata) + * - End of .data (_edata) and start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, + * start of heap. NOTE that the ARM uses a decrement before + * store stack so that the correct initial value is the end of + * the stack + 4; + * 0x2002:ffff - End of internal SRAM1 + * 0x2003:0000 - Start of internal SRAM2 + * 0x2003:ffff - End of internal SRAM2 + */ + +#define SRAM2_START STM32H5_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32H5_SRAM2_SIZE) + +#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ + +const uintptr_t g_idle_topstack = HEAP_BASE; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) arm_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_ARMV8M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) noinstrument_function; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + +#ifdef CONFIG_ARMV8M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile + ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :); +#endif + +#ifdef CONFIG_STM32H5_SRAM2_INIT + /* The SRAM2 region is parity checked, but upon power up, it will be in + * a random state and probably invalid with respect to parity, potentially + * generating faults if accessed. If elected, we will write zeros to the + * memory, forcing the parity to be set to a valid state. + * NOTE: this is optional because this may be inappropriate, especially + * if the memory is being used for it's battery backed purpose. In that + * case, the first-time initialization needs to be performed by the board + * under application-specific circumstances. On the other hand, if we're + * using this memory for, say, additional heap space, then this is handy. + */ + + for (dest = (uint32_t *)SRAM2_START; dest < (uint32_t *)SRAM2_END; ) + { + *dest++ = 0; + } +#endif + + /* Configure the UART so that we can get debug output as soon as possible */ + + stm32h5_clockconfig(); + arm_fpuconfig(); + stm32h5_lowsetup(); + stm32h5_gpioinit(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + showprogress('B'); + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = (const uint32_t *)_eronly, + dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; + ) + { + *dest++ = *src++; + } + + showprogress('C'); + +#ifdef CONFIG_ARMV8M_STACKCHECK + arm_stack_check_init(); +#endif + +#ifdef CONFIG_ARCH_PERF_EVENTS + up_perf_init((void *)STM32H5_SYSCLK_FREQUENCY); +#endif + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + arm_earlyserialinit(); +#endif + showprogress('D'); + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + stm32h5_userspace(); + showprogress('E'); +#endif + + /* Initialize onboard resources */ + + stm32h5_board_initialize(); + showprogress('F'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + + nx_start(); + + /* Shoulnd't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/stm32h5/stm32h5_start.h b/arch/arm/src/stm32h5/stm32h5_start.h new file mode 100644 index 0000000000000..c81da75e4e853 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_start.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_start.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_START_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_board_initialize + * + * Description: + * All STM32H5 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32h5_board_initialize(void); + +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_START_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_timerisr.c b/arch/arm/src/stm32h5/stm32h5_timerisr.c new file mode 100644 index 0000000000000..3d9bf7f5bc7b8 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_timerisr.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "arm_internal.h" +#include "chip.h" +#include "stm32h5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) + * divided by 8. The SysTick can work either with this clock or with the + * Cortex clock (HCLK), configurable in the SysTick Control and Status + * register. + */ + +/* Power up default is HCLK, not HCLK/8. + * And I don't know now to re-configure it yet + */ + +#undef CONFIG_STM32H5_SYSTICK_HCLKd8 + +#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32H5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#else +# define SYSTICK_RELOAD ((STM32H5_HCLK_FREQUENCY / CLK_TCK) - 1) +#endif + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32h5_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int stm32h5_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Make sure that the SYSTICK clock source is set correctly */ + +#if 0 /* Does not work. Comes up with HCLK source and I can't change it */ + regval = getreg32(NVIC_SYSTICK_CTRL); +#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8 + regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; +#else + regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; +#endif + putreg32(regval, NVIC_SYSTICK_CTRL); +#endif + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + irq_attach(STM32H5_IRQ_SYSTICK, (xcpt_t)stm32h5_timerisr, NULL); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(STM32H5_IRQ_SYSTICK); +} diff --git a/arch/arm/src/stm32h5/stm32h5_uart.h b/arch/arm/src/stm32h5/stm32h5_uart.h new file mode 100644 index 0000000000000..7252d3868fa6f --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_uart.h @@ -0,0 +1,573 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_STC_STM32H5_STM32H5_UART_H +#define __ARCH_ARM_STC_STM32H5_STM32H5_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +#if defined(CONFIG_STM32H5_STM32H5XXXX) +# include "hardware/stm32h5_uart.h" +#else +# error "Unsupported STM32H5 chip" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Make sure that we have not enabled more U[S]ARTs than are supported by the + * device. + */ + +#if !defined(CONFIG_STM32H5_HAVE_UART12) +# undef CONFIG_STM32H5_UART12 +#endif +#if !defined(CONFIG_STM32H5_HAVE_USART11) +# undef CONFIG_STM32H5_USART11 +#endif +#if !defined(CONFIG_STM32H5_HAVE_USART10) +# undef CONFIG_STM32H5_USART10 +#endif +#if !defined(CONFIG_STM32H5_HAVE_UART9) +# undef CONFIG_STM32H5_UART9 +#endif +#if !defined(CONFIG_STM32H5_HAVE_UART8) +# undef CONFIG_STM32H5_UART8 +#endif +#if !defined(CONFIG_STM32H5_HAVE_UART7) +# undef CONFIG_STM32H5_UART7 +#endif +#if !defined(CONFIG_STM32H5_HAVE_USART6) +# undef CONFIG_STM32H5_USART6 +#endif +#if !defined(CONFIG_STM32H5_HAVE_UART5) +# undef CONFIG_STM32H5_UART5 +#endif +#if !defined(CONFIG_STM32H5_HAVE_UART4) +# undef CONFIG_STM32H5_UART4 +#endif +#if !defined(CONFIG_STM32H5_HAVE_USART3) +# undef CONFIG_STM32H5_USART3 +#endif +#if !defined(CONFIG_STM32H5_HAVE_USART2) +# undef CONFIG_STM32H5_USART2 +#endif +#if !defined(CONFIG_STM32H5_HAVE_USART1) +# undef CONFIG_STM32H5_USART1 +#endif +#if !defined(CONFIG_STM32H5_HAVE_LPUART1) +# undef CONFIG_STM32H5_LPUART1 +#endif + +/* Sanity checks */ + +#if !defined(CONFIG_STM32H5_LPUART1) +# undef CONFIG_STM32H5_LPUART1_SERIALDRIVER +# undef CONFIG_STM32H5_LPUART1_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_USART1) +# undef CONFIG_STM32H5_USART1_SERIALDRIVER +# undef CONFIG_STM32H5_USART1_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_USART2) +# undef CONFIG_STM32H5_USART2_SERIALDRIVER +# undef CONFIG_STM32H5_USART2_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_USART3) +# undef CONFIG_STM32H5_USART3_SERIALDRIVER +# undef CONFIG_STM32H5_USART3_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_UART4) +# undef CONFIG_STM32H5_UART4_SERIALDRIVER +# undef CONFIG_STM32H5_UART4_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_UART5) +# undef CONFIG_STM32H5_UART5_SERIALDRIVER +# undef CONFIG_STM32H5_UART5_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_USART6) +# undef CONFIG_STM32H5_USART6_SERIALDRIVER +# undef CONFIG_STM32H5_USART6_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_UART7) +# undef CONFIG_STM32H5_UART7_SERIALDRIVER +# undef CONFIG_STM32H5_UART7_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_UART8) +# undef CONFIG_STM32H5_UART8_SERIALDRIVER +# undef CONFIG_STM32H5_UART8_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_UART9) +# undef CONFIG_STM32H5_UART9_SERIALDRIVER +# undef CONFIG_STM32H5_UART9_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_USART10) +# undef CONFIG_STM32H5_USART10_SERIALDRIVER +# undef CONFIG_STM32H5_USART10_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_USART11) +# undef CONFIG_STM32H5_USART11_SERIALDRIVER +# undef CONFIG_STM32H5_USART11_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32H5_UART12) +# undef CONFIG_STM32H5_UART12_SERIALDRIVER +# undef CONFIG_STM32H5_UART12_1WIREDRIVER +#endif + +/* Is there a USART enabled? */ + +#if defined(CONFIG_STM32H5_LPUART1) || defined(CONFIG_STM32H5_USART1) || \ + defined(CONFIG_STM32H5_USART2) || defined(CONFIG_STM32H5_USART3) || \ + defined(CONFIG_STM32H5_UART4) || defined(CONFIG_STM32H5_UART5) || \ + defined(CONFIG_STM32H5_USART6) || defined(CONFIG_STM32H5_UART7) || \ + defined(CONFIG_STM32H5_UART8) || defined(CONFIG_STM32H5_UART9) || \ + defined(CONFIG_STM32H5_USART10) || defined(CONFIG_STM32H5_USART11) || \ + defined(CONFIG_STM32H5_USART12) +# define HAVE_UART 1 +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 1 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART1_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 2 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART2_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 3 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART3_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 4 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART4_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 5 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART5_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 6 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART6_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 7 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART7_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 8 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART8_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 9 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART9_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 10 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART10_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 11 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART11_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_UART12_SERIAL_CONSOLE +# define CONSOLE_UART 12 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART12_SERIALDRIVER) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_UART9_SERIAL_CONSOLE +# undef CONFIG_USART10_SERIAL_CONSOLE +# undef CONFIG_USART11_SERIAL_CONSOLE +# define CONSOLE_UART 13 +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define CONSOLE_UART 0 +# undef HAVE_CONSOLE +#endif + +/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX + * configuration + */ + +#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) +# undef CONFIG_USART1_RXDMA +# undef CONFIG_USART2_RXDMA +# undef CONFIG_USART3_RXDMA +# undef CONFIG_UART4_RXDMA +# undef CONFIG_UART5_RXDMA +# undef CONFIG_USART7_RXDMA +# undef CONFIG_UART7_RXDMA +# undef CONFIG_UART8_RXDMA +# undef CONFIG_UART9_RXDMA +# undef CONFIG_USART10_RXDMA +# undef CONFIG_USART11_RXDMA +# undef CONFIG_UART12_RXDMA +#endif + +/* Disable the DMA configuration on all unused USARTs */ + +#ifndef CONFIG_STM32H5_LPUART1_SERIALDRIVER +# undef CONFIG_LPUART1_RXDMA +#endif + +#ifndef CONFIG_STM32H5_USART1_SERIALDRIVER +# undef CONFIG_USART1_RXDMA +#endif + +#ifndef CONFIG_STM32H5_USART2_SERIALDRIVER +# undef CONFIG_USART2_RXDMA +#endif + +#ifndef CONFIG_STM32H5_USART3_SERIALDRIVER +# undef CONFIG_USART3_RXDMA +#endif + +#ifndef CONFIG_STM32H5_UART4_SERIALDRIVER +# undef CONFIG_UART4_RXDMA +#endif + +#ifndef CONFIG_STM32H5_UART5_SERIALDRIVER +# undef CONFIG_UART5_RXDMA +#endif + +#ifndef CONFIG_STM32H5_USART6_SERIALDRIVER +# undef CONFIG_USART6_RXDMA +#endif + +#ifndef CONFIG_STM32H5_UART7_SERIALDRIVER +# undef CONFIG_UART7_RXDMA +#endif + +#ifndef CONFIG_STM32H5_UART8_SERIALDRIVER +# undef CONFIG_UART8_RXDMA +#endif + +#ifndef CONFIG_STM32H5_UART9_SERIALDRIVER +# undef CONFIG_UART9_RXDMA +#endif + +#ifndef CONFIG_STM32H5_USART10_SERIALDRIVER +# undef CONFIG_USART10_RXDMA +#endif + +#ifndef CONFIG_STM32H5_USART11_SERIALDRIVER +# undef CONFIG_USART11_RXDMA +#endif + +#ifndef CONFIG_STM32H5_UART12_SERIALDRIVER +# undef CONFIG_UART12_RXDMA +#endif + +/* Is DMA available on any (enabled) USART? */ + +#undef SERIAL_HAVE_DMA +#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_USART1_RXDMA) || \ + defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ + defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \ + defined(CONFIG_USART6_RXDMA) || defined(CONFIG_UART7_RXDMA) || \ + defined(CONFIG_UART8_RXDMA) || defined(CONFIG_UART9_RXDMA) || \ + defined(CONFIG_USART10_RXDMA) || defined(CONFIG_USART11_RXDMA) || \ + defined(CONFIG_USART12_RXDMA) +# define SERIAL_HAVE_DMA 1 +#endif + +/* Is DMA used on the console UART? */ + +#undef SERIAL_HAVE_CONSOLE_DMA +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_LPUART1_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_UART9_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_USART10_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_USART11_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_UART12_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#endif + +/* Is DMA used on all (enabled) USARTs */ + +#define SERIAL_HAVE_ONLY_DMA 1 +#if defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32H5_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#endif + +/* Is RS-485 used? */ + +#if defined(CONFIG_LPUART1_RS485) || defined(CONFIG_USART1_RS485) || \ + defined(CONFIG_USART2_RS485) || defined(CONFIG_USART3_RS485) || \ + defined(CONFIG_UART4_RS485) || defined(CONFIG_UART5_RS485) || \ + defined(CONFIG_USART6_RS485) || defined(CONFIG_UART7_RS485) || \ + defined(CONFIG_UART8_RS485) || defined(CONFIG_UART9_RS485) || \ + defined(CONFIG_USART10_RS485) || defined(CONFIG_USART11_RS485) || \ + defined(CONFIG_UART12_RS485) +# define HAVE_RS485 1 +#endif + +#ifdef HAVE_RS485 +# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE) +#else +# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_serial_dma_poll + * + * Description: + * Must be called periodically if any STM32 UART is configured for DMA. + * The DMA callback is triggered for each fifo size/2 bytes, but this can + * result in some bytes being transferred but not collected if the incoming + * data is not a whole multiple of half the FIFO size. + * + * May be safely called from either interrupt or thread context. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_DMA +void stm32h5_serial_dma_poll(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_STC_STM32H5_STM32H5_UART_H */ diff --git a/arch/arm/src/stm32h5/stm32h5_userspace.c b/arch/arm/src/stm32h5/stm32h5_userspace.c new file mode 100644 index 0000000000000..b8eee531c68d9 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_userspace.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/arm/src/stm32l5/stm32l5_userspace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32l5_mpuinit.h" +#include "stm32l5_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l5_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +void stm32l5_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } + + /* Configure the MPU to permit user-space access to its FLASH and RAM */ + + stm32l5_mpuinitialize(); +} + +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32h5/stm32h5_userspace.h b/arch/arm/src/stm32h5/stm32h5_userspace.h new file mode 100644 index 0000000000000..822eae68c3143 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_userspace.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/stm32l5/stm32l5_userspace.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H +#define __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l5_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void stm32l5_userspace(void); +#endif + +#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H */ diff --git a/libs/libc/string/lib_bzero.c b/arch/arm/src/stm32h5/stm32h5_waste.c similarity index 88% rename from libs/libc/string/lib_bzero.c rename to arch/arm/src/stm32h5/stm32h5_waste.c index e73ad4246507f..e1efcf187d062 100644 --- a/libs/libc/string/lib_bzero.c +++ b/arch/arm/src/stm32h5/stm32h5_waste.c @@ -1,7 +1,5 @@ /**************************************************************************** - * libs/libc/string/lib_bzero.c - * - * SPDX-License-Identifier: Apache-2.0 + * arch/arm/src/stm32h5/stm32h5_waste.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -25,18 +23,20 @@ ****************************************************************************/ #include -#include -#include +#include +#include "stm32h5_waste.h" /**************************************************************************** - * Public Functions + * Private Data ****************************************************************************/ +uint32_t idle_wastecounter = 0; + /**************************************************************************** - * Name: bzero + * Public Functions ****************************************************************************/ -void bzero(FAR void *s, size_t n) +void stm32h5_waste(void) { - memset(s, 0, n); + idle_wastecounter++; } diff --git a/arch/arm/src/stm32h5/stm32h5_waste.h b/arch/arm/src/stm32h5/stm32h5_waste.h new file mode 100644 index 0000000000000..b4fc0360adf09 --- /dev/null +++ b/arch/arm/src/stm32h5/stm32h5_waste.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/arm/src/stm32h5/stm32h5_waste.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H5_STM32H5_WASTE_H +#define __ARCH_ARM_SRC_STM32H5_STM32H5_WASTE_H + +/* Waste CPU Time */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* Waste CPU Time + * + * stm32h5_waste() is the logic that will be executed when portions of kernel + * or user-app is polling some register or similar, waiting for desired + * status. This time is wasted away. This function offers a measure of badly + * written piece of software or some undesired behavior. + * + * At the same time this function adds to some IDLE time which portion + * cannot be used for other purposes (yet). + */ + +void stm32h5_waste(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32H5_STM32H5_WASTE_H */ diff --git a/arch/arm64/src/Toolchain.defs b/arch/arm64/src/Toolchain.defs index 1efd0d479c433..ab580d29e0064 100644 --- a/arch/arm64/src/Toolchain.defs +++ b/arch/arm64/src/Toolchain.defs @@ -82,6 +82,14 @@ ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) ARCHOPTIMIZATION += --param asan-globals=1 endif +ifeq ($(CONFIG_MM_KASAN_DISABLE_READS_CHECK),y) + ARCHOPTIMIZATION += --param asan-instrument-reads=0 +endif + +ifeq ($(CONFIG_MM_KASAN_DISABLE_WRITES_CHECK),y) + ARCHOPTIMIZATION += --param asan-instrument-writes=0 +endif + # Instrumentation options ifeq ($(CONFIG_ARCH_INSTRUMENT_ALL),y) @@ -187,6 +195,8 @@ ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y) ifeq ($(shell expr "$(GCCVER)" \>= 12), 1) LDFLAGS += --no-warn-rwx-segments endif + + LDFLAGS += --print-memory-usage endif # Add the builtin library @@ -197,7 +207,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/arm64/src/cmake/Toolchain.cmake b/arch/arm64/src/cmake/Toolchain.cmake index 1e6ab41d030ef..0e900784b79c4 100644 --- a/arch/arm64/src/cmake/Toolchain.cmake +++ b/arch/arm64/src/cmake/Toolchain.cmake @@ -200,4 +200,6 @@ if(CONFIG_ARCH_TOOLCHAIN_GNU) if(GCCVER GREATER_EQUAL 12) add_link_options(-Wl,--no-warn-rwx-segments) endif() + + add_link_options(-Wl,--print-memory-usage) endif() diff --git a/arch/arm64/src/cmake/platform.cmake b/arch/arm64/src/cmake/platform.cmake index 71795cda380e2..130f620fa8bc7 100644 --- a/arch/arm64/src/cmake/platform.cmake +++ b/arch/arm64/src/cmake/platform.cmake @@ -48,7 +48,7 @@ if(NOT CONFIG_LIBM) OUTPUT_VARIABLE extra_library) list(APPEND EXTRA_LIB ${extra_library}) endif() -if(CONFIG_LIBSUPCXX) +if(CONFIG_LIBSUPCXX_TOOLCHAIN) execute_process( COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libsupc++.a diff --git a/arch/arm64/src/common/arm64_cpustart.c b/arch/arm64/src/common/arm64_cpustart.c index 5aeb600944f78..ef8e7a90bb00c 100644 --- a/arch/arm64/src/common/arm64_cpustart.c +++ b/arch/arm64/src/common/arm64_cpustart.c @@ -210,7 +210,7 @@ int up_cpu_start(int cpu) #ifdef CONFIG_ARM64_SMP_BUSY_WAIT uint32_t *address = (uint32_t *)CONFIG_ARM64_SMP_BUSY_WAIT_FLAG_ADDR; *address = 1; - up_flush_dcache((uintptr_t)address, sizeof(address)); + up_flush_dcache((uintptr_t)address, (uintptr_t)address + sizeof(address)); #endif arm64_start_cpu(cpu); diff --git a/arch/arm64/src/common/arm64_perf.c b/arch/arm64/src/common/arm64_perf.c index 3ef47d1e0bf78..ca4a29b349d03 100644 --- a/arch/arm64/src/common/arm64_perf.c +++ b/arch/arm64/src/common/arm64_perf.c @@ -74,7 +74,6 @@ clock_t up_perf_gettime(void) void up_perf_convert(clock_t elapsed, struct timespec *ts) { clock_t left; - unsigned long cpu_freq = read_sysreg(cntfrq_el0); ts->tv_sec = elapsed / g_cpu_freq; left = elapsed - ts->tv_sec * g_cpu_freq; diff --git a/arch/arm64/src/common/arm64_vector_table.S b/arch/arm64/src/common/arm64_vector_table.S index 419b28b47380c..7a64ae45c7db3 100644 --- a/arch/arm64/src/common/arm64_vector_table.S +++ b/arch/arm64/src/common/arm64_vector_table.S @@ -140,12 +140,13 @@ * +------------------+------------------+-------------------------+ */ -GTEXT(_vector_table) +SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table) /* The whole table must be 2K aligned */ .align 11 -SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table) + +GTEXT(_vector_table) /* Current EL with SP0 / Synchronous */ diff --git a/arch/arm64/src/common/arm64_vectors.S b/arch/arm64/src/common/arm64_vectors.S index 667a97fb79804..abb6fb5edca2f 100644 --- a/arch/arm64/src/common/arm64_vectors.S +++ b/arch/arm64/src/common/arm64_vectors.S @@ -141,7 +141,7 @@ SECTION_FUNC(text, arm64_sync_exc) /* if this is a svc call ?*/ - bne arm64_fatal_handler + bne 2f #ifdef CONFIG_LIB_SYSCALL /* Handle user system calls separately */ @@ -189,6 +189,10 @@ reserved_syscall: mov sp, x0 b arm64_exit_exception +2: + adrp x5, arm64_fatal_handler + add x5, x5, #:lo12:arm64_fatal_handler + br x5 /**************************************************************************** * Name: arm64_irq_handler @@ -232,8 +236,10 @@ SECTION_FUNC(text, arm64_irq_handler) GTEXT(arm64_serror_handler) SECTION_FUNC(text, arm64_serror_handler) - mov x0, sp - bl arm64_fatal_handler + mov x0, sp + adrp x5, arm64_fatal_handler + add x5, x5, #:lo12:arm64_fatal_handler + br x5 /* Return here only in case of recoverable error */ b arm64_exit_exception @@ -249,7 +255,9 @@ SECTION_FUNC(text, arm64_serror_handler) GTEXT(arm64_mode32_handler) SECTION_FUNC(text, arm64_mode32_handler) mov x0, sp - bl arm64_fatal_handler + adrp x5, arm64_fatal_handler + add x5, x5, #:lo12:arm64_fatal_handler + br x5 /* Return here only in case of recoverable error */ b arm64_exit_exception @@ -267,7 +275,9 @@ SECTION_FUNC(text, arm64_fiq_handler) #ifndef CONFIG_ARM64_DECODEFIQ mov x0, sp - bl arm64_fatal_handler + adrp x5, arm64_fatal_handler + add x5, x5, #:lo12:arm64_fatal_handler + br x5 /* Return here only in case of recoverable error */ diff --git a/arch/arm64/src/imx9/imx9_lpspi.c b/arch/arm64/src/imx9/imx9_lpspi.c index b373b04c8f213..610276a5f8b21 100644 --- a/arch/arm64/src/imx9/imx9_lpspi.c +++ b/arch/arm64/src/imx9/imx9_lpspi.c @@ -1323,7 +1323,7 @@ static void imx9_lpspi_exchange(struct spi_dev_s *dev, /* Convert the number of word to a number of bytes */ - nbytes = (priv->nbits > 8) ? nwords << 2 : nwords; + nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; /* Invalid DMA channels fall back to non-DMA method. */ @@ -1386,14 +1386,6 @@ static void imx9_lpspi_exchange(struct spi_dev_s *dev, (uintptr_t)priv->txbuf + nbytes); } - if (rxbuffer) - { - /* Prepare the RX buffer for DMA */ - - up_invalidate_dcache((uintptr_t)priv->rxbuf, - (uintptr_t)priv->rxbuf + nbytes); - } - /* Set up the DMA */ adjust = (priv->nbits > 8) ? 2 : 1; @@ -1404,7 +1396,7 @@ static void imx9_lpspi_exchange(struct spi_dev_s *dev, config.daddr = (uintptr_t) (rxbuffer ? priv->rxbuf : rxdummy); config.soff = 0; config.doff = rxbuffer ? adjust : 0; - config.iter = nbytes; + config.iter = nwords; config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; config.ssize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; config.dsize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; @@ -1418,7 +1410,7 @@ static void imx9_lpspi_exchange(struct spi_dev_s *dev, config.daddr = priv->spibase + IMX9_LPSPI_TDR_OFFSET; config.soff = txbuffer ? adjust : 0; config.doff = 0; - config.iter = nbytes; + config.iter = nwords; config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; config.ssize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; config.dsize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; @@ -2079,6 +2071,12 @@ struct spi_dev_s *imx9_lpspibus_initialize(int bus) priv->txbuf = imx9_dma_alloc(CONFIG_IMX9_LPSPI_DMA_BUFFER_SIZE); priv->rxbuf = imx9_dma_alloc(CONFIG_IMX9_LPSPI_DMA_BUFFER_SIZE); DEBUGASSERT(priv->txbuf && priv->rxbuf); + + /* Invalidate the RX buffer area initially */ + + up_invalidate_dcache((uintptr_t)priv->rxbuf, + (uintptr_t)priv->rxbuf + + CONFIG_IMX9_LPSPI_DMA_BUFFER_SIZE); } } else diff --git a/arch/avr/src/avr/Toolchain.defs b/arch/avr/src/avr/Toolchain.defs index 76e236cc3b060..47051a5c197ba 100644 --- a/arch/avr/src/avr/Toolchain.defs +++ b/arch/avr/src/avr/Toolchain.defs @@ -164,7 +164,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/avr/src/avr32/Toolchain.defs b/arch/avr/src/avr32/Toolchain.defs index b2e785ac08d63..68c0f6799f21a 100644 --- a/arch/avr/src/avr32/Toolchain.defs +++ b/arch/avr/src/avr32/Toolchain.defs @@ -94,7 +94,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/hc/src/Makefile b/arch/hc/src/Makefile index cbc12ffd00ae6..907b7bd65a638 100644 --- a/arch/hc/src/Makefile +++ b/arch/hc/src/Makefile @@ -80,7 +80,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a}} endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a}} endif diff --git a/arch/mips/src/mips32/Toolchain.defs b/arch/mips/src/mips32/Toolchain.defs index 819cb1ad1fceb..ff6083a4855ac 100644 --- a/arch/mips/src/mips32/Toolchain.defs +++ b/arch/mips/src/mips32/Toolchain.defs @@ -309,7 +309,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/misoc/src/lm32/Toolchain.defs b/arch/misoc/src/lm32/Toolchain.defs index 01a926d326d32..b10a35e622393 100644 --- a/arch/misoc/src/lm32/Toolchain.defs +++ b/arch/misoc/src/lm32/Toolchain.defs @@ -125,7 +125,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/misoc/src/minerva/Toolchain.defs b/arch/misoc/src/minerva/Toolchain.defs index efbf92a3d91f3..02b471419924d 100644 --- a/arch/misoc/src/minerva/Toolchain.defs +++ b/arch/misoc/src/minerva/Toolchain.defs @@ -73,7 +73,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/or1k/src/mor1kx/Toolchain.defs b/arch/or1k/src/mor1kx/Toolchain.defs index 346c6b7147426..991c2d05b9622 100644 --- a/arch/or1k/src/mor1kx/Toolchain.defs +++ b/arch/or1k/src/mor1kx/Toolchain.defs @@ -111,7 +111,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/renesas/src/Makefile b/arch/renesas/src/Makefile index f2811a63136cc..e66ee275a2557 100644 --- a/arch/renesas/src/Makefile +++ b/arch/renesas/src/Makefile @@ -73,7 +73,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a}} endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a}} endif diff --git a/arch/risc-v/src/cmake/Toolchain.cmake b/arch/risc-v/src/cmake/Toolchain.cmake index b7f6b8805ca84..aecbfcfaf58b3 100644 --- a/arch/risc-v/src/cmake/Toolchain.cmake +++ b/arch/risc-v/src/cmake/Toolchain.cmake @@ -104,6 +104,7 @@ elseif(CONFIG_LTO_FULL) if(CONFIG_ARCH_TOOLCHAIN_GNU) add_compile_options(-fno-builtin) add_compile_options(-fuse-linker-plugin) + add_link_options(-wl,--print-memory-usage) endif() endif() diff --git a/arch/risc-v/src/cmake/platform.cmake b/arch/risc-v/src/cmake/platform.cmake index df38ed77d1e4b..4199655626533 100644 --- a/arch/risc-v/src/cmake/platform.cmake +++ b/arch/risc-v/src/cmake/platform.cmake @@ -52,7 +52,7 @@ if(NOT CONFIG_LIBM) list(APPEND EXTRA_LIB ${extra_library}) endif() -if(CONFIG_LIBSUPCXX) +if(CONFIG_LIBSUPCXX_TOOLCHAIN) execute_process( COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libsupc++.a diff --git a/arch/risc-v/src/common/Toolchain.defs b/arch/risc-v/src/common/Toolchain.defs index ddf814dec3e8a..a99f57e83e068 100644 --- a/arch/risc-v/src/common/Toolchain.defs +++ b/arch/risc-v/src/common/Toolchain.defs @@ -382,6 +382,7 @@ else endif endif + LDFLAGS += --print-memory-usage endif # Add the builtin library @@ -401,7 +402,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/sim/src/cmake/Toolchain.cmake b/arch/sim/src/cmake/Toolchain.cmake index 76be81168d68f..132e7c150465e 100644 --- a/arch/sim/src/cmake/Toolchain.cmake +++ b/arch/sim/src/cmake/Toolchain.cmake @@ -38,16 +38,19 @@ endif() # macOS is built with __APPLE__. We #undef predefined macros for those possible # host OSes here because the OS APIs this library should use are of NuttX, not # the host OS. -add_compile_options( - -U_AIX - -U_WIN32 - -U__APPLE__ - -U__FreeBSD__ - -U__NetBSD__ - -U__linux__ - -U__sun__ - -U__unix__ - -U__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) + +set(SIM_NO_HOST_OPTIONS + -U_AIX + -U_WIN32 + -U__APPLE__ + -U__FreeBSD__ + -U__NetBSD__ + -U__linux__ + -U__sun__ + -U__unix__ + -U__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) + +add_compile_options(${SIM_NO_HOST_OPTIONS}) set(NO_LTO "-fno-lto") diff --git a/arch/sim/src/sim/CMakeLists.txt b/arch/sim/src/sim/CMakeLists.txt index 0607bb8e4d4a5..a6462e1858d5b 100644 --- a/arch/sim/src/sim/CMakeLists.txt +++ b/arch/sim/src/sim/CMakeLists.txt @@ -288,4 +288,14 @@ endforeach() set(HOSTSRCS ${WINHOSTSRCS}) target_sources(nuttx PRIVATE ${HOSTSRCS}) + +get_target_property(HOST_COMPILE_OPTIONS nuttx COMPILE_OPTIONS) +if(HOST_COMPILE_OPTIONS) + foreach(remove_item IN LISTS SIM_NO_HOST_OPTIONS) + list(REMOVE_ITEM HOST_COMPILE_OPTIONS ${remove_item}) + endforeach() + set_target_properties(nuttx PROPERTIES COMPILE_OPTIONS + "${HOST_COMPILE_OPTIONS}") +endif() + target_compile_definitions(nuttx PRIVATE ${HOST_DEFINITIONS}) diff --git a/arch/x86/src/Makefile b/arch/x86/src/Makefile index 1340d16d21e76..e907cdf02205d 100644 --- a/arch/x86/src/Makefile +++ b/arch/x86/src/Makefile @@ -91,7 +91,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a}} endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a}} endif diff --git a/arch/x86_64/src/Makefile b/arch/x86_64/src/Makefile index 6468b4cb0c0e2..ba55db152d70f 100644 --- a/arch/x86_64/src/Makefile +++ b/arch/x86_64/src/Makefile @@ -93,7 +93,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a}} endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a}} endif diff --git a/arch/x86_64/src/cmake/platform.cmake b/arch/x86_64/src/cmake/platform.cmake index 8d2bab0010450..414deb5c328e8 100644 --- a/arch/x86_64/src/cmake/platform.cmake +++ b/arch/x86_64/src/cmake/platform.cmake @@ -52,7 +52,7 @@ if(CONFIG_LIBM_TOOLCHAIN) list(APPEND EXTRA_LIB ${extra_library}) endif() -if(CONFIG_LIBSUPCXX) +if(CONFIG_LIBSUPCXX_TOOLCHAIN) execute_process( COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libsupc++.a diff --git a/arch/x86_64/src/intel64/intel64_handlers.c b/arch/x86_64/src/intel64/intel64_handlers.c index 754b6f4d00f95..c17f8fc8c2871 100644 --- a/arch/x86_64/src/intel64/intel64_handlers.c +++ b/arch/x86_64/src/intel64/intel64_handlers.c @@ -98,6 +98,7 @@ static uint64_t *common_handler(int irq, uint64_t *regs) /* Update scheduler parameters */ + cpu = this_cpu(); nxsched_suspend_scheduler(g_running_tasks[cpu]); nxsched_resume_scheduler(this_task()); @@ -106,7 +107,6 @@ static uint64_t *common_handler(int irq, uint64_t *regs) * crashes. */ - cpu = this_cpu(); tcb = current_task(cpu); g_running_tasks[cpu] = tcb; diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiram.c b/arch/xtensa/src/esp32s3/esp32s3_spiram.c index 2b9d0f01fe983..44b72a027bd47 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiram.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiram.c @@ -149,13 +149,26 @@ extern int cache_invalidate_addr(uint32_t addr, uint32_t size); static inline uint32_t mmu_valid_space(uint32_t *start_address) { - for (int i = 0; i < FLASH_MMU_TABLE_SIZE; i++) + /* Look for an invalid entry for the MMU table from the end of the it + * towards the beginning. This is done to make sure we have a room for + * mapping the the SPIRAM + */ + + for (int i = (FLASH_MMU_TABLE_SIZE - 1); i >= 0; i--) { if (FLASH_MMU_TABLE[i] & MMU_INVALID) { - *start_address = DRAM0_CACHE_ADDRESS_LOW + i * MMU_PAGE_SIZE; - return (FLASH_MMU_TABLE_SIZE - i) * MMU_PAGE_SIZE; + continue; } + + /* Add 1 to i to identify the first MMU table entry not set found + * backwards. + */ + + i++; + + *start_address = DRAM0_CACHE_ADDRESS_LOW + (i) * MMU_PAGE_SIZE; + return (FLASH_MMU_TABLE_SIZE - i) * MMU_PAGE_SIZE; } return 0; diff --git a/arch/xtensa/src/lx6/Toolchain.defs b/arch/xtensa/src/lx6/Toolchain.defs index 37faf063705ed..9f89d1600a1a2 100644 --- a/arch/xtensa/src/lx6/Toolchain.defs +++ b/arch/xtensa/src/lx6/Toolchain.defs @@ -193,7 +193,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/arch/xtensa/src/lx7/Toolchain.defs b/arch/xtensa/src/lx7/Toolchain.defs index 7cf31413af4de..495ece81e7edd 100644 --- a/arch/xtensa/src/lx7/Toolchain.defs +++ b/arch/xtensa/src/lx7/Toolchain.defs @@ -197,7 +197,7 @@ ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif -ifeq ($(CONFIG_LIBSUPCXX),y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) endif diff --git a/boards/Kconfig b/boards/Kconfig index 9a97bc3a5fa03..df01b01dad316 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2795,6 +2795,15 @@ config ARCH_BOARD_STM32L476_MDK The STM32L476ME is a Cortex-M4 optimised for low-power operation at up to 80MHz operation with 1024Kb Flash memory and 96+32Kb SRAM. +config ARCH_BOARD_NUCLEO_H563ZI + bool "NUCLEO_H563ZI" + depends on ARCH_CHIP_STM32H563ZI + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + STMicro Nucleo-H563ZI board based on the STMicro STM32H563ZI MCU. + config ARCH_BOARD_STM32L562E_DK bool "STM32L562E-DK" depends on ARCH_CHIP_STM32L562QE @@ -3512,6 +3521,7 @@ config ARCH_BOARD default "b-l072z-lrwan1" if ARCH_BOARD_B_L072Z_LRWAN1 default "b-l475e-iot01a" if ARCH_BOARD_B_L475E_IOT01A default "b-u585i-iot02a" if ARCH_BOARD_B_U585I_IOT02A + default "nucleo-h563zi" if ARCH_BOARD_NUCLEO_H563ZI default "nucleo-u5a5zj-q" if ARCH_BOARD_NUCLEO_U5A5ZJ_Q default "stm32l476vg-disco" if ARCH_BOARD_STM32L476VG_DISCO default "stm32l476-mdk" if ARCH_BOARD_STM32L476_MDK @@ -4090,6 +4100,9 @@ endif if ARCH_BOARD_STM32L4R9AI_DISCO source "boards/arm/stm32l4/stm32l4r9ai-disco/Kconfig" endif +if ARCH_BOARD_NUCLEO_H563ZI +source "boards/arm/stm32h5/nucleo-h563zi/Kconfig" +endif if ARCH_BOARD_STM32L562E_DK source "boards/arm/stm32l5/stm32l562e-dk/Kconfig" endif diff --git a/boards/arm/mps/mps2-an521/README.txt b/boards/arm/mps/mps2-an521/README.txt deleted file mode 100644 index 311d837a66a6e..0000000000000 --- a/boards/arm/mps/mps2-an521/README.txt +++ /dev/null @@ -1,52 +0,0 @@ -README.txt -========== - -This board configuration will use QEMU to emulate generic ARM v8-M series -hardware platform and provides support for these devices: - - - ARM Generic Timer - - CMSDK UART controller - -Contents -======== - - Getting Started - - Status - - Platform Features - - Debugging with QEMU - - FPU Support and Performance - - SMP Support - - References - -Getting Started -=============== - -1. Configuring and running - 1.1 Single Core - Configuring NuttX and compile: - $ ./tools/configure.sh -l mps2-an521:nsh - $ make - Running with qemu - $ qemu-system-arm -M mps2-an521 -nographic -chardev stdio,id=con,mux=on \ - -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx - - 2.2 Kernel protected mode - TODO - -Debugging with QEMU -=================== - -The nuttx ELF image can be debugged with QEMU. - -1. To debug the nuttx (ELF) with symbols, make sure the following change have - applied to defconfig. - -+CONFIG_DEBUG_SYMBOLS=y - -2. Run QEMU(at shell terminal 1) - - $ qemu-system-arm -M mps2-an521 -nographic -chardev stdio,id=con,mux=on \ - -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx -S -s - -3. Run gdb with TUI, connect to QEMU, load nuttx and continue (at shell terminal 2) - - $ arm-none-eabi-gdb -tui --eval-command='target remote localhost:1234' nuttx diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig new file mode 100644 index 0000000000000..d0ad24b472381 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_WS2812=y +CONFIG_EXAMPLES_WS2812_DEFAULT_DEV="/dev/leddrv0" +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y +CONFIG_WS2812=y +CONFIG_WS2812_FREQUENCY=9000000 +CONFIG_WS2812_LED_COUNT=10 diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c index fb03c70efae7f..96c904e3ad7d0 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c @@ -83,6 +83,10 @@ #include "stm32_lcd_backpack.h" #endif +#ifdef CONFIG_WS2812 +#include "stm32_ws2812.h" +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -328,5 +332,15 @@ int stm32_bringup(void) } #endif +#if defined(CONFIG_WS2812) && defined(CONFIG_WS2812_LED_COUNT) + /* Configure and initialize the WS2812 LEDs. */ + + ret = board_ws2812_initialize(0, WS2812_SPI, CONFIG_WS2812_LED_COUNT); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); + } +#endif + return ret; } diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h b/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h index d123bb0374292..8e55a96154c41 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h @@ -124,6 +124,10 @@ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN5) #endif +/* WS2812 LEDs SPI */ + +#define WS2812_SPI 1 + /* PWM * * The STM32F401RC-RS485 has no real on-board PWM devices, but the board can diff --git a/boards/arm/stm32h5/nucleo-h563zi/Kconfig b/boards/arm/stm32h5/nucleo-h563zi/Kconfig new file mode 100644 index 0000000000000..e9b20410df91b --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NUCLEO_H563ZI + +endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig new file mode 100644 index 0000000000000..1bcf0e50236b6 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h563zi" +CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y +#CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32H563ZI=y +CONFIG_ARCH_CHIP_STM32H5=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV8M_STACKCHECK=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=655360 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_STM32H5_USART3=y +CONFIG_SYSTEM_NSH=y +#CONFIG_SYSTEM_STACKMONITOR=y +#CONFIG_SYSTEM_TEE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h new file mode 100644 index 0000000000000..8eb8ac1a03161 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -0,0 +1,341 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEO-H563ZI-Q supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X3 crystal is not populated. Therefore the + * Nucleo-H563ZI-Q will need to run off the 16MHz HSI clock, or the + * 32kHz-synced CSI. This configuration uses the CSI. + * + * System Clock source : PLL (CSI) + * SYSCLK(Hz) : 250000000 Determined by PLL1 configuration + * HCLK(Hz) : 250000000 (STM32H5_RCC_CFGR_HPRE) (Max 250MHz) + * AHB Prescaler : 1 (STM32H5_RCC_CFGR_HPRE) (Max 250MHz) + * APB1 Prescaler : 1 (STM32H5_RCC_CFGR_PPRE1) (Max 250MHz) + * APB2 Prescaler : 1 (STM32H5_RCC_CFGR_PPRE2) (Max 250MHz) + * CSI Frequency(Hz) : 4000000 (nominal) + * PLL1M : 2 (STM32H5_PLL1CFGR_PLLM) + * PLL1N : 125 (STM32H5_PLL1CFGR_PLLN) + * PLL1P : 0 (STM32H5_PLL1CFGR_PLLP) + * PLL1Q : 0 (STM32H5_PLL1CFGR_PLLQ) + * PLL1R : 1 (STM32H5_PLL1CFGR_PLLR) + * PLL2M : 2 (STM32H5_PLL2CFGR_PLLM) + * PLL2N : 125 (STM32H5_PLL2CFGR_PLLN) + * PLL2P : 0 (STM32H5_PLL2CFGR_PLLP) + * PLL2Q : 0 (STM32H5_PLL2CFGR_PLLQ) + * PLL2R : 1 (STM32H5_PLL2CFGR_PLLR) + * PLL3M : 2 (STM32H5_PLL3CFGR_PLLM) + * PLL3N : 125 (STM32H5_PLL3CFGR_PLLN) + * PLL3P : 0 (STM32H5_PLL3CFGR_PLLP) + * PLL3Q : 0 (STM32H5_PLL3CFGR_PLLQ) + * PLL3R : 1 (STM32H5_PLL3CFGR_PLLR) + * Flash Latency(WS) : 5 + */ + +/* HSI - 32 MHz RC factory-trimmed + * LSI - 32 KHz RC + * CSI - 4 MHz, autotrimmed via LSE + * HSE - not installed + * LSE - 32.768 kHz installed + * SYSCLK = 250 MHz + */ + +#define STM32H5_SYSCLK_FREQUENCY 250000000ul +#define STM32H5_HSI_FREQUENCY 32000000ul +#define STM32H5_LSI_FREQUENCY 32000 +#define STM32H5_LSE_FREQUENCY 32768 + +#define STM32H5_BOARD_USEHSI 1 +#define STM32H5_CR_HSIDIV RCC_CR_HSIDIV(1) + +/* prescaler common to all PLL inputs */ + +/* 'main' PLL1 config; we use this to generate our system clock */ + +/* Use 32 MHz HSI, set M to 2, N to 15, FRAC to 0x1400 (5120) + * SYSCLK = (32000000 / 2) * (15 + (5120/8192)) = 250000000 + */ + +#define STM32H5_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN +#define STM32H5_PLL1CFGR_PLL1VCOSEL 0 +#define STM32H5_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_8_16M + +#define STM32H5_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M(2) +#define STM32H5_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N(15) + +#define STM32H5_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P(1) +#define STM32H5_PLL1CFGR_PLL1P_ENABLED 1 +#define STM32H5_PLL1DIVR_PLL1Q 0 +#undef STM32H5_PLL1CFGR_PLL1Q_ENABLED +#define STM32H5_PLL1DIVR_PLL1R 0 +#undef STM32H5_PLL1CFGR_PLL1R_ENABLED + +#define STM32H5_PLL1FRACR_PLL1FRACN 5120ul + +/* PLL2 config */ + +#define STM32H5_PLL2CFGR_PLL2M RCC_PLL2CFGR_PLL2M(4) +#define STM32H5_PLL2CFGR_PLL2FRACEN RCC_PLL2CFGR_PLL2FRACEN +#define STM32H5_PLL2CFGR_PLL2VCOSEL RCC_PLL2CFGR_PLL2VCOSEL +#define STM32H5_PLL2CFGR_PLL2RGE RCC_PLL2CFGR_PLL2RGE_8_16M + +#define STM32H5_PLL2DIVR_PLL2N RCC_PLL2DIVR_PLL2N(15) + +#define STM32H5_PLL2DIVR_PLL2P RCC_PLL2DIVR_PLL2P(1) +#define STM32H5_PLL2CFGR_PLL2P_ENABLED +#define STM32H5_PLL2DIVR_PLL2Q 0 +#undef STM32H5_PLL2CFGR_PLL2Q_ENABLED +#define STM32H5_PLL2DIVR_PLL2R 0 +#undef STM32H5_PLL2CFGR_PLL2R_ENABLED + +#define STM32H5_PLL2FRACR_PLL2FRACN 5120ul + +/* PLL3 config */ + +#define STM32H5_PLL3CFGR_PLL3M RCC_PLL3CFGR_PLL3M(4) +#define STM32H5_PLL3CFGR_PLL3FRACEN RCC_PLL3CFGR_PLL3FRACEN +#define STM32H5_PLL3CFGR_PLL3VCOSEL RCC_PLL3CFGR_PLL3VCOSEL +#define STM32H5_PLL3CFGR_PLL3RGE RCC_PLL3CFGR_PLL3RGE_8_16M + +#define STM32H5_PLL3DIVR_PLL3N RCC_PLL3DIVR_PLL3N(15) + +#define STM32H5_PLL3DIVR_PLL3P RCC_PLL3DIVR_PLL3P(1) +#define STM32H5_PLL3CFGR_PLL3P_ENABLED +#define STM32H5_PLL3DIVR_PLL3Q 0 +#undef STM32H5_PLL3CFGR_PLL3Q_ENABLED +#define STM32H5_PLL3DIVR_PLL3R 0 +#undef STM32H5_PLL3CFGR_PLL3R_ENABLED + +#define STM32H5_PLL3FRACR_PLL3FRACN 5120ul + + +/* Enable CLK48; get it from HSI48 */ + +#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG) +# define STM32H5_USE_CLK48 1 +# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK +# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE +#endif + +/* Enable LSE (for the RTC) */ + +#define STM32H5_USE_LSE 1 + +/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ + +#define STM32H5_RCC_CFGR2_HPRE RCC_CFGR2_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32H5_HCLK_FREQUENCY STM32H5_SYSCLK_FREQUENCY + +/* Configure the APB1 prescaler */ + +#define STM32H5_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK1 /* PCLK1 = HCLK / 1 */ +#define STM32H5_PCLK1_FREQUENCY (STM32H5_HCLK_FREQUENCY / 1) + +#define STM32H5_APB1_TIM2_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_TIM3_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_TIM4_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_TIM5_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_TIM6_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_TIM7_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_TIM12_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_TIM13_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_TIM14_CLKIN (STM32H5_PCLK1_FREQUENCY) +#define STM32H5_APB1_LPTIM2_CLKIN (STM32H5_PCLK1_FREQUENCY) + +/* Configure the APB2 prescaler */ + +#define STM32H5_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK1 /* PCLK2 = HCLK / 1 */ +#define STM32H5_PCLK2_FREQUENCY (STM32H5_HCLK_FREQUENCY / 1) + +#define STM32H5_APB2_TIM1_CLKIN (STM32H5_PCLK2_FREQUENCY) +#define STM32H5_APB2_TIM8_CLKIN (STM32H5_PCLK2_FREQUENCY) +#define STM32H5_APB2_TIM15_CLKIN (STM32H5_PCLK2_FREQUENCY) +#define STM32H5_APB2_TIM16_CLKIN (STM32H5_PCLK2_FREQUENCY) +#define STM32H5_APB2_TIM17_CLKIN (STM32H5_PCLK2_FREQUENCY) + +/* Configure the APB3 prescaler */ + +#define STM32H5_RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_HCLK1 /* PCLK2 = HCLK / 1 */ +#define STM32H5_PCLK3_FREQUENCY (STM32H5_HCLK_FREQUENCY / 1) + +#define STM32H5_APB3_LPTIM1_CLKIN (STM32H5_PCLK3_FREQUENCY) +#define STM32H5_APB3_LPTIM3_CLKIN (STM32H5_PCLK3_FREQUENCY) +#define STM32H5_APB3_LPTIM4_CLKIN (STM32H5_PCLK3_FREQUENCY) +#define STM32H5_APB3_LPTIM5_CLKIN (STM32H5_PCLK3_FREQUENCY) +#define STM32H5_APB3_LPTIM6_CLKIN (STM32H5_PCLK3_FREQUENCY) +/* The timer clock frequencies are automatically defined by hardware. If the + * APB prescaler equals 1, the timer clock frequencies are set to the same + * frequency as that of the APB domain. Otherwise they are set to twice. + */ + +#define BOARD_TIM1_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM12_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM13_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM14_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_LPTIM3_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_LPTIM4_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_LPTIM5_FREQUENCY STM32H5_HCLK_FREQUENCY +#define BOARD_LPTIM6_FREQUENCY STM32H5_HCLK_FREQUENCY + +/* Configure the Kernel clocks */ + + +/* DMA Channel/Stream Selections ********************************************/ + +/* Alternate function pin selections ****************************************/ + +/* USART3: Connected to Arduino connector D0/D1 (or to STLink VCP if solder + * bridges SB123 to SB130 are re-worked accordingly). + */ + +#define GPIO_USART3_RX GPIO_USART3_RX_4 /* PD9 */ +#define GPIO_USART3_TX GPIO_USART3_TX_4 /* PD8 */ + +/* LED definitions **********************************************************/ + +/* The Nucleo board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Yellow LED, and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_YELLOW BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS- + * related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ ---- + */ +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If the Red LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* Button definitions *******************************************************/ + +/* The Nucleo-H563ZI supports one button: Pushbutton B1, labeled "User", is + * connected to GPIO PC13. + * A high value will be sensed when the button is pressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_board_initialize + * + * Description: + * All STM32H5 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices + * have been initialized. + * + ****************************************************************************/ + +void stm32h5_board_initialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs b/boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs new file mode 100644 index 0000000000000..e4bb4ef55fcd1 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs @@ -0,0 +1,38 @@ +############################################################################## +# boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv8-m/Toolchain.defs + +ARCHSCRIPT = $(BOARD_DIR)$(DELIM)scripts$(DELIM)flash.ld + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32h5/nucleo-h563zi/scripts/flash.ld b/boards/arm/stm32h5/nucleo-h563zi/scripts/flash.ld new file mode 100644 index 0000000000000..f5e49a0de3a6d --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/scripts/flash.ld @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/flash.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32H562/563/573 has 1 MiB of FLASH beginning at address 0x0800:0000 and + * 256 KiB of SRAM beginning at address 0x2000:0000. When booting from + * FLASH, FLASH memory is aliased to address 0x0000:0000 where the code + * expects to begin execution by jumping to the entry point in the + * 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld b/boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld new file mode 100644 index 0000000000000..ae910e64805ac --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This linker script supports running NuttX in the 'Non-Secure' (ns) domain + * in conjunction with TrustedFirmware-M (tfm). + * + * NuttX will run as the 'Non secure application' in the 'Non-Secure Image + * primary primary slot Area 1' in external flash. Compare [UM2671], + * Figure 8. Furthermore, see Figure 15 for the SRAM area used for 'Non- + * Secure application volatile data' + * + * While the 'Non-Secure Image primary slot Area 1' is actually one MiB large + * in the referenced setup, the image will be enriched with a header of 0x400 + * bytes and a trailer of 0x2000 bytes. Thus the 'flash' statement in the + * MEMORY definition below. + * + * References + * [UM2671] STMicroelectronics. UM2671: Getting started with STM32CubeL5 TFM + * application, 2nd edition, July 2020 + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x90000400, LENGTH = 0xFDC00 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 192K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/.gitignore b/boards/arm/stm32h5/nucleo-h563zi/src/.gitignore new file mode 100644 index 0000000000000..726d936e1e339 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile new file mode 100644 index 0000000000000..27f58d4ceedf5 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile @@ -0,0 +1,40 @@ +############################################################################## +# boards/arm/stm32h5/nucleo-h563zi/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c stm32_clockconfig.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h new file mode 100644 index 0000000000000..eb941e582b042 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H +#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "stm32h5_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PROC 1 +#define HAVE_RTC_DRIVER 1 + +#if !defined(CONFIG_FS_PROCFS) +# undef HAVE_PROC +#endif + +#if defined(HAVE_PROC) && defined(CONFIG_DISABLE_MOUNTPOINT) +# warning Mountpoints disabled. No procfs support +# undef HAVE_PROC +#endif + +/* Check if we can support the RTC driver */ + +#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) +# undef HAVE_RTC_DRIVER +#endif + +/* NUCLEO-H563ZI GPIOs ******************************************************/ + +/* LED I/O Color + * LD9 PD3 Red + * LD10 PG12 Green + * + * - When the I/O is LOW, the LED is on. + * - When the I/O is HIGH value, the LED is off + */ + +#define GPIO_LD9 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHZ | \ + GPIO_OUTPUT_SET | GPIO_PORTD | GPIO_PIN3) +#define GPIO_LD10 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHZ | \ + GPIO_OUTPUT_SET | GPIO_PORTG | GPIO_PIN12) + +/* Button definitions *******************************************************/ + +/* B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define MIN_IRQBUTTON BUTTON_USER +#define MAX_IRQBUTTON BUTTON_USER +#define NUM_IRQBUTTONS 1 + +#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ + GPIO_PORTC | GPIO_PIN13) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c new file mode 100644 index 0000000000000..af1977d125263 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nucleo-h563zi.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + /* Did we already initialize via board_late_initialize()? */ + +#ifndef CONFIG_BOARD_LATE_INITIALIZE + return stm32_bringup(); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c new file mode 100644 index 0000000000000..f6931d3ec7c44 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32h5_gpio.h" +#include "nucleo-h563zi.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LD10, + GPIO_LD9, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active Low */ + + stm32h5_gpiowrite(g_ledmap[led], !state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD9 and LD10 GPIOs for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32h5_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_IDLE: + phy_set_led(BOARD_LED_GREEN, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_IDLE: + phy_set_led(BOARD_LED_GREEN, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c new file mode 100644 index 0000000000000..9c27ed0dc72d4 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" +#include "nucleo-h563zi.h" +#include "stm32h5_pwr.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32h5_board_initialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32h5_board_initialize(void) +{ + /* On the NUCLEO-H563ZI Vddio2 is supplied by Vdd_mcu. Thus, when the MCU + * is running Vddio2 is guaranteed to be valid. LED LD10 is driven by + * PG12, whose power is supplied by Vddio2. Thus, its important to report + * Vddio2 to be valid here. + */ + +/* stm32h5_pwr_vddio2_valid(true); */ + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c new file mode 100644 index 0000000000000..37fbc400cb1ca --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "nucleo-h563zi.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + iinfo("Initializing button driver\n"); + + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif +#endif /* CONFIG_INPUT_BUTTONS */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c new file mode 100644 index 0000000000000..865b78a42b049 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32h5_gpio.h" +#include "nucleo-h563zi.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32h5_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. */ + + return stm32h5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32h5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c new file mode 100644 index 0000000000000..3546e849c247c --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c @@ -0,0 +1,48 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_board_clockconfig + * + * Description: + * Currently the NUCLEO-H563ZI board support is restricted to running NuttX + * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this + * setup the clock configuration is done by TFM, not by NuttX. Thus, the + * board's configuration sets CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG + * to avoid the standard clock config logic to run and instead do just + * nothing in this function. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +void stm32h5_board_clockconfig(void) +{ +} +#endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c new file mode 100644 index 0000000000000..4d333261f1274 --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32h5_gpio.h" +#include "nucleo-h563zi.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LD10, + GPIO_LD9, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LEDs from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-2 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32h5_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LEDs from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32h5_gpiowrite(g_ledcfg[led], !ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-2 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32h5_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig b/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig index 2aa238cb9025a..dd53a940a3097 100644 --- a/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig +++ b/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig @@ -14,6 +14,8 @@ CONFIG_ARCH_CHIP_FVP_ARMV8R=y CONFIG_ARCH_CHIP_FVP_R82=y CONFIG_ARCH_EARLY_PRINT=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARM64_SMP_BUSY_WAIT=y +CONFIG_ARM64_SMP_BUSY_WAIT_FLAG_ADDR=0x60000 CONFIG_ARM64_STRING_FUNCTION=y CONFIG_BUILTIN=y CONFIG_DEBUG_ASSERTIONS=y diff --git a/boards/arm64/fvp-v8r/fvp-armv8r/scripts/dramboot.ld b/boards/arm64/fvp-v8r/fvp-armv8r/scripts/dramboot.ld index 5153f3fb55ae7..f65db05a23751 100644 --- a/boards/arm64/fvp-v8r/fvp-armv8r/scripts/dramboot.ld +++ b/boards/arm64/fvp-v8r/fvp-armv8r/scripts/dramboot.ld @@ -18,6 +18,8 @@ * ****************************************************************************/ +#include + OUTPUT_ARCH(aarch64) ENTRY(__start) @@ -93,6 +95,10 @@ SECTIONS } :text _edata = .; /* End+1 of .data */ +#if defined(CONFIG_SMP) && defined(CONFIG_ARM64_SMP_BUSY_WAIT) + . = CONFIG_ARM64_SMP_BUSY_WAIT_FLAG_ADDR + 4; +#endif + .bss : { /* BSS */ . = ALIGN(8); _sbss = .; diff --git a/boards/arm64/imx9/imx93-evk/configs/bootloader/defconfig b/boards/arm64/imx9/imx93-evk/configs/bootloader/defconfig index 95ff53b67c8c2..9bf2d92f7bd15 100644 --- a/boards/arm64/imx9/imx93-evk/configs/bootloader/defconfig +++ b/boards/arm64/imx9/imx93-evk/configs/bootloader/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_CHIP_IMX93=y CONFIG_ARCH_CHIP_IMX9=y CONFIG_ARCH_INTERRUPTSTACK=4096 CONFIG_ARM64_DCACHE_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=241712 CONFIG_BUILTIN=y CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_FEATURES=y diff --git a/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig b/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig index 802d3af9724b2..8bf20e7e9e021 100644 --- a/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig +++ b/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_CHIP_IMX93=y CONFIG_ARCH_CHIP_IMX9=y CONFIG_ARCH_EARLY_PRINT=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_BOARD_LOOPSPERMSEC=241712 CONFIG_BUILTIN=y CONFIG_CDCACM=y CONFIG_DEBUG_ASSERTIONS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/elf/defconfig b/boards/risc-v/bl602/bl602evb/configs/elf/defconfig index 099ef3edac09c..f88350292f096 100644 --- a/boards/risc-v/bl602/bl602evb/configs/elf/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/elf/defconfig @@ -57,6 +57,7 @@ CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INIT_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y CONFIG_LIBC_LOCALE=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c index 33c8a5d4505a0..6ab7c136f9d93 100644 --- a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c @@ -25,8 +25,6 @@ #include #include -#include "riscv_internal.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c index ccf2a843978f3..4605b870c7642 100644 --- a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c @@ -24,8 +24,6 @@ #include -#include "riscv_internal.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_boot.c b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_boot.c index c133d101a31ea..1be97a68192d2 100644 --- a/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_boot.c +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_boot.c @@ -24,8 +24,6 @@ #include -#include "riscv_internal.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_boot.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_boot.c index 60d4022f4e7a5..0d4b0287da435 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_boot.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_boot.c @@ -24,7 +24,6 @@ #include -#include "riscv_internal.h" #include "esp32c6-devkitc.h" /**************************************************************************** diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_boot.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_boot.c index da643c634c7db..d4071137fe68f 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_boot.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_boot.c @@ -24,7 +24,6 @@ #include -#include "riscv_internal.h" #include "esp32c6-devkitm.h" /**************************************************************************** diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_boot.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_boot.c index fa1c5bae28216..d0cf03142cf22 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_boot.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_boot.c @@ -24,8 +24,6 @@ #include -#include "riscv_internal.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/boards/risc-v/hpm6000/hpm6360evk/README.txt b/boards/risc-v/hpm6000/hpm6360evk/README.txt deleted file mode 100644 index 7ef9d1b9e8de6..0000000000000 --- a/boards/risc-v/hpm6000/hpm6360evk/README.txt +++ /dev/null @@ -1,42 +0,0 @@ -1. Download and install toolchain - - $ curl https://github.com/hpmicro/riscv-gnu-toolchain/releases/tag/2022.05.15 - -2. Download and install openocd - - Download hpmicro sdk_env, openocd in the path: sdk_env/tools/openocd - -3. Configure and build NuttX - - $ mkdir ./nuttxspace - $ cd ./nuttxspace - $ git clone https://github.com/apache/nuttx.git nuttx - $ git clone https://github.com/apache/nuttx-apps.git apps - $ cd nuttx - $ make distclean - $ ./tools/configure.sh hpm6750evk2:nsh - $ make menuconfig - $ make V=1 - - Note: make menuconfig to config toolchain - ================== - To switch GNU riscv64 toolchain to GNU riscv32 toolchain, the following option must be selected: - - System Type ---> - Toolchain Selection ---> - [ ] Generic GNU RV64 toolchain - [x] Generic GNU RV32 toolchain - - Make sure HPMicro GNU riscv32 toolchain have been installed and be found in PATH. - -4. Debug the nuttx with openocd and run - - $ picocom -b 115200 /dev/ttyACM0 - - When using fireDAP, command as follows. Those cfg files in the path: sdk_env/hpm_sdk/boards/openocd. - $ openocd -f probes/cmsis_dap.cfg -f soc/hpm6750-single-core.cfg -f boards/hpm6750evk2.cfg - - $ riscv32-unknown-elf-gdb ./nuttx - (gdb) target extended-remote [ip_addr]:3333 - (gdb) load - (gdb) c diff --git a/boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c b/boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c index 786a08d771551..e94fde9005dba 100644 --- a/boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c +++ b/boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c @@ -40,7 +40,6 @@ #include "qemu_rv_memorymap.h" #include "qemu_rv_rptun.h" -#include "riscv_internal.h" #include "riscv_sbi.h" #include "romfs.h" diff --git a/boards/sim/sim/sim/configs/citest/defconfig b/boards/sim/sim/sim/configs/citest/defconfig index d3041e790ed51..c76baa64eb56f 100644 --- a/boards/sim/sim/sim/configs/citest/defconfig +++ b/boards/sim/sim/sim/configs/citest/defconfig @@ -14,7 +14,6 @@ CONFIG_ARCH="sim" CONFIG_ARCH_BOARD="sim" CONFIG_ARCH_BOARD_SIM=y CONFIG_ARCH_CHIP="sim" -CONFIG_ARCH_MATH_H=y CONFIG_ARCH_SIM=y CONFIG_BOARDCTL_APP_SYMTAB=y CONFIG_BOARDCTL_POWEROFF=y @@ -83,6 +82,7 @@ CONFIG_LIBC_MEMFD_ERROR=y CONFIG_LIBC_NETDB=y CONFIG_LIBC_NUMBERED_ARGS=y CONFIG_LIBC_SCANSET=y +CONFIG_LIBM=y CONFIG_LIBUV=y CONFIG_LIBUV_THREADPOOL_SIZE=4 CONFIG_LIBUV_THREAD_STACKSIZE=16384 diff --git a/boards/sim/sim/sim/scripts/Make.defs b/boards/sim/sim/sim/scripts/Make.defs index 399facc8df446..3fa82008769f4 100644 --- a/boards/sim/sim/sim/scripts/Make.defs +++ b/boards/sim/sim/sim/scripts/Make.defs @@ -142,6 +142,9 @@ endif ifeq ($(CONFIG_SIM_M32),y) ARCHCFLAGS += -m32 ARCHCXXFLAGS += -m32 +else + ARCHCFLAGS += -fno-pic -mcmodel=medium + ARCHCXXFLAGS += -fno-pic -mcmodel=medium endif # LLVM style architecture flags @@ -287,9 +290,9 @@ ifeq ($(CONFIG_HOST_MACOS),y) else LDFLAGS += -Wl,--gc-sections - # Let the symbol table link from 0x400000 + # Let the symbol table link from 0x50000000 # which is more convenient for debugging. - LDFLAGS += -Wl,-Ttext-segment=0x400000 + LDFLAGS += -Wl,-Ttext-segment=0x50000000 endif ifeq ($(CONFIG_DEBUG_LINK_MAP),y) diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig index 081899e81cfe1..ac628ab1b291c 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig @@ -29,6 +29,7 @@ CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y CONFIG_LIBC_LOCALE=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBM=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/cxx/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/cxx/defconfig index c08e834e6ef2d..091ca51f0201c 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/cxx/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/cxx/defconfig @@ -29,6 +29,7 @@ CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y CONFIG_LIBC_LOCALE=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBM=y diff --git a/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld b/boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld similarity index 87% rename from boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld rename to boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld index cdae1e4e5f2ee..2c336a4adad58 100644 --- a/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld +++ b/boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld + * boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -28,9 +28,42 @@ _diram_i_start = 0x40378000; SECTIONS { +#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT + .metadata : + { + /* Magic for load header */ + + LONG(0xace637d3) + + /* Application entry point address */ + + KEEP(*(.entry_addr)) + + /* IRAM metadata: + * - Destination address (VMA) for IRAM region + * - Flash offset (LMA) for start of IRAM region + * - Size of IRAM region + */ + + LONG(ADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) + + /* DRAM metadata: + * - Destination address (VMA) for DRAM region + * - Flash offset (LMA) for start of DRAM region + * - Size of DRAM region + */ + + LONG(ADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data)) + LONG(SIZEOF(.dram0.data)) + } >metadata +#endif /* CONFIG_ESP32S3_APP_FORMAT_MCUBOOT */ + /* Send .iram0 code to iram */ - .iram0.vectors : + .iram0.vectors : ALIGN(4) { _iram_start = ABSOLUTE(.); @@ -71,13 +104,13 @@ SECTIONS _init_end = ABSOLUTE(.); } >iram0_0_seg AT>ROM - .iram0.text : + .iram0.text : ALIGN(4) { /* Code marked as running out of IRAM */ *(.iram1 .iram1.*) esp32s3_start.*(.literal .text .literal.* .text.*) - esp32s3_region.*(.text .text.* .literal .literal.*) + esp32s3_region.*(.literal .text .literal.* .text.*) *libarch.a:*esp_loader.*(.literal .text .literal.* .text.*) *libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*) @@ -214,7 +247,39 @@ SECTIONS . = ALIGN(4) + 16; _iram_text = ABSOLUTE(.); - } >iram0_0_seg AT > ROM + } >iram0_0_seg + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and + * 256B alignment for PMS split lines. + */ + + . += 16; + . = ALIGN(256); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(4); + + *(.iram.data) + *(.iram.data.*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(4); + + *(.iram.bss) + *(.iram.bss.*) + + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg .dram0.dummy (NOLOAD) : { @@ -267,9 +332,10 @@ SECTIONS . = ALIGN(4); } >dram0_0_seg - .dram0.data : + .dram0.data : ALIGN(4) { /* .data initialized on power-up in ROMed configurations. */ + . = ALIGN (16); _data_start = ABSOLUTE(.); _sdata = ABSOLUTE(.); @@ -388,16 +454,22 @@ SECTIONS . = ALIGN(0x10000); } > ROM - .flash.rodata : + .flash.rodata : ALIGN(0x10000) { _rodata_reserved_start = ABSOLUTE(.); _srodata = ABSOLUTE(.); - *(EXCLUDE_FILE (esp32s3_start.*) .rodata) - *(EXCLUDE_FILE (esp32s3_start.*) .rodata.*) + *(EXCLUDE_FILE (esp32s3_start.* esp32s3_region.* + *libarch.a:*esp_loader.* + *libarch.a:esp32s3_spiflash.* + *libarch.a:*cache_hal.* *libarch.a:*mmu_hal.* + *libarch.a:*mpu_hal.*) .rodata) + *(EXCLUDE_FILE (esp32s3_start.* esp32s3_region.* + *libarch.a:*esp_loader.* + *libarch.a:esp32s3_spiflash.* + *libarch.a:*cache_hal.* *libarch.a:*mmu_hal.* + *libarch.a:*mpu_hal.*) .rodata.*) - *(.rodata) - *(.rodata.*) #ifdef CONFIG_ESP32S3_WIRELESS *(.rodata_wlog_verbose.*) *(.rodata_wlog_debug.*) @@ -450,31 +522,37 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - } >drom0_0_seg AT>ROM - - .flash.rodata_noload (NOLOAD) : - { - /* - This is a symbol marking the flash.rodata end, this can be - used for mmu driver to maintain virtual address - We don't need to include the noload rodata in this section - */ _rodata_reserved_end = ABSOLUTE(.); - . = ALIGN (4); - mapping[rodata_noload] - } >drom0_0_seg + } >drom0_0_seg AT>ROM _image_irom_vma = ADDR(.flash.text); _image_irom_lma = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma; - .flash.text_dummy (NOLOAD) : + /* The alignment of the ".flash.text" output section is forced to + * 0x00010000 (64KB) to ensure that it will be allocated at the beginning + * of the next available Flash block. + * This is required to meet the following constraint from the external + * flash MMU: + * VMA % 64KB == LMA % 64KB + * i.e. the lower 16 bits of both the virtual address (address seen by the + * CPU) and the load address (physical address of the external flash) must + * be equal. + */ + +#ifndef CONFIG_ESP32S3_RUN_IRAM + .flash.text_dummy (NOLOAD) : ALIGN(0x10000) { - . += SIZEOF(.flash.rodata); - . = ALIGN(0x10000); - } >default_code_seg AT> ROM + /* This section is required to skip .flash.rodata area because irom0_0_seg + * and drom0_0_seg reflect the same address space on different buses. + */ + + . += _image_drom_lma; + . += _image_drom_size; + } >irom0_0_seg +#endif - .flash.text : + .flash.text : ALIGN(0x00010000) { _stext = .; _instruction_reserved_start = ABSOLUTE(.); @@ -504,62 +582,44 @@ SECTIONS _etext = .; } >irom0_0_seg AT>ROM - /* Marks the end of IRAM code segment */ - - .iram0.text_end (NOLOAD) : - { - /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and - * 256B alignment for PMS split lines. - */ - - . += 16; - . = ALIGN(256); - _iram_end = ABSOLUTE(.); - } >iram0_0_seg - - .iram0.data : - { - . = ALIGN(4); - - *(.iram.data) - *(.iram.data.*) - } >iram0_0_seg - - .iram0.bss (NOLOAD) : - { - . = ALIGN(4); - - *(.iram.bss) - *(.iram.bss.*) - - . = ALIGN(4); - _iram_end = ABSOLUTE(.); - } >iram0_0_seg - .rtc.text : { . = ALIGN(4); *(.rtc.literal .rtc.text) } >rtc_iram_seg AT>ROM + .rtc.dummy (NOLOAD) : + { + /* This section is required to skip .rtc.text area because the text and + * data segments reflect the same address space on different buses. + */ + + . = SIZEOF(.rtc.text); + } >rtc_data_seg + /* RTC BSS section. */ .rtc.bss (NOLOAD) : { *(.rtc.bss) - } >rtc_slow_seg + } >rtc_data_seg .rtc.data : { - . = ALIGN(4); *(.rtc.data) *(.rtc.data.*) *(.rtc.rodata) *(.rtc.rodata.*) - /* Whatever is left from the RTC memory is used as a special heap. */ + /* Whatever is left from the RTC memory is used as a special heap. */ . = ALIGN (4); + } >rtc_data_seg AT>ROM + + .rtc.heap : ALIGN(4) + { + /* RTC heap is placed at the slow RTC memory. */ + _srtcheap = ABSOLUTE(.); } >rtc_slow_seg diff --git a/boards/xtensa/esp32s3/common/scripts/flat_memory.ld b/boards/xtensa/esp32s3/common/scripts/flat_memory.ld index 84a84d0e9c146..f576d0cc24b9c 100644 --- a/boards/xtensa/esp32s3/common/scripts/flat_memory.ld +++ b/boards/xtensa/esp32s3/common/scripts/flat_memory.ld @@ -194,4 +194,4 @@ MEMORY /* Mark the end of the RTC heap (top of the RTC region) */ -_ertcheap = 0x50001fff; +_ertcheap = ORIGIN(rtc_slow_seg) + LENGTH(rtc_slow_seg); diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/nsh/defconfig index 2cdf33335f589..2ab4c7fe77085 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/nsh/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/touchscreen/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/touchscreen/defconfig index 4850c03b623e3..e604cd6ed66b9 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/touchscreen/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/touchscreen/defconfig @@ -31,6 +31,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs index 2330231a3631b..2c6b757377054 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs @@ -34,10 +34,8 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + ifneq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) + ARCHSCRIPT += $(call FINDSCRIPT,esp32s3_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig index 1ccfde4249b6a..91b060fa09ceb 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig @@ -34,6 +34,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/audio/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/audio/defconfig index 59efb86383c70..45083f3a81d0a 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/audio/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/audio/defconfig @@ -53,6 +53,7 @@ CONFIG_FS_PROCFS=y CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=124 CONFIG_IOB_THROTTLE=24 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/capture/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/capture/defconfig index 2391bdab7265d..6764d2ef226de 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/capture/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/capture/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/cxx/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/cxx/defconfig index cf1d592057cea..1ce9a56b6ae98 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/cxx/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/cxx/defconfig @@ -29,8 +29,10 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y CONFIG_LIBC_LOCALE=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBM=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/elf/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/elf/defconfig index ed92c2a68d2ce..8d64e17180ffb 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/elf/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/elf/defconfig @@ -35,6 +35,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/gpio/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/gpio/defconfig index ae1c18744b84c..6bd0929405b3d 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/gpio/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/gpio/defconfig @@ -31,6 +31,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2c/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2c/defconfig index a6543c46f3704..16d4c18d1006b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2c/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2c/defconfig @@ -38,6 +38,7 @@ CONFIG_I2C_RESET=y CONFIG_I2C_TRACE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig index 9d25ddb2b491f..0db3ed17a0d73 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/motor/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/motor/defconfig index 98c8e5eb536cf..a5415203c5be3 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/motor/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/motor/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig index f50d86f5425ae..5dad13bc4d051 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/nxlooper/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/nxlooper/defconfig index b1bfd706fcc4c..74624cd66040b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/nxlooper/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/nxlooper/defconfig @@ -54,6 +54,7 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/oneshot/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/oneshot/defconfig index 02b3bd54a5d5f..e0115f7dbc67b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/oneshot/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/oneshot/defconfig @@ -36,6 +36,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig index cb3af08be51b0..fbabacb87b783 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_octal/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_octal/defconfig index 3bd0dac32d510..e3c27ac827c9a 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_octal/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_octal/defconfig @@ -31,6 +31,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_quad/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_quad/defconfig index 2caee8fa869a1..6219a5b20a749 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_quad/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_quad/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_usrheap/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_usrheap/defconfig index 5cac5c167918a..78923d81deb4b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_usrheap/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_usrheap/defconfig @@ -32,6 +32,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=36 CONFIG_IOB_NCHAINS=36 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig index 10340c1fad4dd..c3e65808b33cb 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig @@ -34,6 +34,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/random/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/random/defconfig index e31aa51ef665e..1c17764291e2b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/random/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/random/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig index 9b1d8d91d92bb..f63775df409b5 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig @@ -34,6 +34,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rtc/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rtc/defconfig index 14df9fe3ea370..657b1c95d9e2b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rtc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rtc/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc/defconfig index dea61a7dde72a..b437aa19f4b4a 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MMCSD_CHECK_READY_STATUS_WITHOUT_SLEEP=y CONFIG_MMCSD_MULTIBLOCK_LIMIT=128 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sotest/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sotest/defconfig index afbdb4836bc4a..153325c3dc58f 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sotest/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sotest/defconfig @@ -32,6 +32,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_DLFCN=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig index 62ae1cd01dc5b..6cb575c52add3 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spiflash/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spiflash/defconfig index 823048a6700eb..7e24909e4ff5e 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spiflash/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spiflash/defconfig @@ -31,6 +31,7 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_MACOS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/stack/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/stack/defconfig index 6c4b9afa8f955..e76b317f961b5 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/stack/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/stack/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/temperature_sensor/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/temperature_sensor/defconfig index c5de3f3e2c568..0e5be79a8510f 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/temperature_sensor/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/temperature_sensor/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/tickless/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/tickless/defconfig index cca3a6e54cb1b..9e4dbafbe89c8 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/tickless/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/tickless/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/timer/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/timer/defconfig index 2f9aa55aea7eb..6cceb2292d5ac 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/timer/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/timer/defconfig @@ -33,6 +33,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/twai/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/twai/defconfig index 4905ea5572116..ead53a9f62abd 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/twai/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/twai/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig index d1dc58fed6b6c..917f96163e031 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig @@ -32,6 +32,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs index a462497d548ab..d013412908d06 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs @@ -34,10 +34,8 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + ifneq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) + ARCHSCRIPT += $(call FINDSCRIPT,esp32s3_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/i2c/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/i2c/defconfig index 5be83d8d966e1..33c1996d71299 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/i2c/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/i2c/defconfig @@ -32,6 +32,7 @@ CONFIG_FS_PROCFS=y CONFIG_I2C_RESET=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/lcd/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/lcd/defconfig index 47ab39981243c..14ce9a30189d3 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/lcd/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/lcd/defconfig @@ -35,6 +35,7 @@ CONFIG_EXAMPLES_FB=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD_FRAMEBUFFER=y CONFIG_LCD_PORTRAIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/nsh/defconfig index 973db7aa5ac46..f243acb994b1b 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/nsh/defconfig @@ -28,6 +28,7 @@ CONFIG_ESP32S3_USBSERIAL=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs index 2652922f8d076..9c55e7e5d1e43 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs @@ -34,10 +34,8 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + ifneq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) + ARCHSCRIPT += $(call FINDSCRIPT,esp32s3_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/nsh/defconfig index b7281cfa904e3..0937fcf2fa4c8 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/nsh/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/sdmmc/defconfig b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/sdmmc/defconfig index 0bdc80e0b3b6d..656f216e11c4f 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/sdmmc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/sdmmc/defconfig @@ -34,6 +34,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MMCSD_CHECK_READY_STATUS_WITHOUT_SLEEP=y CONFIG_MMCSD_MULTIBLOCK_LIMIT=128 diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-korvo-2/scripts/Make.defs index 56c7ea045ca68..a419c1ca9b3ac 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/scripts/Make.defs @@ -34,10 +34,8 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + ifneq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) + ARCHSCRIPT += $(call FINDSCRIPT,esp32s3_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig index 14ebe4e53a36d..49b8934a65d55 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/ws2812/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/ws2812/defconfig index dd5fcf3bcb215..dfd1648b30301 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/ws2812/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/ws2812/defconfig @@ -31,6 +31,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs index ad0fac04c1669..c3d5dbd4497bb 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs @@ -34,10 +34,8 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + ifneq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) + ARCHSCRIPT += $(call FINDSCRIPT,esp32s3_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-lhcbit/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-lhcbit/scripts/Make.defs index f8c6db352a57a..5dbd71d72f64d 100644 --- a/boards/xtensa/esp32s3/esp32s3-lhcbit/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-lhcbit/scripts/Make.defs @@ -34,10 +34,8 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + ifneq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) + ARCHSCRIPT += $(call FINDSCRIPT,esp32s3_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-meadow/configs/nsh/defconfig index 7b98bebf1c83c..215c13cb8c92e 100644 --- a/boards/xtensa/esp32s3/esp32s3-meadow/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-meadow/configs/nsh/defconfig @@ -28,6 +28,7 @@ CONFIG_ESP32S3_USBSERIAL=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs index 818ea4dc15047..5a539076ef933 100644 --- a/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs @@ -34,10 +34,8 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + ifneq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) + ARCHSCRIPT += $(call FINDSCRIPT,esp32s3_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index 2683ebdaa01c2..29350380c9dfa 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -3933,7 +3933,10 @@ static int mmcsd_cardidentify(FAR struct mmcsd_state_s *priv) finfo("MMC card detected\n"); priv->type = MMCSD_CARDTYPE_MMC; - priv->buswidth |= MMCSD_SCR_BUSWIDTH_4BIT; + if ((priv->caps & SDIO_CAPS_4BIT_ONLY) != 0) + { + priv->buswidth |= MMCSD_SCR_BUSWIDTH_4BIT; + } /* Now, check if this is a MMC card/chip that supports block * addressing diff --git a/drivers/rpmsg/rpmsg_port_spi.c b/drivers/rpmsg/rpmsg_port_spi.c index 8514a9ea6e854..64b26cdababa0 100644 --- a/drivers/rpmsg/rpmsg_port_spi.c +++ b/drivers/rpmsg/rpmsg_port_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/drivers/rptun/rptun_ivshmem.c b/drivers/rptun/rptun_ivshmem.c index 34ad6030b1f71..0e970e573cc1d 100644 --- a/drivers/rptun/rptun_ivshmem.c +++ b/drivers/rptun/rptun_ivshmem.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index fe09c6a2f67a0..36aeed66d4d0c 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -43,7 +43,7 @@ config SERIAL_CONSOLE config SERIAL_GDBSTUB bool "GDBSTUB Serial support" - depends on ARCH_HAVE_DEBUG + depends on LIB_GDBSTUB default n config SERIAL_GDBSTUB_PATH diff --git a/drivers/syslog/syslog_write.c b/drivers/syslog/syslog_write.c index 2573384050e34..f8d8ae739f650 100644 --- a/drivers/syslog/syslog_write.c +++ b/drivers/syslog/syslog_write.c @@ -37,6 +37,43 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: syslog_safe_to_block + * + * Description: + * Check if it is safe to block for write. If not, the write defaults to a + * non-blocking method. + * + * Input Parameters: + * None. + * + * Returned Value: + * true if it is safe to block; false otherwise. + * + ****************************************************************************/ + +static bool syslog_safe_to_block(void) +{ + FAR const struct tcb_s *rtcb; + + /* It's not safe to block in interrupts or when executing the idle loop */ + + if (up_interrupt_context() || sched_idletask()) + { + return false; + } + + /* It's not safe to block if a signal is being delivered */ + + rtcb = nxsched_self(); + if (rtcb->sigdeliver != NULL) + { + return false; + } + + return true; +} + /**************************************************************************** * Name: syslog_default_write * @@ -59,7 +96,7 @@ static ssize_t syslog_default_write(FAR const char *buffer, size_t buflen) { size_t nwritten; - if (up_interrupt_context() || sched_idletask()) + if (!syslog_safe_to_block()) { #ifdef CONFIG_SYSLOG_INTBUFFER if (up_interrupt_context()) diff --git a/drivers/timers/arch_alarm.c b/drivers/timers/arch_alarm.c index 43371c45d3f60..f9f646c734fbb 100644 --- a/drivers/timers/arch_alarm.c +++ b/drivers/timers/arch_alarm.c @@ -50,22 +50,6 @@ static clock_t g_current_tick; * Private Functions ****************************************************************************/ -static void ndelay_accurate(unsigned long nanoseconds) -{ - struct timespec now; - struct timespec end; - struct timespec delta; - - ONESHOT_CURRENT(g_oneshot_lower, &now); - clock_nsec2time(&delta, nanoseconds); - clock_timespec_add(&now, &delta, &end); - - while (clock_timespec_compare(&now, &end) < 0) - { - ONESHOT_CURRENT(g_oneshot_lower, &now); - } -} - static void udelay_coarse(useconds_t microseconds) { volatile int i; @@ -442,12 +426,5 @@ void weak_function up_udelay(useconds_t microseconds) void weak_function up_ndelay(unsigned long nanoseconds) { - if (g_oneshot_lower != NULL) - { - ndelay_accurate(nanoseconds); - } - else /* Oneshot timer hasn't been initialized yet */ - { - udelay_coarse((nanoseconds + NSEC_PER_USEC - 1) / NSEC_PER_USEC); - } + udelay_coarse((nanoseconds + NSEC_PER_USEC - 1) / NSEC_PER_USEC); } diff --git a/drivers/usbdev/cdcncm.c b/drivers/usbdev/cdcncm.c index 981275bdcb45f..e9d1c773d227b 100644 --- a/drivers/usbdev/cdcncm.c +++ b/drivers/usbdev/cdcncm.c @@ -1073,7 +1073,7 @@ static void cdcncm_receive(FAR struct cdcncm_driver_s *self) if ((ndplen < opts->ndpsize + 2 * (opts->dgramitemlen * 2)) || (ndplen % opts->ndpalign != 0)) { - uerr("Bad NDP length: %x\n", ndplen); + uerr("Bad NDP length: %04" PRIx32 " \n", ndplen); return; } diff --git a/drivers/wireless/bluetooth/bt_slip.c b/drivers/wireless/bluetooth/bt_slip.c index ca48747cb5b8c..08a857f0eb54f 100644 --- a/drivers/wireless/bluetooth/bt_slip.c +++ b/drivers/wireless/bluetooth/bt_slip.c @@ -31,6 +31,7 @@ #include #include +#include #include #include #include diff --git a/fs/v9fs/virtio_9p.c b/fs/v9fs/virtio_9p.c index 652361add510e..67e470d2cd3a0 100644 --- a/fs/v9fs/virtio_9p.c +++ b/fs/v9fs/virtio_9p.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/include/ctype.h b/include/ctype.h index 554ece95535d7..2282bd09dbcb2 100644 --- a/include/ctype.h +++ b/include/ctype.h @@ -35,7 +35,7 @@ #include #include -#ifndef _MSC_VER +#ifdef CONFIG_LIBCXXTOOLCHAIN /* GNU libstdc++ is expecting ctype.h to define a few macros for * locale related functions like C++ streams. diff --git a/include/nuttx/coredump.h b/include/nuttx/coredump.h index 273c0f7cbfeb4..2fdd7af46f392 100644 --- a/include/nuttx/coredump.h +++ b/include/nuttx/coredump.h @@ -79,7 +79,8 @@ int coredump_set_memory_region(FAR const struct memory_region_s *region); * ****************************************************************************/ -int coredump_add_memory_region(FAR const void *ptr, size_t size); +int coredump_add_memory_region(FAR const void *ptr, size_t size, + uint32_t flags); /**************************************************************************** * Name: coredump diff --git a/include/nuttx/tls.h b/include/nuttx/tls.h index cf23f942eaddd..3298959a487ec 100644 --- a/include/nuttx/tls.h +++ b/include/nuttx/tls.h @@ -39,7 +39,10 @@ #include #include #include -#include + +#ifdef CONFIG_PTHREAD_ATFORK +# include +#endif #include diff --git a/include/strings.h b/include/strings.h index 276a8bff80fe1..42383e5ff52f0 100644 --- a/include/strings.h +++ b/include/strings.h @@ -52,6 +52,10 @@ #define bcopy(b1,b2,len) memmove(b2,b1,len) #endif +#ifndef bzero /* See mm/README.txt */ +#define bzero(s,n) memset(s,0,n) +#endif + #define strcasecmp_l(s1, s2, l) strcasecmp(s1, s2) #define strncasecmp_l(s1, s2, n, l) strncasecmp(s1, s2, n) @@ -155,16 +159,6 @@ FAR char *rindex(FAR const char *s, int c); int strcasecmp(FAR const char *, FAR const char *); int strncasecmp(FAR const char *, FAR const char *, size_t); -void bzero(FAR void *s, size_t n); - -#if CONFIG_FORTIFY_SOURCE > 0 -fortify_function(bzero) void bzero(FAR void *s, size_t n) -{ - fortify_assert(n <= fortify_size(s, 0)); - return __real_bzero(s, n); -} -#endif - #undef EXTERN #if defined(__cplusplus) } diff --git a/libs/libc/ctype/lib_ctype.c b/libs/libc/ctype/lib_ctype.c index b97076cc97d14..d369a33f316e2 100644 --- a/libs/libc/ctype/lib_ctype.c +++ b/libs/libc/ctype/lib_ctype.c @@ -32,7 +32,7 @@ * Macro Definitions ****************************************************************************/ -#if defined(_MSC_VER) +#ifndef CONFIG_LIBCXXTOOLCHAIN /* MSVC seems to conflict with theses macro if defined in the public area. * As such, they are defined in the private section to let NuttX build @@ -47,7 +47,7 @@ #define _X 0100 #define _B 0200 -#endif +#else /**************************************************************************** * Private Types @@ -98,3 +98,6 @@ const char _ctype_[] = /**************************************************************************** * Private Functions ****************************************************************************/ + +#endif + diff --git a/libs/libc/gdbstub/lib_gdbstub.c b/libs/libc/gdbstub/lib_gdbstub.c index 6204fffd0135d..a8e4f5689077b 100644 --- a/libs/libc/gdbstub/lib_gdbstub.c +++ b/libs/libc/gdbstub/lib_gdbstub.c @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -1896,7 +1897,7 @@ int gdb_debugpoint_remove(int type, FAR void *addr, size_t size) point.addr = addr; point.size = size; - retrun nxsched_smp_call((1 << CONFIG_SMP_NCPUS) - 1, + return nxsched_smp_call((1 << CONFIG_SMP_NCPUS) - 1, gdb_smp_debugpoint_remove, &point, true); #else return up_debugpoint_remove(type, addr, size); diff --git a/libs/libc/machine/arm/CMakeLists.txt b/libs/libc/machine/arm/CMakeLists.txt index 6dba16de12da5..387be1d42c655 100644 --- a/libs/libc/machine/arm/CMakeLists.txt +++ b/libs/libc/machine/arm/CMakeLists.txt @@ -46,7 +46,7 @@ elseif(CONFIG_ARCH_ARMV8M) # All ARMv8-M add_subdirectory(armv8-m) endif() -if(NOT CONFIG_LIBSUPCXX) +if(NOT CONFIG_LIBSUPCXX_TOOLCHAIN) list(APPEND SRCS aeabi_atexit.c) endif() diff --git a/libs/libc/machine/arm/Make.defs b/libs/libc/machine/arm/Make.defs index 73b41ad4dc37f..63a319eb4a391 100644 --- a/libs/libc/machine/arm/Make.defs +++ b/libs/libc/machine/arm/Make.defs @@ -44,7 +44,7 @@ else ifeq ($(CONFIG_ARCH_ARMV8M),y) # All ARMv8-M include $(TOPDIR)/libs/libc/machine/arm/armv8-m/Make.defs endif -ifneq ($(CONFIG_LIBSUPCXX),y) +ifneq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) CSRCS += aeabi_atexit.c endif diff --git a/libs/libc/string/CMakeLists.txt b/libs/libc/string/CMakeLists.txt index cde0c623bcfa9..2fe47cc738455 100644 --- a/libs/libc/string/CMakeLists.txt +++ b/libs/libc/string/CMakeLists.txt @@ -23,7 +23,6 @@ # Add the string C files to the build set(SRCS - lib_bzero.c lib_ffs.c lib_ffsl.c lib_ffsll.c @@ -31,28 +30,20 @@ set(SRCS lib_flsl.c lib_flsll.c lib_isbasedigit.c - lib_memccpy.c - lib_memrchr.c lib_memmem.c lib_popcount.c lib_popcountl.c lib_popcountll.c lib_skipspace.c - lib_stpcpy.c - lib_stpncpy.c lib_strcasecmp.c - lib_strcat.c lib_strcspn.c - lib_strchrnul.c lib_strdup.c lib_strerror.c lib_strncasecmp.c lib_strncat.c - lib_strncmp.c lib_strndup.c lib_strcasestr.c lib_strpbrk.c - lib_strrchr.c lib_strspn.c lib_strstr.c lib_strtok.c @@ -60,7 +51,6 @@ set(SRCS lib_strsep.c lib_strerrorr.c lib_explicit_bzero.c - lib_bzero.c lib_strsignal.c lib_index.c lib_rindex.c @@ -68,21 +58,16 @@ set(SRCS lib_strverscmp.c lib_mempcpy.c lib_rawmemchr.c - lib_memchr.c - lib_memcmp.c lib_memmove.c lib_memset.c - lib_strchr.c - lib_strcmp.c - lib_strcpy.c lib_strlcat.c lib_strlcpy.c - lib_strlen.c - lib_strncpy.c lib_strnlen.c) if(CONFIG_MEMCPY_VIK) list(APPEND SRCS lib_vikmemcpy.c) +elseif(CONFIG_LIBC_STRING_OPTIMIZE) + list(APPEND SRCS lib_bsdmemcpy.c) else() list(APPEND SRCS lib_memcpy.c) endif() @@ -91,4 +76,44 @@ if(CONFIG_LIBC_LOCALE) list(APPEND SRCS lib_strcoll.c lib_strxfrm.c) endif() +if(CONFIG_LIBC_STRING_OPTIMIZE) + list( + APPEND + SRCS + lib_bsdmemccpy.c + lib_bsdmemcmp.c + lib_bsdmemrchr.c + lib_bsdstpncpy.c + lib_bsdstrchr.c + lib_bsdstrcmp.c + lib_bsdstrlen.c + lib_bsdstrncpy.c + lib_bsdmemchr.c + lib_bsdstpcpy.c + lib_bsdstrcat.c + lib_bsdstrchrnul.c + lib_bsdstrcpy.c + lib_bsdstrncmp.c + lib_bsdstrrchr.c) +else() + list( + APPEND + SRCS + lib_memccpy.c + lib_memcmp.c + lib_memrchr.c + lib_stpncpy.c + lib_strchr.c + lib_strcmp.c + lib_strlen.c + lib_strncpy.c + lib_memchr.c + lib_stpcpy.c + lib_strcat.c + lib_strchrnul.c + lib_strcpy.c + lib_strncmp.c + lib_strrchr.c) +endif() + target_sources(c PRIVATE ${SRCS}) diff --git a/libs/libc/string/Make.defs b/libs/libc/string/Make.defs index 0f8ac1d451f51..0ac85f3b4b556 100644 --- a/libs/libc/string/Make.defs +++ b/libs/libc/string/Make.defs @@ -23,23 +23,25 @@ # Add the string C files to the build CSRCS += lib_ffs.c lib_ffsl.c lib_ffsll.c lib_fls.c lib_flsl.c -CSRCS += lib_flsll.c lib_isbasedigit.c lib_memccpy.c lib_memrchr.c lib_memmem.c +CSRCS += lib_flsll.c lib_isbasedigit.c lib_memmem.c CSRCS += lib_popcount.c lib_popcountl.c lib_popcountll.c -CSRCS += lib_skipspace.c lib_stpcpy.c lib_stpncpy.c lib_strcasecmp.c -CSRCS += lib_strcat.c lib_strcspn.c lib_strchrnul.c lib_strdup.c -CSRCS += lib_strerror.c lib_strncasecmp.c lib_strncat.c lib_strncmp.c -CSRCS += lib_strndup.c lib_strcasestr.c lib_strpbrk.c lib_strrchr.c +CSRCS += lib_skipspace.c lib_strcasecmp.c +CSRCS += lib_strcspn.c lib_strdup.c +CSRCS += lib_strerror.c lib_strncasecmp.c lib_strncat.c +CSRCS += lib_strndup.c lib_strcasestr.c lib_strpbrk.c CSRCS += lib_strspn.c lib_strstr.c lib_strtok.c lib_strtokr.c CSRCS += lib_strsep.c lib_strerrorr.c lib_explicit_bzero.c lib_strsignal.c CSRCS += lib_index.c lib_rindex.c lib_timingsafe_bcmp.c lib_strverscmp.c -CSRCS += lib_mempcpy.c lib_rawmemchr.c lib_bzero.c +CSRCS += lib_mempcpy.c lib_rawmemchr.c -CSRCS += lib_memchr.c lib_memcmp.c lib_memmove.c lib_memset.c -CSRCS += lib_strchr.c lib_strcmp.c lib_strcpy.c lib_strlcat.c -CSRCS += lib_strlcpy.c lib_strlen.c lib_strncpy.c lib_strnlen.c +CSRCS += lib_memmove.c lib_memset.c +CSRCS += lib_strlcat.c +CSRCS += lib_strlcpy.c lib_strnlen.c ifeq ($(CONFIG_MEMCPY_VIK),y) CSRCS += lib_vikmemcpy.c +else ifeq ($(CONFIG_LIBC_STRING_OPTIMIZE),y) +CSRCS += lib_bsdmemcpy.c else CSRCS += lib_memcpy.c endif @@ -48,6 +50,18 @@ ifeq ($(CONFIG_LIBC_LOCALE),y) CSRCS += lib_strcoll.c lib_strxfrm.c endif +ifeq ($(CONFIG_LIBC_STRING_OPTIMIZE),y) +CSRCS += lib_bsdmemccpy.c lib_bsdmemcmp.c lib_bsdmemrchr.c lib_bsdstpncpy.c +CSRCS += lib_bsdstrchr.c lib_bsdstrcmp.c lib_bsdstrlen.c lib_bsdstrncpy.c +CSRCS += lib_bsdmemchr.c lib_bsdstpcpy.c lib_bsdstrcat.c lib_bsdstrchrnul.c +CSRCS += lib_bsdstrcpy.c lib_bsdstrncmp.c lib_bsdstrrchr.c +else +CSRCS += lib_memccpy.c lib_memcmp.c lib_memrchr.c lib_stpncpy.c +CSRCS += lib_strchr.c lib_strcmp.c lib_strlen.c lib_strncpy.c +CSRCS += lib_memchr.c lib_stpcpy.c lib_strcat.c lib_strchrnul.c +CSRCS += lib_strcpy.c lib_strncmp.c lib_strrchr.c +endif + # Add the string directory to the build DEPPATH += --dep-path string diff --git a/libs/libc/string/lib_bsdmemccpy.c b/libs/libc/string/lib_bsdmemccpy.c new file mode 100644 index 0000000000000..7b922cb6b5fc9 --- /dev/null +++ b/libs/libc/string/lib_bsdmemccpy.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdmemccpy.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* How many bytes are copied each iteration of the word copy loop. */ + +#define LITTLEBLOCKSIZE (sizeof(long)) + +/* Threshhold for punting to the byte copier. */ + +#define TOO_SMALL(len) ((len) < LITTLEBLOCKSIZE) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: memccpy + * + * Description: + * The memccpy() function copies bytes from memory area s2 into s1, + * stopping after the first occurrence of byte c (converted to an unsigned + * char) is copied, or after n bytes are copied, whichever comes first. If + * copying takes place between objects that overlap, the behavior is + * undefined. + * + * Returned Value: + * The memccpy() function returns a pointer to the byte after the copy of c + * in s1, or a null pointer if c was not found in the first n bytes of s2. + * + ****************************************************************************/ + +#undef memccpy /* See mm/README.txt */ +FAR void *memccpy(FAR void *s1, FAR const void *s2, int c, size_t n) +{ + FAR void *ptr = NULL; + FAR unsigned char *pout = (FAR unsigned char *)s1; + FAR const unsigned char *pin = (FAR const unsigned char *)s2; + FAR long *paligned_out; + FAR const long *paligned_in; + unsigned char endchar = c & 0xff; + + /* If the size is small, or either pin or pout is unaligned, + * then punt into the byte copy loop. This should be rare. + */ + + if (!TOO_SMALL(n) && !UNALIGNED(pin, pout)) + { + unsigned int i; + unsigned long mask = 0; + + paligned_out = (FAR long *)pout; + paligned_in = (FAR long *)pin; + + /* The fast code reads the ASCII one word at a time and only + * performs the bytewise search on word-sized segments if they + * contain the search character, which is detected by XORing + * the word-sized segment with a word-sized block of the search + * character and then detecting for the presence of NULL in the + * result. + */ + + for (i = 0; i < LITTLEBLOCKSIZE; i++) + { + mask = (mask << 8) + endchar; + } + + /* Copy one long word at a time if possible. */ + + while (n >= LITTLEBLOCKSIZE) + { + unsigned long buffer = (unsigned long)(*paligned_in); + buffer ^= mask; + if (DETECTNULL(buffer)) + { + break; /* endchar is found, go byte by byte from here */ + } + + *paligned_out++ = *paligned_in++; + n -= LITTLEBLOCKSIZE; + } + + /* Pick up any residual with a byte copier. */ + + pout = (FAR unsigned char *)paligned_out; + pin = (FAR unsigned char *)paligned_in; + } + + while (n--) + { + if ((*pout++ = *pin++) == endchar) + { + ptr = pout; + break; + } + } + + return ptr; +} diff --git a/libs/libc/string/lib_bsdmemchr.c b/libs/libc/string/lib_bsdmemchr.c new file mode 100644 index 0000000000000..d0b8c30b1f6b1 --- /dev/null +++ b/libs/libc/string/lib_bsdmemchr.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdmemchr.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define UNALIGNED(x) ((long)(uintptr_t)(x) & (sizeof(long) - 1)) + +/* How many bytes are loaded each iteration of the word copy loop. */ + +#define LBLOCKSIZE (sizeof(long)) + +/* Threshhold for punting to the bytewise iterator. */ + +#define TOO_SMALL(len) ((len) < LBLOCKSIZE) + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +/* DETECTCHAR returns nonzero if (long)x contains the byte used + * to fill (long)mask. + */ + +#define DETECTCHAR(x, mask) (DETECTNULL((x) ^ (mask))) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: memchr + * + * Description: + * The memchr() function locates the first occurrence of 'c' (converted to + * an unsigned char) in the initial 'n' bytes (each interpreted as + * unsigned char) of the object pointed to by s. + * + * Returned Value: + * The memchr() function returns a pointer to the located byte, or a null + * pointer if the byte does not occur in the object. + * + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_MEMCHR) && defined(LIBC_BUILD_MEMCHR) +#undef memchr /* See mm/README.txt */ +FAR void *memchr(FAR const void *s, int c, size_t n) +{ + FAR const unsigned char *p = (FAR const unsigned char *)s; + FAR unsigned long *asrc; + unsigned char d = c; + unsigned long mask; + unsigned int i; + + while (UNALIGNED(p)) + { + if (!n--) + { + return NULL; + } + + if (*p == d) + { + return (FAR void *)p; + } + + p++; + } + + if (!TOO_SMALL(n)) + { + /* If we get this far, we know that n is large and p is + * word-aligned. + * The fast code reads the source one word at a time and only + * performs the bytewise search on word-sized segments if they + * contain the search character, which is detected by XORing + * the word-sized segment with a word-sized block of the search + * character and then detecting for the presence of NUL in the + * result. + */ + + asrc = (FAR unsigned long *)p; + mask = d << 8 | d; + mask = mask << 16 | mask; + for (i = 32; i < LBLOCKSIZE * 8; i <<= 1) + { + mask = (mask << i) | mask; + } + + while (n >= LBLOCKSIZE) + { + if (DETECTCHAR(*asrc, mask)) + { + break; + } + + n -= LBLOCKSIZE; + asrc++; + } + + /* If there are fewer than LBLOCKSIZE characters left, + * then we resort to the bytewise loop. + */ + + p = (FAR unsigned char *)asrc; + } + + while (n--) + { + if (*p == d) + { + return (FAR void *)p; + } + + p++; + } + + return NULL; +} +#endif diff --git a/libs/libc/string/lib_bsdmemcmp.c b/libs/libc/string/lib_bsdmemcmp.c new file mode 100644 index 0000000000000..614f1fefd4e3a --- /dev/null +++ b/libs/libc/string/lib_bsdmemcmp.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdmemcmp.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* How many bytes are copied each iteration of the word copy loop. */ + +#define LBLOCKSIZE (sizeof(long)) + +/* Threshhold for punting to the byte copier. */ + +#define TOO_SMALL(len) ((len) < LBLOCKSIZE) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_MEMCMP) && defined(LIBC_BUILD_MEMCMP) +#undef memcmp /* See mm/README.txt */ +no_builtin("memcmp") +int memcmp(FAR const void *s1, FAR const void *s2, size_t n) +{ + FAR unsigned char *p1 = (FAR unsigned char *)s1; + FAR unsigned char *p2 = (FAR unsigned char *)s2; + FAR unsigned long *a1; + FAR unsigned long *a2; + + /* If the size is too small, or either pointer is unaligned, + * then we punt to the byte compare loop. Hopefully this will + * not turn up in inner loops. + */ + + if (!TOO_SMALL(n) && !UNALIGNED(p1, p2)) + { + /* Otherwise, load and compare the blocks of memory one + * word at a time. + */ + + a1 = (FAR unsigned long *)p1; + a2 = (FAR unsigned long *)p2; + while (n >= LBLOCKSIZE) + { + if (*a1 != *a2) + { + break; + } + + a1++; + a2++; + n -= LBLOCKSIZE; + } + + /* check s mod LBLOCKSIZE remaining characters */ + + p1 = (FAR unsigned char *)a1; + p2 = (FAR unsigned char *)a2; + } + + while (n--) + { + if (*p1 != *p2) + { + return *p1 - *p2; + } + + p1++; + p2++; + } + + return 0; +} +#endif diff --git a/libs/libc/string/lib_bsdmemcpy.c b/libs/libc/string/lib_bsdmemcpy.c new file mode 100644 index 0000000000000..21607b1fc72a0 --- /dev/null +++ b/libs/libc/string/lib_bsdmemcpy.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdmemcpy.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* How many bytes are copied each iteration of the 4X unrolled loop. */ + +#define BIGBLOCKSIZE (sizeof(long) << 2) + +/* How many bytes are copied each iteration of the word copy loop. */ + +#define LITTLEBLOCKSIZE (sizeof(long)) + +/* Threshhold for punting to the byte copier. */ + +#define TOO_SMALL(len) ((len) < BIGBLOCKSIZE) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: memcpy + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_MEMCPY) && defined(LIBC_BUILD_MEMCPY) +#undef memcpy /* See mm/README.txt */ +no_builtin("memcpy") +FAR void *memcpy(FAR void *dest, FAR const void *src, size_t n) +{ + FAR char *pout = dest; + FAR const char *pin = src; + FAR long *paligned_out; + FAR const long *paligned_in; + + /* If the size is small, or either pin or pout is unaligned, + * then punt into the byte copy loop. This should be rare. + */ + + if (!TOO_SMALL(n) && !UNALIGNED(pin, pout)) + { + paligned_out = (FAR long *)pout; + paligned_in = (FAR long *)pin; + + /* Copy 4X long words at a time if possible. */ + + while (n >= BIGBLOCKSIZE) + { + *paligned_out++ = *paligned_in++; + *paligned_out++ = *paligned_in++; + *paligned_out++ = *paligned_in++; + *paligned_out++ = *paligned_in++; + n -= BIGBLOCKSIZE; + } + + /* Copy one long word at a time if possible. */ + + while (n >= LITTLEBLOCKSIZE) + { + *paligned_out++ = *paligned_in++; + n -= LITTLEBLOCKSIZE; + } + + /* Pick up any residual with a byte copier. */ + + pout = (FAR char *)paligned_out; + pin = (FAR char *)paligned_in; + } + + while (n--) + { + *pout++ = *pin++; + } + + return dest; +} +#endif diff --git a/libs/libc/string/lib_bsdmemrchr.c b/libs/libc/string/lib_bsdmemrchr.c new file mode 100644 index 0000000000000..7c8f829e4f6e6 --- /dev/null +++ b/libs/libc/string/lib_bsdmemrchr.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdmemrchr.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Nonzero if x is not aligned on a "long" boundary. */ + +#define UNALIGNED(x) ((long)(uintptr_t)((x) + 1) & (sizeof(long) - 1)) + +/* How many bytes are loaded each iteration of the word copy loop. */ + +#define LBLOCKSIZE (sizeof(long)) + +/* Threshhold for punting to the bytewise iterator. */ + +#define TOO_SMALL(len) ((len) < LBLOCKSIZE) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +#define DETECTCHAR(x, mask) (DETECTNULL((x) ^ (mask))) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: memrchr + * + * Description: + * The memrchr() function locates the last occurrence of 'c' (converted to + * an unsigned char) in the initial 'n' bytes (each interpreted as + * unsigned char) of the object pointed to by s. + * + * Returned Value: + * The memrchr() function returns a pointer to the located byte, or a null + * pointer if the byte does not occur in the object. + * + ****************************************************************************/ + +#undef memrchr /* See mm/README.txt */ +FAR void *memrchr(FAR const void *s, int c, size_t n) +{ + FAR const unsigned char *src0 = + (FAR const unsigned char *)s + n - 1; + FAR unsigned long *asrc; + unsigned char d = c; + unsigned long mask; + unsigned int i; + + while (UNALIGNED(src0)) + { + if (!n--) + { + return NULL; + } + + if (*src0 == d) + { + return (FAR void *)src0; + } + + src0--; + } + + if (!TOO_SMALL(n)) + { + /* If we get this far, we know that n is large and src0 is + * word-aligned. + * The fast code reads the source one word at a time and only + * performs the bytewise search on word-sized segments if they + * contain the search character, which is detected by XORing + * the word-sized segment with a word-sized block of the search + * character and then detecting for the presence of NUL in the + * result. + */ + + asrc = (FAR unsigned long *)(src0 - LBLOCKSIZE + 1); + mask = d << 8 | d; + mask = mask << 16 | mask; + for (i = 32; i < LBLOCKSIZE * 8; i <<= 1) + { + mask = (mask << i) | mask; + } + + while (n >= LBLOCKSIZE) + { + if (DETECTCHAR(*asrc, mask)) + { + break; + } + + n -= LBLOCKSIZE; + asrc--; + } + + /* If there are fewer than LBLOCKSIZE characters left, + * then we resort to the bytewise loop. + */ + + src0 = (FAR unsigned char *)asrc + LBLOCKSIZE - 1; + } + + while (n--) + { + if (*src0 == d) + { + return (FAR void *)src0; + } + + src0--; + } + + return NULL; +} diff --git a/libs/libc/string/lib_bsdstpcpy.c b/libs/libc/string/lib_bsdstpcpy.c new file mode 100644 index 0000000000000..7edcc8d79a139 --- /dev/null +++ b/libs/libc/string/lib_bsdstpcpy.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstpcpy.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stpcpy + * + * Description: + * Copies the string pointed to by 'src' (including the terminating NUL + * character) into the array pointed to by 'dest'. + * + * Returned Value: + * The stpcpy() function returns a pointer to the terminating NUL + * character copied into the 'dest' buffer + * + ****************************************************************************/ + +#ifndef CONFIG_LIBC_ARCH_STPCPY +#undef stpcpy /* See mm/README.txt */ +nosanitize_address +FAR char *stpcpy(FAR char *dest, FAR const char *src) +{ + FAR long *aligned_dst; + FAR const long *aligned_src; + + /* If src or dest is unaligned, then copy bytes. */ + + if (!UNALIGNED(src, dest)) + { + aligned_dst = (FAR long *)dest; + aligned_src = (FAR long *)src; + + /* src and dest are both "long int" aligned, try to do "long int" + * sized copies. + */ + + while (!DETECTNULL(*aligned_src)) + { + *aligned_dst++ = *aligned_src++; + } + + dest = (FAR char *)aligned_dst; + src = (FAR char *)aligned_src; + } + + while ((*dest++ = *src++) != '\0'); + + return --dest; +} +#endif diff --git a/libs/libc/string/lib_bsdstpncpy.c b/libs/libc/string/lib_bsdstpncpy.c new file mode 100644 index 0000000000000..1d4f43a15d77e --- /dev/null +++ b/libs/libc/string/lib_bsdstpncpy.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstpncpy.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* How many bytes are loaded each iteration of the word copy loop. */ + +#define LBLOCKSIZE (sizeof(long)) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +#define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +#define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +#define TOO_SMALL(len) ((len) < sizeof(long)) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stpncpy + * + * Description: + * Copies the string pointed to by 'src' (including the terminating NUL + * character) into the array pointed to by 'dest'. strncpy() will not + * copy more than 'n' bytes from 'src' to 'dest' array (including the + * NUL terminator). + * + * If the array pointed to by 'src' is a string that is shorter than 'n' + * bytes, NUL characters will be appended to the copy in the array + * pointed to by 'dest', until 'n' bytes in all are written. + * + * If copying takes place between objects that overlap, the behavior is + * undefined. + * + * Returned Value: + * If a NUL character is written to the destination, the stpncpy() + * function will return the address of the first such NUL character. + * Otherwise, it will return &dest[n] + * + ****************************************************************************/ + +#ifndef CONFIG_LIBC_ARCH_STPNCPY +#undef stpncpy /* See mm/README.txt */ +FAR char *stpncpy(FAR char *dest, FAR const char *src, size_t n) +{ + FAR char *ret = NULL; + FAR long *aligned_dst; + FAR const long *aligned_src; + + /* If src and dest is aligned and n large enough, then copy words. */ + + if (!UNALIGNED(src, dest) && !TOO_SMALL(n)) + { + aligned_dst = (FAR long *)dest; + aligned_src = (FAR long *)src; + + /* src and dest are both "long int" aligned, try to do "long int" + * sized copies. + */ + + while (n >= LBLOCKSIZE && !DETECTNULL(*aligned_src)) + { + n -= LBLOCKSIZE; + *aligned_dst++ = *aligned_src++; + } + + dest = (FAR char *)aligned_dst; + src = (FAR char *)aligned_src; + } + + while (n > 0) + { + --n; + if ((*dest++ = *src++) == '\0') + { + ret = dest - 1; + break; + } + } + + while (n-- > 0) + { + *dest++ = '\0'; + } + + return ret ? ret : dest; +} +#endif diff --git a/libs/libc/string/lib_bsdstrcat.c b/libs/libc/string/lib_bsdstrcat.c new file mode 100644 index 0000000000000..ced88d72d9077 --- /dev/null +++ b/libs/libc/string/lib_bsdstrcat.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrcat.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ALIGNED(x) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) == 0) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_STRCAT) && defined(LIBC_BUILD_STRCAT) +#undef strcat /* See mm/README.txt */ +nosanitize_address +FAR char *strcat(FAR char *dest, FAR const char *src) +{ + FAR char *ret = dest; + + /* Skip over the data in dest as quickly as possible. */ + + if (ALIGNED(dest)) + { + FAR unsigned long *aligned_s1 = (FAR unsigned long *)dest; + while (!DETECTNULL(*aligned_s1)) + { + aligned_s1++; + } + + dest = (FAR char *)aligned_s1; + } + + while (*dest) + { + dest++; + } + + /* dest now points to the its trailing null character, we can + * just use strcpy to do the work for us now. + * ?!? We might want to just include strcpy here. + * Also, this will cause many more unaligned string copies because + * dest is much less likely to be aligned. I don't know if its worth + * tweaking strcpy to handle this better. + */ + + strcpy(dest, src); + + return ret; +} +#endif diff --git a/libs/libc/string/lib_bsdstrchr.c b/libs/libc/string/lib_bsdstrchr.c new file mode 100644 index 0000000000000..6223f27658d31 --- /dev/null +++ b/libs/libc/string/lib_bsdstrchr.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrchr.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define UNALIGNED(x) ((long)(uintptr_t)(x) & (sizeof(long) - 1)) + +/* How many bytes are loaded each iteration of the word copy loop. */ + +#define LBLOCKSIZE (sizeof(long)) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +#define DETECTCHAR(x, mask) (DETECTNULL((x) ^ (mask))) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: strchr + * + * Description: + * The strchr() function locates the first occurrence of 'c' (converted to + * a char) in the string pointed to by 's'. The terminating null byte is + * considered to be part of the string. + * + * Returned Value: + * Upon completion, strchr() returns a pointer to the byte, or a null + * pointer if the byte was not found. + * + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_STRCHR) && defined(LIBC_BUILD_STRCHR) +#undef strchr /* See mm/README.txt */ +nosanitize_address +FAR char *strchr(FAR const char *s, int c) +{ + FAR const unsigned char *s1 = (FAR const unsigned char *)s; + FAR unsigned long *aligned_addr; + unsigned char i = c; + unsigned long mask; + unsigned long j; + + /* Special case for finding 0. */ + + if (!i) + { + while (UNALIGNED(s1)) + { + if (!*s1) + { + return (FAR char *)s1; + } + + s1++; + } + + /* Operate a word at a time. */ + + aligned_addr = (FAR unsigned long *)s1; + while (!DETECTNULL(*aligned_addr)) + { + aligned_addr++; + } + + /* Found the end of string. */ + + s1 = (FAR const unsigned char *)aligned_addr; + while (*s1) + { + s1++; + } + + return (FAR char *)s1; + } + + /* All other bytes. Align the pointer, then search a long at a time. */ + + while (UNALIGNED(s1)) + { + if (!*s1) + { + return NULL; + } + + if (*s1 == i) + { + return (FAR char *)s1; + } + + s1++; + } + + mask = i; + for (j = 8; j < LBLOCKSIZE * 8; j <<= 1) + { + mask = (mask << j) | mask; + } + + aligned_addr = (FAR unsigned long *)s1; + while (!DETECTNULL(*aligned_addr) && !DETECTCHAR(*aligned_addr, mask)) + { + aligned_addr++; + } + + /* The block of bytes currently pointed to by aligned_addr + * contains either a null or the target char, or both. We + * catch it using the bytewise search. + */ + + s1 = (FAR unsigned char *)aligned_addr; + + while (*s1 && *s1 != i) + { + s1++; + } + + if (*s1 == i) + { + return (FAR char *)s1; + } + + return NULL; +} +#endif diff --git a/libs/libc/string/lib_bsdstrchrnul.c b/libs/libc/string/lib_bsdstrchrnul.c new file mode 100644 index 0000000000000..5e3129005dd77 --- /dev/null +++ b/libs/libc/string/lib_bsdstrchrnul.c @@ -0,0 +1,55 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrchrnul.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "libc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: strchrnul + * + * Description: + * The strchrnul() function locates the first occurrence of 'c' (converted + * to a char) in the string pointed to by 's'. The terminating null byte is + * considered to be part of the string. + * + * Returned Value: + * Upon completion, strchrnul() returns a pointer to the byte, or a + * pointer to null if the byte was not found. + * + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_STRCHRNUL) && defined(LIBC_BUILD_STRCHRNUL) +#undef strchrnul /* See mm/README.txt */ +FAR char *strchrnul(FAR const char *s, int c) +{ + FAR char *s1 = strchr(s, c); + + return s1 ? s1 : (FAR char *)s + strlen(s); +} +#endif diff --git a/libs/libc/string/lib_bsdstrcmp.c b/libs/libc/string/lib_bsdstrcmp.c new file mode 100644 index 0000000000000..270bcbaf87d8f --- /dev/null +++ b/libs/libc/string/lib_bsdstrcmp.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrcmp.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_STRCMP) && defined(LIBC_BUILD_STRCMP) +#undef strcmp /* See mm/README.txt */ +nosanitize_address +int strcmp(FAR const char *cs, FAR const char *ct) +{ + FAR unsigned long *a1; + FAR unsigned long *a2; + + /* If cs or ct are unaligned, then compare bytes. */ + + if (!UNALIGNED(cs, ct)) + { + /* If cs and ct are word-aligned, compare them a word at a time. */ + + a1 = (FAR unsigned long *)cs; + a2 = (FAR unsigned long *)ct; + while (*a1 == *a2) + { + /* To get here, *a1 == *a2, thus if we find a null in *a1, + * then the strings must be equal, so return zero. + */ + + if (DETECTNULL(*a1)) + { + return 0; + } + + a1++; + a2++; + } + + /* A difference was detected in last few bytes of cs, + * so search bytewise. + */ + + cs = (FAR char *)a1; + ct = (FAR char *)a2; + } + + while (*cs != '\0' && *cs == *ct) + { + cs++; + ct++; + } + + return (*(FAR unsigned char *)cs) - (*(FAR unsigned char *)ct); +} +#endif diff --git a/libs/libc/string/lib_bsdstrcpy.c b/libs/libc/string/lib_bsdstrcpy.c new file mode 100644 index 0000000000000..7a674d9655f57 --- /dev/null +++ b/libs/libc/string/lib_bsdstrcpy.c @@ -0,0 +1,98 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrcpy.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: strcpy + * + * Description: + * Copies the string pointed to by 'src' (including the terminating NUL + * character) into the array pointed to by 'des'. + * + * Returned Value: + * The strcpy() function returns the 'dest' pointer + * + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_STRCPY) && defined(LIBC_BUILD_STRCPY) +#undef strcpy /* See mm/README.txt */ +nosanitize_address +FAR char *strcpy(FAR char *dest, FAR const char *src) +{ + FAR char *dst0 = dest; + FAR const char *src0 = src; + FAR unsigned long *aligned_dst; + FAR const unsigned long *aligned_src; + + /* If SRC or DEST is unaligned, then copy bytes. */ + + if (!UNALIGNED(src0, dst0)) + { + aligned_dst = (FAR unsigned long *)dst0; + aligned_src = (FAR unsigned long *)src0; + + /* SRC and DEST are both "long int" aligned, try to do "long int" + * sized copies. + */ + + while (!DETECTNULL(*aligned_src)) + { + *aligned_dst++ = *aligned_src++; + } + + dst0 = (FAR char *)aligned_dst; + src0 = (FAR char *)aligned_src; + } + + while ((*dst0++ = *src0++) != '\0'); + + return dest; +} +#endif diff --git a/libs/libc/string/lib_bsdstrlen.c b/libs/libc/string/lib_bsdstrlen.c new file mode 100644 index 0000000000000..082aa9b00bfe9 --- /dev/null +++ b/libs/libc/string/lib_bsdstrlen.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrlen.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LBLOCKSIZE (sizeof(long)) +#define UNALIGNED(x) ((long)(uintptr_t)(x) & (LBLOCKSIZE - 1)) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_STRLEN) && defined(LIBC_BUILD_STRLEN) +#undef strlen /* See mm/README.txt */ +nosanitize_address +size_t strlen(FAR const char *s) +{ + FAR const char *start = s; + FAR unsigned long *aligned_addr; + + /* Align the pointer, so we can search a word at a time. */ + + while (UNALIGNED(s)) + { + if (!*s) + { + return s - start; + } + + s++; + } + + /* If the string is word-aligned, we can check for the presence of + * a null in each word-sized block. + */ + + aligned_addr = (FAR unsigned long *)s; + while (!DETECTNULL(*aligned_addr)) + { + aligned_addr++; + } + + /* Once a null is detected, we check each byte in that block for a + * precise position of the null. + */ + + s = (FAR char *)aligned_addr; + while (*s) + { + s++; + } + + return s - start; +} +#endif diff --git a/libs/libc/string/lib_bsdstrncmp.c b/libs/libc/string/lib_bsdstrncmp.c new file mode 100644 index 0000000000000..829bb84a1f5bb --- /dev/null +++ b/libs/libc/string/lib_bsdstrncmp.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrncmp.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LBLOCKSIZE (sizeof(long)) + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_STRNCMP) && defined(LIBC_BUILD_STRNCMP) +#undef strncmp /* See mm/README.txt */ +nosanitize_address +int strncmp(FAR const char *cs, FAR const char *ct, size_t nb) +{ + FAR unsigned long *a1; + FAR unsigned long *a2; + + if (nb == 0) + { + return 0; + } + + /* If cs or ct are unaligned, then compare bytes. */ + + if (!UNALIGNED(cs, ct)) + { + /* If cs and ct are word-aligned, compare them a word at a time. */ + + a1 = (FAR unsigned long *)cs; + a2 = (FAR unsigned long *)ct; + while (nb >= LBLOCKSIZE && *a1 == *a2) + { + nb -= LBLOCKSIZE; + + /* If we've run out of bytes or hit a null, return zero + * since we already know *a1 == *a2. + */ + + if (nb == 0 || DETECTNULL(*a1)) + { + return 0; + } + + a1++; + a2++; + } + + /* A difference was detected in last few bytes of cs, so search + * bytewise. + */ + + cs = (FAR char *)a1; + ct = (FAR char *)a2; + } + + while (nb-- > 0 && *cs == *ct) + { + /* If we've run out of bytes or hit a null, return zero + * since we already know *cs == *ct. + */ + + if (nb == 0 || *cs == '\0') + { + return 0; + } + + cs++; + ct++; + } + + return *cs - *ct; +} +#endif diff --git a/libs/libc/string/lib_bsdstrncpy.c b/libs/libc/string/lib_bsdstrncpy.c new file mode 100644 index 0000000000000..29e1aa3f49292 --- /dev/null +++ b/libs/libc/string/lib_bsdstrncpy.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrncpy.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LBLOCKSIZE (sizeof(long)) + +/* Nonzero if either x or y is not aligned on a "long" boundary. */ + +#define UNALIGNED(x, y) \ + (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) + +/* Macros for detecting endchar */ + +#if LONG_MAX == 2147483647 +# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) +#elif LONG_MAX == 9223372036854775807 +/* Nonzero if x (a long int) contains a NULL byte. */ + +# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) +#endif + +#define TOO_SMALL(len) ((len) < sizeof(long)) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: strncpy + * + * Description: + * Copies the string pointed to by 'src' (including the terminating NUL + * character) into the array pointed to by 'dest'. strncpy() will not + * copy more than 'n' bytes from 'src' to 'dest' array (including the + * NUL terminator). + * + * If the array pointed to by 'src' is a string that is shorter than 'n' + * bytes, NUL characters will be appended to the copy in the array + * pointed to by 'dest', until 'n' bytes in all are written. + * + * If copying takes place between objects that overlap, the behavior is + * undefined. + * + * Returned Value: + * The strncpy() function returns the pointer to 'dest' + * + ****************************************************************************/ + +#if !defined(CONFIG_LIBC_ARCH_STRNCPY) && defined(LIBC_BUILD_STRNCPY) +#undef strncpy /* See mm/README.txt */ +nosanitize_address +FAR char *strncpy(FAR char *dest, FAR const char *src, size_t n) +{ + FAR char *dst0 = dest; + FAR const char *src0 = src; + FAR long *aligned_dst; + FAR const long *aligned_src; + + /* If src and dest is aligned and n large enough, then copy words. */ + + if (!UNALIGNED(src0, dst0) && !TOO_SMALL(n)) + { + aligned_dst = (FAR long *)dst0; + aligned_src = (FAR long *)src0; + + /* src and dest are both "long int" aligned, try to do "long int" + * sized copies. + */ + + while (n >= LBLOCKSIZE && !DETECTNULL(*aligned_src)) + { + n -= LBLOCKSIZE; + *aligned_dst++ = *aligned_src++; + } + + dst0 = (FAR char *)aligned_dst; + src0 = (FAR char *)aligned_src; + } + + while (n > 0) + { + --n; + if ((*dst0++ = *src0++) == '\0') + { + break; + } + } + + while (n-- > 0) + { + *dst0++ = '\0'; + } + + return dest; +} +#endif diff --git a/libs/libc/string/lib_bsdstrrchr.c b/libs/libc/string/lib_bsdstrrchr.c new file mode 100644 index 0000000000000..e98a45e4cc71e --- /dev/null +++ b/libs/libc/string/lib_bsdstrrchr.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * libs/libc/string/lib_bsdstrrchr.c + * + * Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the BSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. Any Red Hat trademarks that are + * incorporated in the source code or documentation are not subject to + * the BSD License and may only be used or replicated with the express + * permission of Red Hat, Inc. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "libc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* The strrchr() function returns a pointer to the last + * occurrence of the character c in the string s. + */ + +#if !defined(CONFIG_LIBC_ARCH_STRRCHR) && defined(LIBC_BUILD_STRRCHR) +#undef strrchr /* See mm/README.txt */ +FAR char *strrchr(FAR const char *s, int c) +{ + FAR const char *last = NULL; + + if (c) + { + while ((s = strchr(s, c))) + { + last = s; + s++; + } + } + else + { + last = strchr(s, c); + } + + return (FAR char *)last; +} +#endif diff --git a/libs/libc/string/lib_memccpy.c b/libs/libc/string/lib_memccpy.c index 3cb34c0d2d983..283e5650cf2ea 100644 --- a/libs/libc/string/lib_memccpy.c +++ b/libs/libc/string/lib_memccpy.c @@ -28,36 +28,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* How many bytes are copied each iteration of the word copy loop. */ - -#define LITTLEBLOCKSIZE (sizeof(long)) - -/* Threshhold for punting to the byte copier. */ - -#define TOO_SMALL(len) ((len) < LITTLEBLOCKSIZE) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -81,71 +51,6 @@ #undef memccpy /* See mm/README.txt */ FAR void *memccpy(FAR void *s1, FAR const void *s2, int c, size_t n) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR void *ptr = NULL; - FAR unsigned char *pout = (FAR unsigned char *)s1; - FAR const unsigned char *pin = (FAR const unsigned char *)s2; - FAR long *paligned_out; - FAR const long *paligned_in; - unsigned char endchar = c & 0xff; - - /* If the size is small, or either pin or pout is unaligned, - * then punt into the byte copy loop. This should be rare. - */ - - if (!TOO_SMALL(n) && !UNALIGNED(pin, pout)) - { - unsigned int i; - unsigned long mask = 0; - - paligned_out = (FAR long *)pout; - paligned_in = (FAR long *)pin; - - /* The fast code reads the ASCII one word at a time and only - * performs the bytewise search on word-sized segments if they - * contain the search character, which is detected by XORing - * the word-sized segment with a word-sized block of the search - * character and then detecting for the presence of NULL in the - * result. - */ - - for (i = 0; i < LITTLEBLOCKSIZE; i++) - { - mask = (mask << 8) + endchar; - } - - /* Copy one long word at a time if possible. */ - - while (n >= LITTLEBLOCKSIZE) - { - unsigned long buffer = (unsigned long)(*paligned_in); - buffer ^= mask; - if (DETECTNULL(buffer)) - { - break; /* endchar is found, go byte by byte from here */ - } - - *paligned_out++ = *paligned_in++; - n -= LITTLEBLOCKSIZE; - } - - /* Pick up any residual with a byte copier. */ - - pout = (FAR unsigned char *)paligned_out; - pin = (FAR unsigned char *)paligned_in; - } - - while (n--) - { - if ((*pout++ = *pin++) == endchar) - { - ptr = pout; - break; - } - } - - return ptr; -#else FAR unsigned char *pout = (FAR unsigned char *)s1; FAR unsigned char *pin = (FAR unsigned char *)s2; @@ -170,5 +75,4 @@ FAR void *memccpy(FAR void *s1, FAR const void *s2, int c, size_t n) /* C was not found in the first n bytes of s2 */ return NULL; -#endif } diff --git a/libs/libc/string/lib_memchr.c b/libs/libc/string/lib_memchr.c index e651f21b673c0..2c24e3256f975 100644 --- a/libs/libc/string/lib_memchr.c +++ b/libs/libc/string/lib_memchr.c @@ -30,38 +30,6 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - -#define UNALIGNED(x) ((long)(uintptr_t)(x) & (sizeof(long) - 1)) - -/* How many bytes are loaded each iteration of the word copy loop. */ - -#define LBLOCKSIZE (sizeof(long)) - -/* Threshhold for punting to the bytewise iterator. */ - -#define TOO_SMALL(len) ((len) < LBLOCKSIZE) - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -/* DETECTCHAR returns nonzero if (long)x contains the byte used - * to fill (long)mask. - */ - -#define DETECTCHAR(x, mask) (DETECTNULL((x) ^ (mask))) - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -84,76 +52,6 @@ #undef memchr /* See mm/README.txt */ FAR void *memchr(FAR const void *s, int c, size_t n) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR const unsigned char *p = (FAR const unsigned char *)s; - FAR unsigned long *asrc; - unsigned char d = c; - unsigned long mask; - unsigned int i; - - while (UNALIGNED(p)) - { - if (!n--) - { - return NULL; - } - - if (*p == d) - { - return (FAR void *)p; - } - - p++; - } - - if (!TOO_SMALL(n)) - { - /* If we get this far, we know that n is large and p is - * word-aligned. - * The fast code reads the source one word at a time and only - * performs the bytewise search on word-sized segments if they - * contain the search character, which is detected by XORing - * the word-sized segment with a word-sized block of the search - * character and then detecting for the presence of NUL in the - * result. - */ - - asrc = (FAR unsigned long *)p; - mask = d << 8 | d; - mask = mask << 16 | mask; - for (i = 32; i < LBLOCKSIZE * 8; i <<= 1) - { - mask = (mask << i) | mask; - } - - while (n >= LBLOCKSIZE) - { - if (DETECTCHAR(*asrc, mask)) - { - break; - } - - n -= LBLOCKSIZE; - asrc++; - } - - /* If there are fewer than LBLOCKSIZE characters left, - * then we resort to the bytewise loop. - */ - - p = (FAR unsigned char *)asrc; - } - - while (n--) - { - if (*p == d) - { - return (FAR void *)p; - } - - p++; - } -#else FAR const unsigned char *p = (FAR const unsigned char *)s; while (n--) @@ -165,7 +63,6 @@ FAR void *memchr(FAR const void *s, int c, size_t n) p++; } -#endif return NULL; } diff --git a/libs/libc/string/lib_memcmp.c b/libs/libc/string/lib_memcmp.c index 4960a810fb526..251cbf7bbad1b 100644 --- a/libs/libc/string/lib_memcmp.c +++ b/libs/libc/string/lib_memcmp.c @@ -30,26 +30,6 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* How many bytes are copied each iteration of the word copy loop. */ - -#define LBLOCKSIZE (sizeof(long)) - -/* Threshhold for punting to the byte copier. */ - -#define TOO_SMALL(len) ((len) < LBLOCKSIZE) - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -59,54 +39,6 @@ no_builtin("memcmp") int memcmp(FAR const void *s1, FAR const void *s2, size_t n) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR unsigned char *p1 = (FAR unsigned char *)s1; - FAR unsigned char *p2 = (FAR unsigned char *)s2; - FAR unsigned long *a1; - FAR unsigned long *a2; - - /* If the size is too small, or either pointer is unaligned, - * then we punt to the byte compare loop. Hopefully this will - * not turn up in inner loops. - */ - - if (!TOO_SMALL(n) && !UNALIGNED(p1, p2)) - { - /* Otherwise, load and compare the blocks of memory one - * word at a time. - */ - - a1 = (FAR unsigned long *)p1; - a2 = (FAR unsigned long *)p2; - while (n >= LBLOCKSIZE) - { - if (*a1 != *a2) - { - break; - } - - a1++; - a2++; - n -= LBLOCKSIZE; - } - - /* check s mod LBLOCKSIZE remaining characters */ - - p1 = (FAR unsigned char *)a1; - p2 = (FAR unsigned char *)a2; - } - - while (n--) - { - if (*p1 != *p2) - { - return *p1 - *p2; - } - - p1++; - p2++; - } -#else FAR unsigned char *p1 = (FAR unsigned char *)s1; FAR unsigned char *p2 = (FAR unsigned char *)s2; @@ -124,7 +56,6 @@ int memcmp(FAR const void *s1, FAR const void *s2, size_t n) p1++; p2++; } -#endif return 0; } diff --git a/libs/libc/string/lib_memcpy.c b/libs/libc/string/lib_memcpy.c index 66367cb2f240b..c1ff6ae1e857f 100644 --- a/libs/libc/string/lib_memcpy.c +++ b/libs/libc/string/lib_memcpy.c @@ -30,30 +30,6 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* How many bytes are copied each iteration of the 4X unrolled loop. */ - -#define BIGBLOCKSIZE (sizeof(long) << 2) - -/* How many bytes are copied each iteration of the word copy loop. */ - -#define LITTLEBLOCKSIZE (sizeof(long)) - -/* Threshhold for punting to the byte copier. */ - -#define TOO_SMALL(len) ((len) < BIGBLOCKSIZE) - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -67,58 +43,12 @@ no_builtin("memcpy") FAR void *memcpy(FAR void *dest, FAR const void *src, size_t n) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR char *pout = dest; - FAR const char *pin = src; - FAR long *paligned_out; - FAR const long *paligned_in; - - /* If the size is small, or either pin or pout is unaligned, - * then punt into the byte copy loop. This should be rare. - */ - - if (!TOO_SMALL(n) && !UNALIGNED(pin, pout)) - { - paligned_out = (FAR long *)pout; - paligned_in = (FAR long *)pin; - - /* Copy 4X long words at a time if possible. */ - - while (n >= BIGBLOCKSIZE) - { - *paligned_out++ = *paligned_in++; - *paligned_out++ = *paligned_in++; - *paligned_out++ = *paligned_in++; - *paligned_out++ = *paligned_in++; - n -= BIGBLOCKSIZE; - } - - /* Copy one long word at a time if possible. */ - - while (n >= LITTLEBLOCKSIZE) - { - *paligned_out++ = *paligned_in++; - n -= LITTLEBLOCKSIZE; - } - - /* Pick up any residual with a byte copier. */ - - pout = (FAR char *)paligned_out; - pin = (FAR char *)paligned_in; - } - - while (n--) - { - *pout++ = *pin++; - } -#else FAR unsigned char *pout = (FAR unsigned char *)dest; FAR unsigned char *pin = (FAR unsigned char *)src; while (n-- > 0) { *pout++ = *pin++; } -#endif return dest; } diff --git a/libs/libc/string/lib_memrchr.c b/libs/libc/string/lib_memrchr.c index e8a07e7565af0..9a8f4a69d6865 100644 --- a/libs/libc/string/lib_memrchr.c +++ b/libs/libc/string/lib_memrchr.c @@ -28,37 +28,6 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE -/* Nonzero if x is not aligned on a "long" boundary. */ - -#define UNALIGNED(x) ((long)(uintptr_t)((x) + 1) & (sizeof(long) - 1)) - -/* How many bytes are loaded each iteration of the word copy loop. */ - -#define LBLOCKSIZE (sizeof(long)) - -/* Threshhold for punting to the bytewise iterator. */ - -#define TOO_SMALL(len) ((len) < LBLOCKSIZE) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#define DETECTCHAR(x, mask) (DETECTNULL((x) ^ (mask))) - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -80,77 +49,6 @@ #undef memrchr /* See mm/README.txt */ FAR void *memrchr(FAR const void *s, int c, size_t n) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR const unsigned char *src0 = - (FAR const unsigned char *)s + n - 1; - FAR unsigned long *asrc; - unsigned char d = c; - unsigned long mask; - unsigned int i; - - while (UNALIGNED(src0)) - { - if (!n--) - { - return NULL; - } - - if (*src0 == d) - { - return (FAR void *)src0; - } - - src0--; - } - - if (!TOO_SMALL(n)) - { - /* If we get this far, we know that n is large and src0 is - * word-aligned. - * The fast code reads the source one word at a time and only - * performs the bytewise search on word-sized segments if they - * contain the search character, which is detected by XORing - * the word-sized segment with a word-sized block of the search - * character and then detecting for the presence of NUL in the - * result. - */ - - asrc = (FAR unsigned long *)(src0 - LBLOCKSIZE + 1); - mask = d << 8 | d; - mask = mask << 16 | mask; - for (i = 32; i < LBLOCKSIZE * 8; i <<= 1) - { - mask = (mask << i) | mask; - } - - while (n >= LBLOCKSIZE) - { - if (DETECTCHAR(*asrc, mask)) - { - break; - } - - n -= LBLOCKSIZE; - asrc--; - } - - /* If there are fewer than LBLOCKSIZE characters left, - * then we resort to the bytewise loop. - */ - - src0 = (FAR unsigned char *)asrc + LBLOCKSIZE - 1; - } - - while (n--) - { - if (*src0 == d) - { - return (FAR void *)src0; - } - - src0--; - } -#else FAR const unsigned char *p = (FAR const unsigned char *)s + n; while (n--) @@ -160,7 +58,6 @@ FAR void *memrchr(FAR const void *s, int c, size_t n) return (FAR void *)p; } } -#endif return NULL; } diff --git a/libs/libc/string/lib_stpcpy.c b/libs/libc/string/lib_stpcpy.c index 8728d4c222f05..ae1a9cbfb9146 100644 --- a/libs/libc/string/lib_stpcpy.c +++ b/libs/libc/string/lib_stpcpy.c @@ -28,28 +28,6 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -69,36 +47,9 @@ #ifndef CONFIG_LIBC_ARCH_STPCPY #undef stpcpy /* See mm/README.txt */ -nosanitize_address FAR char *stpcpy(FAR char *dest, FAR const char *src) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR long *aligned_dst; - FAR const long *aligned_src; - - /* If src or dest is unaligned, then copy bytes. */ - - if (!UNALIGNED(src, dest)) - { - aligned_dst = (FAR long *)dest; - aligned_src = (FAR long *)src; - - /* src and dest are both "long int" aligned, try to do "long int" - * sized copies. - */ - - while (!DETECTNULL(*aligned_src)) - { - *aligned_dst++ = *aligned_src++; - } - - dest = (FAR char *)aligned_dst; - src = (FAR char *)aligned_src; - } -#endif - while ((*dest++ = *src++) != '\0'); - return --dest; } #endif diff --git a/libs/libc/string/lib_stpncpy.c b/libs/libc/string/lib_stpncpy.c index b33c0b77d45b3..acbc1f3a45939 100644 --- a/libs/libc/string/lib_stpncpy.c +++ b/libs/libc/string/lib_stpncpy.c @@ -28,34 +28,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* How many bytes are loaded each iteration of the word copy loop. */ - -#define LBLOCKSIZE (sizeof(long)) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -#define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -#define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#define TOO_SMALL(len) ((len) < sizeof(long)) - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -87,49 +59,6 @@ #undef stpncpy /* See mm/README.txt */ FAR char *stpncpy(FAR char *dest, FAR const char *src, size_t n) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR char *ret = NULL; - FAR long *aligned_dst; - FAR const long *aligned_src; - - /* If src and dest is aligned and n large enough, then copy words. */ - - if (!UNALIGNED(src, dest) && !TOO_SMALL(n)) - { - aligned_dst = (FAR long *)dest; - aligned_src = (FAR long *)src; - - /* src and dest are both "long int" aligned, try to do "long int" - * sized copies. - */ - - while (n >= LBLOCKSIZE && !DETECTNULL(*aligned_src)) - { - n -= LBLOCKSIZE; - *aligned_dst++ = *aligned_src++; - } - - dest = (FAR char *)aligned_dst; - src = (FAR char *)aligned_src; - } - - while (n > 0) - { - --n; - if ((*dest++ = *src++) == '\0') - { - ret = dest - 1; - break; - } - } - - while (n-- > 0) - { - *dest++ = '\0'; - } - - return ret ? ret : dest; -#else FAR char *end = dest + n; /* End of dest buffer + 1 byte */ FAR char *ret; /* Value to be returned */ @@ -162,6 +91,5 @@ FAR char *stpncpy(FAR char *dest, FAR const char *src, size_t n) } return ret; -#endif } #endif diff --git a/libs/libc/string/lib_strcat.c b/libs/libc/string/lib_strcat.c index 175ff66776239..7dcc5e4ee8cb2 100644 --- a/libs/libc/string/lib_strcat.c +++ b/libs/libc/string/lib_strcat.c @@ -30,67 +30,14 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - -#define ALIGNED(x) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) == 0) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ #if !defined(CONFIG_LIBC_ARCH_STRCAT) && defined(LIBC_BUILD_STRCAT) #undef strcat /* See mm/README.txt */ -nosanitize_address FAR char *strcat(FAR char *dest, FAR const char *src) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR char *ret = dest; - - /* Skip over the data in dest as quickly as possible. */ - - if (ALIGNED(dest)) - { - FAR unsigned long *aligned_s1 = (FAR unsigned long *)dest; - while (!DETECTNULL(*aligned_s1)) - { - aligned_s1++; - } - - dest = (FAR char *)aligned_s1; - } - - while (*dest) - { - dest++; - } - - /* dest now points to the its trailing null character, we can - * just use strcpy to do the work for us now. - * ?!? We might want to just include strcpy here. - * Also, this will cause many more unaligned string copies because - * dest is much less likely to be aligned. I don't know if its worth - * tweaking strcpy to handle this better. - */ - - strcpy(dest, src); -#else FAR char *ret = dest; dest += strlen(dest); @@ -100,7 +47,6 @@ FAR char *strcat(FAR char *dest, FAR const char *src) } *dest = '\0'; -#endif return ret; } diff --git a/libs/libc/string/lib_strchr.c b/libs/libc/string/lib_strchr.c index 750a56f3b74a3..98538abbb508f 100644 --- a/libs/libc/string/lib_strchr.c +++ b/libs/libc/string/lib_strchr.c @@ -30,32 +30,6 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - -#define UNALIGNED(x) ((long)(uintptr_t)(x) & (sizeof(long) - 1)) - -/* How many bytes are loaded each iteration of the word copy loop. */ - -#define LBLOCKSIZE (sizeof(long)) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#define DETECTCHAR(x, mask) (DETECTNULL((x) ^ (mask))) - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -76,95 +50,8 @@ #if !defined(CONFIG_LIBC_ARCH_STRCHR) && defined(LIBC_BUILD_STRCHR) #undef strchr /* See mm/README.txt */ -nosanitize_address FAR char *strchr(FAR const char *s, int c) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR const unsigned char *s1 = (FAR const unsigned char *)s; - FAR unsigned long *aligned_addr; - unsigned char i = c; - unsigned long mask; - unsigned long j; - - /* Special case for finding 0. */ - - if (!i) - { - while (UNALIGNED(s1)) - { - if (!*s1) - { - return (FAR char *)s1; - } - - s1++; - } - - /* Operate a word at a time. */ - - aligned_addr = (FAR unsigned long *)s1; - while (!DETECTNULL(*aligned_addr)) - { - aligned_addr++; - } - - /* Found the end of string. */ - - s1 = (FAR const unsigned char *)aligned_addr; - while (*s1) - { - s1++; - } - - return (FAR char *)s1; - } - - /* All other bytes. Align the pointer, then search a long at a time. */ - - while (UNALIGNED(s1)) - { - if (!*s1) - { - return NULL; - } - - if (*s1 == i) - { - return (FAR char *)s1; - } - - s1++; - } - - mask = i; - for (j = 8; j < LBLOCKSIZE * 8; j <<= 1) - { - mask = (mask << j) | mask; - } - - aligned_addr = (FAR unsigned long *)s1; - while (!DETECTNULL(*aligned_addr) && !DETECTCHAR(*aligned_addr, mask)) - { - aligned_addr++; - } - - /* The block of bytes currently pointed to by aligned_addr - * contains either a null or the target char, or both. We - * catch it using the bytewise search. - */ - - s1 = (FAR unsigned char *)aligned_addr; - - while (*s1 && *s1 != i) - { - s1++; - } - - if (*s1 == i) - { - return (FAR char *)s1; - } -#else for (; ; s++) { if (*s == c) @@ -177,7 +64,6 @@ FAR char *strchr(FAR const char *s, int c) break; } } -#endif return NULL; } diff --git a/libs/libc/string/lib_strchrnul.c b/libs/libc/string/lib_strchrnul.c index 9cccb44ce9d13..d8433b695c772 100644 --- a/libs/libc/string/lib_strchrnul.c +++ b/libs/libc/string/lib_strchrnul.c @@ -52,11 +52,6 @@ #undef strchrnul /* See mm/README.txt */ FAR char *strchrnul(FAR const char *s, int c) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR char *s1 = strchr(s, c); - - return s1 ? s1 : (FAR char *)s + strlen(s); -#else if (s) { while (*s != '\0' && *s != c) @@ -66,6 +61,5 @@ FAR char *strchrnul(FAR const char *s, int c) } return (FAR char *)s; -#endif } #endif diff --git a/libs/libc/string/lib_strcmp.c b/libs/libc/string/lib_strcmp.c index 8be2157859879..f445d5f99a2ff 100644 --- a/libs/libc/string/lib_strcmp.c +++ b/libs/libc/string/lib_strcmp.c @@ -30,80 +30,14 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ #if !defined(CONFIG_LIBC_ARCH_STRCMP) && defined(LIBC_BUILD_STRCMP) #undef strcmp /* See mm/README.txt */ -nosanitize_address int strcmp(FAR const char *cs, FAR const char *ct) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR unsigned long *a1; - FAR unsigned long *a2; - - /* If cs or ct are unaligned, then compare bytes. */ - - if (!UNALIGNED(cs, ct)) - { - /* If cs and ct are word-aligned, compare them a word at a time. */ - - a1 = (FAR unsigned long *)cs; - a2 = (FAR unsigned long *)ct; - while (*a1 == *a2) - { - /* To get here, *a1 == *a2, thus if we find a null in *a1, - * then the strings must be equal, so return zero. - */ - - if (DETECTNULL(*a1)) - { - return 0; - } - - a1++; - a2++; - } - - /* A difference was detected in last few bytes of cs, - * so search bytewise. - */ - - cs = (FAR char *)a1; - ct = (FAR char *)a2; - } - - while (*cs != '\0' && *cs == *ct) - { - cs++; - ct++; - } - - return (*(FAR unsigned char *)cs) - (*(FAR unsigned char *)ct); -#else register int result; for (; ; ) { @@ -115,6 +49,5 @@ int strcmp(FAR const char *cs, FAR const char *ct) } return result; -#endif } #endif diff --git a/libs/libc/string/lib_strcpy.c b/libs/libc/string/lib_strcpy.c index d51718d0a656c..38c73c3a48153 100644 --- a/libs/libc/string/lib_strcpy.c +++ b/libs/libc/string/lib_strcpy.c @@ -30,28 +30,6 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -70,42 +48,10 @@ #if !defined(CONFIG_LIBC_ARCH_STRCPY) && defined(LIBC_BUILD_STRCPY) #undef strcpy /* See mm/README.txt */ -nosanitize_address FAR char *strcpy(FAR char *dest, FAR const char *src) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR char *dst0 = dest; - FAR const char *src0 = src; - FAR unsigned long *aligned_dst; - FAR const unsigned long *aligned_src; - - /* If SRC or DEST is unaligned, then copy bytes. */ - - if (!UNALIGNED(src0, dst0)) - { - aligned_dst = (FAR unsigned long *)dst0; - aligned_src = (FAR unsigned long *)src0; - - /* SRC and DEST are both "long int" aligned, try to do "long int" - * sized copies. - */ - - while (!DETECTNULL(*aligned_src)) - { - *aligned_dst++ = *aligned_src++; - } - - dst0 = (FAR char *)aligned_dst; - src0 = (FAR char *)aligned_src; - } - - while ((*dst0++ = *src0++) != '\0'); - - return dest; -#else FAR char *tmp = dest; while ((*dest++ = *src++) != '\0'); return tmp; -#endif } #endif diff --git a/libs/libc/string/lib_strlen.c b/libs/libc/string/lib_strlen.c index b465a1dbfbb9b..594f01a4812ae 100644 --- a/libs/libc/string/lib_strlen.c +++ b/libs/libc/string/lib_strlen.c @@ -30,77 +30,16 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - -#define LBLOCKSIZE (sizeof(long)) -#define UNALIGNED(x) ((long)(uintptr_t)(x) & (LBLOCKSIZE - 1)) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ #if !defined(CONFIG_LIBC_ARCH_STRLEN) && defined(LIBC_BUILD_STRLEN) #undef strlen /* See mm/README.txt */ -nosanitize_address size_t strlen(FAR const char *s) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR const char *start = s; - FAR unsigned long *aligned_addr; - - /* Align the pointer, so we can search a word at a time. */ - - while (UNALIGNED(s)) - { - if (!*s) - { - return s - start; - } - - s++; - } - - /* If the string is word-aligned, we can check for the presence of - * a null in each word-sized block. - */ - - aligned_addr = (FAR unsigned long *)s; - while (!DETECTNULL(*aligned_addr)) - { - aligned_addr++; - } - - /* Once a null is detected, we check each byte in that block for a - * precise position of the null. - */ - - s = (FAR char *)aligned_addr; - while (*s) - { - s++; - } - - return s - start; -#else FAR const char *sc; for (sc = s; *sc != '\0'; ++sc); return sc - s; -#endif } #endif diff --git a/libs/libc/string/lib_strncmp.c b/libs/libc/string/lib_strncmp.c index 92f79e957e137..e46c7abbceab9 100644 --- a/libs/libc/string/lib_strncmp.c +++ b/libs/libc/string/lib_strncmp.c @@ -30,99 +30,14 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - -#define LBLOCKSIZE (sizeof(long)) - -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ #if !defined(CONFIG_LIBC_ARCH_STRNCMP) && defined(LIBC_BUILD_STRNCMP) #undef strncmp /* See mm/README.txt */ -nosanitize_address int strncmp(FAR const char *cs, FAR const char *ct, size_t nb) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR unsigned long *a1; - FAR unsigned long *a2; - - if (nb == 0) - { - return 0; - } - - /* If cs or ct are unaligned, then compare bytes. */ - - if (!UNALIGNED(cs, ct)) - { - /* If cs and ct are word-aligned, compare them a word at a time. */ - - a1 = (FAR unsigned long *)cs; - a2 = (FAR unsigned long *)ct; - while (nb >= LBLOCKSIZE && *a1 == *a2) - { - nb -= LBLOCKSIZE; - - /* If we've run out of bytes or hit a null, return zero - * since we already know *a1 == *a2. - */ - - if (nb == 0 || DETECTNULL(*a1)) - { - return 0; - } - - a1++; - a2++; - } - - /* A difference was detected in last few bytes of cs, so search - * bytewise. - */ - - cs = (FAR char *)a1; - ct = (FAR char *)a2; - } - - while (nb-- > 0 && *cs == *ct) - { - /* If we've run out of bytes or hit a null, return zero - * since we already know *cs == *ct. - */ - - if (nb == 0 || *cs == '\0') - { - return 0; - } - - cs++; - ct++; - } - - return *cs - *ct; -#else register int result = 0; for (; nb > 0; nb--) { @@ -134,6 +49,5 @@ int strncmp(FAR const char *cs, FAR const char *ct, size_t nb) } return result; -#endif } #endif diff --git a/libs/libc/string/lib_strncpy.c b/libs/libc/string/lib_strncpy.c index 29a903e92ba20..3e36df4ff53d9 100644 --- a/libs/libc/string/lib_strncpy.c +++ b/libs/libc/string/lib_strncpy.c @@ -30,33 +30,6 @@ #include "libc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - -#define LBLOCKSIZE (sizeof(long)) - -/* Nonzero if either x or y is not aligned on a "long" boundary. */ - -#define UNALIGNED(x, y) \ - (((long)(uintptr_t)(x) & (sizeof(long) - 1)) | ((long)(uintptr_t)(y) & (sizeof(long) - 1))) - -/* Macros for detecting endchar */ - -#if LONG_MAX == 2147483647 -# define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) -#elif LONG_MAX == 9223372036854775807 -/* Nonzero if x (a long int) contains a NULL byte. */ - -# define DETECTNULL(x) (((x) - 0x0101010101010101) & ~(x) & 0x8080808080808080) -#endif - -#define TOO_SMALL(len) ((len) < sizeof(long)) - -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -84,52 +57,8 @@ #if !defined(CONFIG_LIBC_ARCH_STRNCPY) && defined(LIBC_BUILD_STRNCPY) #undef strncpy /* See mm/README.txt */ -nosanitize_address FAR char *strncpy(FAR char *dest, FAR const char *src, size_t n) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR char *dst0 = dest; - FAR const char *src0 = src; - FAR long *aligned_dst; - FAR const long *aligned_src; - - /* If src and dest is aligned and n large enough, then copy words. */ - - if (!UNALIGNED(src0, dst0) && !TOO_SMALL(n)) - { - aligned_dst = (FAR long *)dst0; - aligned_src = (FAR long *)src0; - - /* src and dest are both "long int" aligned, try to do "long int" - * sized copies. - */ - - while (n >= LBLOCKSIZE && !DETECTNULL(*aligned_src)) - { - n -= LBLOCKSIZE; - *aligned_dst++ = *aligned_src++; - } - - dst0 = (FAR char *)aligned_dst; - src0 = (FAR char *)aligned_src; - } - - while (n > 0) - { - --n; - if ((*dst0++ = *src0++) == '\0') - { - break; - } - } - - while (n-- > 0) - { - *dst0++ = '\0'; - } - - return dest; -#else FAR char *ret = dest; /* Value to be returned */ FAR char *end = dest + n; /* End of dest buffer + 1 byte */ @@ -151,6 +80,5 @@ FAR char *strncpy(FAR char *dest, FAR const char *src, size_t n) } return ret; -#endif } #endif diff --git a/libs/libc/string/lib_strrchr.c b/libs/libc/string/lib_strrchr.c index a448f2775750d..d19afc743bc5c 100644 --- a/libs/libc/string/lib_strrchr.c +++ b/libs/libc/string/lib_strrchr.c @@ -42,24 +42,6 @@ #undef strrchr /* See mm/README.txt */ FAR char *strrchr(FAR const char *s, int c) { -#ifdef CONFIG_LIBC_STRING_OPTIMIZE - FAR const char *last = NULL; - - if (c) - { - while ((s = strchr(s, c))) - { - last = s; - s++; - } - } - else - { - last = strchr(s, c); - } - - return (FAR char *)last; -#else FAR const char *r = NULL; do @@ -72,6 +54,5 @@ FAR char *strrchr(FAR const char *s, int c) while (*s++ != '\0'); return (FAR char *)r; -#endif } #endif diff --git a/libs/libxx/Kconfig b/libs/libxx/Kconfig index 27e41cad4f491..62618e15bb603 100644 --- a/libs/libxx/Kconfig +++ b/libs/libxx/Kconfig @@ -67,12 +67,11 @@ config ETL Implements C++ templates such as containers, string singleton math without C++ STL libraries -if LIBCXX || UCLIBCXX +if !LIBCXXMINI choice prompt "C++ low level library select" - default LIBCXXABI if LIBCXX - default LIBSUPCXX + default LIBSUPCXX_TOOLCHAIN config LIBCXXABI bool "LLVM low level C++ Library" @@ -82,21 +81,27 @@ config LIBCXXABI Select if your use libc++abi as lower level c++ library config LIBSUPCXX + bool "GNU compile low level libsupc++" + ---help--- + Select if your compile libsupc++ and use libsupc++ as lower + level c++ library. + +config LIBSUPCXX_TOOLCHAIN bool "GNU low level libsupc++" ---help--- - Select if your toolchain provides libsupc++ and use libsupc++ as lower + Select if your toolchain provides libsupc++ and use toolchain libsupc++ as lower level c++ library. endchoice +endif + config LIBCXXABI_VERSION string "Select libcxxabi version" depends on LIBCXXABI default LIBCXX_VERSION if LIBCXX default "17.0.6" if !LIBCXX -endif - config CXX_STANDARD string "Language standard" default "gnu++20" if LIBCXX diff --git a/libs/libxx/libcxx.cmake b/libs/libxx/libcxx.cmake index 1d7e79e4bef91..9b4c3fee88d80 100644 --- a/libs/libxx/libcxx.cmake +++ b/libs/libxx/libcxx.cmake @@ -73,6 +73,10 @@ set_property( PROPERTY NUTTX_CXX_INCLUDE_DIRECTORIES ${CMAKE_BINARY_DIR}/include/libcxx) add_compile_definitions(_LIBCPP_BUILDING_LIBRARY) +if(CONFIG_LIBSUPCXX_TOOLCHAIN) + add_compile_definitions(__GLIBCXX__) +endif() + if(CONFIG_LIBSUPCXX) add_compile_definitions(__GLIBCXX__) endif() diff --git a/libs/libxx/libcxx.defs b/libs/libxx/libcxx.defs index 730b898b23a95..717af3489e628 100644 --- a/libs/libxx/libcxx.defs +++ b/libs/libxx/libcxx.defs @@ -54,7 +54,11 @@ endif CXXFLAGS += ${DEFINE_PREFIX}_LIBCPP_BUILDING_LIBRARY CXXFLAGS += ${INCDIR_PREFIX}$(CURDIR)/libcxx/src -ifeq ($(CONFIG_LIBSUPCXX), y) +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) +CXXFLAGS += ${DEFINE_PREFIX}__GLIBCXX__ +endif + +ifeq ($(CONFIG_LIBSUPCXX),y) CXXFLAGS += ${DEFINE_PREFIX}__GLIBCXX__ endif diff --git a/sched/misc/coredump.c b/sched/misc/coredump.c index 13947390cbc63..4f39b51fa4fc7 100644 --- a/sched/misc/coredump.c +++ b/sched/misc/coredump.c @@ -768,7 +768,8 @@ int coredump_set_memory_region(FAR const struct memory_region_s *region) * ****************************************************************************/ -int coredump_add_memory_region(FAR const void *ptr, size_t size) +int coredump_add_memory_region(FAR const void *ptr, size_t size, + uint32_t flags) { FAR struct memory_region_s *region; size_t count = 1; /* 1 for end flag */ @@ -838,7 +839,7 @@ int coredump_add_memory_region(FAR const void *ptr, size_t size) region[count - 1].start = (uintptr_t)ptr; region[count - 1].end = (uintptr_t)ptr + size; - region[count - 1].flags = 0; + region[count - 1].flags = flags; region[count].start = 0; region[count].end = 0; region[count].flags = 0; diff --git a/sched/task/task_exit.c b/sched/task/task_exit.c index b4bb1b84019b4..9a021849eba9e 100644 --- a/sched/task/task_exit.c +++ b/sched/task/task_exit.c @@ -29,6 +29,8 @@ #include #include +#include + #include "sched/sched.h" #ifdef CONFIG_SMP @@ -141,6 +143,7 @@ int nxtask_exit(void) #endif dtcb->task_state = TSTATE_TASK_INACTIVE; + sched_note_stop(dtcb); ret = nxsched_release_tcb(dtcb, dtcb->flags & TCB_FLAG_TTYPE_MASK); #ifdef CONFIG_SMP