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On further reflection, the original is not "wrong", it's just unfortunately incomplete. The original declared DATA register is the right one to manipulate all pins at once; the declaration simply fails to provide a way to use the underlying hardware's ability to affect a subset of the pins. Too bad.
Thanks for making these available; I've been unable to get SVD or CMSIS information from TI directly. Can you say where you obtained them?
Reason I ask is the GPIOA_Type declarations have:
I feel reasonably certain this is wrong, and that the correct declaration is:
which permits bit-banded access to pins 0 and 2 through (for example) GPIOA->DATA[0x05].
I'd like to see the SVD to try to confirm my understanding of how the map is supposed to be used.
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