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common.cpp
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common.cpp
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#include "pdbaccess.hpp"
//----------------------------------------------------------------------------
static const char g_spath_prefix[] = "srv*";
static const char g_spath_suffix[] = "*http://msdl.microsoft.com/download/symbols";
//----------------------------------------------------------------------------
HRESULT pdb_access_t::iterate_subtags(
pdb_sym_t &sym,
enum SymTagEnum type,
children_visitor_t &visitor)
{
struct subtag_helper_t : children_visitor_t
{
pdb_access_t *tb;
enum SymTagEnum type;
children_visitor_t &visitor;
virtual HRESULT visit_child(pdb_sym_t &_sym) override
{
return tb->iterate_children(_sym, type, visitor);
}
subtag_helper_t(pdb_access_t *_tb, enum SymTagEnum t, children_visitor_t &_visitor)
: tb(_tb),
type(t),
visitor(_visitor) {}
};
subtag_helper_t helper(this, type, visitor);
return iterate_children(sym, SymTagCompiland, helper);
}
//----------------------------------------------------------------------------
HRESULT pdb_access_t::iterate_children(
pdb_sym_t &sym,
enum SymTagEnum type,
children_visitor_t &visitor)
{
visitor.parent = &sym;
return do_iterate_children(sym, type, visitor);
}
//----------------------------------------------------------------------
void print_pdb_register(qstring *out, int machine, int reg)
{
// Register subset shared by all processor types,
switch ( reg )
{
case CV_ALLREG_ERR: *out = "[*err*]"; return;
case CV_ALLREG_TEB: *out = "[*teb*]"; return;
case CV_ALLREG_TIMER: *out = "[*timer*]"; return;
case CV_ALLREG_EFAD1: *out = "[*efad1*]"; return;
case CV_ALLREG_EFAD2: *out = "[*efad2*]"; return;
case CV_ALLREG_EFAD3: *out = "[*efad3*]"; return;
case CV_ALLREG_VFRAME: *out = "[*vframe*]"; return;
case CV_ALLREG_HANDLE: *out = "[*handle*]"; return;
case CV_ALLREG_PARAMS: *out = "[*params*]"; return;
case CV_ALLREG_LOCALS: *out = "[*locals*]"; return;
case CV_ALLREG_TID: *out = "[*tid*]"; return;
case CV_ALLREG_ENV: *out = "[*env*]"; return;
case CV_ALLREG_CMDLN: *out = "[*cmdln*]"; return;
}
// Processor specific subsets
switch ( machine )
{
case CV_CFL_8080:
case CV_CFL_8086:
case CV_CFL_80286:
case CV_CFL_80386:
case CV_CFL_80486:
case CV_CFL_PENTIUM:
case CV_CFL_PENTIUMII:
case CV_CFL_PENTIUMIII:
// Register set for the Intel 80x86 and ix86 processor series
// (plus PCODE registers)
switch ( reg )
{
case CV_REG_NONE: *out = "none"; return;
case CV_REG_AL: *out = "al"; return;
case CV_REG_CL: *out = "cl"; return;
case CV_REG_DL: *out = "dl"; return;
case CV_REG_BL: *out = "bl"; return;
case CV_REG_AH: *out = "ah"; return;
case CV_REG_CH: *out = "ch"; return;
case CV_REG_DH: *out = "dh"; return;
case CV_REG_BH: *out = "bh"; return;
case CV_REG_AX: *out = "ax"; return;
case CV_REG_CX: *out = "cx"; return;
case CV_REG_DX: *out = "dx"; return;
case CV_REG_BX: *out = "bx"; return;
case CV_REG_SP: *out = "sp"; return;
case CV_REG_BP: *out = "bp"; return;
case CV_REG_SI: *out = "si"; return;
case CV_REG_DI: *out = "di"; return;
case CV_REG_EAX: *out = "eax"; return;
case CV_REG_ECX: *out = "ecx"; return;
case CV_REG_EDX: *out = "edx"; return;
case CV_REG_EBX: *out = "ebx"; return;
case CV_REG_ESP: *out = "esp"; return;
case CV_REG_EBP: *out = "ebp"; return;
case CV_REG_ESI: *out = "esi"; return;
case CV_REG_EDI: *out = "edi"; return;
case CV_REG_ES: *out = "es"; return;
case CV_REG_CS: *out = "cs"; return;
case CV_REG_SS: *out = "ss"; return;
case CV_REG_DS: *out = "ds"; return;
case CV_REG_FS: *out = "fs"; return;
case CV_REG_GS: *out = "gs"; return;
case CV_REG_IP: *out = "ip"; return;
case CV_REG_FLAGS: *out = "flags"; return;
case CV_REG_EIP: *out = "eip"; return;
case CV_REG_EFLAGS: *out = "eflags"; return;
case CV_REG_TEMP: *out = "temp"; return; // PCODE Temp return;
case CV_REG_TEMPH: *out = "temph"; return; // PCODE TempH return;
case CV_REG_QUOTE: *out = "quote"; return; // PCODE Quote return;
case CV_REG_PCDR3: *out = "pcdr3"; return; // PCODE reserved return;
case CV_REG_PCDR4: *out = "pcdr4"; return; // PCODE reserved return;
case CV_REG_PCDR5: *out = "pcdr5"; return; // PCODE reserved return;
case CV_REG_PCDR6: *out = "pcdr6"; return; // PCODE reserved return;
case CV_REG_PCDR7: *out = "pcdr7"; return; // PCODE reserved return;
case CV_REG_CR0: *out = "cr0"; return; // CR0 -- control registers return;
case CV_REG_CR1: *out = "cr1"; return;
case CV_REG_CR2: *out = "cr2"; return;
case CV_REG_CR3: *out = "cr3"; return;
case CV_REG_CR4: *out = "cr4"; return; // Pentium return;
case CV_REG_DR0: *out = "dr0"; return; // Debug register return;
case CV_REG_DR1: *out = "dr1"; return;
case CV_REG_DR2: *out = "dr2"; return;
case CV_REG_DR3: *out = "dr3"; return;
case CV_REG_DR4: *out = "dr4"; return;
case CV_REG_DR5: *out = "dr5"; return;
case CV_REG_DR6: *out = "dr6"; return;
case CV_REG_DR7: *out = "dr7"; return;
case CV_REG_GDTR: *out = "gdtr"; return;
case CV_REG_GDTL: *out = "gdtl"; return;
case CV_REG_IDTR: *out = "idtr"; return;
case CV_REG_IDTL: *out = "idtl"; return;
case CV_REG_LDTR: *out = "ldtr"; return;
case CV_REG_TR: *out = "tr"; return;
case CV_REG_PSEUDO1: *out = "pseudo1"; return;
case CV_REG_PSEUDO2: *out = "pseudo2"; return;
case CV_REG_PSEUDO3: *out = "pseudo3"; return;
case CV_REG_PSEUDO4: *out = "pseudo4"; return;
case CV_REG_PSEUDO5: *out = "pseudo5"; return;
case CV_REG_PSEUDO6: *out = "pseudo6"; return;
case CV_REG_PSEUDO7: *out = "pseudo7"; return;
case CV_REG_PSEUDO8: *out = "pseudo8"; return;
case CV_REG_PSEUDO9: *out = "pseudo9"; return;
case CV_REG_ST0: *out = "st0"; return;
case CV_REG_ST1: *out = "st1"; return;
case CV_REG_ST2: *out = "st2"; return;
case CV_REG_ST3: *out = "st3"; return;
case CV_REG_ST4: *out = "st4"; return;
case CV_REG_ST5: *out = "st5"; return;
case CV_REG_ST6: *out = "st6"; return;
case CV_REG_ST7: *out = "st7"; return;
case CV_REG_CTRL: *out = "ctrl"; return;
case CV_REG_STAT: *out = "stat"; return;
case CV_REG_TAG: *out = "tag"; return;
case CV_REG_FPIP: *out = "fpip"; return;
case CV_REG_FPCS: *out = "fpcs"; return;
case CV_REG_FPDO: *out = "fpdo"; return;
case CV_REG_FPDS: *out = "fpds"; return;
case CV_REG_ISEM: *out = "isem"; return;
case CV_REG_FPEIP: *out = "fpeip"; return;
case CV_REG_FPEDO: *out = "fpedo"; return;
case CV_REG_MM0: *out = "mm0"; return;
case CV_REG_MM1: *out = "mm1"; return;
case CV_REG_MM2: *out = "mm2"; return;
case CV_REG_MM3: *out = "mm3"; return;
case CV_REG_MM4: *out = "mm4"; return;
case CV_REG_MM5: *out = "mm5"; return;
case CV_REG_MM6: *out = "mm6"; return;
case CV_REG_MM7: *out = "mm7"; return;
case CV_REG_XMM0: *out = "xmm0"; return; // KATMAI registers return;
case CV_REG_XMM1: *out = "xmm1"; return;
case CV_REG_XMM2: *out = "xmm2"; return;
case CV_REG_XMM3: *out = "xmm3"; return;
case CV_REG_XMM4: *out = "xmm4"; return;
case CV_REG_XMM5: *out = "xmm5"; return;
case CV_REG_XMM6: *out = "xmm6"; return;
case CV_REG_XMM7: *out = "xmm7"; return;
case CV_REG_XMM00: *out = "xmm00"; return; // KATMAI sub-registers return;
case CV_REG_XMM01: *out = "xmm01"; return;
case CV_REG_XMM02: *out = "xmm02"; return;
case CV_REG_XMM03: *out = "xmm03"; return;
case CV_REG_XMM10: *out = "xmm10"; return;
case CV_REG_XMM11: *out = "xmm11"; return;
case CV_REG_XMM12: *out = "xmm12"; return;
case CV_REG_XMM13: *out = "xmm13"; return;
case CV_REG_XMM20: *out = "xmm20"; return;
case CV_REG_XMM21: *out = "xmm21"; return;
case CV_REG_XMM22: *out = "xmm22"; return;
case CV_REG_XMM23: *out = "xmm23"; return;
case CV_REG_XMM30: *out = "xmm30"; return;
case CV_REG_XMM31: *out = "xmm31"; return;
case CV_REG_XMM32: *out = "xmm32"; return;
case CV_REG_XMM33: *out = "xmm33"; return;
case CV_REG_XMM40: *out = "xmm40"; return;
case CV_REG_XMM41: *out = "xmm41"; return;
case CV_REG_XMM42: *out = "xmm42"; return;
case CV_REG_XMM43: *out = "xmm43"; return;
case CV_REG_XMM50: *out = "xmm50"; return;
case CV_REG_XMM51: *out = "xmm51"; return;
case CV_REG_XMM52: *out = "xmm52"; return;
case CV_REG_XMM53: *out = "xmm53"; return;
case CV_REG_XMM60: *out = "xmm60"; return;
case CV_REG_XMM61: *out = "xmm61"; return;
case CV_REG_XMM62: *out = "xmm62"; return;
case CV_REG_XMM63: *out = "xmm63"; return;
case CV_REG_XMM70: *out = "xmm70"; return;
case CV_REG_XMM71: *out = "xmm71"; return;
case CV_REG_XMM72: *out = "xmm72"; return;
case CV_REG_XMM73: *out = "xmm73"; return;
case CV_REG_XMM0L: *out = "xmm0l"; return;
case CV_REG_XMM1L: *out = "xmm1l"; return;
case CV_REG_XMM2L: *out = "xmm2l"; return;
case CV_REG_XMM3L: *out = "xmm3l"; return;
case CV_REG_XMM4L: *out = "xmm4l"; return;
case CV_REG_XMM5L: *out = "xmm5l"; return;
case CV_REG_XMM6L: *out = "xmm6l"; return;
case CV_REG_XMM7L: *out = "xmm7l"; return;
case CV_REG_XMM0H: *out = "xmm0h"; return;
case CV_REG_XMM1H: *out = "xmm1h"; return;
case CV_REG_XMM2H: *out = "xmm2h"; return;
case CV_REG_XMM3H: *out = "xmm3h"; return;
case CV_REG_XMM4H: *out = "xmm4h"; return;
case CV_REG_XMM5H: *out = "xmm5h"; return;
case CV_REG_XMM6H: *out = "xmm6h"; return;
case CV_REG_XMM7H: *out = "xmm7h"; return;
case CV_REG_MXCSR: *out = "mxcsr"; return; // XMM status register
case CV_REG_EDXEAX: *out = "edxeax"; return; // EDX";EAX pair
case CV_REG_EMM0L: *out = "emm0l"; return; // XMM sub-registers (WNI integer)
case CV_REG_EMM1L: *out = "emm1l"; return;
case CV_REG_EMM2L: *out = "emm2l"; return;
case CV_REG_EMM3L: *out = "emm3l"; return;
case CV_REG_EMM4L: *out = "emm4l"; return;
case CV_REG_EMM5L: *out = "emm5l"; return;
case CV_REG_EMM6L: *out = "emm6l"; return;
case CV_REG_EMM7L: *out = "emm7l"; return;
case CV_REG_EMM0H: *out = "emm0h"; return;
case CV_REG_EMM1H: *out = "emm1h"; return;
case CV_REG_EMM2H: *out = "emm2h"; return;
case CV_REG_EMM3H: *out = "emm3h"; return;
case CV_REG_EMM4H: *out = "emm4h"; return;
case CV_REG_EMM5H: *out = "emm5h"; return;
case CV_REG_EMM6H: *out = "emm6h"; return;
case CV_REG_EMM7H: *out = "emm7h"; return;
case CV_REG_MM00: *out = "mm00"; return; // do not change the order of these regs, first one must be even too
case CV_REG_MM01: *out = "mm01"; return;
case CV_REG_MM10: *out = "mm10"; return;
case CV_REG_MM11: *out = "mm11"; return;
case CV_REG_MM20: *out = "mm20"; return;
case CV_REG_MM21: *out = "mm21"; return;
case CV_REG_MM30: *out = "mm30"; return;
case CV_REG_MM31: *out = "mm31"; return;
case CV_REG_MM40: *out = "mm40"; return;
case CV_REG_MM41: *out = "mm41"; return;
case CV_REG_MM50: *out = "mm50"; return;
case CV_REG_MM51: *out = "mm51"; return;
case CV_REG_MM60: *out = "mm60"; return;
case CV_REG_MM61: *out = "mm61"; return;
case CV_REG_MM70: *out = "mm70"; return;
case CV_REG_MM71: *out = "mm71"; return;
}
break;
// registers for the 68K processors
case CV_CFL_M68000:
case CV_CFL_M68010:
case CV_CFL_M68020:
case CV_CFL_M68030:
case CV_CFL_M68040:
switch ( reg )
{
case CV_R68_D0: *out = "D0"; return;
case CV_R68_D1: *out = "D1"; return;
case CV_R68_D2: *out = "D2"; return;
case CV_R68_D3: *out = "D3"; return;
case CV_R68_D4: *out = "D4"; return;
case CV_R68_D5: *out = "D5"; return;
case CV_R68_D6: *out = "D6"; return;
case CV_R68_D7: *out = "D7"; return;
case CV_R68_A0: *out = "A0"; return;
case CV_R68_A1: *out = "A1"; return;
case CV_R68_A2: *out = "A2"; return;
case CV_R68_A3: *out = "A3"; return;
case CV_R68_A4: *out = "A4"; return;
case CV_R68_A5: *out = "A5"; return;
case CV_R68_A6: *out = "A6"; return;
case CV_R68_A7: *out = "A7"; return;
case CV_R68_CCR: *out = "CCR"; return;
case CV_R68_SR: *out = "SR"; return;
case CV_R68_USP: *out = "USP"; return;
case CV_R68_MSP: *out = "MSP"; return;
case CV_R68_SFC: *out = "SFC"; return;
case CV_R68_DFC: *out = "DFC"; return;
case CV_R68_CACR: *out = "CACR"; return;
case CV_R68_VBR: *out = "VBR"; return;
case CV_R68_CAAR: *out = "CAAR"; return;
case CV_R68_ISP: *out = "ISP"; return;
case CV_R68_PC: *out = "PC"; return;
// reserved 27
case CV_R68_FPCR: *out = "FPCR"; return;
case CV_R68_FPSR: *out = "FPSR"; return;
case CV_R68_FPIAR: *out = "FPIAR"; return;
// reserved 31
case CV_R68_FP0: *out = "FP0"; return;
case CV_R68_FP1: *out = "FP1"; return;
case CV_R68_FP2: *out = "FP2"; return;
case CV_R68_FP3: *out = "FP3"; return;
case CV_R68_FP4: *out = "FP4"; return;
case CV_R68_FP5: *out = "FP5"; return;
case CV_R68_FP6: *out = "FP6"; return;
case CV_R68_FP7: *out = "FP7"; return;
// reserved 40
case CV_R68_MMUSR030:*out = "MMUSR030"; return;
case CV_R68_MMUSR: *out = "MMUSR"; return;
case CV_R68_URP: *out = "URP"; return;
case CV_R68_DTT0: *out = "DTT0"; return;
case CV_R68_DTT1: *out = "DTT1"; return;
case CV_R68_ITT0: *out = "ITT0"; return;
case CV_R68_ITT1: *out = "ITT1"; return;
// reserved 50
case CV_R68_PSR: *out = "PSR"; return;
case CV_R68_PCSR: *out = "PCSR"; return;
case CV_R68_VAL: *out = "VAL"; return;
case CV_R68_CRP: *out = "CRP"; return;
case CV_R68_SRP: *out = "SRP"; return;
case CV_R68_DRP: *out = "DRP"; return;
case CV_R68_TC: *out = "TC"; return;
case CV_R68_AC: *out = "AC"; return;
case CV_R68_SCC: *out = "SCC"; return;
case CV_R68_CAL: *out = "CAL"; return;
case CV_R68_TT0: *out = "TT0"; return;
case CV_R68_TT1: *out = "TT1"; return;
// reserved 63
case CV_R68_BAD0: *out = "BAD0"; return;
case CV_R68_BAD1: *out = "BAD1"; return;
case CV_R68_BAD2: *out = "BAD2"; return;
case CV_R68_BAD3: *out = "BAD3"; return;
case CV_R68_BAD4: *out = "BAD4"; return;
case CV_R68_BAD5: *out = "BAD5"; return;
case CV_R68_BAD6: *out = "BAD6"; return;
case CV_R68_BAD7: *out = "BAD7"; return;
case CV_R68_BAC0: *out = "BAC0"; return;
case CV_R68_BAC1: *out = "BAC1"; return;
case CV_R68_BAC2: *out = "BAC2"; return;
case CV_R68_BAC3: *out = "BAC3"; return;
case CV_R68_BAC4: *out = "BAC4"; return;
case CV_R68_BAC5: *out = "BAC5"; return;
case CV_R68_BAC6: *out = "BAC6"; return;
case CV_R68_BAC7: *out = "BAC7"; return;
}
break;
case CV_CFL_MIPS:
case CV_CFL_MIPS16:
case CV_CFL_MIPS32:
case CV_CFL_MIPS64:
case CV_CFL_MIPSI:
case CV_CFL_MIPSII:
case CV_CFL_MIPSIII:
case CV_CFL_MIPSIV:
case CV_CFL_MIPSV:
switch ( reg )
{
// Register set for the MIPS 4000
case CV_M4_NOREG: *out = "NOREG"; return;
case CV_M4_IntZERO: *out = "IntZERO"; return; /* CPU REGISTER */
case CV_M4_IntAT: *out = "IntAT"; return;
case CV_M4_IntV0: *out = "IntV0"; return;
case CV_M4_IntV1: *out = "IntV1"; return;
case CV_M4_IntA0: *out = "IntA0"; return;
case CV_M4_IntA1: *out = "IntA1"; return;
case CV_M4_IntA2: *out = "IntA2"; return;
case CV_M4_IntA3: *out = "IntA3"; return;
case CV_M4_IntT0: *out = "IntT0"; return;
case CV_M4_IntT1: *out = "IntT1"; return;
case CV_M4_IntT2: *out = "IntT2"; return;
case CV_M4_IntT3: *out = "IntT3"; return;
case CV_M4_IntT4: *out = "IntT4"; return;
case CV_M4_IntT5: *out = "IntT5"; return;
case CV_M4_IntT6: *out = "IntT6"; return;
case CV_M4_IntT7: *out = "IntT7"; return;
case CV_M4_IntS0: *out = "IntS0"; return;
case CV_M4_IntS1: *out = "IntS1"; return;
case CV_M4_IntS2: *out = "IntS2"; return;
case CV_M4_IntS3: *out = "IntS3"; return;
case CV_M4_IntS4: *out = "IntS4"; return;
case CV_M4_IntS5: *out = "IntS5"; return;
case CV_M4_IntS6: *out = "IntS6"; return;
case CV_M4_IntS7: *out = "IntS7"; return;
case CV_M4_IntT8: *out = "IntT8"; return;
case CV_M4_IntT9: *out = "IntT9"; return;
case CV_M4_IntKT0: *out = "IntKT0"; return;
case CV_M4_IntKT1: *out = "IntKT1"; return;
case CV_M4_IntGP: *out = "IntGP"; return;
case CV_M4_IntSP: *out = "IntSP"; return;
case CV_M4_IntS8: *out = "IntS8"; return;
case CV_M4_IntRA: *out = "IntRA"; return;
case CV_M4_IntLO: *out = "IntLO"; return;
case CV_M4_IntHI: *out = "IntHI"; return;
case CV_M4_Fir:
case CV_M4_Psr:
case CV_M4_FltF0: *out = "FltF0"; return; /* Floating point registers */
case CV_M4_FltF1: *out = "FltF1"; return;
case CV_M4_FltF2: *out = "FltF2"; return;
case CV_M4_FltF3: *out = "FltF3"; return;
case CV_M4_FltF4: *out = "FltF4"; return;
case CV_M4_FltF5: *out = "FltF5"; return;
case CV_M4_FltF6: *out = "FltF6"; return;
case CV_M4_FltF7: *out = "FltF7"; return;
case CV_M4_FltF8: *out = "FltF8"; return;
case CV_M4_FltF9: *out = "FltF9"; return;
case CV_M4_FltF10: *out = "FltF10"; return;
case CV_M4_FltF11: *out = "FltF11"; return;
case CV_M4_FltF12: *out = "FltF12"; return;
case CV_M4_FltF13: *out = "FltF13"; return;
case CV_M4_FltF14: *out = "FltF14"; return;
case CV_M4_FltF15: *out = "FltF15"; return;
case CV_M4_FltF16: *out = "FltF16"; return;
case CV_M4_FltF17: *out = "FltF17"; return;
case CV_M4_FltF18: *out = "FltF18"; return;
case CV_M4_FltF19: *out = "FltF19"; return;
case CV_M4_FltF20: *out = "FltF20"; return;
case CV_M4_FltF21: *out = "FltF21"; return;
case CV_M4_FltF22: *out = "FltF22"; return;
case CV_M4_FltF23: *out = "FltF23"; return;
case CV_M4_FltF24: *out = "FltF24"; return;
case CV_M4_FltF25: *out = "FltF25"; return;
case CV_M4_FltF26: *out = "FltF26"; return;
case CV_M4_FltF27: *out = "FltF27"; return;
case CV_M4_FltF28: *out = "FltF28"; return;
case CV_M4_FltF29: *out = "FltF29"; return;
case CV_M4_FltF30: *out = "FltF30"; return;
case CV_M4_FltF31: *out = "FltF31"; return;
case CV_M4_FltFsr: *out = "FltFsr"; return;
}
break;
case CV_CFL_ALPHA:
// case CV_CFL_ALPHA_21064:
case CV_CFL_ALPHA_21164:
case CV_CFL_ALPHA_21164A:
case CV_CFL_ALPHA_21264:
case CV_CFL_ALPHA_21364:
// Register set for the ALPHA AXP
switch ( reg )
{
case CV_ALPHA_NOREG: *out = "NOREG"; return;
case CV_ALPHA_FltF0: *out = "FltF0"; return; // Floating point registers
case CV_ALPHA_FltF1: *out = "FltF1"; return;
case CV_ALPHA_FltF2: *out = "FltF2"; return;
case CV_ALPHA_FltF3: *out = "FltF3"; return;
case CV_ALPHA_FltF4: *out = "FltF4"; return;
case CV_ALPHA_FltF5: *out = "FltF5"; return;
case CV_ALPHA_FltF6: *out = "FltF6"; return;
case CV_ALPHA_FltF7: *out = "FltF7"; return;
case CV_ALPHA_FltF8: *out = "FltF8"; return;
case CV_ALPHA_FltF9: *out = "FltF9"; return;
case CV_ALPHA_FltF10:*out = "FltF10"; return;
case CV_ALPHA_FltF11:*out = "FltF11"; return;
case CV_ALPHA_FltF12:*out = "FltF12"; return;
case CV_ALPHA_FltF13:*out = "FltF13"; return;
case CV_ALPHA_FltF14:*out = "FltF14"; return;
case CV_ALPHA_FltF15:*out = "FltF15"; return;
case CV_ALPHA_FltF16:*out = "FltF16"; return;
case CV_ALPHA_FltF17:*out = "FltF17"; return;
case CV_ALPHA_FltF18:*out = "FltF18"; return;
case CV_ALPHA_FltF19:*out = "FltF19"; return;
case CV_ALPHA_FltF20:*out = "FltF20"; return;
case CV_ALPHA_FltF21:*out = "FltF21"; return;
case CV_ALPHA_FltF22:*out = "FltF22"; return;
case CV_ALPHA_FltF23:*out = "FltF23"; return;
case CV_ALPHA_FltF24:*out = "FltF24"; return;
case CV_ALPHA_FltF25:*out = "FltF25"; return;
case CV_ALPHA_FltF26:*out = "FltF26"; return;
case CV_ALPHA_FltF27:*out = "FltF27"; return;
case CV_ALPHA_FltF28:*out = "FltF28"; return;
case CV_ALPHA_FltF29:*out = "FltF29"; return;
case CV_ALPHA_FltF30:*out = "FltF30"; return;
case CV_ALPHA_FltF31:*out = "FltF31"; return;
case CV_ALPHA_IntV0: *out = "IntV0"; return; // Integer registers
case CV_ALPHA_IntT0: *out = "IntT0"; return;
case CV_ALPHA_IntT1: *out = "IntT1"; return;
case CV_ALPHA_IntT2: *out = "IntT2"; return;
case CV_ALPHA_IntT3: *out = "IntT3"; return;
case CV_ALPHA_IntT4: *out = "IntT4"; return;
case CV_ALPHA_IntT5: *out = "IntT5"; return;
case CV_ALPHA_IntT6: *out = "IntT6"; return;
case CV_ALPHA_IntT7: *out = "IntT7"; return;
case CV_ALPHA_IntS0: *out = "IntS0"; return;
case CV_ALPHA_IntS1: *out = "IntS1"; return;
case CV_ALPHA_IntS2: *out = "IntS2"; return;
case CV_ALPHA_IntS3: *out = "IntS3"; return;
case CV_ALPHA_IntS4: *out = "IntS4"; return;
case CV_ALPHA_IntS5: *out = "IntS5"; return;
case CV_ALPHA_IntFP: *out = "IntFP"; return;
case CV_ALPHA_IntA0: *out = "IntA0"; return;
case CV_ALPHA_IntA1: *out = "IntA1"; return;
case CV_ALPHA_IntA2: *out = "IntA2"; return;
case CV_ALPHA_IntA3: *out = "IntA3"; return;
case CV_ALPHA_IntA4: *out = "IntA4"; return;
case CV_ALPHA_IntA5: *out = "IntA5"; return;
case CV_ALPHA_IntT8: *out = "IntT8"; return;
case CV_ALPHA_IntT9: *out = "IntT9"; return;
case CV_ALPHA_IntT10:*out = "IntT10"; return;
case CV_ALPHA_IntT11:*out = "IntT11"; return;
case CV_ALPHA_IntRA: *out = "IntRA"; return;
case CV_ALPHA_IntT12:*out = "IntT12"; return;
case CV_ALPHA_IntAT: *out = "IntAT"; return;
case CV_ALPHA_IntGP: *out = "IntGP"; return;
case CV_ALPHA_IntSP: *out = "IntSP"; return;
case CV_ALPHA_IntZERO:*out = "IntZERO"; return;
case CV_ALPHA_Fpcr: *out = "Fpcr"; return; // Control registers
case CV_ALPHA_Fir: *out = "Fir"; return;
case CV_ALPHA_Psr: *out = "Psr"; return;
case CV_ALPHA_FltFsr:*out = "FltFsr"; return;
case CV_ALPHA_SoftFpcr:*out = "SoftFpcr"; return;
}
break;
case CV_CFL_PPC601:
case CV_CFL_PPC603:
case CV_CFL_PPC604:
case CV_CFL_PPC620:
case CV_CFL_PPCFP:
case CV_CFL_PPCBE:
// Register Set for Motorola/IBM PowerPC
switch ( reg )
{
/*
** PowerPC General Registers ( User Level )
*/
case CV_PPC_GPR0: *out = "gpr0"; return;
case CV_PPC_GPR1: *out = "gpr1"; return;
case CV_PPC_GPR2: *out = "gpr2"; return;
case CV_PPC_GPR3: *out = "gpr3"; return;
case CV_PPC_GPR4: *out = "gpr4"; return;
case CV_PPC_GPR5: *out = "gpr5"; return;
case CV_PPC_GPR6: *out = "gpr6"; return;
case CV_PPC_GPR7: *out = "gpr7"; return;
case CV_PPC_GPR8: *out = "gpr8"; return;
case CV_PPC_GPR9: *out = "gpr9"; return;
case CV_PPC_GPR10: *out = "gpr10"; return;
case CV_PPC_GPR11: *out = "gpr11"; return;
case CV_PPC_GPR12: *out = "gpr12"; return;
case CV_PPC_GPR13: *out = "gpr13"; return;
case CV_PPC_GPR14: *out = "gpr14"; return;
case CV_PPC_GPR15: *out = "gpr15"; return;
case CV_PPC_GPR16: *out = "gpr16"; return;
case CV_PPC_GPR17: *out = "gpr17"; return;
case CV_PPC_GPR18: *out = "gpr18"; return;
case CV_PPC_GPR19: *out = "gpr19"; return;
case CV_PPC_GPR20: *out = "gpr20"; return;
case CV_PPC_GPR21: *out = "gpr21"; return;
case CV_PPC_GPR22: *out = "gpr22"; return;
case CV_PPC_GPR23: *out = "gpr23"; return;
case CV_PPC_GPR24: *out = "gpr24"; return;
case CV_PPC_GPR25: *out = "gpr25"; return;
case CV_PPC_GPR26: *out = "gpr26"; return;
case CV_PPC_GPR27: *out = "gpr27"; return;
case CV_PPC_GPR28: *out = "gpr28"; return;
case CV_PPC_GPR29: *out = "gpr29"; return;
case CV_PPC_GPR30: *out = "gpr30"; return;
case CV_PPC_GPR31: *out = "gpr31"; return;
/*
** PowerPC Condition Register ( user level )
*/
case CV_PPC_CR: *out = "cr"; return;
case CV_PPC_CR0: *out = "cr0"; return;
case CV_PPC_CR1: *out = "cr1"; return;
case CV_PPC_CR2: *out = "cr2"; return;
case CV_PPC_CR3: *out = "cr3"; return;
case CV_PPC_CR4: *out = "cr4"; return;
case CV_PPC_CR5: *out = "cr5"; return;
case CV_PPC_CR6: *out = "cr6"; return;
case CV_PPC_CR7: *out = "cr7"; return;
/*
** PowerPC Floating Point Registers ( user Level )
*/
case CV_PPC_FPR0: *out = "fpr0"; return;
case CV_PPC_FPR1: *out = "fpr1"; return;
case CV_PPC_FPR2: *out = "fpr2"; return;
case CV_PPC_FPR3: *out = "fpr3"; return;
case CV_PPC_FPR4: *out = "fpr4"; return;
case CV_PPC_FPR5: *out = "fpr5"; return;
case CV_PPC_FPR6: *out = "fpr6"; return;
case CV_PPC_FPR7: *out = "fpr7"; return;
case CV_PPC_FPR8: *out = "fpr8"; return;
case CV_PPC_FPR9: *out = "fpr9"; return;
case CV_PPC_FPR10: *out = "fpr10"; return;
case CV_PPC_FPR11: *out = "fpr11"; return;
case CV_PPC_FPR12: *out = "fpr12"; return;
case CV_PPC_FPR13: *out = "fpr13"; return;
case CV_PPC_FPR14: *out = "fpr14"; return;
case CV_PPC_FPR15: *out = "fpr15"; return;
case CV_PPC_FPR16: *out = "fpr16"; return;
case CV_PPC_FPR17: *out = "fpr17"; return;
case CV_PPC_FPR18: *out = "fpr18"; return;
case CV_PPC_FPR19: *out = "fpr19"; return;
case CV_PPC_FPR20: *out = "fpr20"; return;
case CV_PPC_FPR21: *out = "fpr21"; return;
case CV_PPC_FPR22: *out = "fpr22"; return;
case CV_PPC_FPR23: *out = "fpr23"; return;
case CV_PPC_FPR24: *out = "fpr24"; return;
case CV_PPC_FPR25: *out = "fpr25"; return;
case CV_PPC_FPR26: *out = "fpr26"; return;
case CV_PPC_FPR27: *out = "fpr27"; return;
case CV_PPC_FPR28: *out = "fpr28"; return;
case CV_PPC_FPR29: *out = "fpr29"; return;
case CV_PPC_FPR30: *out = "fpr30"; return;
case CV_PPC_FPR31: *out = "fpr31"; return;
/*
** PowerPC Floating Point Status and Control Register ( User Level )
*/
case CV_PPC_FPSCR: *out = "FPSCR"; return;
/*
** PowerPC Machine State Register ( Supervisor Level )
*/
case CV_PPC_MSR: *out = "msr"; return;
/*
** PowerPC Segment Registers ( Supervisor Level )
*/
case CV_PPC_SR0: *out = "sr0"; return;
case CV_PPC_SR1: *out = "sr1"; return;
case CV_PPC_SR2: *out = "sr2"; return;
case CV_PPC_SR3: *out = "sr3"; return;
case CV_PPC_SR4: *out = "sr4"; return;
case CV_PPC_SR5: *out = "sr5"; return;
case CV_PPC_SR6: *out = "sr6"; return;
case CV_PPC_SR7: *out = "sr7"; return;
case CV_PPC_SR8: *out = "sr8"; return;
case CV_PPC_SR9: *out = "sr9"; return;
case CV_PPC_SR10: *out = "sr10"; return;
case CV_PPC_SR11: *out = "sr11"; return;
case CV_PPC_SR12: *out = "sr12"; return;
case CV_PPC_SR13: *out = "sr13"; return;
case CV_PPC_SR14: *out = "sr14"; return;
case CV_PPC_SR15: *out = "sr15"; return;
/*
** For all of the special purpose registers add 100 to the SPR# that the
** Motorola/IBM documentation gives with the exception of any imaginary
** registers.
*/
/*
** PowerPC Special Purpose Registers ( User Level )
*/
case CV_PPC_PC: *out = "pc"; return; // PC (imaginary register)
case CV_PPC_MQ: *out = "mq"; return; // MPC601
case CV_PPC_XER: *out = "xer"; return;
case CV_PPC_RTCU: *out = "rtcu"; return; // MPC601
case CV_PPC_RTCL: *out = "rtcl"; return; // MPC601
case CV_PPC_LR: *out = "lr"; return;
case CV_PPC_CTR: *out = "ctr"; return;
case CV_PPC_COMPARE: *out = "compare"; return;// part of XER (internal to the debugger only)
case CV_PPC_COUNT: *out = "count"; return;// part of XER (internal to the debugger only)
/*
** PowerPC Special Purpose Registers ( supervisor Level )
*/
case CV_PPC_DSISR: *out = "dsisr"; return;
case CV_PPC_DAR: *out = "dar"; return;
case CV_PPC_DEC: *out = "dec"; return;
case CV_PPC_SDR1: *out = "sdr1"; return;
case CV_PPC_SRR0: *out = "srr0"; return;
case CV_PPC_SRR1: *out = "srr1"; return;
case CV_PPC_SPRG0: *out = "sprg0"; return;
case CV_PPC_SPRG1: *out = "sprg1"; return;
case CV_PPC_SPRG2: *out = "sprg2"; return;
case CV_PPC_SPRG3: *out = "sprg3"; return;
case CV_PPC_ASR: *out = "asr"; return;// 64-bit implementations only
case CV_PPC_EAR: *out = "ear"; return;
case CV_PPC_PVR: *out = "pvr"; return;
case CV_PPC_BAT0U: *out = "bat0u"; return;
case CV_PPC_BAT0L: *out = "bat0l"; return;
case CV_PPC_BAT1U: *out = "bat1u"; return;
case CV_PPC_BAT1L: *out = "bat1l"; return;
case CV_PPC_BAT2U: *out = "bat2u"; return;
case CV_PPC_BAT2L: *out = "bat2l"; return;
case CV_PPC_BAT3U: *out = "bat3u"; return;
case CV_PPC_BAT3L: *out = "bat3l"; return;
case CV_PPC_DBAT0U: *out = "dbat0u"; return;
case CV_PPC_DBAT0L: *out = "dbat0l"; return;
case CV_PPC_DBAT1U: *out = "dbat1u"; return;
case CV_PPC_DBAT1L: *out = "dbat1l"; return;
case CV_PPC_DBAT2U: *out = "dbat2u"; return;
case CV_PPC_DBAT2L: *out = "dbat2l"; return;
case CV_PPC_DBAT3U: *out = "dbat3u"; return;
case CV_PPC_DBAT3L: *out = "dbat3l"; return;
/*
** PowerPC Special Purpose Registers implementation Dependent ( Supervisor Level )
*/
/*
** Doesn't appear that IBM/Motorola has finished defining these.
*/
case CV_PPC_PMR0: *out = "pmr0"; return;// MPC620,
case CV_PPC_PMR1: *out = "pmr1"; return;// MPC620,
case CV_PPC_PMR2: *out = "pmr2"; return;// MPC620,
case CV_PPC_PMR3: *out = "pmr3"; return;// MPC620,
case CV_PPC_PMR4: *out = "pmr4"; return;// MPC620,
case CV_PPC_PMR5: *out = "pmr5"; return;// MPC620,
case CV_PPC_PMR6: *out = "pmr6"; return;// MPC620,
case CV_PPC_PMR7: *out = "pmr7"; return;// MPC620,
case CV_PPC_PMR8: *out = "pmr8"; return;// MPC620,
case CV_PPC_PMR9: *out = "pmr9"; return;// MPC620,
case CV_PPC_PMR10: *out = "pmr10"; return;// MPC620,
case CV_PPC_PMR11: *out = "pmr11"; return;// MPC620,
case CV_PPC_PMR12: *out = "pmr12"; return;// MPC620,
case CV_PPC_PMR13: *out = "pmr13"; return;// MPC620,
case CV_PPC_PMR14: *out = "pmr14"; return;// MPC620,
case CV_PPC_PMR15: *out = "pmr15"; return;// MPC620,
case CV_PPC_DMISS: *out = "dmiss"; return;// MPC603
case CV_PPC_DCMP: *out = "dcmp"; return;// MPC603
case CV_PPC_HASH1: *out = "hash1"; return;// MPC603
case CV_PPC_HASH2: *out = "hash2"; return;// MPC603
case CV_PPC_IMISS: *out = "imiss"; return;// MPC603
case CV_PPC_ICMP: *out = "icmp"; return;// MPC603
case CV_PPC_RPA: *out = "rpa"; return;// MPC603
case CV_PPC_HID0: *out = "hid0"; return;// MPC601, MPC603, MPC620
case CV_PPC_HID1: *out = "hid1"; return;// MPC601
case CV_PPC_HID2: *out = "hid2"; return;// MPC601, MPC603, MPC620 ( IABR )
case CV_PPC_HID3: *out = "hid3"; return;// Not Defined
case CV_PPC_HID4: *out = "hid4"; return;// Not Defined
case CV_PPC_HID5: *out = "hid5"; return;// MPC601, MPC604, MPC620 ( DABR )
case CV_PPC_HID6: *out = "hid6"; return;// Not Defined
case CV_PPC_HID7: *out = "hid7"; return;// Not Defined
case CV_PPC_HID8: *out = "hid8"; return;// MPC620 ( BUSCSR )
case CV_PPC_HID9: *out = "hid9"; return;// MPC620 ( L2CSR )
case CV_PPC_HID10: *out = "hid10"; return;// Not Defined
case CV_PPC_HID11: *out = "hid11"; return;// Not Defined
case CV_PPC_HID12: *out = "hid12"; return;// Not Defined
case CV_PPC_HID13: *out = "hid13"; return;// MPC604 ( HCR )
case CV_PPC_HID14: *out = "hid14"; return;// Not Defined
case CV_PPC_HID15: *out = "hid15"; return;// MPC601, MPC604, MPC620 ( PIR )
}
break;
//
// JAVA VM registers
//
// case CV_JAVA_PC: *out = "PC"; return;
case CV_CFL_SH3:
case CV_CFL_SH3E:
case CV_CFL_SH3DSP:
case CV_CFL_SH4:
//
// Register set for the Hitachi SH3
//
switch ( reg )
{
case CV_SH3_NOREG: *out = "NOREG"; return;
case CV_SH3_IntR0: *out = "IntR0"; return;// CPU REGISTER
case CV_SH3_IntR1: *out = "IntR1"; return;
case CV_SH3_IntR2: *out = "IntR2"; return;
case CV_SH3_IntR3: *out = "IntR3"; return;
case CV_SH3_IntR4: *out = "IntR4"; return;
case CV_SH3_IntR5: *out = "IntR5"; return;
case CV_SH3_IntR6: *out = "IntR6"; return;
case CV_SH3_IntR7: *out = "IntR7"; return;
case CV_SH3_IntR8: *out = "IntR8"; return;
case CV_SH3_IntR9: *out = "IntR9"; return;
case CV_SH3_IntR10: *out = "IntR10"; return;
case CV_SH3_IntR11: *out = "IntR11"; return;
case CV_SH3_IntR12: *out = "IntR12"; return;
case CV_SH3_IntR13: *out = "IntR13"; return;
case CV_SH3_IntFp: *out = "IntFp"; return;
case CV_SH3_IntSp: *out = "IntSp"; return;
case CV_SH3_Gbr: *out = "Gbr"; return;
case CV_SH3_Pr: *out = "Pr"; return;
case CV_SH3_Mach: *out = "Mach"; return;
case CV_SH3_Macl: *out = "Macl"; return;
case CV_SH3_Pc: *out = "Pc"; return;
case CV_SH3_Sr: *out = "Sr"; return;
case CV_SH3_BarA: *out = "BarA"; return;
case CV_SH3_BasrA: *out = "BasrA"; return;
case CV_SH3_BamrA: *out = "BamrA"; return;
case CV_SH3_BbrA: *out = "BbrA"; return;
case CV_SH3_BarB: *out = "BarB"; return;
case CV_SH3_BasrB: *out = "BasrB"; return;
case CV_SH3_BamrB: *out = "BamrB"; return;
case CV_SH3_BbrB: *out = "BbrB"; return;
case CV_SH3_BdrB: *out = "BdrB"; return;
case CV_SH3_BdmrB: *out = "BdmrB"; return;
case CV_SH3_Brcr: *out = "Brcr"; return;
//
// Additional registers for Hitachi SH processors
//
case CV_SH_Fpscr: *out = "Fpscr"; return;// floating point status/control register
case CV_SH_Fpul: *out = "Fpul"; return;// floating point communication register
case CV_SH_FpR0: *out = "FpR0"; return;// Floating point registers
case CV_SH_FpR1: *out = "FpR1"; return;
case CV_SH_FpR2: *out = "FpR2"; return;
case CV_SH_FpR3: *out = "FpR3"; return;
case CV_SH_FpR4: *out = "FpR4"; return;
case CV_SH_FpR5: *out = "FpR5"; return;
case CV_SH_FpR6: *out = "FpR6"; return;
case CV_SH_FpR7: *out = "FpR7"; return;
case CV_SH_FpR8: *out = "FpR8"; return;
case CV_SH_FpR9: *out = "FpR9"; return;
case CV_SH_FpR10: *out = "FpR10"; return;
case CV_SH_FpR11: *out = "FpR11"; return;
case CV_SH_FpR12: *out = "FpR12"; return;
case CV_SH_FpR13: *out = "FpR13"; return;
case CV_SH_FpR14: *out = "FpR14"; return;
case CV_SH_FpR15: *out = "FpR15"; return;
case CV_SH_XFpR0: *out = "XFpR0"; return;
case CV_SH_XFpR1: *out = "XFpR1"; return;
case CV_SH_XFpR2: *out = "XFpR2"; return;
case CV_SH_XFpR3: *out = "XFpR3"; return;
case CV_SH_XFpR4: *out = "XFpR4"; return;
case CV_SH_XFpR5: *out = "XFpR5"; return;
case CV_SH_XFpR6: *out = "XFpR6"; return;
case CV_SH_XFpR7: *out = "XFpR7"; return;
case CV_SH_XFpR8: *out = "XFpR8"; return;
case CV_SH_XFpR9: *out = "XFpR9"; return;
case CV_SH_XFpR10: *out = "XFpR10"; return;
case CV_SH_XFpR11: *out = "XFpR11"; return;
case CV_SH_XFpR12: *out = "XFpR12"; return;
case CV_SH_XFpR13: *out = "XFpR13"; return;
case CV_SH_XFpR14: *out = "XFpR14"; return;
case CV_SH_XFpR15: *out = "XFpR15"; return;
}
break;
case CV_CFL_ARM3:
case CV_CFL_ARM4:
case CV_CFL_ARM4T:
case CV_CFL_ARM5:
case CV_CFL_ARM5T:
case CV_CFL_ARM6:
case CV_CFL_ARM_XMAC:
case CV_CFL_ARM_WMMX:
case CV_CFL_THUMB:
case CV_CFL_ARMNT:
//
// Register set for the ARM processor.
//
switch ( reg )
{
case CV_ARM_NOREG: *out = "noreg"; return;
case CV_ARM_R0: *out = "r0"; return;
case CV_ARM_R1: *out = "r1"; return;
case CV_ARM_R2: *out = "r2"; return;
case CV_ARM_R3: *out = "r3"; return;
case CV_ARM_R4: *out = "r4"; return;
case CV_ARM_R5: *out = "r5"; return;
case CV_ARM_R6: *out = "r6"; return;
case CV_ARM_R7: *out = "r7"; return;
case CV_ARM_R8: *out = "r8"; return;
case CV_ARM_R9: *out = "r9"; return;
case CV_ARM_R10: *out = "r10"; return;
case CV_ARM_R11: *out = "r11"; return;// Frame pointer, if allocated
case CV_ARM_R12: *out = "r12"; return;
case CV_ARM_SP: *out = "sp"; return;// Stack pointer
case CV_ARM_LR: *out = "lr"; return;// Link Register
case CV_ARM_PC: *out = "pc"; return;// Program counter
case CV_ARM_CPSR: *out = "cpsr"; return;// Current program status register
}
break;
case CV_CFL_IA64:
// case CV_CFL_IA64_1:
case CV_CFL_IA64_2:
//
// Register set for Intel IA64
//
switch ( reg )
{
case CV_IA64_NOREG: *out = "noreg"; return;
// Branch Registers
case CV_IA64_Br0: *out = "br0"; return;
case CV_IA64_Br1: *out = "br1"; return;
case CV_IA64_Br2: *out = "br2"; return;
case CV_IA64_Br3: *out = "br3"; return;
case CV_IA64_Br4: *out = "br4"; return;
case CV_IA64_Br5: *out = "br5"; return;
case CV_IA64_Br6: *out = "br6"; return;
case CV_IA64_Br7: *out = "br7"; return;
// Predicate Registers
case CV_IA64_P0: *out = "p0"; return;
case CV_IA64_P1: *out = "p1"; return;
case CV_IA64_P2: *out = "p2"; return;
case CV_IA64_P3: *out = "p3"; return;
case CV_IA64_P4: *out = "p4"; return;
case CV_IA64_P5: *out = "p5"; return;
case CV_IA64_P6: *out = "p6"; return;
case CV_IA64_P7: *out = "p7"; return;
case CV_IA64_P8: *out = "p8"; return;
case CV_IA64_P9: *out = "p9"; return;
case CV_IA64_P10: *out = "p10"; return;
case CV_IA64_P11: *out = "p11"; return;
case CV_IA64_P12: *out = "p12"; return;
case CV_IA64_P13: *out = "p13"; return;
case CV_IA64_P14: *out = "p14"; return;
case CV_IA64_P15: *out = "p15"; return;
case CV_IA64_P16: *out = "p16"; return;
case CV_IA64_P17: *out = "p17"; return;
case CV_IA64_P18: *out = "p18"; return;
case CV_IA64_P19: *out = "p19"; return;
case CV_IA64_P20: *out = "p20"; return;
case CV_IA64_P21: *out = "p21"; return;
case CV_IA64_P22: *out = "p22"; return;
case CV_IA64_P23: *out = "p23"; return;
case CV_IA64_P24: *out = "p24"; return;
case CV_IA64_P25: *out = "p25"; return;
case CV_IA64_P26: *out = "p26"; return;
case CV_IA64_P27: *out = "p27"; return;
case CV_IA64_P28: *out = "p28"; return;
case CV_IA64_P29: *out = "p29"; return;
case CV_IA64_P30: *out = "p30"; return;
case CV_IA64_P31: *out = "p31"; return;
case CV_IA64_P32: *out = "p32"; return;
case CV_IA64_P33: *out = "p33"; return;
case CV_IA64_P34: *out = "p34"; return;
case CV_IA64_P35: *out = "p35"; return;
case CV_IA64_P36: *out = "p36"; return;
case CV_IA64_P37: *out = "p37"; return;
case CV_IA64_P38: *out = "p38"; return;
case CV_IA64_P39: *out = "p39"; return;
case CV_IA64_P40: *out = "p40"; return;
case CV_IA64_P41: *out = "p41"; return;
case CV_IA64_P42: *out = "p42"; return;
case CV_IA64_P43: *out = "p43"; return;
case CV_IA64_P44: *out = "p44"; return;
case CV_IA64_P45: *out = "p45"; return;
case CV_IA64_P46: *out = "p46"; return;
case CV_IA64_P47: *out = "p47"; return;
case CV_IA64_P48: *out = "p48"; return;
case CV_IA64_P49: *out = "p49"; return;
case CV_IA64_P50: *out = "p50"; return;
case CV_IA64_P51: *out = "p51"; return;
case CV_IA64_P52: *out = "p52"; return;
case CV_IA64_P53: *out = "p53"; return;
case CV_IA64_P54: *out = "p54"; return;
case CV_IA64_P55: *out = "p55"; return;
case CV_IA64_P56: *out = "p56"; return;
case CV_IA64_P57: *out = "p57"; return;
case CV_IA64_P58: *out = "p58"; return;
case CV_IA64_P59: *out = "p59"; return;
case CV_IA64_P60: *out = "p60"; return;
case CV_IA64_P61: *out = "p61"; return;
case CV_IA64_P62: *out = "p62"; return;
case CV_IA64_P63: *out = "p63"; return;
case CV_IA64_Preds: *out = "Preds"; return;
// Banked General Registers
case CV_IA64_IntH0: *out = "IntH0"; return;
case CV_IA64_IntH1: *out = "IntH1"; return;
case CV_IA64_IntH2: *out = "IntH2"; return;
case CV_IA64_IntH3: *out = "IntH3"; return;
case CV_IA64_IntH4: *out = "IntH4"; return;
case CV_IA64_IntH5: *out = "IntH5"; return;