From fce9574d7009bedfb1668bcfd376d7f75af04a15 Mon Sep 17 00:00:00 2001 From: Stephen Sun Date: Tue, 9 Nov 2021 23:27:42 +0000 Subject: [PATCH 1/4] Adjust buffer parameters with 2km cable supported for 4600C MSFT SKUs Also recalculated all parameters with the latest algorithm with per-speed peer response time taken into account Detailed information of each SKU: - C64: 32 100G down links and 32 100G up links with 2km cable supported on t1 - D112C8: 112 50G down links and 8 100G up links. - D48C40: 48 50G down links, 32 100G down links and 8 100G up links - D100C12S2: 4 100G down links, 2 10G down links, 100 50G down links and 8 100G uplinks 2km cable is supported for C64 on t1 only Signed-off-by: Stephen Sun --- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- .../pg_profile_lookup.ini | 34 +++++++++---------- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- 9 files changed, 41 insertions(+), 41 deletions(-) diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t0.j2 index 7495b010d3ce..fa4509688831 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t0.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '53379072' %} -{% set ingress_lossless_xoff_size = '1540096' %} +{% set ingress_lossless_pool_size = '49904640' %} +{% set ingress_lossless_xoff_size = '3703808' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '53379072' %} +{% set egress_lossy_pool_size = '49904640' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 index aa8a9990bdf8..efb3829e1f26 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '52723712' %} -{% set ingress_lossless_xoff_size = '2195456' %} +{% set ingress_lossless_pool_size = '44301312' %} +{% set ingress_lossless_xoff_size = '9307136' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '52723712' %} +{% set egress_lossy_pool_size = 44301312' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 index e5785e0744e7..86e6a9bc25f7 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 @@ -1,8 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '48228352' %} -{% set ingress_lossless_xoff_size = '2287616' %} +{% set ingress_lossless_pool_size = '44909568' %} +{% set ingress_lossless_xoff_size = '3271680' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '48228352' %} +{% set egress_lossy_pool_size = '44909568' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 index a8f95220924f..6880a0fbe4bd 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 @@ -1,8 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '46315520' %} -{% set ingress_lossless_xoff_size = '4200448' %} +{% set ingress_lossless_pool_size = '44354560' %} +{% set ingress_lossless_xoff_size = '3826688' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '46315520' %} +{% set egress_lossy_pool_size = '44354560' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 index 9c2309d88a5e..ba49db4448f4 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '47587328' %} -{% set ingress_lossless_xoff_size = '2400256' %} +{% set ingress_lossless_pool_size = '43826176' %} +{% set ingress_lossless_xoff_size = '3703808' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '47587328' %} +{% set egress_lossy_pool_size = '43826176' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 index 249c60571497..ce68bb1c69d0 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '46702592' %} -{% set ingress_lossless_xoff_size = '3284992' %} +{% set ingress_lossless_pool_size = '43047936' %} +{% set ingress_lossless_xoff_size = '4482048' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '46702592' %} +{% set egress_lossy_pool_size = '43047936' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/pg_profile_lookup.ini b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/pg_profile_lookup.ini index d32deb3298aa..d4d085610dfc 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/pg_profile_lookup.ini +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/pg_profile_lookup.ini @@ -17,22 +17,22 @@ # PG lossless profiles. # speed cable size xon xoff threshold 10000 5m 19456 19456 24576 0 - 25000 5m 19456 19456 24576 0 - 40000 5m 19456 19456 24576 0 - 50000 5m 19456 19456 24576 0 - 100000 5m 19456 19456 25600 0 - 10000 40m 19456 19456 24576 0 - 25000 40m 19456 19456 26624 0 - 40000 40m 19456 19456 27648 0 - 50000 40m 19456 19456 28672 0 - 100000 40m 19456 19456 32768 0 + 25000 5m 19456 19456 26624 0 + 40000 5m 19456 19456 30720 0 + 50000 5m 19456 19456 33792 0 + 100000 5m 19456 19456 59392 0 + 10000 40m 19456 19456 25600 0 + 25000 40m 19456 19456 28672 0 + 40000 40m 19456 19456 33792 0 + 50000 40m 19456 19456 36864 0 + 100000 40m 19456 19456 66560 0 10000 300m 19456 19456 30720 0 - 25000 300m 19456 19456 39936 0 - 40000 300m 19456 19456 49152 0 - 50000 300m 19456 19456 55296 0 - 100000 300m 19456 19456 86016 0 + 25000 300m 19456 19456 41984 0 + 40000 300m 19456 19456 54272 0 + 50000 300m 19456 19456 63488 0 + 100000 300m 19456 19456 120832 0 10000 2000m 19456 19456 32768 0 - 25000 2000m 19456 19456 63488 0 - 40000 2000m 19456 19456 94208 0 - 50000 2000m 19456 19456 114688 0 - 100000 2000m 19456 19456 217088 0 + 25000 2000m 19456 19456 64512 0 + 40000 2000m 19456 19456 97280 0 + 50000 2000m 19456 19456 119808 0 + 100000 2000m 19456 19456 234496 0 diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 index 3051dc09ac66..7124eb01e224 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '50995200' %} -{% set ingress_lossless_xoff_size = '1810432' %} +{% set ingress_lossless_pool_size = '47397888' %} +{% set ingress_lossless_xoff_size = '3605504' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '50995200' %} +{% set egress_lossy_pool_size = '47397888' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 index 4b1b6622295c..7d4c1b8f2705 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '50143232' %} -{% set ingress_lossless_xoff_size = '2662400' %} +{% set ingress_lossless_pool_size = '46586880' %} +{% set ingress_lossless_xoff_size = '4416512' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '50143232' %} +{% set egress_lossy_pool_size = '46586880' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} From 1c74e6ad43bf9da0fef62625653d51892a455f9b Mon Sep 17 00:00:00 2001 From: Stephen Sun Date: Wed, 10 Nov 2021 18:26:10 +0800 Subject: [PATCH 2/4] Fix typo Signed-off-by: Stephen Sun --- .../Mellanox-SN4600C-C64/buffers_defaults_t1.j2 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 index efb3829e1f26..4dd727718c3d 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 @@ -18,7 +18,7 @@ {% set ingress_lossless_pool_size = '44301312' %} {% set ingress_lossless_xoff_size = '9307136' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = 44301312' %} +{% set egress_lossy_pool_size = '44301312' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} From 2578731e4c112ca222cb240e263579b1866f5605 Mon Sep 17 00:00:00 2001 From: Stephen Sun Date: Tue, 16 Nov 2021 17:51:45 +0800 Subject: [PATCH 3/4] C64 t1 should be 56 downlinks and 8 uplinks Signed-off-by: Stephen Sun --- .../Mellanox-SN4600C-C64/buffers_defaults_t1.j2 | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 index 4dd727718c3d..73b4661ca002 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '44301312' %} -{% set ingress_lossless_xoff_size = '9307136' %} +{% set ingress_lossless_pool_size = '48331776' %} +{% set ingress_lossless_xoff_size = '5276672' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '44301312' %} +{% set egress_lossy_pool_size = '48331776' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} From a709e5a7863b7cb6f15b80db8d72261c879e51b2 Mon Sep 17 00:00:00 2001 From: Stephen Sun Date: Tue, 7 Dec 2021 16:29:33 +0800 Subject: [PATCH 4/4] Fix error Signed-off-by: Stephen Sun --- .../Mellanox-SN4600C-C64/buffers_defaults_t0.j2 | 6 +++--- .../Mellanox-SN4600C-C64/buffers_defaults_t1.j2 | 6 +++--- .../Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 | 6 +++--- .../Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 | 6 +++--- .../Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 | 6 +++--- .../Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 | 6 +++--- .../Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 | 6 +++--- .../Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 | 6 +++--- 8 files changed, 24 insertions(+), 24 deletions(-) diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t0.j2 index fa4509688831..307296a72c19 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t0.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '49904640' %} -{% set ingress_lossless_xoff_size = '3703808' %} +{% set ingress_lossless_pool_size = '49905664' %} +{% set ingress_lossless_xoff_size = '3702784' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '49904640' %} +{% set egress_lossy_pool_size = '49905664' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 index 73b4661ca002..f0b99b1949ba 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '48331776' %} -{% set ingress_lossless_xoff_size = '5276672' %} +{% set ingress_lossless_pool_size = '48332800' %} +{% set ingress_lossless_xoff_size = '5275648' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '48331776' %} +{% set egress_lossy_pool_size = '48332800' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 index 86e6a9bc25f7..164fc743ac02 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t0.j2 @@ -1,8 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '44909568' %} -{% set ingress_lossless_xoff_size = '3271680' %} +{% set ingress_lossless_pool_size = '44566528' %} +{% set ingress_lossless_xoff_size = '3614720' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '44909568' %} +{% set egress_lossy_pool_size = '44566528' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 index 6880a0fbe4bd..a7d1e5daef5b 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/buffers_defaults_t1.j2 @@ -1,8 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '44354560' %} -{% set ingress_lossless_xoff_size = '3826688' %} +{% set ingress_lossless_pool_size = '43794432' %} +{% set ingress_lossless_xoff_size = '4386816' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '44354560' %} +{% set egress_lossy_pool_size = '43794432' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 index ba49db4448f4..a99f773ea284 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '43826176' %} -{% set ingress_lossless_xoff_size = '3703808' %} +{% set ingress_lossless_pool_size = '43827200' %} +{% set ingress_lossless_xoff_size = '3702784' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '43826176' %} +{% set egress_lossy_pool_size = '43827200' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 index ce68bb1c69d0..63d21a1cebab 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '43047936' %} -{% set ingress_lossless_xoff_size = '4482048' %} +{% set ingress_lossless_pool_size = '43048960' %} +{% set ingress_lossless_xoff_size = '4481024' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '43047936' %} +{% set egress_lossy_pool_size = '43048960' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 index 7124eb01e224..8b7b748e8e67 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t0.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '47397888' %} -{% set ingress_lossless_xoff_size = '3605504' %} +{% set ingress_lossless_pool_size = '47398912' %} +{% set ingress_lossless_xoff_size = '3604480' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '47397888' %} +{% set egress_lossy_pool_size = '47398912' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 index 7d4c1b8f2705..376db07763ab 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/buffers_defaults_t1.j2 @@ -15,10 +15,10 @@ limitations under the License. #} {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '46586880' %} -{% set ingress_lossless_xoff_size = '4416512' %} +{% set ingress_lossless_pool_size = '46587904' %} +{% set ingress_lossless_xoff_size = '4415488' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '46586880' %} +{% set egress_lossy_pool_size = '46587904' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #}