From 97e6b4d15ca5a659ac9fd814795e941697325e86 Mon Sep 17 00:00:00 2001 From: Stephen Sun <5379172+stephenxs@users.noreply.github.com> Date: Wed, 17 Feb 2021 00:53:40 +0800 Subject: [PATCH] Support shared headroom pool for Microsoft SKUs (#6366) - Why I did it Support shared headroom pool Signed-off-by: Stephen Sun stephens@nvidia.com - How I did it Port configurations for SKUs based on 2700/3800 platform from 201911 For SN3800 platform: C64: 32 100G down links and 32 100G up links. D112C8: 112 50G down links and 8 100G up links. D24C52: 24 50G down links, 20 100G down links, and 32 100G up links. D28C50: 28 50G down links, 18 100G down links, and 32 100G up links. For SN2700 platform: D48C8: 48 50G down links and 8 100G up links C32: 16 100G downlinks and 16 100G uplinks Add configuration for Mellanox-SN4600C-D112C8 112 50G down links and 8 100G up links. - How to verify it Run regression test. --- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- .../pg_profile_lookup.ini | 30 +++++++++---------- .../Mellanox-SN2700/buffers_defaults_t0.j2 | 6 ++-- .../Mellanox-SN2700/buffers_defaults_t1.j2 | 6 ++-- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- .../pg_profile_lookup.ini | 30 +++++++++---------- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- .../buffers_defaults_t0.j2 | 6 ++-- .../buffers_defaults_t1.j2 | 6 ++-- .../buffers_defaults_t0.j2 | 10 ++++--- .../buffers_defaults_t1.j2 | 10 ++++--- .../pg_profile_lookup.ini | 30 +++++++++---------- 17 files changed, 105 insertions(+), 77 deletions(-) diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_t0.j2 index 0ad78e08c6b5..6fc5efcf9b88 100644 --- a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_t0.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '6687744' %} +{% set ingress_lossless_pool_size = '7719936' %} +{% set ingress_lossless_pool_xoff = '1032192' %} {% set egress_lossless_pool_size = '13945824' %} -{% set egress_lossy_pool_size = '6687744' %} +{% set egress_lossy_pool_size = '7719936' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_t1.j2 index 82f6a15b33c8..95d35539253e 100644 --- a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_t1.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '8506368' %} +{% set ingress_lossless_pool_size = '9686016' %} +{% set ingress_lossless_pool_xoff = '1179648' %} {% set egress_lossless_pool_size = '13945824' %} -{% set egress_lossy_pool_size = '8506368' %} +{% set egress_lossy_pool_size = '9686016' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/pg_profile_lookup.ini b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/pg_profile_lookup.ini index 15c12c1637e6..cdd674e4e715 100644 --- a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/pg_profile_lookup.ini +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/pg_profile_lookup.ini @@ -1,17 +1,17 @@ # PG lossless profiles. # speed cable size xon xoff threshold - 10000 5m 41984 19456 22528 0 - 25000 5m 41984 19456 22528 0 - 40000 5m 41984 19456 22528 0 - 50000 5m 41984 19456 22528 0 - 100000 5m 43008 19456 23552 0 - 10000 40m 41984 19456 22528 0 - 25000 40m 44032 19456 24576 0 - 40000 40m 45056 19456 25600 0 - 50000 40m 45056 19456 25600 0 - 100000 40m 49152 19456 29696 0 - 10000 300m 47104 19456 27648 0 - 25000 300m 56320 19456 36864 0 - 40000 300m 64512 19456 45056 0 - 50000 300m 69632 19456 50176 0 - 100000 300m 98304 19456 78848 0 + 10000 5m 19456 19456 22528 0 + 25000 5m 19456 19456 22528 0 + 40000 5m 19456 19456 22528 0 + 50000 5m 19456 19456 22528 0 + 100000 5m 19456 19456 23552 0 + 10000 40m 19456 19456 22528 0 + 25000 40m 19456 19456 24576 0 + 40000 40m 19456 19456 25600 0 + 50000 40m 19456 19456 25600 0 + 100000 40m 19456 19456 29696 0 + 10000 300m 19456 19456 27648 0 + 25000 300m 19456 19456 36864 0 + 40000 300m 19456 19456 45056 0 + 50000 300m 19456 19456 50176 0 + 100000 300m 19456 19456 78848 0 diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700/buffers_defaults_t0.j2 index 41afd1f22444..d2bf72b15f7c 100644 --- a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700/buffers_defaults_t0.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '9489408' %} +{% set ingress_lossless_pool_size = '10177536' %} +{% set ingress_lossless_pool_xoff = '688128' %} {% set egress_lossless_pool_size = '13945824' %} -{% set egress_lossy_pool_size = '9489408' %} +{% set egress_lossy_pool_size = '10177536' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700/buffers_defaults_t1.j2 index 08e21ba05f75..c4422556d87a 100644 --- a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700/buffers_defaults_t1.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '7719936' %} +{% set ingress_lossless_pool_size = '9292800' %} +{% set ingress_lossless_pool_xoff = '1572864' %} {% set egress_lossless_pool_size = '13945824' %} -{% set egress_lossy_pool_size = '7719936' %} +{% set egress_lossy_pool_size = '9292800' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/buffers_defaults_t0.j2 index 2bc09d9ccc83..a59beaeeb698 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/buffers_defaults_t0.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '23343104' %} +{% set ingress_lossless_pool_size = '25866240' %} +{% set ingress_lossless_pool_xoff = '2523136' %} {% set egress_lossless_pool_size = '34287552' %} -{% set egress_lossy_pool_size = '23343104' %} +{% set egress_lossy_pool_size = '25866240' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/buffers_defaults_t1.j2 index 531f1587ba7a..d610abeb4f26 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/buffers_defaults_t1.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '19410944' %} +{% set ingress_lossless_pool_size = '23900160' %} +{% set ingress_lossless_pool_xoff = '4489216' %} {% set egress_lossless_pool_size = '34287552' %} -{% set egress_lossy_pool_size = '19410944' %} +{% set egress_lossy_pool_size = '23900160' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/buffers_defaults_t0.j2 index 26e89cf269ff..63e5d5f3a85a 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/buffers_defaults_t0.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '16576512' %} +{% set ingress_lossless_pool_size = '20017152' %} +{% set ingress_lossless_pool_xoff = '3440640' %} {% set egress_lossless_pool_size = '34287552' %} -{% set egress_lossy_pool_size = '16576512' %} +{% set egress_lossy_pool_size = '20017152' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/buffers_defaults_t1.j2 index 31fd4c7692dd..d1ccce62bb14 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/buffers_defaults_t1.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '14790656' %} +{% set ingress_lossless_pool_size = '19124224' %} +{% set ingress_lossless_pool_xoff = '4333568' %} {% set egress_lossless_pool_size = '34287552' %} -{% set egress_lossy_pool_size = '14790656' %} +{% set egress_lossy_pool_size = '19124224' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/pg_profile_lookup.ini b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/pg_profile_lookup.ini index ea772d0823a1..810d7e77e61f 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/pg_profile_lookup.ini +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/pg_profile_lookup.ini @@ -1,17 +1,17 @@ # PG lossless profiles. # speed cable size xon xoff threshold - 10000 5m 45056 19456 25600 0 - 25000 5m 48128 19456 28672 0 - 40000 5m 50176 19456 30720 0 - 50000 5m 52224 19456 32768 0 - 100000 5m 60416 19456 40960 0 - 10000 40m 46080 19456 26624 0 - 25000 40m 50176 19456 30720 0 - 40000 40m 53248 19456 33792 0 - 50000 40m 56320 19456 36864 0 - 100000 40m 67584 19456 48128 0 - 10000 300m 51200 19456 31744 0 - 25000 300m 63488 19456 44032 0 - 40000 300m 74752 19456 55296 0 - 50000 300m 82944 19456 63488 0 - 100000 300m 121856 19456 102400 0 + 10000 5m 19456 19456 25600 0 + 25000 5m 19456 19456 28672 0 + 40000 5m 19456 19456 30720 0 + 50000 5m 19456 19456 32768 0 + 100000 5m 19456 19456 40960 0 + 10000 40m 19456 19456 26624 0 + 25000 40m 19456 19456 30720 0 + 40000 40m 19456 19456 33792 0 + 50000 40m 19456 19456 36864 0 + 100000 40m 19456 19456 48128 0 + 10000 300m 19456 19456 31744 0 + 25000 300m 19456 19456 44032 0 + 40000 300m 19456 19456 55296 0 + 50000 300m 19456 19456 63488 0 + 100000 300m 19456 19456 102400 0 diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/buffers_defaults_t0.j2 index edccf5e652bc..0ff424a30a57 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/buffers_defaults_t0.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '21819392' %} +{% set ingress_lossless_pool_size = '24576000' %} +{% set ingress_lossless_pool_xoff = '2756608' %} {% set egress_lossless_pool_size = '34287552' %} -{% set egress_lossy_pool_size = '21819392' %} +{% set egress_lossy_pool_size = '24576000' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/buffers_defaults_t1.j2 index 90f626db6a52..49adf1331c1c 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/buffers_defaults_t1.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '17862656' %} +{% set ingress_lossless_pool_size = '22597632' %} +{% set ingress_lossless_pool_xoff = '4734976' %} {% set egress_lossless_pool_size = '34287552' %} -{% set egress_lossy_pool_size = '17862656' %} +{% set egress_lossy_pool_size = '22597632' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/buffers_defaults_t0.j2 index e732ff1a3d65..c64f1c548631 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/buffers_defaults_t0.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '21565440' %} +{% set ingress_lossless_pool_size = '24360960' %} +{% set ingress_lossless_pool_xoff = '2795520' %} {% set egress_lossless_pool_size = '34287552' %} -{% set egress_lossy_pool_size = '21565440' %} +{% set egress_lossy_pool_size = '24360960' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/buffers_defaults_t1.j2 index a6556db59587..bbb51cc778b2 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/buffers_defaults_t1.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '17604608' %} +{% set ingress_lossless_pool_size = '22380544' %} +{% set ingress_lossless_pool_xoff = '4775936' %} {% set egress_lossless_pool_size = '34287552' %} -{% set egress_lossy_pool_size = '17604608' %} +{% set egress_lossy_pool_size = '22380544' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_pool_xoff }}", {%- endif %} "type": "ingress", "mode": "dynamic" diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 index 33df493e117e..aa74c4645678 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t0.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '56369152' %} +{% set ingress_lossless_pool_size = '47587328' %} +{% set ingress_lossless_xoff_size = '2400256' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '56369152' %} +{% set egress_lossy_pool_size = '47587328' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_xoff_size }}", {%- endif %} "type": "ingress", "mode": "dynamic" @@ -39,7 +41,7 @@ "dynamic_th":"7" }, "ingress_lossy_profile": { - "pool":"[BUFFER_POOL|ingress_lossy_pool]", + "pool":"[BUFFER_POOL|ingress_lossless_pool]", "size":"0", "dynamic_th":"3" }, @@ -50,7 +52,7 @@ }, "egress_lossy_profile": { "pool":"[BUFFER_POOL|egress_lossy_pool]", - "size":"4096", + "size":"9216", "dynamic_th":"7" }, "q_lossy_profile": { diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 index 7b6e6fdf3883..1cc727f8c85e 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/buffers_defaults_t1.j2 @@ -1,7 +1,8 @@ {% set default_cable = '5m' %} -{% set ingress_lossless_pool_size = '55115776' %} +{% set ingress_lossless_pool_size = '46702592' %} +{% set ingress_lossless_xoff_size = '3284992' %} {% set egress_lossless_pool_size = '60817392' %} -{% set egress_lossy_pool_size = '55115776' %} +{% set egress_lossy_pool_size = '46702592' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} @@ -15,6 +16,7 @@ "ingress_lossless_pool": { {%- if dynamic_mode is not defined %} "size": "{{ ingress_lossless_pool_size }}", + "xoff": "{{ ingress_lossless_xoff_size }}", {%- endif %} "type": "ingress", "mode": "dynamic" @@ -39,7 +41,7 @@ "dynamic_th":"7" }, "ingress_lossy_profile": { - "pool":"[BUFFER_POOL|ingress_lossy_pool]", + "pool":"[BUFFER_POOL|ingress_lossless_pool]", "size":"0", "dynamic_th":"3" }, @@ -50,7 +52,7 @@ }, "egress_lossy_profile": { "pool":"[BUFFER_POOL|egress_lossy_pool]", - "size":"4096", + "size":"9216", "dynamic_th":"7" }, "q_lossy_profile": { diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/pg_profile_lookup.ini b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/pg_profile_lookup.ini index ab397d98de54..4931d4e1d7ae 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/pg_profile_lookup.ini +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/pg_profile_lookup.ini @@ -1,17 +1,17 @@ # PG lossless profiles. # speed cable size xon xoff threshold - 10000 5m 44032 19456 24576 0 - 25000 5m 44032 19456 24576 0 - 40000 5m 44032 19456 24576 0 - 50000 5m 44032 19456 24576 0 - 100000 5m 45056 19456 25600 0 - 10000 40m 44032 19456 24576 0 - 25000 40m 46080 19456 26624 0 - 40000 40m 47104 19456 27648 0 - 50000 40m 48128 19456 28672 0 - 100000 40m 52224 19456 32768 0 - 10000 300m 50176 19456 30720 0 - 25000 300m 59392 19456 39936 0 - 40000 300m 68608 19456 49152 0 - 50000 300m 74752 19456 55296 0 - 100000 300m 105472 19456 86016 0 + 10000 5m 19456 19456 24576 0 + 25000 5m 19456 19456 24576 0 + 40000 5m 19456 19456 24576 0 + 50000 5m 19456 19456 24576 0 + 100000 5m 19456 19456 25600 0 + 10000 40m 19456 19456 24576 0 + 25000 40m 19456 19456 26624 0 + 40000 40m 19456 19456 27648 0 + 50000 40m 19456 19456 28672 0 + 100000 40m 19456 19456 32768 0 + 10000 300m 19456 19456 30720 0 + 25000 300m 19456 19456 39936 0 + 40000 300m 19456 19456 49152 0 + 50000 300m 19456 19456 55296 0 + 100000 300m 19456 19456 86016 0