diff --git a/rtl/caches/esp-caches b/rtl/caches/esp-caches index d32f1d6149..e19abb9e1e 160000 --- a/rtl/caches/esp-caches +++ b/rtl/caches/esp-caches @@ -1 +1 @@ -Subproject commit d32f1d61495fa4eb20b434147e2b05b6550f97ba +Subproject commit e19abb9e1e6f89c7800fdfa0339d9156c840dd39 diff --git a/rtl/cores/ariane/ariane_wrap.sv b/rtl/cores/ariane/ariane_wrap.sv index 8007e20ed8..8f3b4653bf 100644 --- a/rtl/cores/ariane/ariane_wrap.sv +++ b/rtl/cores/ariane/ariane_wrap.sv @@ -592,7 +592,7 @@ module ariane_wrap .AXI_ID_WIDTH ( AXI_ID_WIDTH_SLV ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ), .AXI_MAX_WRITE_TXNS ( 1 ), - .RISCV_WORD_WIDTH ( 64 ) + .RISCV_WORD_WIDTH ( AXI_ADDR_WIDTH ) ) i_axi_riscv_atomics ( .clk_i ( clk ), @@ -766,7 +766,7 @@ module ariane_wrap // --------------- AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_ADDR_WIDTH ( 64 ), .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_WIDTH_SLV ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ) diff --git a/rtl/misc/esp_init.vhd b/rtl/misc/esp_init.vhd index 024aa37205..5976b993ff 100644 --- a/rtl/misc/esp_init.vhd +++ b/rtl/misc/esp_init.vhd @@ -235,7 +235,10 @@ begin -- architecture rtl ahbmo.hbusreq <= msto.hbusreq; ahbmo.hlock <= msto.hlock; ahbmo.htrans <= msto.htrans; - ahbmo.haddr <= msto.haddr; + ahbmo.haddr(31 downto 0) <= msto.haddr; + haddr_padding: if GLOB_PHYS_ADDR_BITS > 32 generate + ahbmo.haddr(GLOB_PHYS_ADDR_BITS-1 downto 32) <= (others => '0'); + end generate; ahbmo.hwrite <= msto.hwrite; ahbmo.hsize <= msto.hsize; ahbmo.hburst <= msto.hburst; diff --git a/rtl/sockets/bus/ahbctrl.vhd b/rtl/sockets/bus/ahbctrl.vhd index fc7fbb75c1..dbf746a959 100644 --- a/rtl/sockets/bus/ahbctrl.vhd +++ b/rtl/sockets/bus/ahbctrl.vhd @@ -31,6 +31,7 @@ use work.stdlib.all; use work.amba.all; use work.config_types.all; use work.config.all; +use work.esp_global.all; -- pragma translate_off use work.devices.all; use std.textio.all; @@ -374,7 +375,7 @@ begin variable cfgsel : std_ulogic; variable hresp : std_logic_vector(1 downto 0); variable hrdata : std_logic_vector(AHBDW-1 downto 0); - variable haddr : std_logic_vector(31 downto 0); + variable haddr : std_logic_vector(GLOB_PHYS_ADDR_BITS-1 downto 0); variable hirq : std_logic_vector(NAHBIRQ-1 downto 0); variable arb : std_ulogic; variable hconfndx : integer range 0 to 7; @@ -445,7 +446,8 @@ begin (slvo(i).hconfig(j)(15 downto 4) /= "000000000000") then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if; when "11" => - if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK))) and + if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and + (haddr(63 downto 32) = X"00000000")) and ((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) = (haddr(19 downto 8) and slvo(i).hconfig(j)(15 downto 4))) and (slvo(i).hconfig(j)(15 downto 4) /= "000000000000") @@ -472,7 +474,8 @@ begin hsel(12) or hsel(13) or hsel(14) or hsel(15); nslave := conv_integer(bnslave(SIMAX downto 0)); - if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0)) + if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0) and + (haddr(63 downto 32) = X"00000000")) or ((IOAREA = haddr(31 downto 20)) and (ioen = 0))) and ((CFGAREA and CFGMSK) = (haddr(19 downto 8) and CFGMSK)) and (cfgmask /= 0) @@ -726,7 +729,7 @@ begin variable hsize : std_logic_vector(2 downto 0); variable htrans : std_logic_vector(1 downto 0); variable hmaster : std_logic_vector(3 downto 0); - variable haddr : std_logic_vector(31 downto 0); + variable haddr : std_logic_vector(GLOB_PHYS_ADDR_BITS-1 downto 0); variable hwdata, hrdata : std_logic_vector(127 downto 0); variable mbit, bitoffs : integer; variable t : integer; diff --git a/rtl/sockets/bus/ahbmst.vhd b/rtl/sockets/bus/ahbmst.vhd index 61f96c4798..8fdb9ba824 100644 --- a/rtl/sockets/bus/ahbmst.vhd +++ b/rtl/sockets/bus/ahbmst.vhd @@ -144,7 +144,7 @@ begin rin <= v; - ahbo.haddr <= haddr; + ahbo.haddr(31 downto 0) <= haddr; ahbo.htrans <= htrans; ahbo.hbusreq <= hbusreq; ahbo.hwdata <= hwdata; diff --git a/rtl/sockets/bus/amba.vhd b/rtl/sockets/bus/amba.vhd index 1aab9c9a75..77c4ad0714 100644 --- a/rtl/sockets/bus/amba.vhd +++ b/rtl/sockets/bus/amba.vhd @@ -292,6 +292,7 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; subtype amba_irq_type is integer range 0 to NAHBIRQ-1; subtype ahb_addr_type is integer range 0 to 16#fff#; constant zx : std_logic_vector(31 downto 0) := (others => '0'); + constant zxl : std_logic_vector(GLOB_PHYS_ADDR_BITS-1 downto 0) := (others => '0'); constant zahbdw : std_logic_vector(AHBDW-1 downto 0) := (others => '0'); constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0'); constant zy : std_logic_vector(0 to 31) := (others => '0'); @@ -301,14 +302,14 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; (zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0); constant apb3_none : apb3_slv_out_type := (zx, '1', '0', zxirq(NAHBIRQ-1 downto 0), (others => zx), 0); - constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx, + constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zxl, '0', "000", "000", "0000", zahbdw, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0); constant ahbm_in_none : ahb_mst_in_type := ((others => '0'), '0', (others => '0'), zahbdw, zxirq(NAHBIRQ-1 downto 0), '0', '0', '0', '0', ztestin); constant ahbs_none : ahb_slv_out_type := ( '1', "00", zahbdw, zx(NAHBMST-1 downto 0), zxirq(NAHBIRQ-1 downto 0), (others => zx), 0); constant ahbs_in_none : ahb_slv_in_type := ( - zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zahbdw, + zy(0 to NAHBSLV-1), zxl, '0', "00", "000", "000", zahbdw, "0000", '1', "0000", '0', zy(0 to NAHBAMR-1), zxirq(NAHBIRQ-1 downto 0), '0', '0', '0', '0', ztestin); diff --git a/rtl/sockets/proxy/ahbslv2noc.vhd b/rtl/sockets/proxy/ahbslv2noc.vhd index a77d4e61da..c0557e7cae 100644 --- a/rtl/sockets/proxy/ahbslv2noc.vhd +++ b/rtl/sockets/proxy/ahbslv2noc.vhd @@ -211,7 +211,7 @@ begin -- rtl end if; -- Set address flit - payload_address(MISC_NOC_FLIT_SIZE-PREAMBLE_WIDTH-1 downto 0) <= ahbsi.haddr; + payload_address(MISC_NOC_FLIT_SIZE-PREAMBLE_WIDTH-1 downto 0) <= ahbsi.haddr(MISC_NOC_FLIT_SIZE-PREAMBLE_WIDTH-1 downto 0); -- Create header flit reserved := (others => '0'); diff --git a/rtl/tiles/tile_cpu.vhd b/rtl/tiles/tile_cpu.vhd index 8f6c49bfd7..22374fb921 100644 --- a/rtl/tiles/tile_cpu.vhd +++ b/rtl/tiles/tile_cpu.vhd @@ -701,7 +701,7 @@ begin SLMDDRBase => X"0000_0000_C000_0000", SLMDDRLength => X"0000_0000_4000_0000", -- Reserving up to 1GB; devtree can set less DRAMBase => X"0000_0000" & conv_std_logic_vector(ddr_haddr(0), 12) & X"0_0000", - DRAMLength => X"0000_0000_4000_0000", + DRAMLength => X"0000_8000_4000_0000", DRAMCachedLength => conv_std_logic_vector(ariane_cacheable_len, 64)) -- TODO: length set automatically to match devtree port map ( clk => clk_feedthru, @@ -733,7 +733,7 @@ begin -- exit() writes to this address right before completing the program -- Next instruction is a jump to current PC. - cpuerr <= '1' when ariane_drami.aw.addr = X"80001000" and ariane_drami.aw.valid = '1' else '0'; + cpuerr <= '1' when ariane_drami.aw.addr(31 downto 0) = X"80001000" and ariane_drami.aw.valid = '1' else '0'; -- RISC-V PLIC/CLINT outputs irq <= irqi.irl(1 downto 0); diff --git a/socs/defconfig/esp_profpga-xc7v2000t_defconfig b/socs/defconfig/esp_profpga-xc7v2000t_defconfig index 931a29a186..6131a558ab 100644 --- a/socs/defconfig/esp_profpga-xc7v2000t_defconfig +++ b/socs/defconfig/esp_profpga-xc7v2000t_defconfig @@ -1,5 +1,6 @@ CPU_ARCH = ariane NCPU_TILE = 1 +GLOB_PHYS_ADDR_BITS = 64 CONFIG_HAS_SG = y CONFIG_NOC_ROWS = 2 CONFIG_NOC_COLS = 2 diff --git a/socs/defconfig/esp_profpga-xcvu440_defconfig b/socs/defconfig/esp_profpga-xcvu440_defconfig index ea86341ea0..731d6454a6 100644 --- a/socs/defconfig/esp_profpga-xcvu440_defconfig +++ b/socs/defconfig/esp_profpga-xcvu440_defconfig @@ -1,5 +1,6 @@ CPU_ARCH = ariane NCPU_TILE = 1 +GLOB_PHYS_ADDR_BITS = 64 CONFIG_HAS_SG = y CONFIG_NOC_ROWS = 2 CONFIG_NOC_COLS = 2 diff --git a/socs/defconfig/esp_xilinx-vc707-xc7vx485t_defconfig b/socs/defconfig/esp_xilinx-vc707-xc7vx485t_defconfig index 16d880cf52..45af064b3e 100644 --- a/socs/defconfig/esp_xilinx-vc707-xc7vx485t_defconfig +++ b/socs/defconfig/esp_xilinx-vc707-xc7vx485t_defconfig @@ -1,5 +1,6 @@ CPU_ARCH = ariane NCPU_TILE = 1 +GLOB_PHYS_ADDR_BITS = 64 CONFIG_HAS_SG = y CONFIG_NOC_ROWS = 2 CONFIG_NOC_COLS = 2 diff --git a/socs/defconfig/esp_xilinx-vcu118-xcvu9p_defconfig b/socs/defconfig/esp_xilinx-vcu118-xcvu9p_defconfig index 6d3b3ab727..94b8e2713f 100644 --- a/socs/defconfig/esp_xilinx-vcu118-xcvu9p_defconfig +++ b/socs/defconfig/esp_xilinx-vcu118-xcvu9p_defconfig @@ -1,5 +1,6 @@ CPU_ARCH = ariane NCPU_TILE = 1 +GLOB_PHYS_ADDR_BITS = 64 CONFIG_HAS_SG = y CONFIG_NOC_ROWS = 2 CONFIG_NOC_COLS = 2 diff --git a/socs/defconfig/esp_xilinx-vcu128-xcvu37p_defconfig b/socs/defconfig/esp_xilinx-vcu128-xcvu37p_defconfig index d2be445081..82f17b5e63 100644 --- a/socs/defconfig/esp_xilinx-vcu128-xcvu37p_defconfig +++ b/socs/defconfig/esp_xilinx-vcu128-xcvu37p_defconfig @@ -1,5 +1,6 @@ CPU_ARCH = ariane NCPU_TILE = 1 +GLOB_PHYS_ADDR_BITS = 64 CONFIG_HAS_SG = y CONFIG_NOC_ROWS = 2 CONFIG_NOC_COLS = 2 diff --git a/socs/defconfig/esp_xilinx-zcu102-xczu9eg_defconfig b/socs/defconfig/esp_xilinx-zcu102-xczu9eg_defconfig index 2a04dced6c..ea9aefac1c 100644 --- a/socs/defconfig/esp_xilinx-zcu102-xczu9eg_defconfig +++ b/socs/defconfig/esp_xilinx-zcu102-xczu9eg_defconfig @@ -1,5 +1,6 @@ CPU_ARCH = ariane NCPU_TILE = 1 +GLOB_PHYS_ADDR_BITS = 64 CONFIG_HAS_SG = y CONFIG_NOC_ROWS = 2 CONFIG_NOC_COLS = 2 diff --git a/socs/defconfig/esp_xilinx-zcu106-xczu7ev_defconfig b/socs/defconfig/esp_xilinx-zcu106-xczu7ev_defconfig index 2a04dced6c..ea9aefac1c 100644 --- a/socs/defconfig/esp_xilinx-zcu106-xczu7ev_defconfig +++ b/socs/defconfig/esp_xilinx-zcu106-xczu7ev_defconfig @@ -1,5 +1,6 @@ CPU_ARCH = ariane NCPU_TILE = 1 +GLOB_PHYS_ADDR_BITS = 64 CONFIG_HAS_SG = y CONFIG_NOC_ROWS = 2 CONFIG_NOC_COLS = 2 diff --git a/socs/xilinx-vc707-xc7vx485t/systest.c b/socs/xilinx-vc707-xc7vx485t/systest.c index bb247e7b4b..2219edc16a 100644 --- a/socs/xilinx-vc707-xc7vx485t/systest.c +++ b/socs/xilinx-vc707-xc7vx485t/systest.c @@ -7,5 +7,20 @@ int main(int argc, char **argv) { printf("Hello from ESP!\n"); + int *x = (int *) 0x8004e110; + int *y = (int *) ((unsigned long) x | (1L << 33)); + printf("1: %x at %lx\n", *x, (unsigned long) x); + printf("2: %x at %lx\n", *y, (unsigned long) y); + + *x = 0xff00ff00; + + printf("3: %x at %lx\n", *x, (unsigned long) x); + printf("4: %x at %lx\n", *y, (unsigned long) y); + + *y = 0x00ff00ff; + + printf("5: %x at %lx\n", *x, (unsigned long) x); + printf("6: %x at %lx\n", *y, (unsigned long) y); + return 0; } diff --git a/socs/xilinx-vc707-xc7vx485t/top.vhd b/socs/xilinx-vc707-xc7vx485t/top.vhd index b0cb77af77..793b69543d 100644 --- a/socs/xilinx-vc707-xc7vx485t/top.vhd +++ b/socs/xilinx-vc707-xc7vx485t/top.vhd @@ -348,7 +348,7 @@ begin generic map ( hindex => 0, tech => 0, - kbytes => 2 * 1024, + kbytes => 4 * 1024, pipe => 0, maccsz => AHBDW, fname => "ram.srec" diff --git a/tools/socgen/esp_creator.py b/tools/socgen/esp_creator.py index 0199477834..68f34f5550 100755 --- a/tools/socgen/esp_creator.py +++ b/tools/socgen/esp_creator.py @@ -208,6 +208,10 @@ def __init__(self, soc, top_frame, main_frame): self.fpu_label = Label(self.cpu_frame, text="None", fg="red") self.fpu_label.grid(row=2, column=2) self.set_cpu_specific_labels(soc) + + Label(self.cpu_frame, text = "Enable Full Address Space: ").grid(row=3, column=1) + Checkbutton(self.cpu_frame, text="", variable=soc.full_addr_space, + onvalue = 1, offvalue = 0).grid(row=3, column=2) ttk.Separator(self, orient="horizontal").pack(anchor="nw", fill=X, pady=10) diff --git a/tools/socgen/soc.py b/tools/socgen/soc.py index 8a960b358e..76c3cb5bb3 100644 --- a/tools/socgen/soc.py +++ b/tools/socgen/soc.py @@ -141,9 +141,17 @@ def read_config(self, temporary): # CPU architecture line = fp.readline() item = line.split() - self.CPU_ARCH.set(item[2]) + arch = item[2] + self.CPU_ARCH.set(arch) # CPU count (skip this info while rebuilding SoC config) line = fp.readline() + # CPU Address bits + line = fp.readline() + item = line.split() + if arch == "ariane" and line.find("32"): + self.full_addr_space.set(0) + else: + self.full_addr_space.set(1) # Scatter-gather line = fp.readline() if line.find("CONFIG_HAS_SG = y") != -1: @@ -301,6 +309,10 @@ def write_config(self, dsu_ip, dsu_eth): has_dvfs = False; fp.write("CPU_ARCH = " + self.CPU_ARCH.get() + "\n") fp.write("NCPU_TILE = " + str(self.noc.get_cpu_num(self)) + "\n") + if self.full_addr_space.get() and (self.CPU_ARCH.get() == "ariane"): + fp.write("GLOB_PHYS_ADDR_BITS = " + str(64) + "\n") + else: + fp.write("GLOB_PHYS_ADDR_BITS = " + str(32) + "\n") if self.transfers.get() == 1: fp.write("CONFIG_HAS_SG = y\n") else: @@ -465,6 +477,7 @@ def __init__(self, DMA_WIDTH, TECH, LINUX_MAC, LEON3_STACK, FPGA_BOARD, EMU_TECH self.transfers = IntVar() # CPU architecture self.CPU_ARCH = StringVar() + self.full_addr_space = IntVar() # Cache hierarchy self.cache_en = IntVar() self.cache_rtl = IntVar() diff --git a/tools/socgen/socmap_gen.py b/tools/socgen/socmap_gen.py index 588bce3ff2..bdbdef86e4 100755 --- a/tools/socgen/socmap_gen.py +++ b/tools/socgen/socmap_gen.py @@ -451,8 +451,10 @@ def print_global_constants(fp, soc): fp.write(" constant GLOB_BYTE_OFFSET_BITS : integer := " + str(int(math.log2(soc.DMA_WIDTH/8))) +";\n") fp.write(" constant GLOB_OFFSET_BITS : integer := GLOB_WORD_OFFSET_BITS + GLOB_BYTE_OFFSET_BITS;\n") fp.write(" constant GLOB_ADDR_INCR : integer := " + str(int(soc.DMA_WIDTH/8)) +";\n") - # TODO: Keep physical address to 32 bits for now to reduce tag size. This will increase to support more memory - fp.write(" constant GLOB_PHYS_ADDR_BITS : integer := " + str(32) +";\n") + if soc.CPU_ARCH.get() == "ariane" and soc.full_addr_space.get(): + fp.write(" constant GLOB_PHYS_ADDR_BITS : integer := " + str(64) +";\n") + else: + fp.write(" constant GLOB_PHYS_ADDR_BITS : integer := " + str(32) +";\n") fp.write(" constant GLOB_MAXIOSLV : integer := " + str(NAPBS) + ";\n\n") # @@ -2279,7 +2281,10 @@ def print_cache_config(fp, soc, esp_config): byte_bits = 2 word_bits = 2 if soc.CPU_ARCH.get() == "ariane": - addr_bits = 32 + if soc.full_addr_space.get(): + addr_bits = 64 + else: + addr_bits = 32 byte_bits = 3 word_bits = 1 fp.write("`define LLSC\n") diff --git a/tools/socketgen/socketgen.py b/tools/socketgen/socketgen.py index 7e71ac28f1..4792434d85 100755 --- a/tools/socketgen/socketgen.py +++ b/tools/socketgen/socketgen.py @@ -117,7 +117,8 @@ def __str__(self): # bits_per_line = 128 words_per_line = 4 -phys_addr_bits = 32 +# TODO: Parameterize based off of .esp_config ideally? +phys_addr_bits = 64 word_offset_bits = 2 byte_offset_bits = 2 offset_bits = 4