From 64571ba9b7376738ae875725627bc9535b6f1a07 Mon Sep 17 00:00:00 2001 From: EIGSEP Pi Date: Thu, 15 Sep 2022 16:17:16 -0700 Subject: [PATCH 1/3] Fixed missing return in snapadc.SnapAdc.readRAM --- src/snapadc.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/snapadc.py b/src/snapadc.py index 744340c..8d9d344 100644 --- a/src/snapadc.py +++ b/src/snapadc.py @@ -398,6 +398,7 @@ def readRAM(self, ram=None, signed=True): length = 1024 vals = self.ram[ram]._read(addr=0, size=length) vals = np.array(struct.unpack(fmt,vals)).reshape(-1,8) + return vals else: raise ValueError From 3e440603af8cbd674a8f4530b82c27001010bf90 Mon Sep 17 00:00:00 2001 From: EIGSEP Pi Date: Thu, 15 Sep 2022 16:27:39 -0700 Subject: [PATCH 2/3] Fixed int32 fail for tap value in snapadc.SnapAdc.delay --- src/snapadc.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/snapadc.py b/src/snapadc.py index 8d9d344..6e3e284 100644 --- a/src/snapadc.py +++ b/src/snapadc.py @@ -506,10 +506,7 @@ def delay(self, tap, chipSel=None, laneSel=None, verify=False): elif laneSel not in self.laneList: raise ValueError("Invalid parameter") - if not isinstance(tap, (int, np.int64)): - raise ValueError("Invalid parameter") - if isinstance(tap, np.int64): - tap = int(tap) # Fix for Py3 + tap = int(tap) # Fix for Py3 strl = ','.join([str(c) for c in laneSel]) strc = ','.join([str(c) for c in chipSel]) From bc924b47c1ff78fb0017a50fd29c4c3130211a35 Mon Sep 17 00:00:00 2001 From: EIGSEP Pi Date: Thu, 15 Sep 2022 16:31:05 -0700 Subject: [PATCH 3/3] Fixed missing verify in snapadc.SnapAdc.bitslip --- src/snapadc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/snapadc.py b/src/snapadc.py index 6e3e284..5cadf43 100644 --- a/src/snapadc.py +++ b/src/snapadc.py @@ -404,7 +404,7 @@ def readRAM(self, ram=None, signed=True): # A lane in this method actually corresponds to a "branch" in HMCAD1511 datasheet. # But I have to follow the naming convention of signals in casper repo. - def bitslip(self, chipSel=None, laneSel=None): + def bitslip(self, chipSel=None, laneSel=None, verify=False): """ Reorder the parallelize data for word-alignment purpose Reorder the parallelized data by asserting a itslip command to the bitslip