patch2019

Make the following modifications to the hardware . Affix the label "patch2019" to the front panel and PCB.

patches for v1.2

• Skip modifications related to clock mux.

• ground floating connectors -- R75, R74, R65, R64 = 0R

• front panel grounding -- strap from available board GND to front panel with wire

• also apply patches for v1.3 below

A patched v1.2 board continues to logically behave like a v1.2 board so use that designation when building CPLD gateware or compiling ARTIQ gateware.

patches for v1.3

• C175 : 10nF ->100pF

• R87 : 1k8 -> 160R

• TPS62175DQC (IC22)

  • replace TPS62175DQC as it may be damaged due to over voltage
  • changes to prevent over voltage again:
    • IC22 : reduce output to 7.0 V -- R134: 47k -> 43k
    • IC21 : reduce output to 6.5V -- R133: 43k->39k

A patched v1.3 board continues to logically behave like a v1.3 board so use that designation when building CPLD gateware or compiling ARTIQ gateware.

NOTE

The label "patch2019" is a designation of a particular patch level of the Urukul PCB. If additional patches are needed for any version of the hardware don't edit this page to reflect them. Instead, create a new wiki page (eg patch2019b) and detail them there.