NEON: implement all intrinsics supported by architecture A64-part1 #1090
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- 4 cvth_f16_{s/u}{32/64}
- 4 cvth_high_{TYPE}
- 16 vcvta{d/h/q}_{TYPE}
- 6 vcvth_{TYPE}
- 3 cvtxd_{TYPE}
- 8 vcvt{s/d}_n_{TYPE}
- 12 vcvth_n_{TYPE}
yyctw
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The build error for "Windows MSVC-Aarch64" reminds me of this note in the Line 99 in 029d749 So maybe try replacing simde/.github/workflows/ci.yml Line 662 in 029d749 with ninja -C build test
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mr-c
requested changes
Oct 23, 2023
1. Correct the native-aliases name. 2. Replace the test command in "Windows MSVC-Aarch64"
It has been fixed. |
mr-c
requested changes
Oct 23, 2023
@mr-c I have addressed all the comments. My apologies for inadvertently deleting and adding the Copyright. Thank you for your review! |
mr-c
requested changes
Oct 23, 2023
Already fixed. |
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Really impressive, thank you @yyctw ! |
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Hi all, this is Eric from Andes Technology Corporation. This PR is part of the previous PR and includes the following:
Add 368 initial implementations and corresponding test cases in 88 families which are listed below:
abd,abdl_high,add,addhn_high,bsl,ceq,ceqz,cgez,cgtz,cle,cltz,cmla,cmla_rot180,cmla_rot270,cmla_rot90,cnt,copy_lane,cvt,cvt_n,cvtm,cvtp,dot,dot_lane,dup_n,eor,fms_n,ld1,ld3,ld4,maxnm,maxv,minnm,minv,mull,mull_high,mvn,pmin,qrdmulh_lane,qrshl,qrshrn_high_n,qrshrun_high_n,qshl_n,qshlu_n,qshrn_high_n,qshrn_n,qshrun_n,qtbl,qtbx,raddhn,raddhn_high,rbit,reinterpret,rev16,rev32,rev64,rnd,rndi,rndm,rndp,rshrn_high_n,rsubhn,rsubhn_high,shr_n,shrn_n,sli_n,sri_n,st1,st1_lane,st1_x2,st1_x3,st1_x4,st1q_x2,st1q_x3,st1q_x4,st2_lane,st3,st3_lane,st4,st4_lane,tbl,tbx,trn,trn1,trn2,tst,uzp,uzp1,uzp2