From 5e7e8bc5f87c0207a8ef83f0b11d904e2cbad7b4 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Tue, 28 Jul 2020 14:06:59 -0700 Subject: [PATCH 1/5] Update to pickup all Koala missing commits --- FreeRTOS-metal | 2 +- Segger_SystemView-metal | 2 +- freedom-devicetree-tools | 2 +- freedom-metal | 2 +- scl-metal | 2 +- scripts/cmsis-svd-generator | 2 +- scripts/devicetree-overlay-generator | 2 +- scripts/elf2hex | 2 +- scripts/esdk-settings-generator | 2 +- scripts/ldscript-generator | 2 +- scripts/openocdcfg-generator | 2 +- wit-manifest.json | 22 +++++++++++----------- 12 files changed, 22 insertions(+), 22 deletions(-) diff --git a/FreeRTOS-metal b/FreeRTOS-metal index 1eaafa44b..29abc5436 160000 --- a/FreeRTOS-metal +++ b/FreeRTOS-metal @@ -1 +1 @@ -Subproject commit 1eaafa44bcb5c7d6c1e1e25b84ac52eeef0b1a4f +Subproject commit 29abc54367d0d8ee150805575ae2e1c34a69c251 diff --git a/Segger_SystemView-metal b/Segger_SystemView-metal index 8f6d4bd2a..cd89dbc2f 160000 --- a/Segger_SystemView-metal +++ b/Segger_SystemView-metal @@ -1 +1 @@ -Subproject commit 8f6d4bd2afabe7e3e8ef6fb533fa2bb3a0547ae3 +Subproject commit cd89dbc2f3d5222d9856780517261ad7a2804805 diff --git a/freedom-devicetree-tools b/freedom-devicetree-tools index 3670edbb3..4c0e8c03b 160000 --- a/freedom-devicetree-tools +++ b/freedom-devicetree-tools @@ -1 +1 @@ -Subproject commit 3670edbb341df75008f51bb7813df1951206802f +Subproject commit 4c0e8c03b7dca6bc48a0a4de23da7e382062ae8f diff --git a/freedom-metal b/freedom-metal index 3abf11da1..bdeb3fd57 160000 --- a/freedom-metal +++ b/freedom-metal @@ -1 +1 @@ -Subproject commit 3abf11da1a6d638aecd648487f15adf5e99442ff +Subproject commit bdeb3fd57b46bc30fceb1fb0ac3841ca19d23620 diff --git a/scl-metal b/scl-metal index a0f13a316..e8ec9d5a7 160000 --- a/scl-metal +++ b/scl-metal @@ -1 +1 @@ -Subproject commit a0f13a3164bca4e7689ca63895fb9457dc7b96bd +Subproject commit e8ec9d5a7e9157b0bf04f2ad8c51f55d74d68145 diff --git a/scripts/cmsis-svd-generator b/scripts/cmsis-svd-generator index 3a6205340..b285612ec 160000 --- a/scripts/cmsis-svd-generator +++ b/scripts/cmsis-svd-generator @@ -1 +1 @@ -Subproject commit 3a6205340b165b29fbc6c0bdf178c8782df2b583 +Subproject commit b285612ecfaf19efea1b4b8f9143bb2f1256831f diff --git a/scripts/devicetree-overlay-generator b/scripts/devicetree-overlay-generator index 5b08c547e..934c69d37 160000 --- a/scripts/devicetree-overlay-generator +++ b/scripts/devicetree-overlay-generator @@ -1 +1 @@ -Subproject commit 5b08c547e4c3f08b45b72d491d858bdcea9cbd3c +Subproject commit 934c69d374e1ef3f5c9661535f4d8a5a65f776cb diff --git a/scripts/elf2hex b/scripts/elf2hex index 5f3ead16a..136c7b9dc 160000 --- a/scripts/elf2hex +++ b/scripts/elf2hex @@ -1 +1 @@ -Subproject commit 5f3ead16ab35bb5a6d39fd2881ffa81b06741bb2 +Subproject commit 136c7b9dc515770f5dde3b2193ecef1d1b060e07 diff --git a/scripts/esdk-settings-generator b/scripts/esdk-settings-generator index 9728da602..795d65bc6 160000 --- a/scripts/esdk-settings-generator +++ b/scripts/esdk-settings-generator @@ -1 +1 @@ -Subproject commit 9728da6024564a8cb7df66baf70920c4ed5af4e0 +Subproject commit 795d65bc6c033c6d97222f2683f2112631558aa2 diff --git a/scripts/ldscript-generator b/scripts/ldscript-generator index 3a1d07eca..0e3f81db4 160000 --- a/scripts/ldscript-generator +++ b/scripts/ldscript-generator @@ -1 +1 @@ -Subproject commit 3a1d07ecaa90471a798e2b2003d7b33038d6c7ae +Subproject commit 0e3f81db4ba27c87387360bae5054783379be949 diff --git a/scripts/openocdcfg-generator b/scripts/openocdcfg-generator index 7e23e1a70..6bba6b25e 160000 --- a/scripts/openocdcfg-generator +++ b/scripts/openocdcfg-generator @@ -1 +1 @@ -Subproject commit 7e23e1a708eb4ccf2fe198261771689a875a9e54 +Subproject commit 6bba6b25e02f68990fdc84ac06d94634189f01df diff --git a/wit-manifest.json b/wit-manifest.json index 8126fe26f..03ac73aec 100644 --- a/wit-manifest.json +++ b/wit-manifest.json @@ -1,41 +1,41 @@ [ { - "commit": "3670edbb341df75008f51bb7813df1951206802f", + "commit": "4c0e8c03b7dca6bc48a0a4de23da7e382062ae8f", "name": "freedom-devicetree-tools", "source": "git@github.com:sifive/freedom-devicetree-tools.git" }, { - "commit": "3abf11da1a6d638aecd648487f15adf5e99442ff", + "commit": "bdeb3fd57b46bc30fceb1fb0ac3841ca19d23620", "name": "freedom-metal", "source": "git@github.com:sifive/freedom-metal.git" }, { - "commit": "5f3ead16ab35bb5a6d39fd2881ffa81b06741bb2", + "commit": "136c7b9dc515770f5dde3b2193ecef1d1b060e07", "name": "elf2hex", "source": "git@github.com:sifive/elf2hex.git" }, { - "commit": "5b08c547e4c3f08b45b72d491d858bdcea9cbd3c", + "commit": "934c69d374e1ef3f5c9661535f4d8a5a65f776cb", "name": "devicetree-overlay-generator", "source": "git@github.com:sifive/devicetree-overlay-generator.git" }, { - "commit": "3a1d07ecaa90471a798e2b2003d7b33038d6c7ae", + "commit": "0e3f81db4ba27c87387360bae5054783379be949", "name": "ldscript-generator", "source": "git@github.com:sifive/ldscript-generator.git" }, { - "commit": "3a6205340b165b29fbc6c0bdf178c8782df2b583", + "commit": "b285612ecfaf19efea1b4b8f9143bb2f1256831f", "name": "cmsis-svd-generator", "source": "git@github.com:sifive/cmsis-svd-generator.git" }, { - "commit": "7e23e1a708eb4ccf2fe198261771689a875a9e54", + "commit": "6bba6b25e02f68990fdc84ac06d94634189f01df", "name": "openocdcfg-generator", "source": "git@github.com:sifive/openocdcfg-generator.git" }, { - "commit": "9728da6024564a8cb7df66baf70920c4ed5af4e0", + "commit": "795d65bc6c033c6d97222f2683f2112631558aa2", "name": "esdk-settings-generator", "source": "git@github.com:sifive/esdk-settings-generator.git" }, @@ -200,12 +200,12 @@ "source": "git@github.com:sifive/benchmark-mem-latency.git" }, { - "commit": "1eaafa44bcb5c7d6c1e1e25b84ac52eeef0b1a4f", + "commit": "29abc54367d0d8ee150805575ae2e1c34a69c251", "name": "FreeRTOS-metal", "source": "git@github.com:sifive/FreeRTOS-metal.git" }, { - "commit": "8f6d4bd2afabe7e3e8ef6fb533fa2bb3a0547ae3", + "commit": "cd89dbc2f3d5222d9856780517261ad7a2804805", "name": "Segger_SystemView-metal", "source": "git@github.com:sifive/Segger_SystemView-metal.git" }, @@ -250,7 +250,7 @@ "source": "git@github.com:sifive/example-hpm.git" }, { - "commit": "a0f13a3164bca4e7689ca63895fb9457dc7b96bd", + "commit": "e8ec9d5a7e9157b0bf04f2ad8c51f55d74d68145", "name": "scl-metal", "source": "git@github.com:sifive/scl-metal.git" }, From 5c19fc5e0b51700a444aa747423dad06bc8844cf Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Tue, 28 Jul 2020 14:12:34 -0700 Subject: [PATCH 2/5] Update BSP files --- bsp/freedom-e310-arty/metal.default.lds | 2 +- bsp/freedom-e310-arty/metal.freertos.lds | 2 +- bsp/freedom-e310-arty/metal.ramrodata.lds | 2 +- bsp/freedom-e310-arty/metal.scratchpad.lds | 11 +---------- bsp/qemu-sifive-e31/metal.default.lds | 6 ++++-- bsp/qemu-sifive-e31/metal.freertos.lds | 6 ++++-- bsp/qemu-sifive-e31/metal.ramrodata.lds | 6 ++++-- bsp/qemu-sifive-e31/metal.scratchpad.lds | 9 +-------- bsp/qemu-sifive-s51/metal.default.lds | 6 ++++-- bsp/qemu-sifive-s51/metal.freertos.lds | 6 ++++-- bsp/qemu-sifive-s51/metal.ramrodata.lds | 6 ++++-- bsp/qemu-sifive-s51/metal.scratchpad.lds | 9 +-------- bsp/qemu-sifive-u54/metal.default.lds | 4 ++-- bsp/qemu-sifive-u54/metal.freertos.lds | 4 ++-- bsp/qemu-sifive-u54/metal.ramrodata.lds | 4 ++-- bsp/qemu-sifive-u54/metal.scratchpad.lds | 11 +---------- bsp/qemu-sifive-u54mc/metal.default.lds | 4 ++-- bsp/qemu-sifive-u54mc/metal.freertos.lds | 4 ++-- bsp/qemu-sifive-u54mc/metal.ramrodata.lds | 4 ++-- bsp/qemu-sifive-u54mc/metal.scratchpad.lds | 11 +---------- bsp/sifive-hifive-unleashed/metal.default.lds | 8 +++++--- bsp/sifive-hifive-unleashed/metal.freertos.lds | 8 +++++--- bsp/sifive-hifive-unleashed/metal.ramrodata.lds | 8 +++++--- .../metal.scratchpad.lds | 17 +---------------- bsp/sifive-hifive1-revb/metal.default.lds | 2 +- bsp/sifive-hifive1-revb/metal.freertos.lds | 2 +- bsp/sifive-hifive1-revb/metal.ramrodata.lds | 2 +- bsp/sifive-hifive1-revb/metal.scratchpad.lds | 11 +---------- bsp/sifive-hifive1/metal.default.lds | 2 +- bsp/sifive-hifive1/metal.freertos.lds | 2 +- bsp/sifive-hifive1/metal.ramrodata.lds | 2 +- bsp/sifive-hifive1/metal.scratchpad.lds | 9 +-------- bsp/spike/metal.default.lds | 4 ++-- bsp/spike/metal.freertos.lds | 4 ++-- bsp/spike/metal.ramrodata.lds | 4 ++-- bsp/spike/metal.scratchpad.lds | 11 +---------- 36 files changed, 75 insertions(+), 138 deletions(-) diff --git a/bsp/freedom-e310-arty/metal.default.lds b/bsp/freedom-e310-arty/metal.default.lds index b29955b15..8be65ec15 100644 --- a/bsp/freedom-e310-arty/metal.default.lds +++ b/bsp/freedom-e310-arty/metal.default.lds @@ -260,7 +260,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/freedom-e310-arty/metal.freertos.lds b/bsp/freedom-e310-arty/metal.freertos.lds index eb8ad6b9f..3e5a6888e 100644 --- a/bsp/freedom-e310-arty/metal.freertos.lds +++ b/bsp/freedom-e310-arty/metal.freertos.lds @@ -281,7 +281,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/freedom-e310-arty/metal.ramrodata.lds b/bsp/freedom-e310-arty/metal.ramrodata.lds index 0b4db2167..4cc334b02 100644 --- a/bsp/freedom-e310-arty/metal.ramrodata.lds +++ b/bsp/freedom-e310-arty/metal.ramrodata.lds @@ -264,7 +264,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds index aed01551b..8ff4491f7 100644 --- a/bsp/freedom-e310-arty/metal.scratchpad.lds +++ b/bsp/freedom-e310-arty/metal.scratchpad.lds @@ -72,15 +72,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 ); - PROVIDE( metal_itim_0_memory_start = 0x8000000 ); - PROVIDE( metal_itim_0_memory_end = 0x8000000 + 0x4000 ); /* ROM SECTION * @@ -261,7 +252,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-e31/metal.default.lds b/bsp/qemu-sifive-e31/metal.default.lds index d550a4ac0..734eb421d 100644 --- a/bsp/qemu-sifive-e31/metal.default.lds +++ b/bsp/qemu-sifive-e31/metal.default.lds @@ -75,8 +75,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -257,7 +259,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-e31/metal.freertos.lds b/bsp/qemu-sifive-e31/metal.freertos.lds index 9b70daa68..e237aa639 100644 --- a/bsp/qemu-sifive-e31/metal.freertos.lds +++ b/bsp/qemu-sifive-e31/metal.freertos.lds @@ -78,8 +78,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -278,7 +280,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-e31/metal.ramrodata.lds b/bsp/qemu-sifive-e31/metal.ramrodata.lds index bc228a21f..b1c9357df 100644 --- a/bsp/qemu-sifive-e31/metal.ramrodata.lds +++ b/bsp/qemu-sifive-e31/metal.ramrodata.lds @@ -79,8 +79,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -261,7 +263,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-e31/metal.scratchpad.lds b/bsp/qemu-sifive-e31/metal.scratchpad.lds index c55ae5af9..691f9a520 100644 --- a/bsp/qemu-sifive-e31/metal.scratchpad.lds +++ b/bsp/qemu-sifive-e31/metal.scratchpad.lds @@ -71,13 +71,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); /* ROM SECTION * @@ -258,7 +251,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-s51/metal.default.lds b/bsp/qemu-sifive-s51/metal.default.lds index d550a4ac0..734eb421d 100644 --- a/bsp/qemu-sifive-s51/metal.default.lds +++ b/bsp/qemu-sifive-s51/metal.default.lds @@ -75,8 +75,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -257,7 +259,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-s51/metal.freertos.lds b/bsp/qemu-sifive-s51/metal.freertos.lds index 9b70daa68..e237aa639 100644 --- a/bsp/qemu-sifive-s51/metal.freertos.lds +++ b/bsp/qemu-sifive-s51/metal.freertos.lds @@ -78,8 +78,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -278,7 +280,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-s51/metal.ramrodata.lds b/bsp/qemu-sifive-s51/metal.ramrodata.lds index bc228a21f..b1c9357df 100644 --- a/bsp/qemu-sifive-s51/metal.ramrodata.lds +++ b/bsp/qemu-sifive-s51/metal.ramrodata.lds @@ -79,8 +79,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -261,7 +263,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-s51/metal.scratchpad.lds b/bsp/qemu-sifive-s51/metal.scratchpad.lds index c55ae5af9..691f9a520 100644 --- a/bsp/qemu-sifive-s51/metal.scratchpad.lds +++ b/bsp/qemu-sifive-s51/metal.scratchpad.lds @@ -71,13 +71,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); /* ROM SECTION * @@ -258,7 +251,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54/metal.default.lds b/bsp/qemu-sifive-u54/metal.default.lds index 027f0d731..aa9416864 100644 --- a/bsp/qemu-sifive-u54/metal.default.lds +++ b/bsp/qemu-sifive-u54/metal.default.lds @@ -74,7 +74,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -258,7 +258,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54/metal.freertos.lds b/bsp/qemu-sifive-u54/metal.freertos.lds index 201c9756e..34111aaf9 100644 --- a/bsp/qemu-sifive-u54/metal.freertos.lds +++ b/bsp/qemu-sifive-u54/metal.freertos.lds @@ -77,7 +77,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -279,7 +279,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54/metal.ramrodata.lds b/bsp/qemu-sifive-u54/metal.ramrodata.lds index f4677cb0d..26cdef561 100644 --- a/bsp/qemu-sifive-u54/metal.ramrodata.lds +++ b/bsp/qemu-sifive-u54/metal.ramrodata.lds @@ -78,7 +78,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -262,7 +262,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54/metal.scratchpad.lds b/bsp/qemu-sifive-u54/metal.scratchpad.lds index 030e42b01..aae9d6cd2 100644 --- a/bsp/qemu-sifive-u54/metal.scratchpad.lds +++ b/bsp/qemu-sifive-u54/metal.scratchpad.lds @@ -70,15 +70,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ - /* User is recommended to enable the full size for manual RTL simulation run! */ - PROVIDE( metal_memory_0_memory_start = 0x80000000 ); - PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -259,7 +250,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54mc/metal.default.lds b/bsp/qemu-sifive-u54mc/metal.default.lds index 2c52566ff..1d9c96fa5 100644 --- a/bsp/qemu-sifive-u54mc/metal.default.lds +++ b/bsp/qemu-sifive-u54mc/metal.default.lds @@ -74,7 +74,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -261,7 +261,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54mc/metal.freertos.lds b/bsp/qemu-sifive-u54mc/metal.freertos.lds index 2a6e15345..51c7427b0 100644 --- a/bsp/qemu-sifive-u54mc/metal.freertos.lds +++ b/bsp/qemu-sifive-u54mc/metal.freertos.lds @@ -77,7 +77,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -282,7 +282,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54mc/metal.ramrodata.lds b/bsp/qemu-sifive-u54mc/metal.ramrodata.lds index 1ecc9f417..705f52444 100644 --- a/bsp/qemu-sifive-u54mc/metal.ramrodata.lds +++ b/bsp/qemu-sifive-u54mc/metal.ramrodata.lds @@ -78,7 +78,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -265,7 +265,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54mc/metal.scratchpad.lds b/bsp/qemu-sifive-u54mc/metal.scratchpad.lds index 9779d960d..19ae93a56 100644 --- a/bsp/qemu-sifive-u54mc/metal.scratchpad.lds +++ b/bsp/qemu-sifive-u54mc/metal.scratchpad.lds @@ -70,15 +70,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ - /* User is recommended to enable the full size for manual RTL simulation run! */ - PROVIDE( metal_memory_0_memory_start = 0x80000000 ); - PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -262,7 +253,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds index 4ed71b1e8..897b78dea 100644 --- a/bsp/sifive-hifive-unleashed/metal.default.lds +++ b/bsp/sifive-hifive-unleashed/metal.default.lds @@ -80,9 +80,11 @@ SECTIONS PROVIDE( metal_dtim_0_memory_end = 0x1000000 + 0x2000 ); PROVIDE( metal_itim_0_memory_start = 0x1800000 ); PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_itim_1_memory_start = 0x1808000 ); - PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 ); - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -270,7 +272,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive-unleashed/metal.freertos.lds b/bsp/sifive-hifive-unleashed/metal.freertos.lds index 9f37ace1a..6f95b9489 100644 --- a/bsp/sifive-hifive-unleashed/metal.freertos.lds +++ b/bsp/sifive-hifive-unleashed/metal.freertos.lds @@ -83,9 +83,11 @@ SECTIONS PROVIDE( metal_dtim_0_memory_end = 0x1000000 + 0x2000 ); PROVIDE( metal_itim_0_memory_start = 0x1800000 ); PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_itim_1_memory_start = 0x1808000 ); - PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 ); - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -291,7 +293,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds index 0597a813a..fdbdff9c2 100644 --- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds +++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds @@ -84,9 +84,11 @@ SECTIONS PROVIDE( metal_dtim_0_memory_end = 0x1000000 + 0x2000 ); PROVIDE( metal_itim_0_memory_start = 0x1800000 ); PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_itim_1_memory_start = 0x1808000 ); - PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 ); - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -345,7 +347,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds index 8db14f043..1e33179b8 100644 --- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds +++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds @@ -72,21 +72,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x1000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x1000000 + 0x2000 ); - PROVIDE( metal_itim_0_memory_start = 0x1800000 ); - PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 ); - PROVIDE( metal_itim_1_memory_start = 0x1808000 ); - PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 ); - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ - /* User is recommended to enable the full size for manual RTL simulation run! */ - PROVIDE( metal_memory_0_memory_start = 0x80000000 ); - PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -271,7 +256,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1-revb/metal.default.lds b/bsp/sifive-hifive1-revb/metal.default.lds index 37261aadc..93a94dce0 100644 --- a/bsp/sifive-hifive1-revb/metal.default.lds +++ b/bsp/sifive-hifive1-revb/metal.default.lds @@ -260,7 +260,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1-revb/metal.freertos.lds b/bsp/sifive-hifive1-revb/metal.freertos.lds index 581bdaf06..f5c59cfa8 100644 --- a/bsp/sifive-hifive1-revb/metal.freertos.lds +++ b/bsp/sifive-hifive1-revb/metal.freertos.lds @@ -281,7 +281,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1-revb/metal.ramrodata.lds b/bsp/sifive-hifive1-revb/metal.ramrodata.lds index de816fa10..7cc59ba98 100644 --- a/bsp/sifive-hifive1-revb/metal.ramrodata.lds +++ b/bsp/sifive-hifive1-revb/metal.ramrodata.lds @@ -264,7 +264,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1-revb/metal.scratchpad.lds b/bsp/sifive-hifive1-revb/metal.scratchpad.lds index 80c581e33..26bfa6633 100644 --- a/bsp/sifive-hifive1-revb/metal.scratchpad.lds +++ b/bsp/sifive-hifive1-revb/metal.scratchpad.lds @@ -72,15 +72,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 ); - PROVIDE( metal_itim_0_memory_start = 0x8000000 ); - PROVIDE( metal_itim_0_memory_end = 0x8000000 + 0x2000 ); /* ROM SECTION * @@ -261,7 +252,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds index b8ce9b4d6..0c657f537 100644 --- a/bsp/sifive-hifive1/metal.default.lds +++ b/bsp/sifive-hifive1/metal.default.lds @@ -257,7 +257,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1/metal.freertos.lds b/bsp/sifive-hifive1/metal.freertos.lds index e52a891f7..92821515a 100644 --- a/bsp/sifive-hifive1/metal.freertos.lds +++ b/bsp/sifive-hifive1/metal.freertos.lds @@ -278,7 +278,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds index 6114d2846..11bd35ecb 100644 --- a/bsp/sifive-hifive1/metal.ramrodata.lds +++ b/bsp/sifive-hifive1/metal.ramrodata.lds @@ -261,7 +261,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds index ac9521f8c..d788aa24f 100644 --- a/bsp/sifive-hifive1/metal.scratchpad.lds +++ b/bsp/sifive-hifive1/metal.scratchpad.lds @@ -71,13 +71,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 ); /* ROM SECTION * @@ -258,7 +251,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/spike/metal.default.lds b/bsp/spike/metal.default.lds index 027f0d731..aa9416864 100644 --- a/bsp/spike/metal.default.lds +++ b/bsp/spike/metal.default.lds @@ -74,7 +74,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -258,7 +258,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/spike/metal.freertos.lds b/bsp/spike/metal.freertos.lds index 201c9756e..34111aaf9 100644 --- a/bsp/spike/metal.freertos.lds +++ b/bsp/spike/metal.freertos.lds @@ -77,7 +77,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -279,7 +279,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/spike/metal.ramrodata.lds b/bsp/spike/metal.ramrodata.lds index f4677cb0d..26cdef561 100644 --- a/bsp/spike/metal.ramrodata.lds +++ b/bsp/spike/metal.ramrodata.lds @@ -78,7 +78,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -262,7 +262,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/spike/metal.scratchpad.lds b/bsp/spike/metal.scratchpad.lds index 030e42b01..aae9d6cd2 100644 --- a/bsp/spike/metal.scratchpad.lds +++ b/bsp/spike/metal.scratchpad.lds @@ -70,15 +70,6 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ - PROVIDE(__metal_eccscrub_bit = 0); - - /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ - /* User is recommended to enable the full size for manual RTL simulation run! */ - PROVIDE( metal_memory_0_memory_start = 0x80000000 ); - PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -259,7 +250,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); From 0e8d167c1839bca76fb4e79dd6a45c18c3da2ae6 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Tue, 28 Jul 2020 14:40:08 -0700 Subject: [PATCH 3/5] Update HCA example to macth scl-metal --- software/example-hca-metal | 2 +- wit-manifest.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/software/example-hca-metal b/software/example-hca-metal index fa7f4f372..82c3f5933 160000 --- a/software/example-hca-metal +++ b/software/example-hca-metal @@ -1 +1 @@ -Subproject commit fa7f4f372439af72a5a20c681428ab9ef861b75d +Subproject commit 82c3f59331cb51d2b9234bde5cefae96187e2267 diff --git a/wit-manifest.json b/wit-manifest.json index 03ac73aec..951e316f2 100644 --- a/wit-manifest.json +++ b/wit-manifest.json @@ -255,7 +255,7 @@ "source": "git@github.com:sifive/scl-metal.git" }, { - "commit": "fa7f4f372439af72a5a20c681428ab9ef861b75d", + "commit": "82c3f59331cb51d2b9234bde5cefae96187e2267", "name": "example-hca-metal", "source": "git@github.com:sifive/example-hca-metal.git" } From b90a3ea4c7c15c5c0bbebc536d722618419a9af1 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Tue, 28 Jul 2020 14:55:06 -0700 Subject: [PATCH 4/5] Revert "Update HCA example to macth scl-metal" This reverts commit 0e8d167c1839bca76fb4e79dd6a45c18c3da2ae6. --- software/example-hca-metal | 2 +- wit-manifest.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/software/example-hca-metal b/software/example-hca-metal index 82c3f5933..fa7f4f372 160000 --- a/software/example-hca-metal +++ b/software/example-hca-metal @@ -1 +1 @@ -Subproject commit 82c3f59331cb51d2b9234bde5cefae96187e2267 +Subproject commit fa7f4f372439af72a5a20c681428ab9ef861b75d diff --git a/wit-manifest.json b/wit-manifest.json index 951e316f2..03ac73aec 100644 --- a/wit-manifest.json +++ b/wit-manifest.json @@ -255,7 +255,7 @@ "source": "git@github.com:sifive/scl-metal.git" }, { - "commit": "82c3f59331cb51d2b9234bde5cefae96187e2267", + "commit": "fa7f4f372439af72a5a20c681428ab9ef861b75d", "name": "example-hca-metal", "source": "git@github.com:sifive/example-hca-metal.git" } From 492f61679b5b7356ad0fdb881e3026b2eaefe73e Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Tue, 28 Jul 2020 15:25:27 -0700 Subject: [PATCH 5/5] Revert SCL metal and HCA example --- scl-metal | 2 +- wit-manifest.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scl-metal b/scl-metal index e8ec9d5a7..a0f13a316 160000 --- a/scl-metal +++ b/scl-metal @@ -1 +1 @@ -Subproject commit e8ec9d5a7e9157b0bf04f2ad8c51f55d74d68145 +Subproject commit a0f13a3164bca4e7689ca63895fb9457dc7b96bd diff --git a/wit-manifest.json b/wit-manifest.json index 03ac73aec..e614fbce8 100644 --- a/wit-manifest.json +++ b/wit-manifest.json @@ -250,7 +250,7 @@ "source": "git@github.com:sifive/example-hpm.git" }, { - "commit": "e8ec9d5a7e9157b0bf04f2ad8c51f55d74d68145", + "commit": "a0f13a3164bca4e7689ca63895fb9457dc7b96bd", "name": "scl-metal", "source": "git@github.com:sifive/scl-metal.git" },