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Xilinx FPGA Bitstream #27

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2 of 8 tasks
ben-marshall opened this issue Aug 25, 2020 · 0 comments
Open
2 of 8 tasks

Xilinx FPGA Bitstream #27

ben-marshall opened this issue Aug 25, 2020 · 0 comments
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Flow Change relating to flow/scripting RTL Changes required to the RTL code

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  • Memory Primitive Updates
  • Re-do Top-Level Block Diagram
  • Update Vivado FSBL generation.
  • Verify boot in simulation.
  • Verify boot on hardware.
  • Save new Bitstream.
  • Check GPIOs work.
  • Update project re-generation script.
@ben-marshall ben-marshall self-assigned this Aug 25, 2020
@ben-marshall ben-marshall added Flow Change relating to flow/scripting RTL Changes required to the RTL code labels Aug 25, 2020
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